DAP miniWiggler V3

DAP miniWiggler V3
AP56004
A pplication Note
V1.0 2013-07
Microcontrollers
Edition 2013-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
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miniWiggler V3
AP56004
Document Change History
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Application Note
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miniWiggler V3
AP56004
Table of Contents
1 Preface ............................................................................................................................... 5 2 2.1 Introduction ....................................................................................................................... 6 Comparison with DAP miniWiggler V2.0 ............................................................................. 6 3 3.1 Automotive JTAG Connector ........................................................................................... 7 Comparison with OCDS L1 Connector................................................................................ 8 4 Frontend Connector (JTAG + EXT) .................................................................................. 9 5 Frontend Identifiers......................................................................................................... 10 6 Target Communication ................................................................................................... 11 7 References ....................................................................................................................... 12 Application Note
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Preface
DAP miniWiggler V3.1 is the successor of DAP miniWiggler V2.0.
Target group for this application note are tool partners and users.
This application note assumes that the reader knows the tool interfaces of Infineon devices.
Hints
•
•
•
Never connect the DAP cable to the EXT connector of the miniWiggler. This will destroy the target
and/or the miniWiggler.
Never connect both JTAG and DAP cables to targets at the same time
In case of JTAG please make sure that the JPD pin is connected to GND on target side.
Application Note
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Introduction
EXT
DAP
JTAG
Figure 1 shows the location and orientation of the different connectors.
Figure 1
DAP miniWiggler V3.1
2.1
Comparison with DAP miniWiggler V2.0
•
•
•
•
•
RESET pin is controlled with pull-down transistor
UART RXD is connected to SWV pin on SWD/DAP connector
Large OCDS L1 connector is replaced by small 20 pin Automotive JTAG connector
Connector for frontend extensions (e.g. for galvanic isolation) added
USER1/DAPEN pin has a strong pull-up. Allows DAP hot attach if device is powered first.
Application Note
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Automotive JTAG Connector
This 20 pin connector in two rows with 1.27 mm pitch is a space saving alternative to the OCDS L1
[6]
connector. The pin layout is compatible with Lauterbach's 20 pin Automotive Connector (AUTO-20)
Table 1
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Automotive JTAG Connector on Target Board
Name
VREF
TMS
GND
TCK
GND
TDO
KEY
(GND in
cable)
TDI
GND
RESET
I
I
O
-
I
IO
GND
RESETOUT O
13
14
GND
USER1
15
16
17
18
GND
TRST
GND
TGI_RXD
19
GND
20
Dir.
O
I(O)
I
IO
-
USER0_TXD IO
Application Note
Description
Supply voltage from the target system. It has to be strong enough to supply
the target side of the level shifters within the tool hardware up to about 10
MHz JTAG operating frequency. The required supply current is in the range
of 1 to 5 mA, mainly caused by signal switching. It can be reduced by lower
frequency and capacitance.
JTAG TMS signal.
JTAG TCK signal.
JTAG TDO signal.
If the connector on the board has no keying shroud, this pin provides
another option to enforce polarization. For that this pin is removed from the
target connector and the associated jack in the cable connector closed.
JTAG TDI signal.
Low active target reset signal. Open drain active low signal. May be used bidirectionally to drive or sense the target reset signal. Usually driven by the
tool to reset the target system. The target system is responsible for providing
a pull up to VREF on this signal to establish a logic one. The resistor shall
not have a value less than 1 kOhms.
Optional low active reset output signal. Left open on tool side if not
supported by tool.
Optional user defined IO pin e.g. for WDTDIS or /OCDSE.
Default direction is input and default level is High. Pulled (10kR) to VREF on
tool side if not supported by tool.
Low active JTAG reset.
Low active trigger in (default) or out signal
Or UART RXD input of device.
Target presence detection. Connected to GND on target side. Pull-up and
sensing on tool side.
Optional user defined IO pin.
Or UART TXD output of device.
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3.1
Comparison with OCDS L1 Connector
The larger OCDS L1 connector is specified in AP24001
Table 2
Comparison with OCDS L1 Connector
Automotive
VREF
TMS
TCK
TDO
TDI
RESET
TGI_RXD
TGO_TXD
USER0
USER1
-
[5]
OCDS L1
VDD
TMS
TCK
TDO
TDI
RESET
BRKIN
Comment
New trigger pin naming starting with AURIX devices.
Optional RXD function.
BRKOUT
New trigger pin naming starting with AURIX devices.
Optional TXD function.
Automotive connector is aligned with DAP connector
Automotive connector is aligned with DAP connector
RCAP1
Undefined behavior
RCAP2
Undefined behavior
OCDSE
Obsolete
CPU_CLOCK Obsolete
Application Note
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Frontend Connector (JTAG + EXT)
Additional 10 pins (EXT) for a 34 pin cable are used. There is a gap of 4 pins to allow the plugging of
the 20 pin JTAG connector.
Table 3
Pin
1
2
3
4
5
6
Frontend Connector (JTAG + EXT)
Name
VREF
TMS
GND
TCK
GND
TDO
Dir. Comment
I
O
DAP0
O
DAP1
I/IO Note that this DAP/JTAG signal mapping is not compliant with the
standard DAP1/TMS mapping on device side.
7
GND
8
TDI
DAP1O O
DAP1 output signal in case of DAP and galvanic isolation.
9
GND
10
RESET
O
11
GND
12
RESETOUT
I
Not supported. Left open.
13
GND
14
USER1
IO
Just output direction in case of galvanic isolation.
15
GND
16
TRST
USER8 O
17
GND
18
TXD
O
Connects to RXD input of device. Voltage level is VREF.
19
JPD
I
JTAG presence detection with internal pull-up. Connect to GND on
target side if the target uses the JTAG interface.
20
USER0_RXD
IO
USER0: Default is input. Only input case of galvanic isolation.
RXD: Connects to TXD output of device. Voltage level is VREF.
21, 23 GND
Connector gap – not assembled.
22, 24 VSUP5
O
Connector gap – not assembled. (5 V supply for frontend)
25
GND
26
DAPDIR O
DAP1 direction. Low for direction target out to tool in.
27
GND
28
DAP1PULL
O
For optional control of DAP1 pull-up/down resistor.
29
GND
30
FEI0
Frontend identification 0 with internal pull-up.
31
VSUP33
O
3.3 V supply for frontend
32
FEI1
Frontend identification 1 with internal pull-up.
33
VSUP33
O
3.3 V supply for frontend
34
FEI2
Frontend identification 2 with internal pull-up.
Application Note
DAP
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Frontend Identifiers
FEIx pins are connected to FT2232 BCBUSx pins similar to JPD connected to ADBUS5 pins.
Note: Frontend boards may only pull (5kR) FEIx signals and not hardwire them. Reason is that the
FT2232 may come up in a mode where it drives the FEIx signals. It is only needed to pull to
GND, since the FT2232 has internal pull-ups active.
Table 4
FEIx 2-1-0
H-H-H
H-H-L
H-L-H
Other
Frontend Identifiers (FEIx Pins)
Comment
No frontend or transparent frontends like connector adaptors
Galvanic isolation frontend
JTAG or DAP/SPD/SWD decided with JPD pin level.
Operating frequency is limited to 10 MHz.
DAP1O operated as output. DAP1, DAP1O, DAPDIR and DAPPULL are operated as
unidirectional signals.
Note that DAP1 is still bidirectional in the DAP miniWiggler V3.1 design. For a simple
galvanic isolation frontend a resistor can be used to limit the current of frontend and
miniWiggler are driving DAP1.
CAN transceiver for DXCPL (DAP over CAN Physical Layer).
Reserved
Application Note
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Target Communication
[1]
[2]
Supports DAS infrastructure with MCD API as interface.
[3]
The DAP miniWiggler V3 provides an R/W latency to the target 150 µs for single accesses and up to
2 MByte/s bandwidth for block data accesses. This bandwidth depends on the frequency, used
protocol and device type. The highest performance is achieved with a direct connection to a fast highspeed USB port of the host computer for DAP and AURIX devices at 30 MHz.
Application Note
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References
[1]
DAS (Device Access Server) www.infineon.com/DAS
[2]
MCD API (Multi-Core Debug) link on page www.infineon.com/DAS
[3]
DAP miniWiggler www.infineon.com/miniWiggler
[4]
AP24003 DAP Connector http://www.infineon.com/microcontrollers
[5]
AP24001 OCDS Level 1 JTAG Connector http://www.infineon.com/microcontrollers
[6]
Lauterbach Automotive Debug Connector (AUTO-20) www.lauterbach.com
Application Note
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V1.0, 2013-07
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Published by Infineon Technologies AG
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