Design of an Isolated 2 W Bias Supply for Telecom Systems Using the NCP1030

!
" #$%&%
Prepared by: Juan Carlos Pastrana
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
• Proprietary Active Leading Edge Blanking (LEB)
INTRODUCTION
Power converters using secondary side controllers
provide better transient response, higher efficiency and
usually require less components than their primary side
referenced counterparts. However, secondary side
controllers require a primary side referenced bias supply to
start operation. After start-up, the controller power can be
provided from the secondary side.
The NCP1030 incorporates in a single IC all the active
power, control logic and protection circuitry required for
implementing, with a minimum of external components, a
highly integrated isolated bias supply. The features included
in the NCP1030 can result in a footprint area reduction by up
to 91% compared to a solution implemented using discrete
components.
The NCP1030 Power Switch Circuit is rated at 200 V,
making it ideal for 48 V Telecom and 42 V automotive
applications. In addition, this IC can operate from an
existing 12 V supply. The NCP1030 includes an extensive
set of features including:
• On Board Power Switch: Eliminates the need for an
external switch. As the Power Switch characteristics
are well known the gate drive is tailored to control
switching transitions and help reduce electromagnetic
interference (EMI).
• An Internal Start-up Regulator: Provides power to
the NCP1030 during start-up. After start-up, the
regulator is disabled, thus reducing power consumption.
The regulator can be powered directly from the input
line.
• Internal Error Amplifier: Allows the implementation
of an isolated supply using primary side regulation
without the need for an optocoupler.
• Internal Cycle by Cycle Current Limit: Eliminates
the need for external sensing components. The
programmed current limit is 500 mA.
 Semiconductor Components Industries, LLC, 2003
July, 2003 - Rev. 0
•
•
•
•
Circuit: Provides better current limit control compared
to a fixed blanking period. The active LEB circuit
masks the current signal during the Power Switch turn
ON transition.
Individual Line Undervoltage and Overvoltage
(UV/OV) Detectors with Hysteresis: Eliminate the
need for external supervisory function. The UV/OV
detectors can be disabled if not needed.
Single Capacitor Oscillator: Eliminates traditional
timing resistor. Oscillator is optimized for operation up
to 1.0 MHz.
Internal $2% Voltage Reference: Eliminates the
need for an external bypass capacitor.
Thermal Shutdown Circuit: Protects the device in the
event the maximum junction temperature is exceeded.
DESIGN SPECIFICATIONS
An isolated bias supply for a telecom system is designed
and implemented using the NCP1030. The supply delivers
2.0 W at 12 V. The converter specifications are listed in
Table 1.
Table 1. Bias Supply Specifications
Parameter
Symbol
Min
Max
Input Voltage
Vin
35 V
76 V
Frequency
İ
250 kHz
300 kHz
Peak Efficiency
h
80%
-
Output Voltage
Vout
10.8 V
13.2 V
Output Current
Iout
0.017 A
0.17 A
Output Power
Pout
2.0 W
-
A Flyback topology operating in discontinuous mode is
selected because of its simplicity and low part count.
1
Publication Order Number:
AND8119/D
AND8119/D
FLYBACK CONVERTER
where, VƒD1 is the forward voltage drop across D1 and
RDS(on) is the Power Switch on resistance. Equation 2
relates the on-time volt-second product to the reset
volt-second product and adds a 20% dead time to insure the
converter operates in discontinuous mode. Solving
Equation 2 assuming a 0.5 V drop across D1,
A dual output Flyback converter is shown in Figure 1.
OUTPUT 1 is regulated by means of OUTPUT 2, providing
an isolated OUTPUT 1 without the need for an optocoupler.
TX
D1
+
Cout
Np
Vout (OUTPUT1)
Ns
+
Snubber
-
CCC
VCC (OUTPUT2)
-
R1
-
PWM
Controller
Vstress + Vin(max) )
EA
+
M1
+
VREF
R2
Current flows in the primary side when the Power Switch,
M1, is ON. The transformer primary side dot end becomes
positive with respect to the non-dot end. While the Power
Switch is ON, energy is stored in the transformer and D1 and
D2 are reverse biased. When M1 turns OFF, the transformer
winding polarities are reversed, forward biasing D1 and D2.
Energy is transferred to the secondary outputs during this
period. If the secondary current decays to zero before the
switch turns ON again, the converter operates in
discontinuous mode. Otherwise, it operates in continuous
mode.
The converter regulates the output by sampling the output
voltage and comparing it to a reference voltage. A signal
proportional to their difference is generated and used to
adjust the ON time of M1 such that the voltage difference is
reduced.
The Snubber limits the voltage across the Power Switch
and helps reduce noise.
Parameter
Ns
(Vout ) VfD1)
(0.8 * DC)
Magnetizing
Inductance @ 0.4 A
1,2-3,4
102 mH
-
Leakage Inductance
1,2-3,4
-
0.955 mH
1-4
2-3
5-6
7-8
-
0.655 W
0.82 W
0.248 W
0.248 W
-
Cout +
3.8 MHz (typ.)
Iout
f
(1 * DC)
Vdroop
(eq. 5)
Solving Equation 5, a maximum voltage droop of 50 mV
requires a 7.4 mF capacitor. However, Cout may be increased
to facilitate frequency compensation.
The secondary peak current, ISPK, and the diode blocking
voltage, Vblock, determine the selection of rectification
diodes, D1 and D2.
The primary peak current and transformer turns ratio
determine the secondary peak current as given by
Equation 6.
(eq. 1)
DC
Max
Two main factors, voltage ripple and frequency
compensation, are considered for the selection of the output
capacitor, Cout. This section will focus on voltage ripple,
while frequency compensation is covered in a latter section.
The output capacitor provides the load current during the
switch ON time. If the target voltage droop is known, Cout
is calculated using Equation 5.
ǒNp
Ǔ is calculated
Ns
RDS(on)))
(Vout ) VfD1) (eq. 4)
MAIN OUTPUT
using Equation 2
(Vin * (IPPK
Ns
Min
Resonant Frequency
Solving Equation 1, a primary inductance of 127 mH is
w
Np
Terminals
DC Resistance
The converter is designed to operate at a maximum duty
cycle (DC) of 40 % and a primary peak current (IPPK) of
400 mA. The required primary inductance, LP, is calculated
using Equation 1.
Np
(eq. 3)
Table 2. Transformer Specifications
DESIGN PROCEDURE
V
DC
Lp + in(min)
f IPPK
7 W)) 0.4
(0.8 * 0.4)
The voltage is significantly below the 200 V maximum
rating of the NCP1030 internal Power Switch.
The transformer winding arrangement includes a split
primary with bifilar secondaries. The transformer can be
ordered from Coilcraft under part number B0226-E. Table 2
summarizes the specifications of the transformer.
-
Figure 1. Isolated Flyback Converter
required. The transformer turns ratio
(35 V * (0.4 A
(12 V ) 0.5 V)
a turns ratio greater than 2.58 is required. A turns ratio of
2.78 is selected.
A maximum stress voltage of 110 V across the primary
switch during the turn OFF period is calculated using
Equation 4.
D2
+
Vin
w
(eq. 2)
ISPK + IPPK
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2
Np
Ns
(eq. 6)
AND8119/D
The voltage across the rectification diode is given by
Equation 7.
Cout
Rout Vout
-
(eq. 7)
+
ǒNNpsǓ
+
Vblock + Vout ) Vin(max)
D1
TX
B
D2
Vin
Solving Equations 6 and 7, the rectification diode needs
to handle 1.11 A and 39.34 V. In addition to the voltage
calculated using equation 7, voltage spikes during switching
transitions need to be considered when selecting the
blocking voltage rating. A Schottky diode is selected to
reduce the forward voltage drop, thus reducing power
dissipation. On Semiconductor’s MBRA160 is selected as it
meets all the requirements.
-
RESR
Rout(eq)
Cout(eq)
Z1
A
Zf
-
PWM
Controller
EA
+
+
VREF
AUXILIARY SUPPLY REGULATOR
NCP1030
The auxiliary supply (OUTPUT 2) provides a means to
regulate the main output (OUTPUT 1). In addition, the
auxiliary winding disables the internal start-up circuit and
provides power to the NCP1030 after initial power up. The
same turns ratio and rectification diode used for the main
output are used for the auxiliary winding to improve voltage
tracking between the outputs.
The auxiliary winding capacitor, CCC, is selected such
that a voltage greater than 7.5 V is maintained on the VCC pin
while the output reaches regulation. The time the output
reaches regulation is measured at 0.8 ms. Once the start-up
time is known, CCC is calculated using Equation 8.
I
t
CCC + CC
2.5 V
Rbias
-
Figure 2. Flyback Converters
The open loop frequency response of the system (from A
to B) is approximated by the modulator gain and the output
network frequency response. Additional high frequency
components are present but are not considered for our
analysis as they are far beyond the crossover frequency. The
modulator gain, GMOD, is approximated by Equation 9.
GMOD + 3 Vin
2
Ǹ
Rout(eq) h
2 f Lp
(eq. 9)
The output network block is comprised of Cout, RESR and
Rout. The frequency response of the output network is given
by Equation 10.
(eq. 8)
where, ICC includes the NCP1030 bias current (ICC3) and
any additional current supplied by CCC. Assuming an ICC3
of 3.0 mA and a 2.0 mA bias current for the feedback
sensing resistors, CCC is calculated at 1.6 mF. The VCC
capacitor is set at 2.2 mF. Please note that if CCC is increased
to match Cout, the transient response of the converter will
suffer. This is because the capacitance to current ratio of the
auxiliary winding is significantly greater then the output
winding, taking it longer for CCC to follow Cout during a
transient condition.
H(f) +
sRESRCout(eq) ) 1
sCout(eq) (RESR ) Rout(eq)) ) 1
(eq. 10)
The total open loop frequency response is the product of
Equations 9 and 10. Please note that Cout(eq) includes CCC
and Cout reflected to the auxiliary winding by the
transformer turns ratio. As the same turns ratio is used for
both the auxiliary and output windings, Cout adds directly to
CCC. The output network has one zero and one pole and they
are given by Equations 11 and 12, respectively.
FEEDBACK LOOP
fz1 +
If the feedback loop is not stable, the converter will
oscillate. To insure the loop is stable, the open loop
frequency response needs to cross 0 dB at a slope of
-20 dB/dec, with a phase margin above 45° under all line
and load conditions. This is accomplished by shaping the
loop response using the internal error amplifier (EA).
The block diagram shown in Figure 2 is used to evaluate
the converter open loop response.
1
2p Cout RESR
(eq. 11)
1
2p Rout Cout
(eq. 12)
fp1 [
The modulator gain response depends on Vin. Two
extreme conditions, both minimum Rout and input voltage
(GMOD1) as well as both maximum Rout and input voltage
(GMOD2) are considered for frequency compensation. In
order to facilitate frequency compensation, Cout is increased
to 22 mF. The simulated open loop frequency responses for
GMOD1 and GMOD2 are shown in Figures 3 and 4,
respectively.
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3
AND8119/D
0
50
Magnitude
Phase
30
-20
20
-30
10
-40
0
-50
-10
-60
-20
-70
-30
-80
-40
-90
102
103
104
105
fp3 +
Figure 3. Open Loop Frequency Response for GMOD1
0
Magnitude
Phase
-10
30
-20
20
-30
10
-40
0
-50
-10
-60
-20
-70
-30
-80
-40
-90
-50
101
10 2
10 3
10 4
R4 +
(eq. 15)
Frequency (Hz)
Figure 4. Open Loop Frequency Response for GMOD2
VCC
* R5
Ibias1
The frequency compensation can be achieved using a type
II error amplifier (EA) as the one shown in Figure 5.
Z1
C2
EA
Output
+
(R5)
Table 3. System Gain, Poles and Zeros
R7
+
Rbias
Zf
R6
R4
VREF
Parameter
Frequency (kHz)
Magnitude (dB)
fP1 (@ GMOD1)
0.091
-
fP1 (@ GMOD2)
0.009
-
fP2
0
-
fP3
23.9
-
fZ1
77.4
-
fZ2
0.482
-
GEA
-
6.03
-
Figure 5. Type II Error Amplifier
A type II error amplifier has 2 poles and 1 zero. The
transfer function is given by Equation 13.
H(f) +
(eq. 18)
4
The error amplifier zero, fz2, is placed before the system
response crosses 0 dB. Pole, fp3, is placed after fCO to
attenuate high frequency components. Table 3 summarizes
the system gain, poles and zeros. Figure 6 shows the EA
frequency response.
Input
C6
(eq. 17)
ǒRR7Ǔ
GEA + 20 log
Ibias1
(eq. 16)
Using a bias current of 2.0 mA, R4 and R5 are calculated at
4.99 kW and 1.30 kW, respectively. Resistor R6 provides a
test point to measure the open loop frequency response. It is
set at 10 W to avoid disrupting the DC bias point.
The error amplifier DC gain, GEA, is calculated using
Equation 18. It is set at 6.03 dB to achieve a gain of 0 dB at
10 kHz for GMOD1.
-100
10 6
10 5
(C2 ) C6)
2pR7C2C6
V
R5 + REF
Ibias1
Angle (degrees)
Magnitude (dB)
40
(eq. 14)
The EA poles and zero locations are selected to achieve
the desired crossover frequency, fCO. A system crossover
frequency of 10 kHz is selected for GMOD1. As the
modulator gain depends on the input voltage, a higher fCO
is obtained for the maximum input voltage condition with
equivalent output load.
The selection of the compensation components begins by
noting that the voltage on the VFB pin should be equal to
2.5 V (VREF) when the output is in regulation (12 V). If the
feedback sensing resistor network bias current (Ibias1) is
known, R4 and R5 are calculated using Equations 16 and 17,
respectively.
Frequency (Hz)
50
1
2pR7C2
fz2 +
-100
106
-50
101
One of the poles, fp2, is at the origin. The frequency of the
remaining pole and zero are given by Equations 14 and 15,
respectively.
-10
Angle (degrees)
Magnitude (dB)
40
sR7C2 ) 1
sR4(C2 ) C6)ǒ1 ) sR7 C
C7 C6
7)C6
Ǔ
(eq. 13)
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4
AND8119/D
60
0
Magnitude (dB)
50
40
-20
30
-30
20
-40
10
-50
0
-60
-10
-70
-20
-80
-30
-90
-40
102
103
104
105
The NCP1030 eliminates the need for additional
supervisory circuitry by incorporating individual under and
overvoltage detectors with hysteresis. The controller is
enabled if the voltage on the UV pin is above 2.5 V and the
voltage on the OV pin is below 2.5 V. The UV/OV detectors
can be biased using an external resistor divider as shown in
Figure 8.
Vin
R1
-100
106
R2
Frequency (Hz)
VOV
-
The phase contributions of a zero and a pole at the
crossover frequency are given by Equations 19 and 20,
respectively.
ǒfCO
Ǔ
fz
fCO
Ǔ
qp + tan - 1ǒ
fp
qz + tan - 1
R1 [
The phase margin, qM, is evaluated taking into account the
phase contribution of all the poles and zeros as shown below
in Equation 21.
R3 [
(eq. 21)
qM + 180° * 89.5° * 90 ° * 22.7 ° ) 7.33° ) 87.24° + 72.4°
-100
-110
40
-120
Phase
(Vin = 76V,
Rout = 720W)
Magnitude
(Vin = 36V,
Rout = 72W)
30
20
10
0
Magnitude
(Vin = 76V,
Rout = 720W)
-10
-20
101
10 2
103
-130
-140
-150
105
(eq. 24)
An oscillator frequency of 275 kHz is obtained with a
timing capacitor (CT) of 680 pF. The tolerance of CT is set
at 5%.
SNUBBER
-160
An RCD snubber as shown in Figure 9 is added to help
reduce noise. The snubber is returned to the positive supply
rail to reduce the voltage stress on C9 to Vin. If returned to
the negative supply rail, the voltage stress is 2Vin.
-170
104
R3 DVin
Vin(min)
OSCILLATOR FREQUENCY
Angle (degrees)
Magnitude (dB)
-90
50
(eq. 22)
Using a bias current of 78 mA, a turn ON voltage of 35 V,
a turn OFF voltage of 80 V and a VOV threshold of 2.55 V,
R1, R2 and R3 are calculated at approximately 1.0 MW,
45.3 kW and 34 kW, respectively. Capacitors C7 and C8 help
reduce noise and provide a stable voltage during turn ON
and turn OFF transitions. They are set at 10 nF.
-80
60
Vin(max)
Ibias2
(eq. 23)
VOV
R1 Vin(min)
Vin(min)Vin(max) * VOV(DVin ) Vin(min) )
R2 [
The calculated phase margin is 72.4°. The 180° term
arises because the EA is in an inverting configuration. The
simulated system frequency responses for GMOD1 and
GMOD2 are shown in Figure 7.
Phase
(Vin = 36V,
Rout = 72W)
-
If the resistor network bias current, Ibias2, is known, and
the VOV and VUV thresholds are equal, R1, R3 and R2 are
calculated using Equations 22, 23 and 24, respectively.
(eq. 20)
80
VUV
C8 R3
Figure 8. UV/OV Resistor Bias Network
(eq. 19)
qM°+ 180 * qp1 * qp2 * qp3 ) qz1 ) qz2
C7
+
Figure 6. Error Amplifier Frequency Response
70
Ibias2
+
101
UNDER/OVERVOLTAGE DETECTORS
-10
Angle (degrees)
Magnitude
Phase
-180
10 6
Frequency (Hz)
Figure 7. System Frequency Response
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5
AND8119/D
40
TX
Converter Input Impedance
30
R9
C9
20
10
0
-10
-20
LC Filter Output Impedance
-30
Figure 9. RCD Snubber
-40
102
(eq. 25)
Switching regulators can be noisy! However, with careful
layout, noise is reduced. A few things to remember are:
1. Keep switching elements and high current traces
away from the controller and sensitive nodes.
2. Keep trace lengths to a minimum, especially
important for high current paths and timing
components.
3. Use wide traces for high current paths.
4. Place bypass capacitors close to the components.
5. Use a ground plane if possible or a single point
ground system.
The bias supply is built using a single layer FR4, board.
The board size is 2.0 in x 3.5 in. The complete circuit
schematic is shown in Figure 12 and an actual size picture
of the board is shown in Figure 13. The Bill of Material is
listed in Table 4.
An L-C filter at the converter input is used to reduce EMI.
The input L-C filter reduces noise and provides a solid input
voltage to the converter. The filter is shown in Figure 10.
Capacitor C10 is used for common mode noise reduction.
L1
2.2 mH
2.2
C10
0.022
Figure 10. Input L-C Filter Schematic
+
35-76V
-
Oscillation may occur if the converter input impedance,
Zin, is lower than the LC filter output impedance[1]. The
converter input impedance can be approximated as a
negative resistor using Equation 26.
Zin(dB * Ohm) [ - 20 log
outǓ
ǒVIout
1:2.78 MBRA160T3
2.2
2.2
0.022
(eq. 26)
The converter closed loop input impedance is ultimately
determined by the converter feedback loop as well as the
open loop input impedance. However, a resistor is a good
approximation and will be used for our analysis. Figure 11
shows the theoretical input filter output impedance and the
approximated converter input impedance.
680p
499
22
NCP1030
GND VDRAIN
VCC
CT
UV
VFB
OV
COMP
2.2
0.01
45k3
34k
0.033 10k
Figure 12. Complete Circuit Schematic
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6
10
4k99
0.01
680p
+
12V
-
MBRA160T3
1M
100 p
C5
106
LAYOUT CONSIDERATIONS
INPUT FILTER
Vin
105
Figure 11. LC Filter Output Impedance and
Approximated Converter Input Impedance
The snubber components are not assembled in the
converter. However, electrical connections are provided if
the user wants to add the snubber components.
+
104
FREQUENCY (Hz)
The power dissipation of R9 is determined by C9 and is
given by equation 25.
P + 1 C9 Vin2 f
2
103
MURA110T3
D3
MAGNITUDE (dB)
+
Vin
-
1k30
AND8119/D
Figure 13. Demonstration Board (Actual Size)
DESIGN VERIFICATION
Table 4. Bill of Materials
Ref
Value
Vendor
Part Number
C1
680 pF
Vishay
VJ0805A681JXA
C2
0.033 mF
Vishay
VJ0805Y333KXXA
C3
22 mF
TDK
C4532X5R1E226M
C4
2.2 mF
TDK
C4532X7R1H225M
C5
2.2 mF
TDK
C4532X7R2A225M
C6
680 pF
Vishay
VJ0805A681JXA
C7, C8
0.01 mF
Vishay
VJ0805Y103KXXAT
C9
100 pF
TDK
C1608C0G2E101J
C10
0.022 mF
TDK
C2012X7RE223K
D1, D2
-
ON Semiconductor
MBRA160T3
D3
-
ON Semiconductor
MURA110T3
J1-J4
-
Mill-Max
Terminal
L1
2.2 mH
Vishay
IMC-1210
R1
1 MW
Vishay
CRCW08051004F
R2
45.3 kW
Vishay
CRCW08054532F
R3
34 kW
Vishay
CRCW08053402F
R4
4.99 kW
Vishay
CRCW08054991F
R5
1.30 kW
Vishay
CRCW08051301F
R6
10 W
Vishay
CRCW080510R0F
R7
10 kW
Vishay
CRCW08051002F
R8
0W
Vishay
CRCW0805000ZJ
R9
499 W
Vishay
CRCW12104990F
TX1
-
Coilcraft
B0226-E
U1
-
ON Semiconductor
NCP1030DR2
The final step in our design includes validation and test of
the bias supply. Before powering the supply, it should be
inspected for potential problems. A few suggestions
include:
1. Verify all connections. Check for shorts and opens,
especially on the input and output terminals.
2. Verify component values.
3. Slowly increase the input voltage while
monitoring the input current. If the input current
exceeds 10 mA, repeat steps 1 to 3.
4. Once the input voltage reaches 25 V, measure the
voltage on critical nodes. The NCP1030 start-up
regulator should be ON. If the voltages are not
correct, remove power and repeat steps 1 to 3.
5. Increase the input voltage to 36 V. Measure the
output voltage. If it is not approximately 12 V,
repeat steps 1 to 3.
6. Increase the input voltage above 80 V. The output
should turn OFF.
Please be careful when probing and testing the converter.
High voltage may be present. Exercise CAUTION!
Once the converter functionality is verified, the board
performance is evaluated and compared to our original
goals. The evaluation criteria includes:
1. Open loop frequency response.
2. Efficiency.
3. Line and load regulation.
4. Step load response.
5. Start-up response.
The open loop response is measured injecting an AC
signal across R6 using a network analyzer as shown in
Figure 14.
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AND8119/D
Line and load regulation are
Equations 27 and 28, respectively.
D2
+
To Converter
CCC
VCC
DVout
RegLINE +
DVin
-
R6
To Error
Amplifier
RegLOAD +
1:1
Z1
calculated
A
(eq. 27)
Vout(No Load) * Vout(Full Load)
Vout(No Load)
(eq. 28)
Line regulation is measured below 0.5% and load
regulation is measured below 8%. Figure 17 shows the
output voltage variation to output current under several
input voltage conditions.
REF
Rbias
using
Network
Analyzer
B
12.0
11.9
Figure 14. Open Loop Frequency Response
Measurement Set-up
Vout, Output Voltage (V)
11.8
11.7
The measured frequency response is shown in Figure 15.
The crossover frequency is measured at 9 kHz.
11.6
11.5
50
Magnitude (dB)
30
11.3
Vin = 48V
Vin = 76V
11.2
20
11.1
10
11.0
0
0
-10
75
100
125
150
175
102
103
104
105
106
Frequency (Hz)
Iout, Output Current
(20 mA/DIV)
Figure 15. Open Loop Frequency Response
Peak efficiency is measured at 83%. Figure 16 shows the
efficiency vs. output current under several input voltage
conditions.
90
Vout, Output Voltage
(50 mV/DIV)
85
Vin = 36V
Vin = 48V
75
Vin = 76V
70
Vin = 48 V
Iout = 87 mA
Vout = 11.6 V
50 ms/DIV
65
Figure 18. Output Voltage Response to a
Step Load from 87 mA to 127 mA
60
0
200
The dynamic response of the converter is evaluated
stepping the load current from 50% to 75% and from 75%
to 50% of Iout(max). The step load transient responses are
shown in Figures 18 and 19.
-40
80
50
Figure 17. Output Voltage vs. Output Current
-30
-50
25
Iout, OUTPUT CURRENT (mA)
-20
h, Efficiency (%)
Vin = 36V
11.4
Vin = 36 V
Rout = 72 W
40
25
50
75
100
125
150
175
200
Iout, OUTPUT CURRENT (mA)
Figure 16. Efficiency vs Output Current
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8
Finally, the converter turn ON response at full load is
evaluated. Figure 21 shows the output turn ON transient
response at full load.
Vin = 48 V
Iout = 127 mA
Vout, Output Voltage (2.0 V/DIV)
Vout, Output Voltage
(50 mV/DIV)
Iout, Output Current
(20 mA/DIV)
AND8119/D
Vout = 11.45 V
Iout = 170 mA
DSS Operation
OUTPUT2
OUTPUT1 (Isolated)
50 ms/DIV
0V
Figure 19. Output Voltage Response to a
Step Load from 127 mA to 87 mA
1.0 ms/DIV
Output voltage ripple is measured at 25 mV for an output
current of 170 mA. It is significantly below the 50 mV
target. The output voltage ripple waveform is shown in
Figure 20.
Figure 21. Output Voltage During Turn ON
at Full Load
Output 2 operates in DSS while the converter is disabled.
Once the converter is enabled, Output 1 tracks Output 2.
Vout, Output Voltage (20 mV/DIV)
Vin = 48 V
SUMMARY
Iout = 170 mA
An isolated 12 V bias supply for a 48 V telecom system is
implemented using the NCP1030. The converter achieves a
peak efficiency of 83% while providing good transient
response.
REFERENCES
1. Ridley, Ray. “The Evolution of Power Electronics’’,
Switching Power Magazine, Fall 2001:16-30.
2. Pressman, Abraham I. Switching Power Supply
Design. 2nd ed. New York, NY: MacGraw Hill.
Vout = 11.33 V
2.0 ms/DIV
Figure 20. Output Voltage Ripple
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AND8119/D
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