ISL59532 ® Data Sheet July 24, 2006 FN7432.3 32x32 Video Crosspoint Features The ISL59532 is a 300MHz 32x32 Video Crosspoint Switch. Each input has an integrated DC-restore clamp and an input buffer. Each output has a fast On-Screen Display (OSD) switch (for inserting graphics or other video) and an output buffer. The switch is non-blocking, so any combination of inputs to outputs can be chosen, including one channel driving multiple outputs. The Broadcast Mode directs one input to all 32 outputs. The output buffers can be individually controlled through the SPI interface, the gain can be programmed to x1 or x2, and each output can be placed into a high impedance mode. • 32x32 non-blocking switch with buffered inputs and outputs • 300MHz typical bandwidth • 0.025%/0.05° dG/dP • Output gain switchable x1 or x2 for each channel • Individual outputs can be put in a high impedance state • -90dB Isolation at 6MHz • SPI digital interface • Single +5V supply operation The ISL59532 offers a typical -3dB signal bandwidth of 300MHz. Differential gain of 0.025% and differential phase of 0.05°, along with 0.1dB flatness out to 50MHz, make the ISL59532 suitable for many video applications. • Pb-free plus anneal available (RoHS compliant) Applications • Security camera switching The switch matrix configuration and output buffer gain are programmed through an SPI/QSPI™-compatible three-wire serial interface. The ISL59532 interface is designed to facilitate both fast updates and initialization. On power-up, all outputs are high impedance to avoid output conflicts. • RGB routing • HDTV routing Ordering Information The ISL59532 is available in a 356 ball BGA package and specified over an extended -40°C to +85°C temperature range. PART NUMBER The single-supply ISL59532 can accommodate input signals from 0V to 3.5V and output voltages from 0V to 3.8V. Each input includes a clamp circuit that restores the input level to an externally applied reference in AC-coupled applications. ISL59532IKEZ TAPE & REEL - PACKAGE (Pb-Free) 356 Ld BGA PKG. DWG. # V356.27x27A NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. The ISL59533 is a fully differential input version of this device. Block Diagram VS+ VOVERn OVERn 32 OVERLAY INPUT + REF 32 LOGIC CONTROL 2uA Power-on 32 INPUTS Clamp Enable SWITCH MATRIX 32 OUTPUTS + 2uA Av x1, x2 SDI SCLK SLATCH SPI INTERFACE, REGISTER 1 Output Enable Power-on SDO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL59532 Pinout ISL59532 (356 LD BGA) TOP VIEW A In24 In25 In26 In27 In28 In29 In30 In31 Over31 Over30 Over29 Over28 Out27 Out26 Out25 Out24 B Out31 Out30 Out29 Out28 Over27 Over26 Over25 Over24 C In23 Vover31 Vover30 Vover29 Vover28 Vover27 Vover26 Vover25 Vover24 Vover23 Out23 Over23 D VSDO In22 Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vover22 Out22 Over22 Vs Vover21 Out21 Over21 E In21 Vs In20 Vs GND GND GND GND GND GND GND GND GND GND Vs Vover20 Out20 Over20 F G In19 SDO Vs GND GND GND GND GND GND GND GND GND GND Vs Vover19 Over19 Out19 In18 RESET Vs GND GND GND GND GND GND GND GND GND GND Vs Vover18 Over18 Out18 In17 SLATCH Vs GND GND GND GND GND GND GND GND GND GND Vs Vover17 Over17 Out17 In16 SCLK Vs GND GND GND GND GND GND GND GND GND GND Vs Vover16 Over16 Out16 In15 SDI Vs GND GND GND GND GND GND GND GND GND GND Vs Vover15 Out15 Over15 In14 VREF Vs GND GND GND GND GND GND GND GND GND GND Vs Vover14 Out14 Over14 In13 Vs GND GND GND GND GND GND GND GND GND GND Vs Vover13 Out13 Over13 In12 Vs GND GND GND GND GND GND GND GND GND GND Vs Vover12 Out12 Over12 In11 Vs GND GND GND GND GND GND GND GND GND GND Vs Vover11 Over11 In10 Vs Vs Vover10 Over10 Out10 In9 Vs Vs Vover9 Over9 Out9 Vover0 Vover1 Vover2 Vover3 Vover4 Vover5 Vover6 Vover7 Vover8 Over8 Out8 19 20 H J K L M N P R Out11 T U Vs Vs NC NC Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs V In8 NC W Over0 Over1 Over2 Over3 Out4 Out5 Out6 Out7 Out0 Out1 Out2 Out3 Over4 Over5 Over6 Over7 10 11 12 13 14 15 16 17 Y In7 In6 In5 In4 In3 In2 In1 In0 1 2 3 4 5 6 7 8 9 18 = NO BALLS Balls labelled “NC” should be left unconnected - do not tie them to ground! Balls with no labels may be tied to ground to slightly reduce thermal impedance. 2 FN7432.3 July 24, 2006 ISL59532 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . . 6.0V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum power supply (VS) slew rate . . . . . . . . . . . . . . . . . . 1V/µs ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VS = 5V, RL = 150Ω unless otherwise noted. DESCRIPTION CONDITION MIN TYP MAX UNIT 4.5 5.5 V 5.5 V VS Power Supply Voltage VSDO Power Supply for SDO output pin Establishes serial data output high level 1.2 AV Gain AV = 1 0.98 1 1.02 V/V AV = 2 1.96 2 2.04 V/V AV = 1 -1.5 +1.5 % AV = 2 -1.5 +1.5 % GM Gain Matching (to average of all other outputs) VIN Video Input Voltage Range AV = 1 0 3.5 V VOUT Video Output Voltage Range AV = 2 0.1 3.8 V IB Input Bias Current Clamp function disabled (DC coupled inputs) -10 -5 1 µA Clamp function enabled, VIN = VREF + 0.5V 0.5 2 10 µA AV = 1 -20 8 35 mV AV = 2 -100 -24 40 mV Sourcing, RL = 10Ω to GND 60 108 mA Sinking, RL = 10Ω to 2.5V 24 31 mA dB VOS IOUT Output Offset Voltage Output Current PSRR Power Supply Rejection Ratio AV = 2 50 70 IS Supply Current Enabled, all outputs enabled, no load current 560 640 720 mA Enabled, all outputs disabled, no load current 280 320 360 mA Disabled 1.2 1.8 2.4 mA MIN TYP MAX UNIT AC Electrical Specifications PARAMETER VS = 5V, RL = 150Ω unless otherwise noted. DESCRIPTION CONDITION BW -3dB 3dB Bandwidth VOUT = 200mVP-P, AV = 2 300 MHz BW 0.1dB 0.1dB Bandwidth VOUT = 200mVP-P, AV = 2 50 MHz SR Slew Rate VOUT = 2VP-P, AV = 2 TS Settling Time to 0.1% VOUT = 2VP-P, AV = 2 12 ns Glitch Switching Glitch, Peak AV = 1 40 mV Tover Overlay Delay Time From OVER rising edge to output transition 6 ns dG Diff Gain AV = 2, RL = 150Ω 0.025 % dP Diff Phase AV = 2, RL = 150Ω 0.05 ° Xt Hostile Crosstalk 6MHz -85 dB VN Input Referred Noise Voltage 18 nV/√Hz 3 300 520 740 V/µs FN7432.3 July 24, 2006 ISL59532 Pin Descriptions (Continued) Pin Descriptions NAME NUMBER Crosspoint Video Input OUT6 W16 Crosspoint Video Output Y7 Crosspoint Video Input OUT7 W17 Crosspoint Video Output IN2 Y6 Crosspoint Video Input OUT8 V20 Crosspoint Video Output IN3 Y5 Crosspoint Video Input OUT9 U20 Crosspoint Video Output IN4 Y4 Crosspoint Video Input OUT10 T20 Crosspoint Video Output IN5 Y3 Crosspoint Video Input OUT11 R20 Crosspoint Video Output IN6 Y2 Crosspoint Video Input OUT12 P19 Crosspoint Video Output IN7 Y1 Crosspoint Video Input OUT13 N19 Crosspoint Video Output IN8 V1 Crosspoint Video Input OUT14 M19 Crosspoint Video Output IN9 U1 Crosspoint Video Input OUT15 L19 Crosspoint Video Output IN10 T1 Crosspoint Video Input OUT16 K20 Crosspoint Video Output IN11 R1 Crosspoint Video Input OUT17 J20 Crosspoint Video Output IN12 P1 Crosspoint Video Input OUT18 H20 Crosspoint Video Output IN13 N1 Crosspoint Video Input OUT19 G20 Crosspoint Video Output IN14 M1 Crosspoint Video Input OUT20 F19 Crosspoint Video Output IN15 L1 Crosspoint Video Input OUT21 E19 Crosspoint Video Output IN16 K1 Crosspoint Video Input OUT22 D19 Crosspoint Video Output IN17 J1 Crosspoint Video Input OUT23 C19 Crosspoint Video Output IN18 H1 Crosspoint Video Input OUT24 A17 Crosspoint Video Output IN19 G1 Crosspoint Video Input OUT25 A16 Crosspoint Video Output IN20 F1 Crosspoint Video Input OUT26 A15 Crosspoint Video Output IN21 E1 Crosspoint Video Input OUT27 A14 Crosspoint Video Output IN22 D1 Crosspoint Video Input OUT28 B13 Crosspoint Video Output IN23 C1 Crosspoint Video Input OUT29 B12 Crosspoint Video Output IN24 A1 Crosspoint Video Input OUT30 B11 Crosspoint Video Output IN25 A2 Crosspoint Video Input OUT31 B10 Crosspoint Video Output IN26 A3 Crosspoint Video Input OVER0 W10 Overlay Logic Control (with pull-down) IN27 A4 Crosspoint Video Input OVER1 W11 Overlay Logic Control (with pull-down) IN28 A5 Crosspoint Video Input OVER2 W12 Overlay Logic Control (with pull-down) IN29 A6 Crosspoint Video Input OVER3 W13 Overlay Logic Control (with pull-down) IN30 A7 Crosspoint Video Input OVER4 Y14 Overlay Logic Control (with pull-down) IN31 A8 Crosspoint Video Input OVER5 Y15 Overlay Logic Control (with pull-down) OUT0 Y10 Crosspoint Video Output OVER6 Y16 Overlay Logic Control (with pull-down) OUT1 Y11 Crosspoint Video Output OVER7 Y17 Overlay Logic Control (with pull-down) OUT2 Y12 Crosspoint Video Output OVER8 V19 Overlay Logic Control (with pull-down) OUT3 Y13 Crosspoint Video Output OVER9 U19 Overlay Logic Control (with pull-down) OUT4 W14 Crosspoint Video Output OVER10 T19 Overlay Logic Control (with pull-down) OUT5 W15 Crosspoint Video Output OVER11 R19 Overlay Logic Control (with pull-down) NAME NUMBER IN0 Y8 IN1 DESCRIPTION 4 DESCRIPTION FN7432.3 July 24, 2006 ISL59532 Pin Descriptions (Continued) NAME NUMBER OVER12 P20 OVER13 DESCRIPTION Pin Descriptions (Continued) NAME NUMBER Overlay Logic Control (with pull-down) VOVER18 H18 Overlay Video Input N20 Overlay Logic Control (with pull-down) VOVER19 G18 Overlay Video Input OVER14 M20 Overlay Logic Control (with pull-down) VOVER20 F18 Overlay Video Input OVER15 L20 Overlay Logic Control (with pull-down) VOVER21 E18 Overlay Video Input OVER16 K19 Overlay Logic Control (with pull-down) VOVER22 D18 Overlay Video Input OVER17 J19 Overlay Logic Control (with pull-down) VOVER23 C18 Overlay Video Input OVER18 H19 Overlay Logic Control (with pull-down) VOVER24 C17 Overlay Video Input OVER19 G19 Overlay Logic Control (with pull-down) VOVER25 C16 Overlay Video Input OVER20 F20 Overlay Logic Control (with pull-down) VOVER26 C15 Overlay Video Input OVER21 E20 Overlay Logic Control (with pull-down) VOVER27 C14 Overlay Video Input OVER22 D20 Overlay Logic Control (with pull-down) VOVER28 C13 Overlay Video Input OVER23 C20 Overlay Logic Control (with pull-down) VOVER29 C12 Overlay Video Input OVER24 B17 Overlay Logic Control (with pull-down) VOVER30 C11 Overlay Video Input OVER25 B16 Overlay Logic Control (with pull-down) VOVER31 C10 Overlay Video Input OVER26 B15 Overlay Logic Control (with pull-down) VREF M3 OVER27 B14 Overlay Logic Control (with pull-down) OVER28 A13 Overlay Logic Control (with pull-down) OVER29 A12 Overlay Logic Control (with pull-down) OVER30 A11 Overlay Logic Control (with pull-down) OVER31 A10 Overlay Logic Control (with pull-down) VOVER0 V10 Overlay Video Input DC-restore clamp reference input. In an AC-coupled configuration (DC-Restore clamp enabled), the sync tip of composite video inputs will be restored to this level. Set to 0.3 to 0.7V for optimum performance. In an DC-coupled configuration (DC-Restore clamp disabled), this pin should be tied to ground. Never let the VREF pin float! A floating VOVER1 V11 Overlay Video Input VOVER2 V12 Overlay Video Input VOVER3 V13 Overlay Video Input VOVER4 V14 Overlay Video Input VOVER5 V15 Overlay Video Input VOVER6 V16 Overlay Video Input VOVER7 V17 Overlay Video Input VOVER8 V18 Overlay Video Input another ISL59532 to enable daisy- VOVER9 U18 Overlay Video Input chaining of multiple devices. VOVER10 T18 Overlay Video Input VOVER11 R18 Overlay Video Input VOVER12 P18 Overlay Video Input VOVER13 N18 Overlay Video Input VOVER14 M18 Overlay Video Input VS VOVER15 L18 Overlay Video Input GND VOVER16 K18 Overlay Video Input NC VOVER17 J18 Overlay Video Input 5 DESCRIPTION VREF pin drifts high (and if the clamp function is enabled) will cause all of the outputs to simultaneously try to drive ~4V DC into their 150Ω loads. SLATCH J3 Serial Latch. Serial data is latched into ISL59532 on rising edge of SLATCH. SCLK K3 Serial data clock SDI L3 Serial data input SDO G3 Serial data output. Can be tied to SDI of RESET H3 VSDO D3 Reset input. Pull high then low to reset device, but not needed in normal operation. Tie to ground in final application. Power supply for SDO pin. Tie to +5V for a 0 to 5V SDO output signal swing. +5V power supply Ground No Connect - Do not electrically connect to anything, including ground. FN7432.3 July 24, 2006 ISL59532 Typical Performance Curves 33pF MUX mode AV = 1 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 MUX mode AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 27pF 22pF 15pF 33pF 27pF 22pF 15pF 10pF 10pF 4.7pF 4.7pF 0pF 0pF FIGURE 1. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, MUX MODE FIGURE 2. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, MUX MODE 100Ω 100Ω 150Ω 150Ω 500Ω 500Ω 1.07kΩ MUX mode AV = 2 CL = 0 INPUT_CH 0 OUTPUT_CH 0 MUX mode AV = 1 CL = 0 INPUT_CH 0 OUTPUT_CH 0 FIGURE 3. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, MUX MODE Overlay mode AV = 1 RL = 100Ω CL = 0pF INPUT_CH 31 OUTPUT_CH 31 1.07kΩ FIGURE 4. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, MUX MODE Overlay mode AV = 2 RL = 100Ω CL = 0pF INPUT_CH 31 OUTPUT_CH 31 FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 1 6 FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 2 FN7432.3 July 24, 2006 ISL59532 Typical Performance Curves (Continued) Broadcast mode AV = 1 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 33pF Broadcast mode AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 27pF 22pF 15pF 33pF 27pF 22pF 15pF 10pF 10pF 4.7pF 0pF 4.7pF 0pF FIGURE 7. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, BROADCAST MODE FIGURE 8. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, BROADCAST MODE 100Ω 100Ω 150Ω 503Ω 1.07kΩ Broadcast mode AV = 1 CL = 0 INPUT_CH 0 OUTPUT_CH 0 FIGURE 9A. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, BROADCAST MODE AV = 1 RL = 100Ω CL = 0 FIGURE 10. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, BROADCAST MODE AV = 2 RL = 100Ω CL = 0 ADJACENT INPUT_CH30 OUTPUT_CH31 ALL HOSTILE INPUT_CH0 OUTPUT_CH31 FIGURE 11. CROSSTALK - AV = 1 7 1.07kΩ Broadcast mode AV = 2 CL = 0 INPUT_CH 0 OUTPUT_CH 0 ADJACENT INPUT_CH30 OUTPUT_CH31 ALL HOSTILE INPUT_CH0 OUTPUT_CH31 FIGURE 12. CROSSTALK - AV = 2 FN7432.3 July 24, 2006 ISL59532 Typical Performance Curves (Continued) AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 VOP-P = 2V THD 2nd HD AV = 2 RL = 100Ω INPUT_CH 0 OUTPUT_CH 0 FREQUENCY = 1MHz THD 2nd HD 3rd HD 3rd HD FIGURE 13. HARMONIC DISTORTION vs FREQUENCY FIGURE 14. HARMONIC DISTORTION vs VOUT_P-P FIGURE 15. DISABLED OUTPUT IMPEDANCE FIGURE 16. ENABLED OUTPUT IMPEDANCE MUX MODE AV = 1 RL = 100Ω INPUT_CH 31 OUTPUT_CH 31 FALL TIME 2.65ns RISE TIME 2.35ns FIGURE 17. RISE TIME - AV = 1 8 MUX MODE AV = 1 RL = 100Ω INPUT_CH 31 OUTPUT_CH 31 FIGURE 18. FALL TIME - AV = 1 FN7432.3 July 24, 2006 ISL59532 Typical Performance Curves (Continued) MUX MODE AV = 2 RL = 100Ω INPUT_CH 31 OUTPUT_CH 31 FALL TIME 2.35ns RISE TIME 2.19ns FIGURE 19. RISE TIME - AV = 2 MUX MODE AV = 2 RL = 100Ω INPUT_CH 31 OUTPUT_CH 31 FIGURE 20. FALL TIME - AV = 2 MUX MODE AV = 1 RL = 100Ω INPUT_CH 31 OUTPUT_CH 31 SLEW RATE -436V/µs SLEW RATE 448V/µs MUX MODE AV = 1 RL = 100Ω INPUT_CH 31 OUTPUT_CH 31 FIGURE 21. RISING SLEW RATE - AV = 1 FIGURE 22. FALLING SLEW RATE - AV = 1 MUX MODE AV = 2 RL = 100Ω INPUT_CH 31 OUTPUT_CH 31 SLEW RATE -511V/µs SLEW RATE 531V/µs MUX MODE AV = 2 RL = 100Ω INPUT_CH 31 OUTPUT_CH 31 FIGURE 23. RISING SLEW RATE - AV = 2 9 FIGURE 24. FALLING SLEW RATE - AV = 2 FN7432.3 July 24, 2006 ISL59532 Typical Performance Curves (Continued) OUTPUT OUTPUT OVERLAY LOGIC INPUT FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME OVERLAY LOGIC INPUT FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME AV = 2 RL = 150Ω INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV AV = 2 RL = 150Ω INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV FIGURE 27. DIFFERENTIAL GAIN, AV = 2 FIGURE 28. DIFFERENTIAL PHASE, AV = 2 AV = 2 RL = 150Ω INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV AV = 2 RL = 150Ω INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV FIGURE 29. DIFFERENTIAL GAIN, AV = 2 10 FIGURE 30. DIFFERENTIAL PHASE, AV = 2 FN7432.3 July 24, 2006 ISL59532 Typical Performance Curves (Continued) AV = 1 RL = 150Ω INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV AV = 1 RL = 150Ω INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV FIGURE 31. DIFFERENTIAL GAIN, AV = 1 FIGURE 32. DIFFERENTIAL PHASE, AV = 1 AV = 1 RL = 150Ω INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV AV = 1 RL = 150Ω INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV FIGURE 33. DIFFERENTIAL GAIN, AV = 1 FIGURE 34. DIFFERENTIAL GAIN, AV = 1 AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV FIGURE 35. DIFFERENTIAL GAIN, AV = 2 11 FIGURE 36. DIFFERENTIAL PHASE, AV = 2 FN7432.3 July 24, 2006 ISL59532 Typical Performance Curves (Continued) AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV FIGURE 37. DIFFERENTIAL GAIN, AV = 2 FIGURE 38. DIFFERENTIAL PHASE, AV = 2 AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV FIGURE 39. DIFFERENTIAL GAIN, AV = 1 FIGURE 40. DIFFERENTIAL PHASE, AV = 1 AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV FIGURE 41. DIFFERENTIAL GAIN, AV = 1 12 FIGURE 42. DIFFERENTIAL PHASE, AV = 1 FN7432.3 July 24, 2006 ISL59532 Typical Performance Curves (Continued) AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV AV = 2 RL = 150Ω INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, AV = 2 FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, AV = 2 AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV AV = 1 RL = 150Ω INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, AV = 1 13 FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, AV = 1 FN7432.3 July 24, 2006 3dB Bandwidth, MUX Mode, AV = 1, RL = 100Ω [MHz] INPUT CHANNELS 0 0 1 2 3 262 1 5 6 7 8 270 10 11 13 268 18 19 235 20 21 22 23 24 236 25 26 27 28 29 14 247 236 268 278 269 271 277 273 275 274 11 256 272 274 12 255 258 14 271 268 304 299 307 304 198 309 299 300 292 290 286 16 17 274 283 290 278 286 268 18 282 21 296 298 283 272 283 281 252 214 FN7432.3 July 24, 2006 238 294 285 206 30 297 277 199 29 293 216 247 267 28 311 283 269 27 313 336 271 26 309 350 196 264 221 275 268 24 311 288 285 23 326 264 265 266 22 308 277 255 281 299 276 265 19 292 252 230 238 220 280 287 274 ISL59532 264 290 267 272 13 289 259 290 271 292 31 272 268 288 298 30 235 277 267 9 31 17 203 8 25 16 211 7 20 15 214 6 15 14 217 4 OUTPUT CHANNELS 12 214 3 10 9 224 2 5 4 3dB Bandwidth, MUX Mode, AV = 2, RL = 100Ω [MHz] INPUT CHANNELS 0 0 1 2 3 1 5 6 7 8 10 11 13 18 19 20 21 22 23 24 313 25 26 27 28 29 348 15 349 310 348 371 376 360 366 363 351 363 350 11 317 350 337 12 350 340 14 351 327 366 360 366 363 280 366 357 360 348 348 343 16 17 341 337 348 325 338 330 18 351 350 353 356 321 352 353 357 348 318 295 FN7432.3 July 24, 2006 311 352 366 290 30 354 360 288 29 348 334 300 338 28 368 348 350 27 367 377 360 26 364 381 289 354 173 353 361 24 366 354 371 23 372 350 347 22 364 355 344 21 358 345 339 19 352 308 313 314 297 336 345 314 ISL59532 13 349 340 336 348 348 331 370 372 353 31 308 295 346 360 30 320 353 9 31 17 302 8 25 16 294 7 20 15 305 290 6 15 14 290 4 OUTPUT CHANNELS 12 324 291 3 10 9 323 2 5 4 304 3dB Bandwidth, Broadcast Mode, AV = 1, RL = 100Ω [MHz] INPUT CHANNELS 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 196 204 193 175 154 154 158 161 169 157 155 146 125 121 115 109 81 81 79 80 85 85 86 86 83 82 82 77 80 82 85 86 1 185 189 85 87 2 172 3 161 4 165 5 160 6 152 7 141 8 133 9 133 10 132 104 163 104 138 99 128 FN7432.3 July 24, 2006 11 130 125 13 125 14 127 15 125 16 124 17 119 18 116 19 113 20 114 21 112 22 108 23 107 24 106 25 107 26 108 27 107 28 104 29 104 30 105 106 31 107 110 129 124 118 109 109 110 112 113 110 107 106 95 93 90 88 89 88 89 88 85 97 88 88 93 100 102 100 104 99 106 99 110 98 114 99 123 105 80 103 98 98 98 99 101 99 97 95 87 86 84 81 115 106 113 98 102 80 108 95 103 78 102 91 98 81 98 86 98 81 97 89 100 80 96 92 100 79 96 93 88 78 96 97 100 80 96 96 87 82 94 94 86 84 99 95 100 82 97 95 85 88 84 89 92 84 91 85 93 81 88 88 92 90 87 91 90 88 90 94 89 85 91 107 89 82 90 113 89 84 86 113 89 81 91 113 89 82 95 119 87 79 97 123 87 81 99 126 12 85 112 112 114 126 126 128 129 124 118 114 111 120 122 119 118 125 129 131 ISL59532 OUTPUT CHANNELS 0 0 3dB Bandwidth, Broadcast Mode, AV = 2, RL = 100Ω [MHz] INPUT CHANNELS 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 270 277 268 247 213 216 227 244 258 223 208 196 147 142 132 123 85 85 85 86 91 91 92 93 90 88 86 85 89 90 92 94 1 256 261 93 93 2 240 3 219 4 233 5 225 6 204 7 187 8 172 9 171 10 170 117 223 112 189 106 158 FN7432.3 July 24, 2006 11 167 152 13 153 14 155 15 151 16 146 17 138 18 133 19 127 20 129 21 126 22 119 23 118 24 116 25 118 26 120 27 118 28 113 29 114 30 115 116 31 117 121 155 146 134 123 125 126 126 128 123 123 114 103 99 96 94 94 94 93 94 91 105 92 93 99 107 112 106 114 107 117 107 125 108 135 108 142 113 81 112 105 105 106 108 110 107 104 101 93 91 88 85 133 123 130 104 113 82 118 102 114 82 110 98 105 85 106 93 106 84 103 93 109 84 103 99 109 83 103 99 94 83 103 102 109 84 105 102 93 86 102 102 92 89 106 102 109 90 106 103 89 92 90 95 99 88 97 91 101 89 93 94 98 96 93 99 96 94 97 103 94 93 97 119 94 85 96 126 95 89 92 128 95 88 99 128 95 86 105 137 92 83 106 146 92 86 108 152 12 88 127 127 130 153 150 158 163 149 140 133 126 140 146 143 138 155 161 164 ISL59532 OUTPUT CHANNELS 0 0 ISL59532 Block Diagram VS+ VOVERn OVERn 32 OVERLAY INPUT + REF 32 LOGIC CONTROL 2uA Power-on 32 INPUTS SWITCH MATRIX Clamp Enable 32 OUTPUTS + 2uA Av x1, x2 SDI SCLK SLATCH SPI INTERFACE, REGISTER General Description The ISL59532 is a 32x32 integrated video crosspoint switch matrix with input and output buffers and On-Screen Display (OSD) insertion. This device operates from a single +5V supply. Any output can be generated from any of the 32 input video signal sources, and each output can have OSD information inserted through a dedicated, fast 2:1 mux located before the output buffer. There is also a Broadcast mode allowing any one input to be broadcast to all 32 outputs. A DC restore clamp function enables the ISL59532 to AC-couple incoming video. The ISL59532 offers a -3dB signal bandwidth of 300MHz. Differential gain and differential phase of 0.025% and 0.05° respectively, along with 0.1dB flatness out to 50MHz make this ideal for multiplexing composite NTSC and PAL signals. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPI™-compatible, three-wire serial interface. The ISL59532 interface is designed to facilitate both fast initialization and configuration changes. On power-up, all outputs are initialized to the disabled state to avoid output conflicts in the user’s system. Digital Interface The ISL59532 uses a serial interface to program the configuration registers. The serial interface uses three signals (SCLK, SDI, and SLATCH) for programming the ISL59532, while a fourth signal (SDO) enables optional 18 Output Enable Power-on SDO daisy-chaining of multiple devices. The serial clock can run at up to 5MHz (5Mbits/s). Serial Interface The ISL59532 is programmed through a simple serial interface. Data on the SDI (serial data input) pin is shifted into a 16-bit shift register on the rising edge of the SCLK (serial clock) signal. (This is continuously done regardless of the state of the SLATCH signal.) The LSB (bit 0) is loaded first and the MSB (bit 15) is loaded last (see the Serial Timing Diagram). After all 16 bits of data have been loaded into the shift register, the rising edge of SLATCH updates the internal registers. While the ISL59532 has an SDO (Serial Data Out) pin, it does not have a register readback feature. The data on the SDO pin is an exact replica of the incoming data on the SDI pin, delayed by 15.5 SCLKs (an input bit is latched on the rising edge of SLCK, and is output on SDO on the falling edge of SLCK 15.5 SCLKs later). Multiple ISL59532’s can be daisy-chained by connecting the SDO of one to the SDI of the other, with SCLK and SLATCH common to all the daisychained parts. After all the serial data is transmitted (16 bits * n devices = 16*n SCLKs), the rising edge of SLATCH will update the configuration registers of all n devices simultaneously. The Serial Timing Diagram and Serial Timing Parameters table show the timing requirements for the serial interface. FN7432.3 July 24, 2006 ISL59532 Serial Timing Diagram SLATCH SLATCH falling edge timing/placement is a “don’t care.” Serial data is latched only on rising edge of SLATCH. tSL T SCLK tHD tw tSD B0 (LSB) SDI SDO B1 B15 (MSB) B2 B0 B1 B2 B15 (previous) (previous) (previous) (previous) B0 (LSB) B1 B2 SDO = SDI delayed by 15.5 SCLKs to allow daisy-chaining of multiple ISL59532s. SDO changes on the falling edge of SCLK. TABLE 1. SERIAL TIMING PARAMETERS PARAMETER RECOMMENDED OPERATING RANGE DESCRIPTION T ≥200ns SCLK period tW 0.50 * T Clock Pulse Width tSD ≥20ns Data Setup Time tHD ≥20ns Data Hold Time tSL ≥20ns Final SLCK rising edge (latching B15) to SLATCH rising edge Programming Model The ISL59532 is configured by a series of 16 bit serial control words. The three MSBs (B15-13) of each serial word determine the basic command: TABLE 2. COMMAND FORMAT B15 B14 B13 COMMAND NUMBER OF WRITES 0 0 0 INPUT/OUTPUT: Maps input channels to output channels 32 (1 channel per write) 0 0 1 OUTPUT ENABLE: Output enable for individual channels 4 (8 channels per write) 0 1 0 GAIN SET: Gain (x1 or x2) for each channel 4 (8 channels per write) 0 1 1 BROADCAST: Enables broadcast mode and selects the input channel to be broadcast to all output channels 1 1 1 1 CONTROL: Clamp on/off, operational/standby mode, and global output enable/disable 1 Mapping Inputs to Outputs Inputs are mapped to their desired outputs using the input/output control word. Its format is: TABLE 3. INPUT/OUTPUT WORD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 I4 I3 I2 I1 I0 - - - O4 O3 O2 O1 O0 I4:I0 form the 5 bit word indicating the input channel (0 to 31), and O4:O0 determine the output channel which that input channel will map to. One input can be mapped to one or multiple outputs. To fully program the ISL59532, 32 INPUT/OUTPUT words must be transmitted - one for each input channel. 19 FN7432.3 July 24, 2006 ISL59532 Enabling Outputs The output enable control word is used to enable individual outputs. There are 32 channels to configure, so this is accomplished by writing 4 serial words, each controlling a bank of eight outputs at a time. The bank is selected by bits B9 and B8. The output enable control word format is: TABLE 4. OUTPUT ENABLE FORMAT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 0 0 0 0 0 O7 O6 O5 O4 O3 O2 O1 O0 0 0 1 0 0 0 0 1 O15 O14 O13 O12 O11 O10 O9 O8 0 0 1 0 0 0 1 0 O23 O22 O21 O20 O19 O18 O17 O16 0 0 1 0 0 0 1 1 O31 O30 O29 O28 O27 O26 O25 O24 Setting the ON bit = 0 tristates the output. Setting the ON bit = 1 enables the output if the Global Output Enable bit is also set (the individual output enable bits are ANDed with the Global Output Enable bit before they are sent to the output stage). Setting the Gain The gain of each output may be set to x1 or x2 using the Gain Set word. It is in the same format as the output enable control word: TABLE 5. GAIN SET FORMAT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 0 0 0 G7 G6 G5 G4 G3 G2 G1 G0 0 1 0 0 0 0 0 1 G15 G14 G13 G12 G11 G10 G9 G8 0 1 0 0 0 0 1 0 G23 G22 G21 G20 G19 G18 G17 G16 0 1 0 0 0 0 1 1 G31 G30 G29 G28 G27 G26 G25 G24 Set GN = 0 for a gain of x1 or 1 for a gain of x2. Broadcast Mode The Broadcast Mode routes one input to all 32 outputs. The broadcast control word is: TABLE 6. BROADCAST FORMAT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 0 1 1 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 B0 Enable Broadcast 0: Broadcast Mode Disabled 1: Broadcast Mode Enabled I4:I0 form the 5 bit word indicating the input channel (0 to 31) to be sent to all 32 outputs. Set the Enable Broadcast bit (B0) = 1 to enable Broadcast Mode, or to 0 to disable Broadcast Mode. When Broadcast Mode is disabled, the previous channel assignments are restored. Control Word The ISL59532’s power-on reset disables all outputs and places the part in a low-power standby mode. To enable the device, the following control word should be sent: TABLE 7. CONTROL WORD FORMAT B15 B14 B13 B12 B11 B10 1 1 1 0 0 0 B9 B8 B7 B6 B5 B4 B3 B2 0 Clamp 0: Clamp Disabled 1: Clamp Enabled 0 0 0 0 0 0 B1 B0 Global Output Enable Power 0: All outputs tristated 0: Standby 1: Operational 1: Individual Output Enable bits control outputs The Clamp bit enables the input clamp function, forcing the AC-coupled signal’s most negative point to be equal to VREF. Note: The Clamp bit turns the DC-Restore clamp function on or off for all channels - there is no DC-Restore on/off control for individual channels. The DC-Restore function only works with signals with sync tips (composite video). Signals that do not have sync tips (the Chroma/C signal in s-video and the Pb, Pr signals in Component video), will be severely distorted if run through a DC-Restore/clamp function. 20 FN7432.3 July 24, 2006 ISL59532 For this reason, the ISL59532 must be in DC-coupled mode (Clamp Disabled) to be compatible with s-video and component video signals. Bandwidth Considerations Wide frequency response (high bandwidth) in a video system means better video resolution. Four sets of frequency response curves are shown in Figure 47. Depending on the switch configurations, and the routing (the path from the input to the output), bandwidth can vary between 100MHz and 350MHz. A short discussion of the trade-offs — including matrix configuration, output buffer gain selection, channel selection, and loading — follows. Linear Operating Region In addition to bandwidth optimization, to get the best linearity the ISL59532 should be configured to operate in its most linear operating region. Figure 48 shows the differential gain curve. The ISL59532 is a single supply 5V design with its most linear region between 0.1 and 2V. This range is fine for most video signals whose nominal signal amplitude is 1V. The most negative input level (the sync tip for composite video) should be maintained at 0.3V or above for best operation. 2 Mux, Av = 2 Normalized Gain [dB] 0 Mux, Av = 1 Broadcast, Av = 2 -2 Broadcast, Av = 1 -4 -6 -8 -10 1 10 100 Frequency [MHz] 1000 FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES In multiplexer mode, one input typically drives one output channel, while in broadcast mode, one input drives all 32 outputs. As the number of outputs driven increases, the parasitic loading on that input increases. Broadcast Mode is the worst-case, where the capacitance of all 32 channels loads one input, reducing the overall bandwidth. In addition, due to internal device compensation, an output buffer gain of x2 has higher bandwidth than a gain of x1. Therefore, the highest bandwidth configuration is multiplexer mode (with each input mapped to only one output) and an output buffer gain of x2. The relative locations of the input and output channels also have significant impact on the device bandwidth (due to the layout of the ISL59530 silicon). When the input and output channels are further away, there are additional parasitics as a result of the additional routing, resulting in lower bandwidth. FIGURE 48. DIFFERENTIAL GAIN RESPONSE In a DC-coupled application, it is the system designer’s responsibility to ensure that the video signal is always in the optimum range. When AC coupling, the ISL59532’s DC restore function automatically adjusts the DC level so that the most negative portion of the video is always equal to VREF. A discussion of the benefits of the DC-restored system begins by understanding the block diagram of a typical DC-restore circuit (Figure 49). It consists of 4 sections: an AC coupling (DC blocking) capacitor at the input, an opamp, a FET switch, and a current source. In the absence of an input signal, RTERM pulls the input node to ground. The 2µA current source slowly drains the input capacitor of charge, slowly lowering VOUT. However when VOUT goes below VREF, Q1 turns on, sourcing current into the capacitor until VOUT is equal to VREF, at which point Q1 will turn off. So with no VIN signal, the voltage at the noninverting input of the opamp will settle to approximately VREF, with Q1 sourcing the same 2µA as the current source. The bandwidth does not change significantly with resistive loading as shown in the typical performance curves. However several of the curves demonstrate that frequency response is sensitive to capacitance loading. This is most significant when laying out the PCB. If the PCB trace length between the output of the crosspoint switch and the backtermination resistor is not minimized, the additional parasitic capacitance will result in some peaking and eventually a reduction in overall bandwidth. 21 FN7432.3 July 24, 2006 ISL59532 delivering acceptable droop and CIN = 0.001µF producing excessive droop VS VREF + Q1 VOUT VIN RTERM CIN 2uA FIGURE 49. DC RESTORE BLOCK DIAGRAM When a video signal is applied to VIN, the most negative signal will be the sync tip. If the sync tip goes below VREF, Q1 will turn on and quickly source enough current into CIN so that the sync tip is forced to be equal to VREF. After the sync tip, the video jumps up by 300mV or more, so VOUT becomes >> VREF, so Q1 will not turn on for the rest of the video line. However the 2µA current source continues to slowly discharge CIN, so that by the end of the video line, the next sync tip will again be slightly below VREF, forcing Q1 to source some current into C1 to make VOUT = VREF during the sync tip. This is how the video is “DC-restored” after being AC coupled into the ISL59532. The sync tip voltage will be equal to VREF, on the right side of CIN, regardless of the DC level of the video on the left side of CIN. Due to various sources of offset in the actual clamp function, the actual sync tip level is typically about 75mV higher than VREF (for VREF = 0.5V). When the clamp function is disabled in the CONTROL register (Clamp = 0) to allow DC-coupled operation, the ICLAMP current sinks/sources are disabled and the input passes through the DC Restore block unaffected. In this application VREF may be tied to GND. Overlay Operation The ISL59532 features an overlay feature, that allows an external video signal or DC level to be inserted in place of that output channel’s video. When the OVERN signal is taken high, the output signal on the OUTN pin is replaced with the signal on the VOVERN pin. There are several ways the overlay feature can be used. Toggling the OVERN signal at the frame rate or slower will replace the video frame(s) on the OUTN pin with the video supplied on the VOVERN pin. Another option (for OSD displays, for example), is to put a DC level on the VOVERN line and toggle the OVERN signal at the pixel rate to create a monocolor image “overlaid” on channel N’s output signal. Finally, by enabling the OVERN signal for some portion of each line over a certain amount of lines, a picture-in-picture function can be constructed. It’s important to note that the overlay inputs do not have the DC Restore function previously described - the overlay signal is DC coupled into the output. It is the system designer’s responsibility to ensure that the video levels are in the ISL59532’s linear region and matching the output channel’s offset and amplitude. One easy way to do this is to run the video to be overlaid through one of the ISL59532’s unused channels and then into the VOVERN input. The OVERN pins all have weak pulldowns, so if they are unused, they can either be left unconnected or tied to GND. Power Dissipation and Thermal Resistance FIGURE 50. DC RESTORE VIDEO WAVEFORMS It is important to choose the correct value for CIN. Too small a value will generate too much droop, and the image will be visibly darker on the right than on the left. A CIN value that is too large may cause the clamp to fail to converge. The droop rate (dV/dt) is iPULLDOWN/CIN volts/second. In general, the droop voltage should be limited to <1 IRE over a period of one line of video; so for 1 IRE = 7mV, IB = 10µA maximum, and an NTSC waveform we will set CIN > 10µA*60µs/7mV = 0.086µF. Figure 50 shows the result of CIN = 0.1µF 22 With a large number of switches, it is possible to exceed the 150°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the crosspoint switch in a safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX PD MAX = -------------------------------------------Θ JA FN7432.3 July 24, 2006 ISL59532 Where: • TJMAX = Maximum junction temperature = 125°C • TAMAX = Maximum ambient temperature = 85°C • θJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: n V OUTi ∑ ( VS – VOUTi ) × ---------------R Li PD MAX = V S × I SMAX + i=1 Where: • VS = Supply voltage = 5V • ISMAX = Maximum quiescent supply current = 700mA • VOUT = Maximum output voltage of the application = 2V • RLOAD = Load resistance tied to ground = 150 • n = 1 to 32 channels n PD MAX = V S × I SMAX + V OUTi -= ∑ ( VS – VOUTi ) × ---------------R Li 4.8W i=1 The required θJA to dissipate 4.8W is: T JMAX – T AMAX Θ JA = --------------------------------------------- = 8.33 ( °C/W ) PD MAX Table 8 shows θJA thermal resistance results with a Wakefield heatsink and without heatsink and various airflow. At the thermal resistance equation shows, the required thermal resistance depends on the maximum ambient temperature. TABLE 8. θJA THERMAL RESISTANCE [°C/W] Airflow [LFM] 0 250 500 750 No Heatsink 18 14.3 13.0 12.6 Wakefield 658-25AB Heatsink 16.0 7.0 6.0 4.7 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 FN7432.3 July 24, 2006 356 Lead HBGA Package 24 ISL59532 FN7432.3 July 24, 2006