INTERSIL 5962R9663601TEC

CD4049UBT
Data Sheet
July 1999
File Number
CMOS Hex Buffer/Converter
Features
Intersil’s Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
• QML Class T, Per MIL-PRF-38535
The CD4049UBT is an Inverting Hex Buffer and features
logic level conversion using only one supply (voltage (VCC).
The input signal high level (VIH) can exceed the VCC supply
voltage when this device is used for logic level conversions.
This device is intended for use as CMOS to DTL/TTL
converters and can drive directly two DTL/TTL loads. (VCC =
5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.
• High Sink Current for Driving 2 TTL Loads
The CD4049UBT is the designated replacement for the
CD4009UB. Because the CD4049UBT requires only one
power supply, it is preferred over the CD4009UB and
CD4010B and should be used in place of the CD4009UB in
all inverter, current driver, or logic level conversion
applications. In these applications the CD4049UBT is pin
compatible with the CD4009UB, and can be substituted for
this device in existing as well as in new designs. Terminal
No. 16 is not connected internally on the CD4049UBT,
therefore, connection to this terminal is of no consequence
to circuit operation. For applications not requiring high sink
current or voltage conversion, the CD4069UB Hex Inverter is
recommended.
CD4049BT (SBDIP), CDIP2-T16
TOP VIEW
4622.1
• Radiation Performance
- Gamma Dose (γ) 1 x 105 RAD(Si)
- SEP Effective LET >75 MEV-gm/cm2
• Inverting Type
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
Pinouts
VCC
1
16 NC
G=A
2
15 L = F
A
3
14 F
H=B
4
13 NC
B
5
12 K = E
I=C
6
11 E
C
7
10 J = D
VSS
8
9 D
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
CD4049BT (FLATPACK), CDFP4-F16
TOP VIEW
VCC
1
16
NC
G=A
2
15
L=F
A
3
14
F
H=B
4
13
NC
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our website.
B
5
12
K=E
I=C
6
11
E
C
7
10
J=D
www.intersil.com/quality/manuals.asp
VSS
8
9
Detailed Electrical Specifications for the CD4049UBT are
contained in SMD 5962-96636. A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
D
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(oC)
5962R9663601TEC
CD4049UBDTR
-55 to 125
5962R9663601TXC
CD4049UBKTR
-55 to 125
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
CD4049UBT
Functional Diagram
A
B
C
D
VCC
VSS
NC = 13
NC = 16
3
2
5
4
7
6
9
10
11
12
14
15
G=A
H=B
I=C
J=D
1
8
E
F
K=E
L=F
Schematic
VCC
P
R
IN
OUT
N
VSS
SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS
2
CD4049UBT
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
(1448µm x 1880µm x 533µm ±25.4µm)
Type: Phosphorus Doped Silox (SiO2)
57 x 74 x 21mils ±1mil
Thickness: 13.0kÅ ±2.6kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm2
Type: Al
Thickness: 12.5kÅ ±1.5kÅ
TRANSISTOR COUNT:
SUBSTRATE POTENTIAL:
12
Leave Floating or Tie to VCC
PROCESS:
Bond Pad #1 (VCC) First
Bulk CMOS
BACKSIDE FINISH:
Silicon
Metallization Mask Layout
CD4049UBT
74mils
57mils
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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3
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