CD4536BMS CMOS Programmable Timer December 1992 Features Description • High Voltage Type (20V Rating) 0 • 24 Flip-Flop Stage - Counts from 2 to 2 24 • Last 16 Stages Selectable by BCD Select Code • Bypass Input Allows Bypassing First 8 Stages • On-Chip RC Oscillator Provision • Clock Inhibit Input • Schmitt Trigger in clock Line Permits Operation with Very Long Rise and Fall Times • On-Chip Monostable Output Provision • Typical fCL = 3MHz at VDD = 10V • Test Mode Allows Fast Test Sequence • Set and Reset Inputs • Capable of Driving Two Low Power TTL Loads, One Lower Power Schottky Load, or Two HTL Loads Over the Rated Temperature Range • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized, Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” CD4536BMS is a programmable timer consisting of 24 ripple binary counter stages. The salient feature of this device is its flexibility. The device can count from 1 to 224 or the first 8 stages can be bypassed to allow an output, selectable by a 4-bit code, from any one of the remaining 16 stages. It can be driven by an external clock or an RC oscillator that can be constructed using on-chip components. Input IN1 serves as either the external clock input or the input to the on-chip RC oscillator. OUT1 and OUT2 are connection terminals for the external RC components. In addition, an on-chip monostable circuit is provided to allow a variable pulse width output. Various timing functions can be achieved using combinations of these capabilities. A logic 1 on the 8-BYPASS input enables a bypass of the first 8 stages and makes stage 9 the first counter stage of the last 16 stages. Selection of 1 of 16 outputs is accomplished by the decoder and the BCD inputs A, B, C and D. MONO IN is the timing input for the on-chip monostable oscillator. Grounding of the MONO IN terminal through a resistor of 10kΩ or higher, disables the one-shot circuit and connects the decoder directly to the DECODE OUT terminal. A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the one-shot circuit and controls its pulse width. A fast test mode is enabled by a logic 1 on 8-BYPASS, SET, and RESET. This mode divides the 24-stage counter into three 8-stage sections to facilitate a fast test sequence. The CD4536BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6W Functional Diagram Pinout CD4536BMS TOP VIEW SET 1 CLOCK INHIBIT OSC INHIBIT 16 VDD 8-BYPASS RESET 2 15 MONO IN IN 1 3 14 OSC INHIBIT OUT 1 4 13 DECODE OUT 6 A 5 12 D 8-BYPASS 6 11 C 7 10 B OUT 2 CLOCK INHIBIT VSS 8 IN 1 BINARY SELECT B C D BINARY SELECT SET RESET 9 A MONO IN CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1236 9 10 11 12 1 2 15 14 7 RS 3 4 OUT 1 RT 5 OUT 2 13 DECODE OUT VSS = 8 VDD = 16 File Number 3345 Specifications CD4536BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125oC - 1000 µA 3 -55oC - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA Output Current (Sink) Output Current (Source) IOL15 IOH5A VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH15 VNTH VPTH F VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1237 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4536BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) Propagation Delay Clock to Q1 8-Bypass High TPHL1 TPLH1 VDD = 5V, VIN = VDD or GND Propagation Delay Clock to Q1 8-Bypass Low TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Clock to Q16 TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND Propagation Delay Reset to QN TPHL4 VDD = 5V, VIN = VDD or GND Transition Time Maximum Clock Input Frequency TTHL TTLH GROUP A SUBGROUPS TEMPERATURE FCL MAX UNITS 9 +25oC - 2000 ns 10, 11 +125oC, -55oC - 2700 ns 9 +25oC - 5000 ns - 6750 ns 10, 11 VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND LIMITS MIN +125oC, -55oC 9 +25oC - 8000 ns 10, 11 +125oC, -55oC - 10800 ns 9 +25oC - 6000 ns 10, 11 +125oC, -55oC - 8100 ns 9 +25oC - 200 ns 10, 11 +125oC, -55oC - 270 ns o 9 +25 C .5 - MHz 10, 11 +125oC, -55oC .37 - MHz MAX UNITS NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND 1, 2 1, 2 TEMPERATURE -55 C, +25 C - 5 µA +125oC - 150 µA - 10 µA o o o o -55 C, +25 C +125 C - 300 µA -55oC, +25oC - 10 µA +125oC - 600 µA o VDD = 15V, VIN = VDD or GND 1, 2 MIN o o Output Voltage VOL VDD = 5V, No Load 1, 2 +25 C, +125 C, 55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, 55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 7-1238 1, 2 +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA Specifications CD4536BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH15 CONDITIONS NOTES VDD =15V, VOUT = 13.5V TEMPERATURE MIN MAX UNITS - -2.4 mA -55 C - -4.2 mA +25oC, +125oC, -55oC - 3 V +7 - V o 1, 2 +125 C o Input Voltage Low Input Voltage High Propagation Delay Clock to Q1 8-Bypass High Propagation Delay Clock to Q1 8-Bypass Low VIL VIH TPHL1 TPLH1 TPHL2 TPLH2 Propagation Delay Clock to Q16 TPHL3 TPLH3 Propagation Delay Qn to Qn+1 TPHL TPLH Propagation Delay Set to Qn Propagation Delay Reset to Qn Transition Time TPLH TPHL4 TTHL TTLH Maximum Clock Input Frequency. Unlimited Input Rise or Fall Time FCL Minimum Clock Pulse Width TW Minimum Set Pulse Width Minimum Reset Pulse Width Minimum Set Recovery Time TW TW TREM VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V TREM CIN o o +25 C, +125 C, -55 C o VDD = 10V 1, 2, 3 +25 C - 1000 ns 1, 2, 3 +25oC - 700 ns o VDD = 10V 1, 2, 3 +25 C - 1600 ns VDD = 15V 1, 2, 3 +25oC - 1200 ns o - 3000 ns o ns VDD = 10V 1, 2, 3 +25 C VDD = 15V 1, 2, 3 +25 C - 2000 VDD = 5V 1, 2, 3 +25oC - 300 VDD = 10V 1, 2, 3 +25oC - 150 o VDD = 15V 1, 2, 3 +25 C - 100 VDD = 5V 1, 2, 3 +25oC - 600 o VDD = 10V 1, 2, 3 +25 C - 250 VDD = 15V 1, 2, 3 +25oC - 160 o - 2000 ns o VDD = 10V 1, 2, 3 +25 C VDD = 15V 1, 2, 3 +25 C - 1500 ns VDD = 10V 1, 2, 3 +25oC - 100 ns o - 80 ns o VDD = 15V 1, 2, 3 +25 C VDD = 10V 1, 2, 3 +25 C 1.5 - MHz VDD = 15V 1, 2, 3 +25oC 2.5 - MHz VDD = 5V 1, 2, 3 +25oC - 400 ns o VDD = 10V 1, 2, 3 +25 C - 150 ns VDD = 15V 1, 2, 3 +25oC - 100 ns o - 400 ns o VDD = 5V 1, 2, 3 +25 C VDD = 10V 1, 2, 3 +25 C - 200 ns VDD = 15V 1, 2, 3 +25oC - 120 ns 1, 2, 3 +25oC - 6 µs VDD = 10V 1, 2, 3 +25oC - 2 µs VDD = 15V 1, 2, 3 +25oC - 1.5 µs VDD = 5V 1, 2, 3 +25oC - 5 µs VDD = 10V 1, 2, 3 +25oC - 2 µs 1, 2, 3 +25oC - 1.6 µs VDD = 5V 1, 2, 3 +25oC - 7 µs VDD = 10V 1, 2, 3 +25oC - 3 µs 1, 2, 3 +25oC - 2 µs 1, 2 +25oC - 7.5 pF VDD = 5V VDD = 15V Input Capacitance 1, 2 o VDD = 15V VDD = 15V Minimum Reset Recovery Time 1, 2 Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 7-1239 Specifications CD4536BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Supply Current N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 7-1240 Specifications CD4536BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 4, 5, 13 1-3, 6-12, 14, 15 16 Static Burn-In 2 Note 1 4, 5, 13 8 1-3, 6, 7, 9-12, 14-16 Dynamic BurnIn Note 1 - 1, 2, 6-8, 14, 15 9-12, 16 4, 5, 13 8 1-3, 6, 7, 9-12, 14-16 Irradiation Note 2 9V ± -0.5V 50kHz 4, 5, 13 3 25kHz NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram 6* 8-BYPASS VDD RESET * SET * 2 VSS 1 *INPUTS PROTECTED BY CMOS PROTECTION NETWORK S CLOCK * INH 7 Q CLDIS CL R p n A B FF25 p n C D E F R Q CLEN CL Q R Q φ CL Q φ FF1 FF2 D R Q φ Q φ FF3 R Q Q FF8 CL OSC * INH 14 RS RT IN 1 * 3 CT OUT 1 * 4 OUT 2 * 5 NOTE: f ≈ 1 3RT CT , RS ≈ (5 → 10) x RT G FIGURE 1. 7-1241 CD4536BMS Logic Diagram (Continued) A p n B p n C D E F R R R Q CLDIS CL Q Q φ CL Q φ FF9 FF10 FF11 D Q φ Q φ R Q φ Q φ FF16 R Q φ Q φ FF17 R Q φ Q φ FF18 R Q Q FF24 1 OF 16 DECODER (TRANSMISSION-GATE TREE LOGIC) VSS N P DECODE 13 OUT 9 A * 10 B * 11 C * 12 D * 15 * MONO IN G DETAIL FOR DETAIL FOR FF3-8, 11-16, 17-24 FF1, FF2, FF10, FF9, FF25 CLEN (CLDIS FOR FF9 AND FF25) φ φ VDD Q Q Q Q R φ p e n p P P Q φ φ f n c n φ n φ p P φ N P φ φ N P φ N p n CL R CLEN φ Q CL R N p d n Q FF1 φ R R Q φ a φ φ φ N N φ e R c d n Q N R φ b p n S p b a f P R p D N φ D Q R CLDIS Q CL Q CL FF2, 10 Q R CLDIS Q CL S FF9 Q FF25 FF1: AS SHOWN EXCEPT Q NOT BROUGHT OUT FF9: SAME AS FF1 EXCEPT Q IS BROUGHT OUT AND Q, Q GO TO TGf AND TGe RESP. VSS FF2, FF10: DELETE TGe, TGf, AND INVf; FEED Q TO D; DELETE CLEN, CLDIS FF25: INVa AND INVd BECOME 2-INPUT NAND GATES, WITH ADDED INPUTS S; FEED Q TO TGf VSS TO TGe PREVIOUS Q INPUT; DELETE Q OUTPUT FIGURE 1. (Continued) 7-1242 CD4536BMS TRUTH TABLE IN SET RESET CLOCK INH OSC INH 0 0 0 0 No Change 0 0 0 0 Advance to Next State X 1 0 0 0 0 1 1 X 0 1 0 0 0 1 0 X 0 0 1 0 0 0 0 0 X 1 0 0 0 0 = Low Level 1 = High Level OUT1 OUT2 DECODE OUT No Change 0 1 No Change Advance to Next State X = Don’t Care AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 10V 7.5 5.0 2.5 5V 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -5 -15 -20 -25 -15V 10.0 FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -10 -10V GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -30 FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC 15.0 0 FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC 0 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -15V -10 -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 7-1243 CD4536BMS (Continued) 2 AMBIENT TEMPERATURE (TA) = +25oC 1.5 SUPPLY VOLTAGE (VDD) = 5V 1 10V 0.5 15V 0 0 20 40 60 80 4 PROPAGATION DELAY TIME (tPHL, tPLH) (µs) PROPAGATION DELAY TIME (tPHL, tPLH) (µs) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 3 SUPPLY VOLTAGE (VDD) = 5V 2 10V 1 15V 0 100 0 20 2 AMBIENT TEMPERATURE (TA) = +25oC 1.5 SUPPLY VOLTAGE (VDD) = 5V 1 10V 15V 0 0 20 40 60 80 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 15V 50 0 0 20 FREQUENCY DEVIATION (∆f) (%) OSCILLATOR FREQUENCY (F) (KHz) 103 8 AMBIENT TEMPERATURE (TA) = EXTERNAL RESISTANCE (RE) = 56kΩ EXTERNAL CAPACITANCE (CX) = 1000pF RS = 0, f = 7900Hz 20 10 RS = 120kΩ, f = 5900Hz 0 102 8 6 4 2 9 11 13 8 10 12 SUPPLY VOLTAGE (VDD) (V) 100 f vs Rtc CT = 1000pF RS = 2Rtc 10 8 6 4 2 f vs CT Rtc = 56kΩ RS = 120kΩ 08 6 4 2 10-1 8 6 4 2 102 7 80 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 10V 1 f= 3Rtc CT 6 4 2 10-2 -10 6 60 FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (QN TO QN + 1) 40 -20 5 40 LOAD CAPACITANCE (CL) (pF) +25oC 30 100 AMBIENT TEMPERATURE (TA) = +25oC 100 FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q16, 8-BYPASS HIGH) 50 80 200 LOAD CAPACITANCE (CL) (pF) 60 60 FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q1, 8-BYPASS LOW) PROPAGATION DELAY TIME (tPHL, tPLH) (µs) PROPAGATION DELAY TIME (tPHL, tPLH) (µs) FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q1, 8-BYPASS HIGH) 0.5 40 LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF) 14 FIGURE 10. TYPICAL RC OSCILLATOR FREQUENCY DEVIATION AS A FUNCTION OF SUPPLY VOLTAGE 15 1 2 4 68 2 4 68 2 4 68 2 103 104 105 EXTERNAL CAPACITANCE (CT) (pF) 103 10 102 EXTERNAL RESISTANCE (Rtc) (kΩ) 4 68 106 104 FIGURE 11. TYPICAL RC OSCILLATOR FREQUENCY DEVIATION AS A FUNCTION OF TIME CONSTANT RESISTANCE AND CAPACITANCE 7-1244 CD4536BMS Typical Performance Characteristics (Continued) 10.0 Rtc = 56kΩ RS = 0 CX = 1000pF 7.5 5.0 FREQUENCY DEVIATION (∆f) (%) FREQUENCY DEVIATION (∆f) (%) 10.0 SUPPLY VOLTAGE (VDD) = 5V 2.5 10V 15V 15V 0 10V 5V -2.5 -5.0 -7.5 -10.0 0 -50 50 100 Rtc = 56kΩ RE = 120kΩ CX = 1000pF 7.5 5.0 SUPPLY VOLTAGE (VDD) = 5V 2.5 10V 15V 0 -2.5 5V -5.0 -7.5 -10.0 150 -50 0 o FIGURE 12. TYPICAL RC OSCILLATOR FREQUENCY DEVIATION AS A FUNCTION OF AMBIENT TEMPERATURE (RS = 0) 2 2 102 8 6 4 RX = 1mΩ 10 8 6 4 2 18 100K 50K 2 10K 6 4 0.1 2 2 4 68 2 4 68 2 4 68 2 4 68 105 PULSE WIDTH (µs) 6 4 2 10 8 RX = 1mΩ 6 4 2 100kΩ 50kΩ 2 4 68 2 4 68 2 4 68 2 4 68 10 102 103 104 EXTERNAL CAPACITANCE (CX) (pF) 2 4 68 105 200 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 10kΩ 2 1 10kΩ 2 AMBIENT TEMPERATURE (TA) = +25oC 2 0.1 100kΩ 50kΩ FIGURE 15. TYPICAL PULSE WIDTH AS A FUNCTION OF EXTERNAL CAPACITANCE (VDD = 10V) 102 8 6 4 2 1 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 18 6 4 0.1 TRANSITION TIME (tTHL, tTLH) (ns) 6 4 10 8 RX = 1mΩ 2 FIGURE 14. TYPICAL PULSE WIDTH AS A FUNCTION OF EXTERNAL CAPACITANCE (VDD = 5V) 103 8 2 6 4 10 102 103 104 EXTERNAL CAPACITANCE (CX) (pF) 1 6 4 18 4 68 150 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 10V 6 4 PULSE WIDTH (µs) PULSE WIDTH (µs) 103 8 102 8 2 100 FIGURE 13. TYPICAL RC OSCILLATOR FREQUENCY DEVIATION AS A FUNCTION OF AMBIENT TEMPERATURE (RS = 120kΩ) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 6 4 50 AMBIENT TEMPERATURE (TA) oC AMBIENT TEMPERATURE (TA) C 103 8 15V 10V 4 68 2 4 68 2 4 68 2 4 68 10 102 103 104 EXTERNAL CAPACITANCE (CX) (pF) 2 0 0 4 68 FIGURE 16. TYPICAL PULSE WIDTH AS A FUNCTION OF EXTERNAL CAPACITANCE (VDD = 15V) 105 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 17. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 7-1245 CD4536BMS Typical Performance Characteristics 105 8 POWER DISSIPATION (PD) (µW) 6 4 (Continued) AMBIENT TEMPERATURE (TA) = +25oC 2 104 8 SUPPLY VOLTAGE (VDD) = 15V 6 4 2 10V 103 8 5V 6 4 2 102 8 6 4 CL = 50pF CL = 15pF 2 10 2 4 6 8 2 4 6 8 2 4 6 8 1 10 102 PULSE INPUT FREQUENCY (kHz) 0.1 2 4 6 8 103 FIGURE 18. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT PULSE FREQUENCY Applications 11 12 1 2 6 15 >10K 14 A B CX OUT 1 4 C 5 D SET 3 RESET OUT 2 12 8-BYPASS 11 C INH 13 MONO IN OSC INH DECODE OUT IN 1 8 VSS 1 RX 2 +TR -TR R +TR -TR R 15 14 16 R Q1 CD4098BMS 10 VDD VDD 16 9 CL CODE OUT (CL ÷ 8) Q1 OUTPUT CD4098BMS 8 FIGURE 19. APPLICATION SHOWING USE OF CD4098BMS AND CD4536BMS TO GET DECODE PULSE 8 CLOCK PULSES AFTER RESET PULSE VDD VDD A A B B OUT 1 C D D SET SET RESET RESET OUT 2 8-BYPASS CLOCK OUT 2 8-BYPASS R C INH ≥10kΩ OUT 1 C MONO IN C INH t MONO IN OSC INH DECODE OUT IN 1 CL t CLOCK VSS OSC INH DECODE OUT IN 1 VSS FIGURE 20. TIME INTERVAL CONFIGURATION USING EXTERNAL CLOCK; SET AND CLOCK INHIBIT FUNCTIONS FIGURE 21. TIME INTERVAL CONFIGURATION USING EXTERNAL CLOCK; RESET AND OUTPUT MONOSTABLE TO ACHIEVE A PULSE OUTPUT 7-1246 CD4536BMS Applications (Continued) VDD A C B RS 3µs MIN R OUT 1 C Rtc D CLOCK SET RESET START DCBA 0000 (÷2) 0001 (÷4) OUT 2 8-BYPASS 0010 (÷8) C INH MONO IN OSC INH DECODE OUT IN 1 1 Rtc C f≅ 2.3 RS ≥ 2Rtc f IN Hz, R IN Ω, C IN F t VSS NOTE: SHADED PULSE REPRESENTS DECODE OUTPUT IN MONOSTABLE MODE. IF AN OUTPUT PULSE IS REQUIRED 1 FULL COUNTDOWN AFTER REMOVAL OF RESET PULSE, SEE FIGURE 19 FOR USE OF CD4098BMS FIGURE 22. TIME INTERVAL CONFIGURATION USING ONCHIP RC OSCILLATOR AND RESET INPUT TO INITIATE TIME INTERVAL FIGURE 23. TIMING DIAGRAM DECODE OUT SELECTION TABLE NUMBER OF STAGES IN DIVIDER CHAIN D C B A 8-BYPASS = 0 8-BYPASS = 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 9 10 11 12 1 2 3 4 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 13 14 15 16 5 6 7 8 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 17 18 19 20 9 10 11 12 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 21 22 23 24 13 14 15 16 0 = Low Level 1 = High Level Functional Block Diagram SET RESET OUT 1 OUT 2 6 2 OSC 14 INHIBIT IN 8-BYPASS 1 3 OSC INHIBIT LOGIC CLOCK INHIBIT LOGIC STAGES 1-8 STAGES 9-24 8-BYPASS LOGIC Q9 - - - Q24 4 5 A BINARY SELECT CLOCK 7 INHIBIT B C D VSS = 8 VDD = 16 MONO IN FIGURE 24. 7-1247 9 13 DECODE OUT 10 11 12 15 DECODER CD4536BMS FUNCTIONAL TEST SEQUENCE INPUTS OUTPUTS COMMENTS IN 1 SET RESET 8-BYPASS DECODE OUT Q1 THRU 24 1 0 1 1 0 ALL 24 STEPS ARE IN RESET MODE 1 1 1 1 0 Counter is in three 8-stage section in parallel mode 0 1 1 1 0 First “1” to “0” transition of clock 1 0 - 255 “1” to “0” transitions are clocked in the counter 1 1 1 0 1 1 1 1 The 255 “1” to “0” transition 0 0 0 0 1 Counter converted back to 24 stages in series mode. Set and Reset must be connected together and simultaneously go from “1” to “0” 1 0 0 0 1 In1 Switches to a “1” 0 0 0 0 0 Counter Ripples from an all “1” state to an all “0” state Functional Test Sequence Test Function has been included for the reduction of test time required to exercise all 24 counter stages. This test function divides the counter into three 8-stage sections and 255 counts are loaded in each of the 8-stage sections in par- allel. All flip-flops are now at a “1”. The counter is now returned to the normal 24 steps in series configuration. One more pulse is entered into In1 which will cause the counter to ripple from an all “1” state to an all “0” state. Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). L SI R TE METALLIZATION: IN PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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