16/32-Bit Architecture XC2385A, XC2387A 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line Data Sheet V2.12 2014-06 Microcontrollers Edition 2014-06 Published by Infineon Technologies AG 81726 Munich, Germany © 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). 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If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 16/32-Bit Architecture XC2385A, XC2387A 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line Data Sheet V2.12 2014-06 Microcontrollers XC2385A, XC2387A XC2000 Family / Base Line XC238xA Revision History: V2.12, 2014-06 Previous Version(s): V2.1, 2011-07 V2.0, 2009-03 V1.3, 2008-11 V1.2, 2008-09 V1.1, 2008-06 Preliminary V1.0, 2008-06 (Intermediate version) Page Subjects (major changes since last revisions) V2.0 to V2.1 49 ID registers added 96 ADC capacitances corrected (typ. vs. max.) 100 Conditions relaxed for ΔfINT Range for fWU adapted according to PCN 2010-013-A Added startup time from power-on tSPO 140 Quality declarations added V2.1 to V2.12 9 Basic device types replaced 10 Special device types added 137 Package type added Trademarks C166™, TriCore™, and DAVE™ are trademarks of Infineon Technologies AG. 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Please send your proposal (including a reference to this document) to: [email protected] Data Sheet V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Table of Contents Table of Contents 1 1.1 1.2 1.3 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Basic Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Special Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 2.1 2.2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Checker Module (MCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capture/Compare Unit (CAPCOM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . . MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 4.2.3 4.3 4.4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Absolut Maximum Rating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Pad Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 89 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Data Sheet 5 50 51 54 55 57 57 58 59 60 63 65 69 71 72 74 75 76 76 77 78 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Table of Contents 4.5 4.6 4.6.1 4.6.2 4.6.2.1 4.6.2.2 4.6.2.3 4.6.3 4.6.4 4.6.5 4.6.5.1 4.6.5.2 4.6.6 4.6.7 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wakeup Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting and Changing the Operating Frequency . . . . . . . . . . . . . External Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Cycle Control with the READY Input . . . . . . . . . . . . . . . . . . . . External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 105 105 106 107 110 110 111 113 116 122 124 127 131 5 5.1 5.2 5.3 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 137 139 140 Data Sheet 6 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Summary of Features 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC238xA (XC2000 Family) 1 Summary of Features For a quick overview and easy reference, the features of the XC238xA are summarized here. • • • • • • • High-performance CPU with five-stage pipeline and MPU – 12.5 ns instruction cycle at 80 MHz CPU clock (single-cycle execution) – One-cycle 32-bit addition and subtraction with 40-bit result – One-cycle multiplication (16 × 16 bit) – Background division (32 / 16 bit) in 21 cycles – One-cycle multiply-and-accumulate (MAC) instructions – Enhanced Boolean bit manipulation facilities – Zero-cycle jump execution – Additional instructions to support HLL and operating systems – Register-based design with multiple variable register banks – Fast context switching support with two additional local register banks – 16 Mbytes total linear address space for code and data – 1024 Bytes on-chip special function register area (C166 Family compatible) – Integrated Memory Protection Unit (MPU) Interrupt system with 16 priority levels for up to 96 sources – Selectable external inputs for interrupt generation and wake-up – Fastest sample-rate 12.5 ns Eight-channel interrupt-driven single-cycle data transfer with Peripheral Event Controller (PEC), 24-bit pointers cover total address space Clock generation from internal or external clock sources, using on-chip PLL or prescaler Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip Memory Areas On-chip memory modules – 8 Kbytes on-chip stand-by RAM (SBRAM) – 2 Kbytes on-chip dual-port RAM (DPRAM) – Up to 16 Kbytes on-chip data SRAM (DSRAM) – Up to 32 Kbytes on-chip program/data SRAM (PSRAM) – Up to 832 Kbytes on-chip program memory (Flash memory) – Memory content protection through Error Correction Code (ECC) On-Chip Peripheral Modules – Multi-functional general purpose timer unit with 5 timers – 16-channel general purpose capture/compare unit (CAPCOM2) – Up to 4 capture/compare units for flexible PWM signal generation (CCU6x) Data Sheet 7 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Summary of Features • • • • • • • • – Two Synchronizable A/D Converters with a total of up to 24 channels, 10-bit resolution, conversion time below 1 μs, optional data preprocessing (data reduction, range check), broken wire detection – Up to 6 serial interface channels to be used as UART, LIN, high-speed synchronous channel (SPI), IIC bus interface (10-bit addressing, 400 kbit/s), IIS interface – On-chip MultiCAN interface (Rev. 2.0B active) with up to 64 message objects (Full CAN/Basic CAN) on up to 3 CAN nodes and gateway functionality – On-chip system timer and on-chip real time clock Up to 12 Mbytes external address space for code and data – Programmable external bus characteristics for different address ranges – Multiplexed or demultiplexed external address/data buses – Selectable address bus width – 16-bit or 8-bit data bus width – Four programmable chip-select signals – Hold- and hold-acknowledge bus arbitration support Single power supply from 3.0 V to 5.5 V Programmable watchdog timer and oscillator watchdog Up to 119 general purpose I/O lines On-chip bootstrap loaders Supported by a full range of development tools including C compilers, macroassembler packages, emulators, evaluation boards, HLL debuggers, simulators, logic analyzer disassemblers, programming boards On-chip debug support via Device Access Port (DAP) or JTAG interface 144-pin Green LQFP package, 0.5 mm (19.7 mil) pitch Data Sheet 8 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Summary of Features Ordering Information The ordering code for an Infineon microcontroller provides an exact reference to a specific product. This ordering code identifies: • • • the function set of the corresponding product type the temperature range: – SAF-…: -40°C to 85°C – SAH-…: -40°C to 110°C – SAK-…: -40°C to 125°C the package and the type of delivery. For ordering codes for the XC238xA please contact your sales representative or local distributor. This document describes several derivatives of the XC238xA group: Basic Device Types are readily available and Special Device Types are only available on request. As this document refers to all of these derivatives, some descriptions may not apply to a specific product, in particular to the special device types. For simplicity the term XC238xA is used for all derivatives throughout this document. 1.1 Basic Device Types Basic device types are available and can be ordered through Infineon’s direct and/or distribution channels. Table 1 Synopsis of XC238xA Basic Device Types 1) Derivative Flash Memory2) XC2387A104FxxLR 832 Kbytes 32 Kbytes 16 Kbytes Capt./Comp. ADC4) Interfaces4) Modules Chan. PSRAM DSRAM3) CC2 16 + 8 3 CAN Nodes, CCU60/1/2/3 6 Serial Chan. 1) xx is a placeholder for the available speed grade (in MHz). 2) Specific information about the on-chip Flash memory in Table 3. 3) All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM. 4) Specific information about the available channels in Table 5. Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1). Data Sheet 9 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Summary of Features 1.2 Special Device Types Special device types are only available for high-volume applications on request. Table 2 Synopsis of XC238xA Special Device Types Derivative1) Flash Memory2) XC2387A104FxxL 832 Kbytes 32 Kbytes 16 Kbytes CC2 16 + 8 3 CAN Nodes, CCU60/1/2/3 6 Serial Chan. XC2387A72FxxL 576 Kbytes 32/16 Kbytes 16 Kbytes CC2 16 + 8 3 CAN Nodes, CCU60/1/2/3 6 Serial Chan. XC2387A56FxxL 448 Kbytes 32/16 Kbytes 16 Kbytes CC2 16 + 8 3 CAN Nodes, CCU60/1/2/3 6 Serial Chan. XC2385A104FxxL 832 Kbytes 32 Kbytes 16 Kbytes CC2 CCU60/1 16 + 8 2 CAN Nodes, 4 Serial Chan. XC2385A72FxxL 576 Kbytes 32/16 Kbytes 16 Kbytes CC2 CCU60/1 16 + 8 2 CAN Nodes, 4 Serial Chan. XC2385A56FxxL 448 Kbytes 32/16 Kbytes 16 Kbytes CC2 CCU60/1 16 + 8 2 CAN Nodes, 4 Serial Chan. PSRAM DSRAM3) Capt./Comp. ADC4) Interfaces4) Modules Chan. 1) xx is a placeholder for the available speed grade (in MHz). 2) Specific information about the on-chip Flash memory in Table 3. 3) All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM. 4) Specific information about the available channels in Table 5. Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1). Data Sheet 10 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Summary of Features 1.3 Definition of Feature Variants The XC238xA types are offered with several Flash memory sizes. Table 3 describes the location of the available memory areas for each Flash memory size. Table 3 Flash Memory Allocation Total Flash Size Flash Area A1) Flash Area B Flash Area C 832 Kbytes C0’0000H … C0’EFFFH C1’0000H … CC’FFFFH n.a. 576 Kbytes C0’0000H … C0’EFFFH C1’0000H … C7’FFFFH CC’0000H … CC’FFFFH 448 Kbytes C0’0000H … C0’EFFFH C1’0000H … C5’FFFFH CC’0000H … CC’FFFFH 1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH). Table 4 Flash Memory Module Allocation (in Kbytes) Total Flash Size Flash 01) Flash 1 Flash 2 Flash 3 832 Kbytes 256 256 256 64 576 Kbytes 256 256 --- 64 448 Kbytes 256 128 --- 64 1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH). The XC238xA types are offered with different interface options. Table 5 lists the available channels for each option. Table 5 Interface Channel Association Total Number Available Channels 16 ADC0 channels CH0 … CH15 8 ADC1 channels CH0 … CH7 (overlay: CH8 … CH11) 3 CAN nodes CAN0, CAN1, CAN2 64 message objects 2 CAN nodes CAN0, CAN1 64 message objects 6 serial channels U0C0, U0C1, U1C0, U1C1, U2C0, U2C1 4 serial channels U0C0, U0C1, U1C0, U1C1 Data Sheet 11 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Summary of Features The XC238xA types are offered with several SRAM memory sizes. Figure 1 shows the allocation rules for PSRAM and DSRAM. Note that the rules differ: • • PSRAM allocation starts from the lower address DSRAM allocation starts from the higher address For example 8 Kbytes of PSRAM will be allocated at E0’0000h-E0’1FFFh and 8 Kbytes of DSRAM will be at 00’C000h-00’DFFFh. E7'FFFFh (EF'FFFFh) 00'DFFFh Reserved for PSRAM Available DSRAM Available PSRAM Reserved for DSRAM E0'0000h (E8'0000h) 00'8000h MC_XC_SRAM_ALLOCATION Figure 1 Data Sheet SRAM Allocation 12 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information 2 General Device Information The XC238xA series (16/32-Bit Single-Chip Microcontroller with 32-Bit Performance) is a part of the Infineon XC2000 Family of full-feature single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 80 million instructions per second) with extended peripheral functionality and enhanced IO capabilities. Optimized peripherals can be adapted flexibly to meet the application requirements. These derivatives utilize clock generation via PLL and internal or external clock sources. On-chip memory modules include program Flash, program RAM, and data RAM. VAREFVAGND VDDIM VDDI1 VDDP VSS (2) (1) (1) (3) (9) (4) Port 0 8 bit XTAL1 XTAL2 Port 1 8 bit ESR0 ESR1 ESR2 Port 2 14 bit Port 11 6 bit Port 3 8 bit Port 10 16 bit Port 4 8 bit Port 9 8 bit Port 6 4 bit Port 15 8 bit Port 7 5 bit Port 5 16 bit Port 8 7 bit PORST TRST DAP/JTAG Debug 2 bit 2 / 4 bit via Port Pins TESTM MC_XY_ LOGSYMB 144 Figure 2 Data Sheet XC238xA Logic Symbol 13 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information 2.1 Pin Configuration and Definition 1 44 1 43 1 42 1 41 1 40 1 39 1 38 1 37 1 36 1 35 1 34 1 33 1 32 1 31 1 30 1 29 1 28 1 27 1 26 1 25 1 24 1 23 1 22 1 21 1 20 1 19 1 18 1 17 1 16 1 15 1 14 1 13 1 12 1 11 1 10 1 09 V DDPB P8.5 P8.6 ESR0 ESR2 ES R1 POR ST XTAL 1 XTAL2 P1 .7 P9.7 P1.6 P9.6 P1.5 P10.15 P1.4 P10.14 V DDI1 P9 .5 P9 .4 P1.3 P10.13 P9.3 P10.12 P1.2 P9.2 P10.11 P10.10 P1.1 P10.9 P9.1 P10.8 P9.0 P1.0 V DDPB V SS The pins of the XC238xA are described in detail in Table 6, which includes all alternate functions. For further explanations please refer to the footnotes at the end of the table. The following figure summarizes all pins, showing their locations on the four sides of the package. VSS VDDPB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP-144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDDPB P3.7 P0.7 P10.7 P3.6 P10.6 P0.6 P3.5 P10.5 P3.4 P10.4 P3.3 P0.5 P10.3 P2.10 P3.2 P2.13 VDDI1 P0.4 P10.2 P3.1 P0.3 P10.1 P3.0 P10.0 P0.2 P2.9 P4.7 P2.8 P0.1 P2.7 P4.6 P4.5 P0.0 VDDPB VSS V SS V DDPB P5 .4 P5 .5 P5.6 P5.7 P5 .8 P5 .9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 P2.12 P2.11 P11 .5 V DDI1 P2 .0 P2 .1 P11 .4 P2.2 P11 .3 P4 .0 P2 .3 P11 .2 P4 .1 P2 .4 P11 .1 P11 .0 P2 .5 P4 .2 P2 .6 P4 .4 P4 .3 V DDPB 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TESTM P7.2 P8.4 TRST P8.3 P7.0 P7.3 P8.2 P7.1 P7.4 P8.1 P8.0 VDDIM P6.0 P6.1 P6.2 P6.3 VDDPA P15.0 P15.1 P15.2 P15.3 P15.4 P15.5 P15.6 P15.7 VAREF1 VAREF0 VAGND P5.0 P5.1 P5.2 P5.3 VDDPB MC_XY_PIN144 Figure 3 Data Sheet XC238xA Pin Configuration (top view) 14 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Key to Pin Definitions • • Ctrl.: The output signal for a port pin is selected by bit field PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to 1x00B, output O1 is selected by 1x01B, etc. Output signal OH is controlled by hardware. Type: Indicates the pad type and its power supply domain (A, B, M, 1). – St: Standard pad – Sp: Special pad e.g. XTALx – DP: Double pad - can be used as standard or high speed pad – In: Input only pad – PS: Power supply pad Table 6 Pin Definitions and Functions Pin Symbol Ctrl. Type Function 3 TESTM I In/B 4 P7.2 O0 / I St/B Bit 2 of Port 7, General Purpose Input/Output EMUX0 O1 5 Testmode Enable Enables factory test modes, must be held HIGH for normal operation (connect to VDDPB). An internal pull-up device will hold this pin high when nothing is driving it. St/B External Analog MUX Control Output 0 (ADC1) CCU62_CCP I OS0A St/B CCU62 Position Input 0 TDI_C IH St/B JTAG Test Data Input If JTAG pos. C is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. P8.4 O0 / I St/B Bit 4 of Port 8, General Purpose Input/Output CCU60_COU O1 T61 St/B CCU60 Channel 1 Output CCU62_CC6 1 O2 St/B CCU62 Channel 1 Output TMS_D IH St/B JTAG Test Mode Selection Input If JTAG pos. D is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. CCU62_CC6 1INB I St/B CCU62 Channel 1 Input Data Sheet 15 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function 6 TRST I In/B 7 P8.3 O0 / I St/B 8 Test-System Reset Input For normal system operation, pin TRST should be held low. A high level at this pin at the rising edge of PORST activates the XC238xA’s debug system. In this case, pin TRST must be driven low once to reset the debug system. An internal pull-down device will hold this pin low when nothing is driving it. Bit 3 of Port 8, General Purpose Input/Output CCU60_COU O1 T60 St/B CCU60 Channel 0 Output CCU62_CC6 0 O2 St/B CCU62 Channel 0 Output TDI_D IH St/B JTAG Test Data Input If JTAG pos. D is selected during start-up, an internal pull-up device will hold this pin low when nothing is driving it. CCU62_CC6 0INB I St/B CCU62 Channel 0 Input P7.0 O0 / I St/B Bit 0 of Port 7, General Purpose Input/Output T3OUT O1 St/B GPT12E Timer T3 Toggle Latch Output T6OUT O2 St/B GPT12E Timer T6 Toggle Latch Output TDO_A OH / IH St/B JTAG Test Data Output / DAP1 Input/Output If DAP pos. 0 or 2 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. ESR2_1 I St/B ESR2 Trigger Input 1 Data Sheet 16 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 9 P7.3 O0 / I St/B Bit 3 of Port 7, General Purpose Input/Output EMUX1 10 11 Type Function O1 St/B External Analog MUX Control Output 1 (ADC1) U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output U0C0_DOUT O3 St/B USIC0 Channel 0 Shift Data Output CCU62_CCP I OS1A St/B CCU62 Position Input 1 TMS_C IH St/B JTAG Test Mode Selection Input If JTAG pos. C is selected during start-up, an internal pull-up device will hold this pin low when nothing is driving it. U0C1_DX0F I St/B USIC0 Channel 1 Shift Data Input P8.2 O0 / I St/B Bit 2 of Port 8, General Purpose Input/Output CCU60_CC6 2 O1 St/B CCU60 Channel 2 Output TxDC1 O2 St/B CAN Node 1 Transmit Data Output U1C1_DOUT O3 St/B USIC1 Channel 1 Shift Data output CCU60_CC6 2INB I St/B CCU60 Channel 2 Input P7.1 O0 / I St/B Bit 1 of Port 7, General Purpose Input/Output EXTCLK O1 St/B Programmable Clock Signal Output CCU62_CTR APA I St/B CCU62 Emergency Trap Input BRKIN_C I St/B OCDS Break Signal Input Data Sheet 17 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 12 P7.4 O0 / I St/B Bit 4 of Port 7, General Purpose Input/Output EMUX2 13 14 16 Type Function O1 St/B External Analog MUX Control Output 2 (ADC1) U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output U0C1_SCLK OUT St/B USIC0 Channel 1 Shift Clock Output CCU62_CCP I OS2A St/B CCU62 Position Input 2 TCK_C IH St/B DAP0/JTAG Clock Input If JTAG pos. C is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. If DAP pos. 2 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. U0C0_DX0D I St/B USIC0 Channel 0 Shift Data Input U0C1_DX1E I St/B USIC0 Channel 1 Shift Clock Input P8.1 O0 / I St/B Bit 1 of Port 8, General Purpose Input/Output CCU60_CC6 1 O1 St/B CCU60 Channel 1 Output CCU60_CC6 1INB I St/B CCU60 Channel 1 Input RxDC1F I St/B CAN Node 1 Receive Data Input P8.0 O0 / I St/B Bit 0 of Port 8, General Purpose Input/Output CCU60_CC6 0 O1 St/B CCU60 Channel 0 Output CCU60_CC6 0INB I St/B CCU60 Channel 0 Input O3 P6.0 O0 / I DA/A Bit 0 of Port 6, General Purpose Input/Output EMUX0 O1 DA/A External Analog MUX Control Output 0 (ADC0) TxDC2 O2 DA/A CAN Node 2 Transmit Data Output BRKOUT O3 DA/A OCDS Break Signal Output ADCx_REQG I TyG DA/A External Request Gate Input for ADC0/1 U1C1_DX0E DA/A USIC1 Channel 1 Shift Data Input Data Sheet I 18 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 17 P6.1 O0 / I DA/A Bit 1 of Port 6, General Purpose Input/Output EMUX1 O1 DA/A External Analog MUX Control Output 1 (ADC0) T3OUT O2 DA/A GPT12E Timer T3 Toggle Latch Output 18 19 Type Function U1C1_DOUT O3 DA/A USIC1 Channel 1 Shift Data Output ADCx_REQT I RyE DA/A External Request Trigger Input for ADC0/1 RxDC2E I DA/A CAN Node 2 Receive Data Input ESR1_6 I DA/A ESR1 Trigger Input 6 P6.2 O0 / I DA/A Bit 2 of Port 6, General Purpose Input/Output EMUX2 O1 DA/A External Analog MUX Control Output 2 (ADC0) T6OUT O2 DA/A GPT12E Timer T6 Toggle Latch Output U1C1_SCLK OUT O3 DA/A USIC1 Channel 1 Shift Clock Output U1C1_DX1C I DA/A USIC1 Channel 1 Shift Clock Input P6.3 O0 / I DA/A Bit 3 of Port 6, General Purpose Input/Output T3OUT O2 DA/A GPT12E Timer T3 Toggle Latch Output U1C1_SELO 0 O3 DA/A USIC1 Channel 1 Select/Control 0 Output U1C1_DX2D I DA/A USIC1 Channel 1 Shift Control Input ADCx_REQT I RyF DA/A External Request Trigger Input for ADC0/1 P15.0 I In/A Bit 0 of Port 15, General Purpose Input ADC1_CH0 I In/A Analog Input Channel 0 for ADC1 22 P15.1 I In/A Bit 1 of Port 15, General Purpose Input ADC1_CH1 I In/A Analog Input Channel 1 for ADC1 23 P15.2 I In/A Bit 2 of Port 15, General Purpose Input ADC1_CH2 I In/A Analog Input Channel 2 for ADC1 21 24 T5INA I In/A GPT12E Timer T5 Count/Gate Input P15.3 I In/A Bit 3 of Port 15, General Purpose Input ADC1_CH3 I In/A Analog Input Channel 3 for ADC1 T5EUDA I In/A GPT12E Timer T5 External Up/Down Control Input Data Sheet 19 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function 25 P15.4 I In/A Bit 4 of Port 15, General Purpose Input ADC1_CH4 I In/A Analog Input Channel 4 for ADC1 T6INA I In/A GPT12E Timer T6 Count/Gate Input P15.5 I In/A Bit 5 of Port 15, General Purpose Input 26 27 28 29 30 31 32 33 34 35 ADC1_CH5 I In/A Analog Input Channel 5 for ADC1 T6EUDA I In/A GPT12E Timer T6 External Up/Down Control Input P15.6 I In/A Bit 6 of Port 15, General Purpose Input ADC1_CH6 I In/A Analog Input Channel 6 for ADC1 P15.7 I In/A Bit 7 of Port 15, General Purpose Input ADC1_CH7 I In/A Analog Input Channel 7 for ADC1 VAREF1 VAREF0 VAGND - PS/A Reference Voltage for A/D Converter ADC1 - PS/A Reference Voltage for A/D Converter ADC0 - PS/A Reference Ground for A/D Converters ADC0/1 P5.0 I In/A Bit 0 of Port 5, General Purpose Input ADC0_CH0 I In/A Analog Input Channel 0 for ADC0 P5.1 I In/A Bit 1 of Port 5, General Purpose Input ADC0_CH1 I In/A Analog Input Channel 1 for ADC0 P5.2 I In/A Bit 2 of Port 5, General Purpose Input ADC0_CH2 I In/A Analog Input Channel 2 for ADC0 TDI_A I In/A JTAG Test Data Input P5.3 I In/A Bit 3 of Port 5, General Purpose Input ADC0_CH3 I In/A Analog Input Channel 3 for ADC0 T3INA I In/A GPT12E Timer T3 Count/Gate Input Data Sheet 20 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function 39 P5.4 I In/A Bit 4 of Port 5, General Purpose Input ADC0_CH4 I In/A Analog Input Channel 4 for ADC0 CCU63_T12 HRB I In/A External Run Control Input for T12 of CCU63 T3EUDA I In/A GPT12E Timer T3 External Up/Down Control Input TMS_A I In/A JTAG Test Mode Selection Input 40 41 42 43 44 P5.5 I In/A Bit 5 of Port 5, General Purpose Input ADC0_CH5 I In/A Analog Input Channel 5 for ADC0 CCU60_T12 HRB I In/A External Run Control Input for T12 of CCU60 P5.6 I In/A Bit 6 of Port 5, General Purpose Input ADC0_CH6 I In/A Analog Input Channel 6 for ADC0 P5.7 I In/A Bit 7 of Port 5, General Purpose Input ADC0_CH7 I In/A Analog Input Channel 7 for ADC0 P5.8 I In/A Bit 8 of Port 5, General Purpose Input ADC0_CH8 I In/A Analog Input Channel 8 for ADC0 ADC1_CH8 I In/A Analog Input Channel 8 for ADC1 CCU6x_T12H I RC In/A External Run Control Input for T12 of CCU60/1/2/3 CCU6x_T13H I RC In/A External Run Control Input for T13 of CCU60/1/2/3 U2C0_DX0F I In/A USIC2 Channel 0 Shift Data Input P5.9 I In/A Bit 9 of Port 5, General Purpose Input ADC0_CH9 I In/A Analog Input Channel 9 for ADC0 ADC1_CH9 I In/A Analog Input Channel 9 for ADC1 CC2_T7IN I In/A CAPCOM2 Timer T7 Count Input Data Sheet 21 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function 45 P5.10 I In/A Bit 10 of Port 5, General Purpose Input ADC0_CH10 I In/A Analog Input Channel 10 for ADC0 ADC1_CH10 I In/A Analog Input Channel 10 for ADC1 BRKIN_A I In/A OCDS Break Signal Input U2C1_DX0F I In/A USIC2 Channel 1 Shift Data Input CCU61_T13 HRA I In/A External Run Control Input for T13 of CCU61 46 47 48 49 50 51 P5.11 I In/A Bit 11 of Port 5, General Purpose Input ADC0_CH11 I In/A Analog Input Channel 11 for ADC0 ADC1_CH11 I In/A Analog Input Channel 11 for ADC1 P5.12 I In/A Bit 12 of Port 5, General Purpose Input ADC0_CH12 I In/A Analog Input Channel 12 for ADC0 P5.13 I In/A Bit 13 of Port 5, General Purpose Input ADC0_CH13 I In/A Analog Input Channel 13 for ADC0 CCU63_T13 HRF I In/A External Run Control Input for T13 of CCU63 P5.14 I In/A Bit 14 of Port 5, General Purpose Input ADC0_CH14 I In/A Analog Input Channel 14 for ADC0 P5.15 I In/A Bit 15 of Port 5, General Purpose Input ADC0_CH15 I In/A Analog Input Channel 15 for ADC0 RxDC2F I In/A CAN Node 2 Receive Data Input P2.12 O0 / I St/B Bit 12 of Port 2, General Purpose Input/Output U0C0_SELO 4 O1 St/B USIC0 Channel 0 Select/Control 4 Output U0C1_SELO 3 O2 St/B USIC0 Channel 1 Select/Control 3 Output TXDC2 O3 St/B CAN Node 2 Transmit Data Output READY IH St/B External Bus Interface READY Input Data Sheet 22 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 52 P2.11 O0 / I St/B Bit 11 of Port 2, General Purpose Input/Output U0C0_SELO 2 O1 St/B USIC0 Channel 0 Select/Control 2 Output U0C1_SELO 2 O2 St/B USIC0 Channel 1 Select/Control 2 Output BHE/WRH OH St/B External Bus Interf. High-Byte Control Output Can operate either as Byte High Enable (BHE) or as Write strobe for High Byte (WRH). P11.5 O0 / I St/B Bit 5 of Port 11, General Purpose Input/Output CCU61_CC6 0 O1 St/B CCU61 Channel 0 Output CCU61_COU O2 T63 St/B CCU61 Channel 3 Output CCU61_CC6 0INB I St/B CCU61 Channel 0 Input P2.0 O0 / I St/B Bit 0 of Port 2, General Purpose Input/Output CCU63_CC6 0 O2 St/B CCU63 Channel 0 Output AD13 OH / IH St/B External Bus Interface Address/Data Line 13 53 55 Type Function RxDC0C I St/B CAN Node 0 Receive Data Input CCU63_CC6 0INB I St/B CCU63 Channel 0 Input T5INB I St/B GPT12E Timer T5 Count/Gate Input Data Sheet 23 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 56 P2.1 O0 / I St/B Bit 1 of Port 2, General Purpose Input/Output TxDC0 O1 St/B CAN Node 0 Transmit Data Output CCU63_CC6 1 O2 St/B CCU63 Channel 1 Output AD14 OH / IH St/B External Bus Interface Address/Data Line 14 CCU63_CC6 1INB I St/B CCU63 Channel 1 Input T5EUDB I St/B GPT12E Timer T5 External Up/Down Control Input ESR1_5 I St/B ESR1 Trigger Input 5 57 58 59 Type Function P11.4 O0 / I St/B Bit 4 of Port 11, General Purpose Input/Output CCU61_CC6 2 O1 St/B CCU61 Channel 2 Output CCU61_CC6 2INB I St/B CCU61 Channel 2 Input P2.2 O0 / I St/B Bit 2 of Port 2, General Purpose Input/Output TxDC1 O1 St/B CAN Node 1 Transmit Data Output CCU63_CC6 2 O2 St/B CCU63 Channel 2 Output AD15 OH / IH St/B External Bus Interface Address/Data Line 15 CCU63_CC6 2INB I St/B CCU63 Channel 2 Input ESR2_5 I St/B ESR2 Trigger Input 5 P11.3 O0 / I St/B Bit 3 of Port 11, General Purpose Input/Output CCU61_COU O1 T63 St/B CCU61 Channel 3 Output CCU61_COU O2 T62 St/B CCU61 Channel 2 Output CCU61_T13 HRF St/B External Run Control Input for T13 of CCU61 Data Sheet I 24 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 60 P4.0 O0 / I St/B Bit 0 of Port 4, General Purpose Input/Output CC2_CC24 O3 / I St/B CAPCOM2 CC24IO Capture Inp./ Compare Out. CS0 OH External Bus Interface Chip Select 0 Output P2.3 O0 / I St/B 61 62 63 Type Function St/B Bit 3 of Port 2, General Purpose Input/Output U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output CCU63_COU O2 T63 St/B CCU63 Channel 3 Output CC2_CC16 O3 / I St/B CAPCOM2 CC16IO Capture Inp./ Compare Out. A16 OH St/B External Bus Interface Address Line 16 ESR2_0 I St/B ESR2 Trigger Input 0 U0C0_DX0E I St/B USIC0 Channel 0 Shift Data Input U0C1_DX0D I St/B USIC0 Channel 1 Shift Data Input RxDC0A I St/B CAN Node 0 Receive Data Input P11.2 O0 / I St/B Bit 2 of Port 11, General Purpose Input/Output CCU61_CC6 1 O1 St/B CCU61 Channel 1 Output CCU63_CCP I OS2A St/B CCU63 Position Input 2 CCU61_CC6 1INB I St/B CCU61 Channel 1 Input P4.1 O0 / I St/B Bit 1 of Port 4, General Purpose Input/Output TxDC2 O2 CAN Node 2 Transmit Data Output CC2_CC25 O3 / I St/B CAPCOM2 CC25IO Capture Inp./ Compare Out. CS1 OH St/B External Bus Interface Chip Select 1 Output CCU62_CCP I OS0B St/B CCU62 Position Input 0 T4EUDB I St/B GPT12E Timer T4 External Up/Down Control Input ESR1_8 I St/B ESR1 Trigger Input 8 Data Sheet St/B 25 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 64 P2.4 O0 / I St/B 65 66 67 Type Function Bit 4 of Port 2, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CC2_CC17 O3 / I St/B CAPCOM2 CC17IO Capture Inp./ Compare Out. A17 OH St/B External Bus Interface Address Line 17 ESR1_0 I St/B ESR1 Trigger Input 0 U0C0_DX0F I St/B USIC0 Channel 0 Shift Data Input RxDC1A I St/B CAN Node 1 Receive Data Input P11.1 O0 / I St/B Bit 1 of Port 11, General Purpose Input/Output CCU61_COU O1 T61 St/B CCU61 Channel 1 Output TxDC0 St/B CAN Node 0 Transmit Data Output CCU63_CCP I OS1A St/B CCU63 Position Input 1 CCU61_CTR APD I St/B CCU61 Emergency Trap Input P11.0 O0 / I St/B O2 Bit 0 of Port 11, General Purpose Input/Output CCU61_COU O1 T60 St/B CCU61 Channel 0 Output CCU63_CCP I OS0A St/B CCU63 Position Input 0 RxDC0F I St/B CAN Node 0 Receive Data Input ESR1_7 I St/B ESR1 Trigger Input 7 P2.5 O0 / I St/B Bit 5 of Port 2, General Purpose Input/Output U0C0_SCLK OUT O1 St/B USIC0 Channel 0 Shift Clock Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CC2_CC18 O3 / I St/B CAPCOM2 CC18IO Capture Inp./ Compare Out. A18 OH St/B External Bus Interface Address Line 18 U0C0_DX1D I St/B USIC0 Channel 0 Shift Clock Input ESR1_10 I St/B ESR1 Trigger Input 10 Data Sheet 26 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 68 P4.2 O0 / I St/B Bit 2 of Port 4, General Purpose Input/Output TxDC2 O2 CAN Node 2 Transmit Data Output CC2_CC26 O3 / I St/B CAPCOM2 CC26IO Capture Inp./ Compare Out. CS2 OH St/B External Bus Interface Chip Select 2 Output T2INA I St/B GPT12E Timer T2 Count/Gate Input CCU62_CCP I OS1B St/B CCU62 Position Input 1 69 70 71 Type Function St/B P2.6 O0 / I St/B Bit 6 of Port 2, General Purpose Input/Output U0C0_SELO 0 O1 St/B USIC0 Channel 0 Select/Control 0 Output U0C1_SELO 1 O2 St/B USIC0 Channel 1 Select/Control 1 Output CC2_CC19 O3 / I St/B CAPCOM2 CC19IO Capture Inp./ Compare Out. A19 OH St/B External Bus Interface Address Line 19 U0C0_DX2D I St/B USIC0 Channel 0 Shift Control Input RxDC0D I St/B CAN Node 0 Receive Data Input ESR2_6 I St/B ESR2 Trigger Input 6 P4.4 O0 / I St/B CC2_CC28 O3 / I St/B CAPCOM2 CC28IO Capture Inp./ Compare Out. CS4 OH St/B External Bus Interface Chip Select 4 Output CLKIN2 I St/B Clock Signal Input 2 P4.3 O0 / I St/B U0C1_DOUT O1 St/B Bit 4 of Port 4, General Purpose Input/Output Bit 3 of Port 4, General Purpose Input/Output USIC0 Channel 1 Shift Data Output CC2_CC27 O3 / I St/B CAPCOM2 CC27IO Capture Inp./ Compare Out. CS3 OH St/B External Bus Interface Chip Select 3 Output RxDC2A I St/B CAN Node 2 Receive Data Input T2EUDA I St/B GPT12E Timer T2 External Up/Down Control Input CCU62_CCP I OS2B St/B CCU62 Position Input 2 Data Sheet 27 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 75 P0.0 O0 / I St/B 76 77 78 Type Function Bit 0 of Port 0, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output CCU61_CC6 0 O3 St/B CCU61 Channel 0 IOutput A0 OH St/B External Bus Interface Address Line 0 U1C0_DX0A I St/B USIC1 Channel 0 Shift Data Input CCU61_CC6 0INA I St/B CCU61 Channel 0 Input ESR1_11 I St/B ESR1 Trigger Input 11 P4.5 O0 / I St/B Bit 5 of Port 4, General Purpose Input/Output CC2_CC29 O3 / I St/B CAPCOM2 CC29IO Capture Inp./Compare Out. CCU61_CCP I OS0A St/B CCU61 Position Input 0 ESR2_10 I St/B ESR2 Trigger Input 10 P4.6 O0 / I St/B Bit 6 of Port 4, General Purpose Input/Output CC2_CC30 O3 / I St/B CAPCOM2 CC30IO Capture Inp./ Compare Out. T4INA I St/B GPT12E Timer T4 Count/Gate Input CCU61_CCP I OS1A St/B CCU61 Position Input 1 P2.7 O0 / I St/B Bit 7 of Port 2, General Purpose Input/Output U0C1_SELO 0 O1 St/B USIC0 Channel 1 Select/Control 0 Output U0C0_SELO 1 O2 St/B USIC0 Channel 0 Select/Control 1 Output CC2_CC20 O3 / I St/B CAPCOM2 CC20IO Capture Inp./ Compare Out. A20 OH St/B External Bus Interface Address Line 20 U0C1_DX2C I St/B USIC0 Channel 1 Shift Control Input RxDC1C I St/B CAN Node 1 Receive Data Input ESR2_7 I St/B ESR2 Trigger Input 7 Data Sheet 28 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 79 P0.1 O0 / I St/B 80 81 Type Function Bit 1 of Port 0, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CCU61_CC6 1 O3 St/B CCU61 Channel 1 Output A1 OH St/B External Bus Interface Address Line 1 U1C0_DX0B I St/B USIC1 Channel 0 Shift Data Input CCU61_CC6 1INA I St/B CCU61 Channel 1 Input U1C0_DX1A I St/B USIC1 Channel 0 Shift Clock Input P2.8 O0 / I DP/B Bit 8 of Port 2, General Purpose Input/Output U0C1_SCLK OUT O1 DP/B USIC0 Channel 1 Shift Clock Output EXTCLK O2 DP/B Programmable Clock Signal Output CC2_CC21 O3 / I DP/B CAPCOM2 CC21IO Capture Inp./ Compare Out. A21 OH DP/B External Bus Interface Address Line 21 U0C1_DX1D I DP/B USIC0 Channel 1 Shift Clock Input P4.7 O0 / I St/B Bit 7 of Port 4, General Purpose Input/Output CC2_CC31 O3 / I St/B CAPCOM2 CC31IO Capture Inp./ Compare Out. T4EUDA I St/B GPT12E Timer T4 External Up/Down Control Input CCU61_CCP I OS2A St/B CCU61 Position Input 2 Data Sheet 1) 29 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 82 P2.9 O0 / I St/B 83 Type Function Bit 9 of Port 2, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output TxDC1 O2 St/B CAN Node 1 Transmit Data Output CC2_CC22 O3 / I St/B CAPCOM2 CC22IO Capture Inp./ Compare Out. A22 OH St/B External Bus Interface Address Line 22 CLKIN1 I St/B Clock Signal Input 1 TCK_A IH St/B DAP0/JTAG Clock Input If JTAG pos. A is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. If DAP pos. 0 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. P0.2 O0 / I St/B Bit 2 of Port 0, General Purpose Input/Output U1C0_SCLK OUT O1 St/B USIC1 Channel 0 Shift Clock Output TxDC0 O2 St/B CAN Node 0 Transmit Data Output CCU61_CC6 2 O3 St/B CCU61 Channel 2 Output A2 OH St/B External Bus Interface Address Line 2 U1C0_DX1B I St/B USIC1 Channel 0 Shift Clock Input CCU61_CC6 2INA I St/B CCU61 Channel 2 Input Data Sheet 30 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 84 P10.0 O0 / I St/B 85 86 Type Function Bit 0 of Port 10, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output CCU60_CC6 0 O2 St/B CCU60 Channel 0 Output AD0 OH / IH St/B External Bus Interface Address/Data Line 0 CCU60_CC6 0INA I St/B CCU60 Channel 0 Input ESR1_2 I St/B ESR1 Trigger Input 2 U0C0_DX0A I St/B USIC0 Channel 0 Shift Data Input U0C1_DX0A I St/B USIC0 Channel 1 Shift Data Input P3.0 O0 / I St/B Bit 0 of Port 3, General Purpose Input/Output U2C0_DOUT O1 St/B USIC2 Channel 0 Shift Data Output BREQ OH St/B External Bus Request Output ESR1_1 I St/B ESR1 Trigger Input 1 U2C0_DX0A I St/B USIC2 Channel 0 Shift Data Input U2C0_DX1A I St/B USIC2 Channel 0 Shift Clock Input P10.1 O0 / I St/B Bit 1 of Port 10, General Purpose Input/Output U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output CCU60_CC6 1 O2 St/B CCU60 Channel 1 Output AD1 OH / IH St/B External Bus Interface Address/Data Line 1 CCU60_CC6 1INA I St/B CCU60 Channel 1 Input U0C0_DX1A I St/B USIC0 Channel 0 Shift Clock Input U0C0_DX0B I St/B USIC0 Channel 0 Shift Data Input Data Sheet 31 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 87 P0.3 O0 / I St/B Bit 3 of Port 0, General Purpose Input/Output U1C0_SELO 0 O1 St/B USIC1 Channel 0 Select/Control 0 Output U1C1_SELO 1 O2 St/B USIC1 Channel 1 Select/Control 1 Output CCU61_COU O3 T60 St/B CCU61 Channel 0 Output A3 St/B External Bus Interface Address Line 3 88 89 OH Type Function U1C0_DX2A I St/B USIC1 Channel 0 Shift Control Input RxDC0B I St/B CAN Node 0 Receive Data Input P3.1 O0 / I St/B Bit 1 of Port 3, General Purpose Input/Output U2C0_DOUT O1 St/B USIC2 Channel 0 Shift Data Output HLDA OH / IH St/B External Bus Hold Acknowledge Output/Input Output in master mode, input in slave mode. U2C0_DX0B I St/B USIC2 Channel 0 Shift Data Input P10.2 O0 / I St/B Bit 2 of Port 10, General Purpose Input/Output U0C0_SCLK OUT O1 St/B USIC0 Channel 0 Shift Clock Output CCU60_CC6 2 O2 St/B CCU60 Channel 2 Output AD2 OH / IH St/B External Bus Interface Address/Data Line 2 CCU60_CC6 2INA I St/B CCU60 Channel 2 Input U0C0_DX1B I St/B USIC0 Channel 0 Shift Clock Input Data Sheet 32 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 90 P0.4 O0 / I St/B Bit 4 of Port 0, General Purpose Input/Output U1C1_SELO 0 O1 St/B USIC1 Channel 1 Select/Control 0 Output U1C0_SELO 1 O2 St/B USIC1 Channel 0 Select/Control 1 Output CCU61_COU O3 T61 St/B CCU61 Channel 1 Output A4 St/B External Bus Interface Address Line 4 92 93 94 OH Type Function U1C1_DX2A I St/B USIC1 Channel 1 Shift Control Input RxDC1B I St/B CAN Node 1 Receive Data Input ESR2_8 I St/B ESR2 Trigger Input 8 P2.13 O0 / I St/B Bit 13 of Port 2, General Purpose Input/Output U2C1_SELO 2 O1 St/B USIC2 Channel 1 Select/Control 2 Output RxDC2D I St/B CAN Node 2 Receive Data Input P3.2 O0 / I St/B Bit 2 of Port 3, General Purpose Input/Output U2C0_SCLK OUT O1 St/B USIC2 Channel 0 Shift Clock Output U2C0_DX1B I St/B USIC2 Channel 0 Shift Clock Input HOLD IH St/B External Bus Master Hold Request Input P2.10 O0 / I St/B Bit 10 of Port 2, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output U0C0_SELO 3 O2 St/B USIC0 Channel 0 Select/Control 3 Output CC2_CC23 O3 / I St/B CAPCOM2 CC23IO Capture Inp./ Compare Out. A23 OH St/B External Bus Interface Address Line 23 U0C1_DX0E I St/B USIC0 Channel 1 Shift Data Input CAPINA I St/B GPT12E Register CAPREL Capture Input Data Sheet 33 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 95 P10.3 O0 / I St/B 96 97 98 Type Function Bit 3 of Port 10, General Purpose Input/Output CCU60_COU O2 T60 St/B CCU60 Channel 0 Output AD3 OH / IH St/B External Bus Interface Address/Data Line 3 U0C0_DX2A I St/B USIC0 Channel 0 Shift Control Input U0C1_DX2A I St/B USIC0 Channel 1 Shift Control Input P0.5 O0 / I St/B Bit 5 of Port 0, General Purpose Input/Output U1C1_SCLK OUT O1 St/B USIC1 Channel 1 Shift Clock Output U1C0_SELO 2 O2 St/B USIC1 Channel 0 Select/Control 2 Output CCU61_COU O3 T62 St/B CCU61 Channel 2 Output A5 OH St/B External Bus Interface Address Line 5 U1C1_DX1A I St/B USIC1 Channel 1 Shift Clock Input U1C0_DX1C I St/B USIC1 Channel 0 Shift Clock Input P3.3 O0 / I St/B Bit 3 of Port 3, General Purpose Input/Output U2C0_SELO 0 O1 St/B USIC2 Channel 0 Select/Control 0 Output U2C1_SELO 1 O2 St/B USIC2 Channel 1 Select/Control 1 Output U2C0_DX2A I St/B USIC2 Channel 0 Shift Control Input P10.4 O0 / I St/B Bit 4 of Port 10, General Purpose Input/Output U0C0_SELO 3 O1 St/B USIC0 Channel 0 Select/Control 3 Output CCU60_COU O2 T61 St/B CCU60 Channel 1 Output AD4 OH / IH St/B External Bus Interface Address/Data Line 4 U0C0_DX2B I St/B USIC0 Channel 0 Shift Control Input U0C1_DX2B I St/B USIC0 Channel 1 Shift Control Input ESR1_9 I St/B ESR1 Trigger Input 9 Data Sheet 34 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 99 P3.4 O0 / I St/B Bit 4 of Port 3, General Purpose Input/Output U2C1_SELO 0 O1 St/B USIC2 Channel 1 Select/Control 0 Output U2C0_SELO 1 O2 St/B USIC2 Channel 0 Select/Control 1 Output U0C0_SELO 4 O3 St/B USIC0 Channel 0 Select/Control 4 Output U2C1_DX2A I St/B USIC2 Channel 1 Shift Control Input P10.5 O0 / I St/B Bit 5 of Port 10, General Purpose Input/Output U0C1_SCLK OUT O1 St/B USIC0 Channel 1 Shift Clock Output CCU60_COU O2 T62 St/B CCU60 Channel 2 Output U2C0_DOUT O3 St/B USIC2 Channel 0 Shift Data Output AD5 OH / IH St/B External Bus Interface Address/Data Line 5 U0C1_DX1B I St/B USIC0 Channel 1 Shift Clock Input 100 101 Type Function P3.5 O0 / I St/B Bit 5 of Port 3, General Purpose Input/Output U2C1_SCLK OUT O1 St/B USIC2 Channel 1 Shift Clock Output U2C0_SELO 2 O2 St/B USIC2 Channel 0 Select/Control 2 Output U0C0_SELO 5 O3 St/B USIC0 Channel 0 Select/Control 5 Output U2C1_DX1A I St/B USIC2 Channel 1 Shift Clock Input Data Sheet 35 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 102 P0.6 O0 / I St/B 103 104 Type Function Bit 6 of Port 0, General Purpose Input/Output U1C1_DOUT O1 St/B USIC1 Channel 1 Shift Data Output TxDC1 O2 St/B CAN Node 1 Transmit Data Output CCU61_COU O3 T63 St/B CCU61 Channel 3 Output A6 OH St/B External Bus Interface Address Line 6 U1C1_DX0A I St/B USIC1 Channel 1 Shift Data Input CCU61_CTR APA I St/B CCU61 Emergency Trap Input U1C1_DX1B I St/B USIC1 Channel 1 Shift Clock Input P10.6 O0 / I St/B Bit 6 of Port 10, General Purpose Input/Output U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output U1C0_SELO 0 O3 St/B USIC1 Channel 0 Select/Control 0 Output AD6 OH / IH St/B External Bus Interface Address/Data Line 6 U0C0_DX0C I St/B USIC0 Channel 0 Shift Data Input U1C0_DX2D I St/B USIC1 Channel 0 Shift Control Input CCU60_CTR APA I St/B CCU60 Emergency Trap Input P3.6 O0 / I St/B Bit 6 of Port 3, General Purpose Input/Output U2C1_DOUT O1 St/B USIC2 Channel 1 Shift Data Output U0C0_SELO 6 O3 St/B USIC0 Channel 0 Select/Control 6 Output U2C1_DX0A I St/B USIC2 Channel 1 Shift Data Input U2C1_DX1B I St/B USIC2 Channel 1 Shift Clock Input Data Sheet 36 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 105 P10.7 O0 / I St/B 106 107 Type Function Bit 7 of Port 10, General Purpose Input/Output U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output CCU60_COU O2 T63 St/B CCU60 Channel 3 Output AD7 OH / IH St/B External Bus Interface Address/Data Line 7 U0C1_DX0B I St/B USIC0 Channel 1 Shift Data Input CCU60_CCP I OS0A St/B CCU60 Position Input 0 T4INB I St/B GPT12E Timer T4 Count/Gate Input P0.7 O0 / I St/B Bit 7 of Port 0, General Purpose Input/Output U1C1_DOUT O1 St/B USIC1 Channel 1 Shift Data Output U1C0_SELO 3 O2 St/B USIC1 Channel 0 Select/Control 3 Output A7 OH St/B External Bus Interface Address Line 7 U1C1_DX0B I St/B USIC1 Channel 1 Shift Data Input CCU61_CTR APB I St/B CCU61 Emergency Trap Input P3.7 O0 / I St/B Bit 7 of Port 3, General Purpose Input/Output U2C1_DOUT O1 St/B USIC2 Channel 1 Shift Data Output U2C0_SELO 3 O2 St/B USIC2 Channel 0 Select/Control 3 Output U0C0_SELO 7 O3 St/B USIC0 Channel 0 Select/Control 7 Output U2C1_DX0B I St/B USIC2 Channel 1 Shift Data Input Data Sheet 37 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 111 P1.0 O0 / I St/B Bit 0 of Port 1, General Purpose Input/Output U1C0_MCLK OUT O1 St/B USIC1 Channel 0 Master Clock Output U1C0_SELO 4 O2 St/B USIC1 Channel 0 Select/Control 4 Output A8 OH St/B External Bus Interface Address Line 8 ESR1_3 I St/B ESR1 Trigger Input 3 CCU62_CTR APB I St/B CCU62 Emergency Trap Input T6INB I St/B GPT12E Timer T6 Count/Gate Input 112 113 Type Function P9.0 O0 / I St/B Bit 0 of Port 9, General Purpose Input/Output CCU63_CC6 0 O1 St/B CCU63 Channel 0 Output CCU63_CC6 0INA I St/B CCU63 Channel 0 Input T6EUDB I St/B GPT12E Timer T6 External Up/Down Control Input P10.8 O0 / I St/B Bit 8 of Port 10, General Purpose Input/Output U0C0_MCLK OUT O1 St/B USIC0 Channel 0 Master Clock Output U0C1_SELO 0 O2 St/B USIC0 Channel 1 Select/Control 0 Output U2C1_DOUT O3 St/B USIC2 Channel 1 Shift Data Output AD8 St/B External Bus Interface Address/Data Line 8 CCU60_CCP I OS1A St/B CCU60 Position Input 1 U0C0_DX1C I St/B USIC0 Channel 0 Shift Clock Input BRKIN_B I St/B OCDS Break Signal Input T3EUDB I St/B GPT12E Timer T3 External Up/Down Control Input Data Sheet OH / IH 38 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 114 P9.1 O0 / I St/B Bit 1 of Port 9, General Purpose Input/Output CCU63_CC6 1 O1 St/B CCU63 Channel 1 Output CCU63_CC6 1INA I St/B CCU63 Channel 1 Input P10.9 O0 / I St/B Bit 9 of Port 10, General Purpose Input/Output U0C0_SELO 4 O1 St/B USIC0 Channel 0 Select/Control 4 Output U0C1_MCLK OUT O2 St/B USIC0 Channel 1 Master Clock Output AD9 OH / IH St/B External Bus Interface Address/Data Line 9 CCU60_CCP I OS2A St/B CCU60 Position Input 2 TCK_B IH St/B DAP0/JTAG Clock Input If JTAG pos. B is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. If DAP pos. 1 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. T3INB I St/B GPT12E Timer T3 Count/Gate Input P1.1 O0 / I St/B 115 116 Type Function Bit 1 of Port 1, General Purpose Input/Output CCU62_COU O1 T62 St/B CCU62 Channel 2 Output U1C0_SELO 5 St/B USIC1 Channel 0 Select/Control 5 Output U2C1_DOUT O3 St/B USIC2 Channel 1 Shift Data Output A9 OH St/B External Bus Interface Address Line 9 ESR2_3 I St/B ESR2 Trigger Input 3 U2C1_DX0C I St/B USIC2 Channel 1 Shift Data Input Data Sheet O2 39 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 117 P10.10 O0 / I St/B Bit 10 of Port 10, General Purpose Input/Output U0C0_SELO 0 O1 St/B USIC0 Channel 0 Select/Control 0 Output CCU60_COU O2 T63 St/B CCU60 Channel 3 Output AD10 OH / IH St/B External Bus Interface Address/Data Line 10 U0C0_DX2C I St/B USIC0 Channel 0 Shift Control Input 118 119 Type Function U0C1_DX1A I St/B USIC0 Channel 1 Shift Clock Input TDI_B IH St/B JTAG Test Data Input If JTAG pos. B is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. P10.11 O0 / I St/B Bit 11 of Port 10, General Purpose Input/Output U1C0_SCLK OUT O1 St/B USIC1 Channel 0 Shift Clock Output BRKOUT O2 St/B OCDS Break Signal Output AD11 OH / IH St/B External Bus Interface Address/Data Line 11 U1C0_DX1D I St/B USIC1 Channel 0 Shift Clock Input RxDC2B I St/B CAN Node 2 Receive Data Input TMS_B IH St/B JTAG Test Mode Selection Input If JTAG pos. B is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. P9.2 O0 / I St/B Bit 2 of Port 9, General Purpose Input/Output CCU63_CC6 2 O1 St/B CCU63 Channel 2 Output CCU63_CC6 2INA I St/B CCU63 Channel 2 Input CAPINB I St/B GPT12E Register CAPREL Capture Input Data Sheet 40 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 120 P1.2 O0 / I St/B Bit 2 of Port 1, General Purpose Input/Output CCU62_CC6 2 O1 St/B CCU62 Channel 2 Output U1C0_SELO 6 O2 St/B USIC1 Channel 0 Select/Control 6 Output U2C1_SCLK OUT O3 St/B USIC2 Channel 1 Shift Clock Output A10 OH St/B External Bus Interface Address Line 10 ESR1_4 I St/B ESR1 Trigger Input 4 CCU61_T12 HRB I St/B External Run Control Input for T12 of CCU61 CCU62_CC6 2INA I St/B CCU62 Channel 2 Input U2C1_DX0D I St/B USIC2 Channel 1 Shift Data Input U2C1_DX1C I St/B USIC2 Channel 1 Shift Clock Input P10.12 O0 / I St/B 121 122 Type Function Bit 12 of Port 10, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output TxDC2 O2 St/B CAN Node 2 Transmit Data Output TDO_B OH / IH St/B JTAG Test Data Output / DAP1 Input/Output If DAP pos. 1 is selected during start-up, an internal pull-down device will hold this pin low when nothing is driving it. AD12 OH / IH St/B External Bus Interface Address/Data Line 12 U1C0_DX0C I St/B USIC1 Channel 0 Shift Data Input U1C0_DX1E I St/B USIC1 Channel 0 Shift Clock Input P9.3 O0 / I St/B Bit 3 of Port 9, General Purpose Input/Output CCU63_COU O1 T60 St/B CCU63 Channel 0 Output BRKOUT St/B OCDS Break Signal Output Data Sheet O2 41 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 123 P10.13 O0 / I St/B 124 125 Type Function Bit 13 of Port 10, General Purpose Input/Output U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output U1C0_SELO 3 O3 St/B USIC1 Channel 0 Select/Control 3 Output WR/WRL OH St/B External Bus Interface Write Strobe Output Active for each external write access, when WR, active for ext. writes to the low byte, when WRL. U1C0_DX0D I St/B USIC1 Channel 0 Shift Data Input P1.3 O0 / I St/B Bit 3 of Port 1, General Purpose Input/Output CCU62_COU O1 T63 St/B CCU62 Channel 3 Output U1C0_SELO 7 O2 St/B USIC1 Channel 0 Select/Control 7 Output U2C0_SELO 4 O3 St/B USIC2 Channel 0 Select/Control 4 Output A11 OH St/B External Bus Interface Address Line 11 ESR2_4 I St/B ESR2 Trigger Input 4 CCU62_T12 HRB I St/B External Run Control Input for T12 of CCU62 P9.4 O0 / I St/B Bit 4 of Port 9, General Purpose Input/Output CCU63_COU O1 T61 St/B CCU63 Channel 1 Output U2C0_DOUT O2 St/B USIC2 Channel 0 Shift Data Output CCU62_COU O3 T63 St/B CCU62 Channel 3 Output Data Sheet 42 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 126 P9.5 O0 / I St/B 128 129 130 Type Function Bit 5 of Port 9, General Purpose Input/Output CCU63_COU O1 T62 St/B CCU63 Channel 2 Output U2C0_DOUT O2 St/B USIC2 Channel 0 Shift Data Output CCU62_COU O3 T62 St/B CCU62 Channel 2 Output U2C0_DX0E I St/B USIC2 Channel 0 Shift Data Input CCU60_CCP I OS2B St/B CCU60 Position Input 2 P10.14 O0 / I St/B Bit 14 of Port 10, General Purpose Input/Output U1C0_SELO 1 O1 St/B USIC1 Channel 0 Select/Control 1 Output U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output RD OH St/B External Bus Interface Read Strobe Output ESR2_2 I St/B ESR2 Trigger Input 2 U0C1_DX0C I St/B USIC0 Channel 1 Shift Data Input P1.4 O0 / I St/B Bit 4 of Port 1, General Purpose Input/Output CCU62_COU O1 T61 St/B CCU62 Channel 1 Output U1C1_SELO 4 O2 St/B USIC1 Channel 1 Select/Control 4 Output U2C0_SELO 5 O3 St/B USIC2 Channel 0 Select/Control 5 Output A12 OH St/B External Bus Interface Address Line 12 U2C0_DX2B I St/B USIC2 Channel 0 Shift Control Input P10.15 O0 / I St/B Bit 15 of Port 10, General Purpose Input/Output U1C0_SELO 2 O1 St/B USIC1 Channel 0 Select/Control 2 Output U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output U1C0_DOUT O3 St/B USIC1 Channel 0 Shift Data Output ALE OH St/B External Bus Interf. Addr. Latch Enable Output U0C1_DX1C I St/B USIC0 Channel 1 Shift Clock Input Data Sheet 43 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 131 P1.5 O0 / I St/B 132 133 Type Function Bit 5 of Port 1, General Purpose Input/Output CCU62_COU O1 T60 St/B CCU62 Channel 0 Output U1C1_SELO 3 O2 St/B USIC1 Channel 1 Select/Control 3 Output BRKOUT O3 St/B OCDS Break Signal Output A13 OH St/B External Bus Interface Address Line 13 U2C0_DX0C I St/B USIC2 Channel 0 Shift Data Input P9.6 O0 / I St/B Bit 6 of Port 9, General Purpose Input/Output CCU63_COU O1 T63 St/B CCU63 Channel 3 Output CCU63_COU O2 T62 St/B CCU63 Channel 2 Output CCU62_COU O3 T61 St/B CCU62 Channel 1 Output CCU63 _CTRAPA I St/B CCU63 Emergency Trap Input CCU60_CCP I OS1B St/B CCU60 Position Input 1 P1.6 O0 / I St/B Bit 6 of Port 1, General Purpose Input/Output CCU62_CC6 1 O1 / I St/B CCU62 Channel 1 Output U1C1_SELO 2 O2 St/B USIC1 Channel 1 Select/Control 2 Output U2C0_DOUT O3 St/B USIC2 Channel 0 Shift Data Output A14 St/B External Bus Interface Address Line 14 OH U2C0_DX0D I St/B USIC2 Channel 0 Shift Data Input CCU62_CC6 1INA I St/B CCU62 Channel 1 Input Data Sheet 44 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 134 P9.7 O0 / I St/B 135 Type Function Bit 7 of Port 9, General Purpose Input/Output CCU62_COU O1 T60 St/B CCU62 Channel 0 Output CCU62_COU O2 T63 St/B CCU62 Channel 3 Output CCU63_CTR APB I St/B CCU63 Emergency Trap Input U2C0_DX1D I St/B USIC2 Channel 0 Shift Clock Input CCU60_CCP I OS0B St/B CCU60 Position Input 0 P1.7 O0 / I St/B Bit 7 of Port 1, General Purpose Input/Output CCU62_CC6 0 O1 St/B CCU62 Channel 0 Output U1C1_MCLK OUT O2 St/B USIC1 Channel 1 Master Clock Output U2C0_SCLK OUT O3 St/B USIC2 Channel 0 Shift Clock Output A15 OH St/B External Bus Interface Address Line 15 U2C0_DX1C I St/B USIC2 Channel 0 Shift Clock Input CCU62_CC6 0INA I St/B CCU62 Channel 0 Input 136 XTAL2 O Sp/M Crystal Oscillator Amplifier Output 137 XTAL1 I Sp/M Crystal Oscillator Amplifier Input To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Voltages on XTAL1 must comply to the core supply voltage VDDIM. ESR2_9 I St/B Data Sheet ESR2 Trigger Input 9 45 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function 138 PORST I In/B 139 ESR1 O0 / I St/B External Service Request 1 After power-up, an internal weak pull-up device holds this pin high when nothing is driving it. RxDC0E I St/B CAN Node 0 Receive Data Input 140 Power On Reset Input A low level at this pin resets the XC238xA completely. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 120 ns. An internal pull-up device will hold this pin high when nothing is driving it. U1C0_DX0F I St/B USIC1 Channel 0 Shift Data Input U1C0_DX2C I St/B USIC1 Channel 0 Shift Control Input U1C1_DX0C I St/B USIC1 Channel 1 Shift Data Input U1C1_DX2B I St/B USIC1 Channel 1 Shift Control Input U2C1_DX2C I St/B USIC2 Channel 1 Shift Control Input ESR2 O0 / I St/B External Service Request 2 After power-up, an internal weak pull-up device holds this pin high when nothing is driving it. RxDC1E I St/B CAN Node 1 Receive Data Input CCU60_CTR APC I St/B CCU60 Emergency Trap Input CCU61_CTR APC I St/B CCU61 Emergency Trap Input CCU62_CTR APC I St/B CCU62 Emergency Trap Input CCU63_CTR APC I St/B CCU63 Emergency Trap Input U1C1_DX0D I St/B USIC1 Channel 1 Shift Data Input U1C1_DX2C I St/B USIC1 Channel 1 Shift Control Input U2C1_DX0E I St/B USIC2 Channel 1 Shift Data Input U2C1_DX2B I St/B USIC2 Channel 1 Shift Control Input Data Sheet 46 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 141 ESR0 O0 / I St/B External Service Request 0 After power-up, ESR0 operates as open-drain bidirectional reset with a weak pull-up. U1C0_DX0E I St/B USIC1 Channel 0 Shift Data Input U1C0_DX2B I St/B USIC1 Channel 0 Shift Control Input P8.6 O0 / I St/B 142 143 Type Function Bit 6 of Port 8, General Purpose Input/Output CCU60_COU O1 T63 St/B CCU60 Channel 3 Output MCHK_MAT CH O3 St/B Memory Checker Match Output CCU60_CTR APB I St/B CCU60 Emergency Trap Input BRKIN_D I St/B OCDS Break Signal Input CCU62_CTR APD I St/B CCU62 Emergency Trap Input P8.5 O0 / I St/B Bit 5 of Port 8, General Purpose Input/Output CCU60_COU O1 T62 St/B CCU60 Channel 2 Output CCU62_CC6 2 O2 St/B CCU62 Channel 2 Output TCK_D IH St/B DAP0/JTAG Clock Input If JTAG pos. D is selected during start-up, an internal pull-up device will hold this pin high when nothing is driving it. CCU62_CC6 2INB I St/B CCU62 Channel 2 Input 15 VDDIM - PS/M Digital Core Supply Voltage for Domain M Decouple with a ceramic capacitor, see Data Sheet for details. 54, 91, 127 VDDI1 - PS/1 Digital Core Supply Voltage for Domain 1 Decouple with a ceramic capacitor, see Data Sheet for details. All VDDI1 pins must be connected to each other. Data Sheet 47 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information Table 6 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. Type Function 20 VDDPA - PS/A Digital Pad Supply Voltage for Domain A Connect decoupling capacitors to adjacent VDDP/VSS pin pairs as close as possible to the pins. Note: The A/D_Converters and ports P5, P6 and P15 are fed from supply voltage VDDPA. VDDPB 2, 36, 38, 72, 74, 108, 110, 144 1, 37, 73, 109 VSS - PS/B Digital Pad Supply Voltage for Domain B Connect decoupling capacitors to adjacent VDDP/VSS pin pairs as close as possible to the pins. Note: The on-chip voltage regulators and all ports except P5, P6 and P15 are fed from supply voltage VDDPB. - PS/-- Digital Ground All VSS pins must be connected to the ground-line or ground-plane. Note: Also the exposed pad is connected internally to VSS. To improve the EMC behavior, it is recommended to connect the exposed pad to the board ground. For thermal aspects, please refer to the Data Sheet. Board layout examples are given in an application note. 1) To generate the reference clock output for bus timing measurement, fSYS must be selected as source for EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This configuration is referred to as reference clock output signal CLKOUT. Data Sheet 48 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line General Device Information 2.2 Identification Registers The identification registers describe the current version of the XC238xA and of its modules. Table 7 XC238xA Identification Registers Short Name Value Address SCU_IDMANUF 1820H 00’F07EH SCU_IDCHIP 3801H 00’F07CH SCU_IDMEM 30D0H 00’F07AH SCU_IDPROG 1313H 00’F078H JTAG_ID 0017’E083H --- Data Sheet Notes marking EES-AA, ES-AA or AA 49 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3 Functional Description The architecture of the XC238xA combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a well-balanced design. On-chip memory blocks allow the design of compact systems-on-silicon with maximum performance suited for computing, control, and communication. The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data SRAM) and the generic peripherals are connected to the CPU by separate high-speed buses. Another bus, the LXBus, connects additional on-chip resources and external resources (see Figure 4). This bus structure enhances overall system performance by enabling the concurrent operation of several subsystems of the XC238xA. The block diagram gives an overview of the on-chip components and the advanced internal bus structure of the XC238xA. DPRAM OCDS Debug Support DSRAM DMU CPU PMU Flash Memory IMB PSRAM MAC Unit EBC LXBus Control External Bus Control System Functions Clock, Reset, Power Control, StandBy RAM MPU WDT Interrupt & PEC RTC LXB us MCHK ADC0 ADC1 Module Module 10 -Bit 8-Bit GPT CC2 Modules CCU6 x Modules 10 -Bit 8-Bit 5 Timers 16 Chan. 3+1 Chan. each Periph eral Data Bu s Interrupt Bus USICx Modules 2 Chan. each Multi CAN Shared MOs for Nodes Analog and Digital General Purpose IO (GPIO) Ports MC_BL_BLOCKDIAGRAM Figure 4 Data Sheet Block Diagram 50 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.1 Memory Subsystem and Organization The memory space of the XC238xA is configured in the von Neumann architecture. In this architecture all internal and external resources, including code memory, data memory, registers and I/O ports, are organized in the same linear address space. Table 8 XC238xA Memory Map 1) Address Area Start Loc. End Loc. Area Size2) Notes IMB register space FF’FF00H FF’FFFFH 256 Bytes – Reserved (Access trap) F0’0000H FF’FEFFH <1 Mbyte Minus IMB registers Reserved for EPSRAM E8’8000H EF’FFFFH 480 Kbytes Mirrors EPSRAM Emulated PSRAM E8’0000H E8’7FFFH 32 Kbytes With Flash timing Reserved for PSRAM E0’8000H E7’FFFFH 480 Kbytes Mirrors PSRAM Program SRAM E0’0000H E0’7FFFH 32 Kbytes Maximum speed Reserved for Flash CD’0000H DF’FFFFH <1.25 Mbytes – Program Flash 3 CC’0000H CC’FFFFH 64 Kbytes – Program Flash 2 C8’0000H CB’FFFFH 256 Kbytes – Program Flash 1 C4’0000H C7’FFFFH 256 Kbytes – Program Flash 0 C0’0000H C3’FFFFH 256 Kbytes 3) 40’0000H BF’FFFFH 8 Mbytes – 21’0000H 3F’FFFFH < 2 Mbytes Minus USIC/CAN External memory area 4) Available Ext. IO area Reserved 20’BC00H 20’FFFFH 17 Kbytes – USIC alternate regs. 20’B000H 20’BFFFH 4 Kbytes Accessed via EBC MultiCAN alternate regs. 20’8000H 20’AFFFH 12 Kbytes Accessed via EBC Reserved 20’6000H 20’7FFFH 8 Kbytes – USIC registers 20’4000H 20’5FFFH 8 Kbytes Accessed via EBC MultiCAN registers 20’0000H 20’3FFFH 16 Kbytes Accessed via EBC External memory area 01’0000H 1F’FFFFH < 2 Mbytes Minus segment 0 SFR area 00’FE00H 00’FFFFH 0.5 Kbyte – Dual-Port RAM 00’F600H 00’FDFFH 2 Kbytes – Reserved for DPRAM 00’F200H 00’F5FFH 1 Kbyte – ESFR area 00’F000H 00’F1FFH 0.5 Kbyte – XSFR area 00’E000H 00’EFFFH 4 Kbytes – Data Sheet 51 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description Table 8 XC238xA Memory Map (cont’d)1) Address Area Start Loc. End Loc. Area Size2) Notes Data SRAM 00’A000H 00’DFFFH 16 Kbytes – Reserved for DSRAM 00’8000H 00’9FFFH 8 Kbytes – External memory area 00’0000H 00’7FFFH 32 Kbytes – 1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate external bus accesses. 2) The areas marked with “<” are slightly smaller than indicated. See column “Notes”. 3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH). 4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external peripherals properly. This common memory space consists of 16 Mbytes organized as 256 segments of 64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the register spaces (ESFR/SFR) additionally are directly bit addressable. The internal data memory areas and the Special Function Register areas (SFR and ESFR) are mapped into segment 0, the system segment. The Program Management Unit (PMU) handles all code fetches and, therefore, controls access to the program memories such as Flash memory and PSRAM. The Data Management Unit (DMU) handles all data transfers and, therefore, controls access to the DSRAM and the on-chip peripherals. Both units (PMU and DMU) are connected to the high-speed system bus so that they can exchange data. This is required if operands are read from program memory, code or data is written to the PSRAM, code is fetched from external memory, or data is read from or written to external resources. These include peripherals on the LXBus such as USIC or MultiCAN. The system bus allows concurrent two-way communication for maximum transfer performance. Up to 32 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data. The PSRAM is accessed via the PMU and is optimized for code fetches. A section of the PSRAM with programmable size can be write-protected. Up to 16 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data. The DSRAM is accessed via a separate interface and is optimized for data access. 2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined variables, for the system stack, and for general purpose register banks. A register bank can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7, RH7) General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR, any location in the DPRAM is bit addressable. Data Sheet 52 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 8 Kbytes of on-chip Stand-By SRAM (SBRAM) provide storage for system-relevant user data that must be preserved while the major part of the device is powered down. The SBRAM is accessed via a specific interface and is powered in domain M. 1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are word-wide registers which are used to control and monitor functions of the different on-chip units. Unused SFR addresses are reserved for future members of the XC2000 Family. In order to ensure upward compatibility they should either not be accessed or written with zeros. The on-chip Flash memory stores code, constant data, and control data. The on-chip Flash memory consists of 1 module of 64 Kbytes (preferably for data storage) and modules with a maximum capacity of 256 Kbytes each. Each module is organized in sectors of 4 Kbytes. The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used internally to store operation control parameters and protection information. Note: The actual size of the Flash memory depends on the chosen device type. Each sector can be separately write protected1), erased and programmed (in blocks of 128 Bytes). The complete Flash area can be read-protected. A user-defined password sequence temporarily unlocks protected areas. The Flash modules combine 128-bit read access with protected and efficient writing algorithms for programming and erasing. Dynamic error correction provides extremely high read data security for all read access operations. Access to different Flash modules can be executed in parallel. For Flash parameters, please see Section 4.5. Memory Content Protection The contents of on-chip memories can be protected against soft errors (induced e.g. by radiation) by activating the parity mechanism or the Error Correction Code (ECC). The parity mechanism can detect a single-bit error and prevent the software from using incorrect data or executing incorrect instructions. The ECC mechanism can detect and automatically correct single-bit errors. This supports the stable operation of the system. It is strongly recommended to activate the ECC mechanism wherever possible because this dramatically increases the robustness of an application against such soft errors. 1) To save control bits, sectors are clustered for protection purposes, they remain separate for programming/erasing. Data Sheet 53 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.2 External Bus Controller All external memory access operations are performed by a special on-chip External Bus Controller (EBC). The EBC also controls access to resources connected to the on-chip LXBus (MultiCAN and the USIC modules). The LXBus is an internal representation of the external bus that allows access to integrated peripherals and modules in the same way as to external components. The EBC can be programmed either to Single Chip Mode, when no external memory is required, or to an external bus mode with the following selections1): • • • Address Bus Width with a range of 0 … 24-bit Data Bus Width 8-bit or 16-bit Bus Operation Multiplexed or Demultiplexed The bus interface uses Port 10 and Port 2 for addresses and data. In the demultiplexed bus modes, the lower addresses are output separately on Port 0 and Port 1. The number of active segment address lines is selectable, restricting the external address space to 8 Mbytes … 64 Kbytes. This is required when interface lines shall be assigned to Port 2. External CS signals (address windows plus default) can be generated and output on Port 4 in order to save external glue logic. External modules can be directly connected to the common address/data bus and their individual select lines. A HOLD/HLDA protocol is available for bus arbitration; this allows the sharing of external resources with other bus masters. The bus arbitration is enabled by software, after which pins P3.0 … P3.2 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA pin is an output. In Slave Mode pin HLDA is switched to be an input. This allows the direct connection of the slave controller to another master controller without glue logic. Important timing characteristics of the external bus interface are programmable (with registers TCONCSx/FCONCSx) to allow the user to adapt it to a wide range of different types of memories and external peripherals. Access to very slow memories or modules with varying access times is supported by a special ‘Ready’ function. The active level of the control input signal is selectable. In addition, up to four independent address windows may be defined (using registers ADDRSELx) to control access to resources with different bus characteristics. These address windows are arranged hierarchically where window 4 overrides window 3, and window 2 overrides window 1. All accesses to locations not covered by these four address windows are controlled by TCONCS0/FCONCS0. The currently active window can generate a chip select signal. The external bus timing is based on the rising edge of the reference clock output CLKOUT. The external bus protocol is compatible with that of the standard C166 Family. 1) Bus modes are switched dynamically if several address windows with different mode settings are used. Data Sheet 54 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.3 Central Processing Unit (CPU) The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instructionfetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three register banks, and dedicated SFRs. The ALU features a multiply-and-divide unit, a bit-mask generator, and a barrel shifter. PSRAM Flash/ROM PMU CPU Prefetch Unit Branch Unit FIFO CSP IP VECSEG CPUCON1 CPUCON2 Return Stack IDX0 IDX1 QX0 QX1 QR0 QR1 +/- +/- Multiply Unit MRW +/- MCW MSW MAH MAL 2-Stage Prefetch Pipeline TFR Injection/ Exception Handler 5-Stage Pipeline IFU DPP0 DPP1 DPP2 DPP3 DPRAM IPIP SPSEG SP STKOV STKUN ADU Division Unit Bit-Mask-Gen. Multiply Unit Barrel-Shifter MDC MDH MDL ZEROS ONES MAC R15 R15 R14 R15 R14 R14 R15 R14 GPRs GPRs GPRs GPRs R1 R1 R0 R0R1 R0 R1 R0 RF +/- PSW CP Buffer ALU WB DSRAM EBC Peripherals DMU mca04917_x.vsd Figure 5 Data Sheet CPU Block Diagram 55 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description With this hardware most XC238xA instructions are executed in a single machine cycle of 12.5 ns with an 80-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle, no matter how many bits are shifted. Also, multiplication and most MAC instructions execute in one cycle. All multiple-cycle instructions have been optimized so that they can be executed very fast; for example, a 32-/16-bit division is started within 4 cycles while the remaining cycles are executed in the background. Another pipeline optimization, the branch target prediction, eliminates the execution time of branch instructions if the prediction was correct. The CPU has a register context consisting of up to three register banks with 16 wordwide GPRs each at its disposal. One of these register banks is physically allocated within the on-chip DPRAM area. A Context Pointer (CP) register determines the base address of the active register bank accessed by the CPU at any time. The number of these register bank copies is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 32 Kwords is provided for storage of temporary data. The system stack can be allocated to any location within the address space (preferably in the on-chip RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during each stack access to detect stack overflow or underflow. The high performance of the CPU hardware implementation can be best utilized by the programmer with the highly efficient XC238xA instruction set. This includes the following instruction classes: • • • • • • • • • • • • • Standard Arithmetic Instructions DSP-Oriented Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Data Sheet 56 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.4 Memory Protection Unit (MPU) The XC238xA’s Memory Protection Unit (MPU) protects user-specified memory areas from unauthorized read, write, or instruction fetch accesses. The MPU can protect the whole address space including the peripheral area. This completes establisched mechanisms such as the register security mechanism or stack overrun/underrun detection. Four Protection Levels support flexible system programming where operating system, low level drivers, and applications run on separate levels. Each protection level permits different access restrictions for instructions and/or data. Every access is checked (if the MPU is enabled) and an access violating the permission rules will be marked as invalid and leads to a protection trap. A set of protection registers for each protection level specifies the address ranges and the access permissions. Applications requiring more than 4 protection levels can dynamically re-program the protection registers. 3.5 Memory Checker Module (MCHK) The XC238xA’s Memory Checker Module calculates a checksum (fractional polynomial division) on a block of data, often called Cyclic Redundancy Code (CRC). It is based on a 32-bit linear feedback shift register and may, therefore, also be used to generate pseudo-random numbers. The Memory Checker Module is a 16-bit parallel input signature compression circuitry which enables error detection within a block of data stored in memory, registers, or communicated e.g. via serial communication lines. It reduces the probability of error masking due to repeated error patterns by calculating the signature of blocks of data. The polynomial used for operation is configurable, so most of the commonly used polynomials may be used. Also, the block size for generating a CRC result is configurable via a local counter. An interrupt may be generated if testing the current data block reveals an error. An autonomous CRC compare circuitry is included to enable redundant error detection, e.g. to enable higher safety integrity levels. The Memory Checker Module provides enhanced fault detection (beyond parity or ECC) for data and instructions in volatile and non volatile memories. This is especially important for the safety and reliability of embedded systems. Data Sheet 57 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.6 Interrupt System The architecture of the XC238xA supports several mechanisms for fast and flexible response to service requests; these can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). Where in a standard interrupt service the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source pointer, the destination pointer, or both. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. PEC services are particularly well suited to supporting the transmission or reception of blocks of data. The XC238xA has eight PEC channels, each whith fast interrupt-driven data transfer capabilities. With a minimum interrupt response time of 7/111) CPU clocks, the XC238xA can react quickly to the occurrence of non-deterministic events. Interrupt Nodes and Source Selection The interrupt system provides 96 physical nodes with separate control register containing an interrupt request flag, an interrupt enable flag and an interrupt priority bit field. Most interrupt sources are assigned to a dedicated node. A particular subset of interrupt sources shares a set of nodes. The source selection can be programmed using the interrupt source selection (ISSR) registers. External Request Unit (ERU) A dedicated External Request Unit (ERU) is provided to route and preprocess selected on-chip peripheral and external interrupt requests. The ERU features 4 programmable input channels with event trigger logic (ETL) a routing matrix and 4 output gating units (OGU). The ETL features rising edge, falling edge, or both edges event detection. The OGU combines the detected interrupt events and provides filtering capabilities depending on a programmable pattern match or miss. Trap Processing The XC238xA provides efficient mechanisms to identify and process exceptions or error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap causes an immediate system reaction similar to a standard interrupt service (branching 1) Depending if the jump cache is used or not. Data Sheet 58 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description to a dedicated vector table location). The occurrence of a hardware trap is also indicated by a single bit in the trap flag register (TFR). Unless another higher-priority trap service is in progress, a hardware trap will interrupt any ongoing program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Depending on the package option up to 3 External Service Request (ESR) pins are provided. The ESR unit processes their input values and allows to implement user controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup and power control can be efficiently realized. Software interrupts are supported by the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. Alternatively to emulate an interrupt by software a program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an interrupt control register. 3.7 On-Chip Debug Support (OCDS) The On-Chip Debug Support system built into the XC238xA provides a broad range of debug and emulation features. User software running on the XC238xA can be debugged within the target system environment. The OCDS is controlled by an external debugging device via the debug interface. This either consists of the 2-pin Device Access Port (DAP) or of the JTAG port conforming to IEEE-1149. The debug interface can be completed with an optional break interface. The debugger controls the OCDS with a set of dedicated registers accessible via the debug interface (DAP or JTAG). In addition the OCDS system can be controlled by the CPU, e.g. by a monitor program. An injection interface allows the execution of OCDSgenerated instructions by the CPU. Multiple breakpoints can be triggered by on-chip hardware, by software, or by an external trigger input. Single stepping is supported, as is the injection of arbitrary instructions and read/write access to the complete internal address space. A breakpoint trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the activation of an external signal. Tracing data can be obtained via the debug interface, or via the external bus interface for increased performance. Tracing of program execution is supported by the XC2000 Family emulation device. The DAP interface uses two interface signals, the JTAG interface uses four interface signals, to communicate with external circuitry. The debug interface can be amended with two optional break lines. Data Sheet 59 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.8 Capture/Compare Unit (CAPCOM2) The CAPCOM2 unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). The CAPCOM2 unit is typically used to handle high-speed I/O tasks such as pulse and waveform generation, pulse width modulation (PWM), digital to analog (D/A) conversion, software timing, or time recording with respect to external events. Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range or variation for the timer period and resolution and allows precise adjustments to the application-specific requirements. In addition, an external count input allows event scheduling for the capture/compare registers relative to external events. The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer and programmed for capture or compare function. All registers have each one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Table 9 Compare Modes Compare Modes Function Mode 0 Interrupt-only compare mode; Several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; Several compare events per timer period are possible Data Sheet 60 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description Table 9 Compare Modes (cont’d) Compare Modes Function Mode 2 Interrupt-only compare mode; Only one compare interrupt per timer period is generated Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow; Only one compare event per timer period is generated Double Register Mode Two registers operate on one pin; Pin toggles on each compare match; Several compare events per timer period are possible Single Event Mode Generates single edges or pulses; Can be used with any compare mode Data Sheet 61 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description Reload Reg. T7REL fCC T7IN T6OUF T7 Input Control Timer T7 CC16IO CC17IO CC16IRQ CC17IRQ Mode Control (Capture or Compare) Sixteen 16-bit Capture/ Compare Registers CC31IO fCC T6OUF T7IRQ CC31IRQ T8 Input Control Timer T8 T8IRQ Reload Reg. T8REL MC_CAPCOM2_BLOCKDIAG Figure 6 Data Sheet CAPCOM2 Unit Block Diagram 62 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.9 Capture/Compare Units CCU6x The XC238xA types feature the CCU60, CCU61, CCU62 and CCU63 unit(s). The CCU6 is a high-resolution capture and compare unit with application-specific modes. It provides inputs to start the timers synchronously, an important feature in devices with several CCU6 modules. The module provides two independent timers (T12, T13), that can be used for PWM generation, especially for AC motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features • • • • • • • • • • Three capture/compare channels, where each channel can be used either as a capture or as a compare channel. Supports generation of a three-phase PWM (six outputs, individual signals for highside and low-side switches) 16-bit resolution, maximum count frequency = peripheral clock Dead-time control for each channel to avoid short circuits in the power stage Concurrent update of the required T12/13 registers Center-aligned and edge-aligned PWM can be generated Single-shot mode supported Many interrupt request sources Hysteresis-like control mode Automatic start on a HW event (T12HR, for synchronization purposes) Timer 13 Features • • • • • • One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock Can be synchronized to T12 Interrupt generation at period match and compare match Single-shot mode supported Automatic start on a HW event (T13HR, for synchronization purposes) Additional Features • • • • • • • Block commutation for brushless DC drives implemented Position detection via Hall sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC drives Output levels can be selected and adapted to the power stage Data Sheet 63 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description CCU6 Module Kernel fSYS T13 Channel 3 com pare 1 3 2 2 2 3 trap i nput st art Trap Control output select 1 Multichannel Control Hal l i nput Channel 2 Deadtime Control compa re 1 compa re Interrupts Channel 1 compa re T12 1 capture TxHR Channel 0 output select com pare 1 CTRAP CCPOS0 CCPOS1 CCPOS2 COUT60 CC60 COUT61 CC61 COUT62 CC62 COUT63 Input / Output Control m c_ccu6_blockdiagram . vsd Figure 7 CCU6 Block Diagram Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. Timer T13 can work in compare mode only. The multi-channel control unit generates output patterns that can be modulated by timer T12 and/or timer T13. The modulation sources can be selected and combined for signal modulation. Data Sheet 64 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.10 General Purpose Timer (GPT12E) Unit The GPT12E unit is a very flexible multifunctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT12E unit incorporates five 16-bit timers organized in two separate modules, GPT1 and GPT2. Each timer in each module may either operate independently in a number of different modes or be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation: Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the system clock and divided by a programmable prescaler. Counter Mode allows timer clocking in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes each timer has one associated port pin (TxIN) which serves as a gate or clock input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles. The counting direction (up/down) for each timer can be programmed by software or altered dynamically by an external signal on a port pin (TxEUD), e.g. to facilitate position tracking. In Incremental Interface Mode the GPT1 timers can be directly connected to the incremental position sensor signals A and B through their respective inputs TxIN and TxEUD. Direction and counting signals are internally derived from these two input signals, so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components. It may also be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to the basic operating modes, T2 and T4 may be configured as reload or capture register for timer T3. A timer used as capture or reload register is stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at the associated input pin (TxIN). Timer T3 is reloaded with the contents of T2 or T4, triggered either by an external signal or a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be continuously generated without software intervention. Data Sheet 65 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description T3CON.BPS1 fGPT 2n:1 Basic Clock Interrupt Request (T2IRQ) Aux. Timer T2 T2IN T2EUD U/D T2 Mode Reload Control Capture Interrupt Request (T3IRQ) T3IN T3 Mode Control T3EUD Core Timer T3 U/D T3OTL T3OUT Toggle Latch Capture T4IN T4EUD T4 Mode Control Reload Aux. Timer T4 U/D Interrupt Request (T4IRQ) MC_GPT_BLOCK1 Figure 8 Data Sheet Block Diagram of GPT1 66 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The counting direction (up/down) for each timer can be programmed by software or altered dynamically with an external signal on a port pin (TxEUD). Concatenation of the timers is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, and/or it may be output on pin T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2 timers and to initiate a reload from the CAPREL register. The CAPREL register can capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared after the capture procedure. This allows the XC238xA to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) can also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. Data Sheet 67 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description T6CON.BPS2 fGPT 2n:1 Basic Clock Interrupt Request (T5IRQ) GPT2 Timer T5 T5IN T5EUD T5 Mode Control U/D Clear Capture CAPIN T3IN/ T3EUD CAPREL Mode Control GPT2 CAPREL Interrupt Request (CRIRQ) Reload Clear Interrupt Request (T6IRQ) Toggle FF T6IN T6 Mode Control GPT2 Timer T6 T6OTL T6OUT T6OUF U/D T6EUD MC_GPT_BLOCK2 Figure 9 Data Sheet Block Diagram of GPT2 68 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.11 Real Time Clock The Real Time Clock (RTC) module of the XC238xA can be clocked with a clock signal selected from internal sources or external sources (pins). The RTC basically consists of a chain of divider blocks: • • • Selectable 32:1 and 8:1 dividers (on - off) The reloadable 16-bit timer T14 The 32-bit RTC timer block (accessible via registers RTCH and RTCL) consisting of: – a reloadable 10-bit timer – a reloadable 6-bit timer – a reloadable 6-bit timer – a reloadable 10-bit timer All timers count up. Each timer can generate an interrupt request. All requests are combined to a common node request. fRTC :32 M UX RUN M UX Interrupt Sub Node :8 PRE REFCLK CNT INT0 CNT INT1 CNT INT2 RTCINT CNT INT3 REL-Register f CNT T14REL 10 Bits 6 Bits 6 Bits 10 Bits T14 10 Bits 6 Bits 6 Bits 10 Bits T14-Register CNT-Register M CB05568B Figure 10 RTC Block Diagram Note: The registers associated with the RTC are only affected by a power reset. Data Sheet 69 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description The RTC module can be used for different purposes: • • • • System clock to determine the current time and date Cyclic time-based interrupt, to provide a system time tick independent of CPU frequency and other resources 48-bit timer for long-term measurements Alarm interrupt at a defined time Data Sheet 70 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.12 A/D Converters For analog signal measurement, up to two 10-bit A/D converters (ADC0, ADC1) with 16 + 8 multiplexed input channels and a sample and hold circuit have been integrated on-chip. 4 inputs can be converted by both A/D converters. Conversions use the successive approximation method. The sample time (to charge the capacitors) and the conversion time are programmable so that they can be adjusted to the external circuit. The A/D converters can also operate in 8-bit conversion mode, further reducing the conversion time. Several independent conversion result registers, selectable interrupt requests, and highly flexible conversion sequences provide a high degree of programmability to meet the application requirements. Both modules can be synchronized to allow parallel sampling of two input channels. For applications that require more analog input channels, external analog multiplexers can be controlled automatically. For applications that require fewer analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converters of the XC238xA support two types of request sources which can be triggered by several internal and external events. • • Parallel requests are activated at the same time and then executed in a predefined sequence. Queued requests are executed in a user-defined sequence. In addition, the conversion of a specific channel can be inserted into a running sequence without disturbing that sequence. All requests are arbitrated according to the priority level assigned to them. Data reduction features reduce the number of required CPU access operations allowing the precise evaluation of analog inputs (high conversion rate) even at a low CPU speed. Result data can be reduced by limit checking or accumulation of results. The Peripheral Event Controller (PEC) can be used to control the A/D converters or to automatically store conversion results to a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. Each A/D converter contains eight result registers which can be concatenated to build a result FIFO. Wait-for-read mode can be enabled for each result register to prevent the loss of conversion data. In order to decouple analog inputs from digital noise and to avoid input trigger noise, those pins used for analog input can be disconnected from the digital input stages. This can be selected for each pin separately with the Port x Digital Input Disable registers. The Auto-Power-Down feature of the A/D converters minimizes the power consumption when no conversion is in progress. Broken wire detection for each channel and a multiplexer test mode provide information to verify the proper operation of the analog signal sources (e.g. a sensor system). Data Sheet 71 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.13 Universal Serial Interface Channel Modules (USIC) The XC238xA features the USIC modules USIC0, USIC1, USIC2. Each module provides two serial communication channels. The Universal Serial Interface Channel (USIC) module is based on a generic data shift and data storage structure which is identical for all supported serial communication protocols. Each channel supports complete full-duplex operation with a basic data buffer structure (one transmit buffer and two receive buffer stages). In addition, the data handling software can use FIFOs. The protocol part (generation of shift clock/data/control signals) is independent of the general part and is handled by protocol-specific preprocessors (PPPs). The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and outputs of each USIC channel can be assigned to different interface pins, providing great flexibility to the application software. All assignments can be made during runtime. Bus Buffer & Shift Structure Protocol Preprocessors Pins Control 0 DBU 0 PPP_B DSU 0 PPP_C PPP_D Control 1 PPP_A DBU 1 Pin Routing Shell Bus Interface PPP_A PPP_B DSU 1 PPP_C PPP_D fsys Fractional Dividers Baud rate Generators USIC_basic.vsd Figure 11 General Structure of a USIC Module The regular structure of the USIC module brings the following advantages: • • • Higher flexibility through configuration with same look-and-feel for data management Reduced complexity for low-level drivers serving different protocols Wide range of protocols with improved performances (baud rate, buffer handling) Data Sheet 72 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description Target Protocols Each USIC channel can receive and transmit data frames with a selectable data word width from 1 to 16 bits in each of the following protocols: • • • • • UART (asynchronous serial channel) – module capability: maximum baud rate = fSYS / 4 – data frame length programmable from 1 to 63 bits – MSB or LSB first LIN Support (Local Interconnect Network) – module capability: maximum baud rate = fSYS / 16 – checksum generation under software control – baud rate detection possible by built-in capture event of baud rate generator SSC/SPI (synchronous serial channel with or without data buffer) – module capability: maximum baud rate = fSYS / 2, limited by loop delay – number of data bits programmable from 1 to 63, more with explicit stop condition – MSB or LSB first – optional control of slave select signals IIC (Inter-IC Bus) – supports baud rates of 100 kbit/s and 400 kbit/s IIS (Inter-IC Sound Bus) – module capability: maximum baud rate = fSYS / 2 Note: Depending on the selected functions (such as digital filters, input synchronization stages, sample point adjustment, etc.), the maximum achievable baud rate can be limited. Please note that there may be additional delays, such as internal or external propagation delays and driver delays (e.g. for collision detection in UART mode, for IIC, etc.). Data Sheet 73 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.14 MultiCAN Module The MultiCAN module contains independently operating CAN nodes with Full-CAN functionality which are able to exchange Data and Remote Frames using a gateway function. Transmission and reception of CAN frames is handled in accordance with CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. All CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to set up a FIFO buffer. Note: The number of CAN nodes and message objects depends on the selected device type. The message objects are organized in double-chained linked lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to its own message object list and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations. MultiCAN Module Kernel Clock Control CAN Node 0 Interrupt Control Port Control ... Linked List Control TXDCn RXDCn ... Message Object Buffer ... Address Decoder CAN Node n fCAN TXDC0 RXDC0 CAN Control mc_multican_block.vsd Figure 12 Data Sheet Block Diagram of MultiCAN Module 74 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description MultiCAN Features • • • • • • • • • • CAN functionality conforming to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) Independent CAN nodes Set of independent message objects (shared by the CAN nodes) Dedicated control registers for each CAN node Data transfer rate up to 1 Mbit/s, individually programmable for each node Flexible and powerful message transfer control and error handling capabilities Full-CAN functionality for message objects: – Can be assigned to one of the CAN nodes – Configurable as transmit or receive objects, or as message buffer FIFO – Handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering – Remote Monitoring Mode, and frame counter for monitoring Automatic Gateway Mode support 16 individually programmable interrupt nodes Analyzer mode for CAN bus monitoring 3.15 System Timer The System Timer consists of a programmable prescaler and two concatenated timers (10 bits and 6 bits). Both timers can generate interrupt requests. The clock source can be selected and the timers can also run during power reduction modes. Therefore, the System Timer enables the software to maintain the current time for scheduling functions or for the implementation of a clock. Data Sheet 75 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.16 Watchdog Timer The Watchdog Timer is one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after an application reset of the chip. It can be disabled and enabled at any time by executing the instructions DISWDT and ENWDT respectively. The software has to service the Watchdog Timer before it overflows. If this is not the case because of a hardware or software failure, the Watchdog Timer overflows, generating a prewarning interrupt and then a reset request. The Watchdog Timer is a 16-bit timer clocked with the system clock divided by 16,384 or 256. The Watchdog Timer register is set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the Watchdog Timer is reloaded and the prescaler is cleared. Time intervals between 3.2 μs and 13.42 s can be monitored (@ 80 MHz). The default Watchdog Timer interval after power-up is 6.5 ms (@ 10 MHz). 3.17 Clock Generation The Clock Generation Unit can generate the system clock signal fSYS for the XC238xA from a number of external or internal clock sources: • • • • External clock signals with pad voltage or core voltage levels External crystal or resonator using the on-chip oscillator On-chip clock source for operation without crystal/resonator Wake-up clock (ultra-low-power) to further reduce power consumption The programmable on-chip PLL with multiple prescalers generates a clock signal for maximum system performance from standard crystals, a clock input signal, or from the on-chip clock source. See also Section 4.6.2. The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency falls below a certain limit or stops completely. In this case, the system can be supplied with an emergency clock to enable operation even after an external clock failure. All available clock signals can be output on one of two selectable pins. Data Sheet 76 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.18 Parallel Ports The XC238xA provides up to 119 I/O lines which are organized into 11 input/output ports and 2 input ports. All port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port control registers. This configuration selects the direction (input/output), push/pull or open-drain operation, activation of pull devices, and edge characteristics (shape) and driver characteristics (output current) of the port drivers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs without pull devices active. All port lines have alternate input or output functions associated with them. These alternate functions can be programmed to be assigned to various port pins to support the best utilization for a given application. For this reason, certain functions appear several times in Table 10. All port lines that are not used for alternate functions may be used as general purpose I/O lines. Table 10 Summary of the XC238xA’s Ports Port Width I/O Connected Modules P0 8 I/O EBC (A7…A0), CCU6, USIC, CAN P1 8 I/O EBC (A15…A8), CCU6, USIC P2 14 I/O EBC (READY, BHE, A23…A16, AD15…AD13, D15…D13), CAN, CC2, GPT12E, USIC, DAP/JTAG P3 8 I/O CAN, USIC P4 8 I/O EBC (CS3…CS0), CC2, CAN, GPT12E, USIC P5 16 I Analog Inputs, CCU6, DAP/JTAG, GPT12E, CAN P6 4 I/O ADC, CAN, GPT12E P7 5 I/O CAN, GPT12E, SCU, DAP/JTAG, CCU6, ADC, USIC P8 7 I/O CCU6, DAP/JTAG, USIC P9 8 I/O CCU6, DAP/JTAG, CAN P10 16 I/O EBC (ALE, RD, WR, AD12…AD0, D12…D0), CCU6, USIC, DAP/JTAG, CAN P11 6 I/O CCU6, USIC, CAN P15 8 I Analog Inputs, GPT12E Data Sheet 77 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description 3.19 Instruction Set Summary Table 11 lists the instructions of the XC238xA. The addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “Instruction Set Manual”. This document also provides a detailed description of each instruction. Table 11 Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2/4 ADDC(B) Add word (byte) operands with Carry 2/4 SUB(B) Subtract word (byte) operands 2/4 SUBC(B) Subtract word (byte) operands with Carry 2/4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16- × 16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2/4 OR(B) Bitwise OR, (word/byte operands) 2/4 XOR(B) Bitwise exclusive OR, (word/byte operands) 2/4 BCLR/BSET Clear/Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/BFLDL Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 CMP(B) Compare word (byte) operands 2/4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2/4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2 SHL/SHR Shift left/right direct word GPR 2 Data Sheet 78 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description Table 11 Instruction Set Summary (cont’d) Mnemonic Description Bytes ROL/ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2/4 MOVBS/Z Move byte operand to word op. with sign/zero extension 2/4 JMPA/I/R Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 JB(C) Jump relative if direct bit is set (and clear bit) 4 JNB(S) Jump relative if direct bit is not set (and set bit) 4 CALLA/I/R Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH/POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update register with word operand 4 RET(P) Return from intra-segment subroutine (and pop direct word register from system stack) 2 RETS Return from inter-segment subroutine 2 RETI Return from interrupt service subroutine 2 SBRK Software Break 2 SRST Software Reset 4 IDLE Enter Idle Mode PWRDN Unused instruction 4 1) 4 SRVWDT Service Watchdog Timer 4 DISWDT/ENWDT Disable/Enable Watchdog Timer 4 EINIT End-of-Initialization Register Lock 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2/4 EXTS(R) Begin EXTended Segment (and Register) sequence 2/4 Data Sheet 79 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Functional Description Table 11 Instruction Set Summary (cont’d) Mnemonic Description Bytes NOP Null operation 2 CoMUL/CoMAC Multiply (and accumulate) 4 CoADD/CoSUB Add/Subtract 4 Co(A)SHR (Arithmetic) Shift right 4 CoSHL Shift left 4 CoLOAD/STORE Load accumulator/Store MAC register 4 CoCMP Compare 4 CoMAX/MIN Maximum/Minimum 4 CoABS/CoRND Absolute value/Round accumulator 4 CoMOV Data move 4 CoNEG/NOP Negate accumulator/Null operation 4 1) The Enter Power Down Mode instruction is not used in the XC238xA, due to the enhanced power control scheme. PWRDN will be correctly decoded, but will trigger no action. Data Sheet 80 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4 Electrical Parameters The operating range for the XC238xA is defined by its electrical parameters. For proper operation the specified limits must be respected when integrating the device in its target environment. 4.1 General Parameters These parameters are valid for all subsequent descriptions, unless otherwise noted. 4.1.1 Absolut Maximum Rating Conditions Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for an extended time may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Table 12 Absolute Maximum Rating Parameters Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Output current on a pin when high value is driven IOH SR -30 − − mA Output current on a pin when low value is driven IOL SR − − 30 mA -10 − 10 mA 1) − − 100 mA 1) -40 − 150 °C -65 − 150 °C -0.5 − 6.0 V -0.5 − VDDP V IOV SR Absolute sum of overload Σ|IOV| Overload current currents SR Junction Temperature TJ SR TST SR VDDPA, VDDPB Storage Temperature Digital supply voltage for IO pads and voltage regulators Voltage on any pin with respect to ground (Vss) SR VIN SR + 0.5 VIN ≤ VDDP(max) 1) Overload condition occurs if the input voltage VIN is out of the absolute maximum rating range. In this case the current must be limited to the listed values by design measures. Data Sheet 81 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.1.2 Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XC238xA. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Note: Typical parameter values refer to room temperature and nominal supply voltage, minimum/maximum parameter values also include conditions of minimum/maximum temperature and minimum/maximum supply voltage. Additional details are described where applicable. Table 13 Operating Conditions Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Voltage Regulator Buffer Capacitance for DMP_M CEVRM 1.0 − 4.7 μF 1) Voltage Regulator Buffer Capacitance for DMP_1 CEVR1 0.47 − 2.2 μF 1)2) External Load Capacitance CL SR − 203) − pF pin out driver= default System frequency fSYS SR − IOVA SR -2 Overload current for analog inputs6) SR SR 4) Overload current for digital IOVD SR -5 inputs6) Overload current coupling KOVA factor for analog inputs7) CC − − Overload current coupling KOVD CC factor for digital I/O pins − − Data Sheet 82 − 100 MHz 5) − 5 mA not subject to production test − 5 mA not subject to production test 2.5 x 10-4 1.5 x 10-3 - IOV < 0 mA; 1.0 x 10-6 1.0 x 10-4 - 1.0 x 10-2 3.0 x 10-2 IOV < 0 mA; 1.0 x 10-4 5.0 x 10-3 IOV > 0 mA; not subject to production test IOV > 0 mA; not subject to production test not subject to production test not subject to production test V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 13 Operating Conditions (cont’d) Parameter Symbol Values Unit Note / Test Condition mA not subject to production test Min. Typ. Max. Σ|IOV| SR − − 50 Digital core supply voltage VDDIM for domain M8) CC − 1.5 − Digital core supply voltage VDDI1 for domain 18) CC − 1.5 − − 5.5 V 0 − V Absolute sum of overload currents Digital supply voltage for IO pads and voltage regulators VDDP SR 4.5 Digital ground voltage VSS SR − 1) To ensure the stability of the voltage regulators the EVRs must be buffered with ceramic capacitors. Separate buffer capacitors with the recomended values shall be connected as close as possible to each VDDIM and VDDI1 pin to keep the resistance of the board tracks below 2 Ohm. Connect all VDDI1 pins together. The minimum capacitance value is required for proper operation under all conditions (e.g. temperature). Higher values slightly increase the startup time. 2) Use one Capacitor for each pin. 3) This is the reference load. For bigger capacitive loads, use the derating factors listed in the PAD properties section. 4) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output current may lead to increased delays or reduced driving capability (CL). 5) The operating frequency range may be reduced for specific device types. This is indicated in the device designation (...FxxL). 80 MHz devices are marked ...F80L. 6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin ((IOV < 0). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified limits. Proper operation under overload conditions depends on the application. Overload conditions must not occur on pin XTAL1 (powered by VDDIM). 7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error current adds to the respective pins leakage current (IOZ). The amount of error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it.The total current through a pin is |ITOT| = |IOZ| + (|IOV| KOV). The additional error current may distort the input voltage on analog inputs. 8) Value is controlled by on-chip regulator Data Sheet 83 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.1.3 Pad Timing Definition If not otherwise noted, all timing parameters are tested and are valid for the corresponding output pins operating in strong driver, fast edge mode. See also “Pad Properties” on Page 113. 4.1.4 Parameter Interpretation The parameters listed in the following include both the characteristics of the XC238xA and its demands on the system. To aid in correctly interpreting the parameters when evaluating them for a design, they are marked accordingly in the column “Symbol”: CC (Controller Characteristics): The logic of the XC238xA provides signals with the specified characteristics. SR (System Requirement): The external system must provide signals with the specified characteristics to the XC238xA. Data Sheet 84 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.2 DC Parameters These parameters are static or average values that may be exceeded during switching transitions (e.g. output current). Leakage current is strongly dependent on the operating temperature and the voltage level at the respective pin. The maximum values in the following tables apply under worst case conditions, i.e. maximum temperature and an input level equal to the supply voltage. The value for the leakage current in an application can be determined by using the respective leakage derating formula (see tables) with values from that application. The pads of the XC238xA are designed to operate in various driver modes. The DC parameter specifications refer to the pad current limits specified in Section 4.6.4. Supply Voltage Restrictions The XC238xA can operate within a wide supply voltage range from 3.0 V to 5.5 V. However, during operation this supply voltage must remain within 10 percent of the selected nominal supply voltage. It cannot vary across the full operating voltage range. Because of the supply voltage restriction and because electrical behavior depends on the supply voltage, the parameters are specified separately for the upper and the lower voltage range. During operation, the supply voltages may only change with a maximum speed of dV/dt < 1 V/ms. During power-on sequences, the supply voltages may only change with a maximum speed of dV/dt < 5 V/μs, i.e. the target supply voltage may be reached earliest after approx. 1 μs. Note: To limit the speed of supply voltage changes, the employment of external buffer capacitors at pins VDDPA/VDDPB is recommended. Data Sheet 85 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Pullup/Pulldown Device Behavior Most pins of the XC238xA feature pullup or pulldown devices. For some special pins these are fixed; for the port pins they can be selected by the application. The specified current values indicate how to load the respective pin depending on the intended signal level. Figure 13 shows the current paths. The shaded resistors shown in the figure may be required to compensate system pull currents that do not match the given limit values. VDDP Pullup Pulldown VSS MC_XC2X_PULL Figure 13 Data Sheet Pullup/Pulldown Current Definition 86 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.2.1 DC Parameters Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. Note: Operating Conditions apply. Table 14 is valid under the following conditions: VDDP ≥ 4.5 V; VDDPtyp = 5 V; VDDP ≤ 5.5 V Table 14 DC Characteristics for Upper Voltage Range Parameter Symbol Values Pin capacitance (digital inputs/outputs). To be doubled for double bond pins.1) CIO CC Input Hysteresis2) HYS CC 0.11 x Unit Note / Test Condition Min. Typ. Max. − − 10 pF not subject to production test − − V RS = 0 Ohm VDDP Absolute input leakage current on pins of analog ports3) |IOZ1| CC − 10 200 nA VIN > 0 V; VIN < VDDP Absolute input leakage current for all other pins. To be doubled for double bond pins.3)1)4) |IOZ2| CC − 0.2 5 μA − 0.2 15 μA TJ ≤ 110 °C; VIN < VDDP; VIN > VSS TJ≤ 150 °C; VIN < VDDP; VIN > VSS Pull Level Force Current5) |IPLF| SR 250 − − μA 6) Pull Level Keep Current7) |IPLK| SR − − 30 μA 6) Input high voltage (all except XTAL1) VIH SR 0.7 x − VDDP V Input low voltage (all except XTAL1) VIL SR 0.3 x V Output High voltage8) VOH CC VDDP − − V IOH ≥ IOHmax VDDP − − V IOH ≥ IOHnom9) VDDP + 0.3 − -0.3 VDDP - 1.0 - 0.4 Data Sheet 87 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 14 DC Characteristics for Upper Voltage Range (cont’d) Parameter Symbol Values Min. Output Low Voltage8) VOL CC Typ. Unit Note / Test Condition IOL ≤ IOLmax IOL ≤ IOLnom9) Max. − − 1.0 V − − 0.4 V 1) Because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the normal value. For a list of affected pins refer to the pin definitions table in chapter 2. 2) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions. 3) If the input voltage exceeds the respective supply voltage due to ground bouncing (VIN < VSS) or supply ripple (VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to the definition of the overload coupling factor KOV. 4) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation which applies for maximum temperature. 5) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN ≤ VILmax for a pullup; VPIN ≥ VIHmin for a pulldown. 6) These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose IO pins. 7) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN ≥ VIHmin for a pullup; VPIN ≤ VILmax for a pulldown. 8) The maximum deliverable output current of a port driver depends on the selected output driver mode. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is determined by the external circuit. 9) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS, VOH->VDDP). However, only the levels for nominal output currents are verified. Data Sheet 88 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.2.2 DC Parameters for Lower Voltage Area Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. Note: Operating Conditions apply. Table 15 is valid under the following conditions: VDDP ≥ 3.0 V; VDDPtyp = 3.3 V; VDDP ≤ 4.5 V Table 15 DC Characteristics for Lower Voltage Range Parameter Symbol Values Pin capacitance (digital inputs/outputs). To be doubled for double bond pins.1) CIO CC Input Hysteresis2) HYS CC 0.07 x Unit Note / Test Condition Min. Typ. Max. − − 10 pF not subject to production test − − V RS = 0 Ohm VDDP Absolute input leakage current on pins of analog ports3) |IOZ1| CC − 10 200 nA VIN > VSS; VIN < VDDP Absolute input leakage current for all other pins. To be doubled for double bond pins.3)1)4) |IOZ2| CC − 0.2 2.5 μA − 0.2 8 μA TJ ≤ 110 °C; VIN < VDDP; VIN > VSS TJ ≤ 150 °C; VIN < VDDP; VIN > VSS Pull Level Force Current5) |IPLF| SR 150 − − Pull Level Keep Current7) |IPLK| SR − − 10 μA Input high voltage (all except XTAL1) VIH SR 0.7 x − VDDP V Input low voltage (all except XTAL1) VIL SR 0.3 x V Output High voltage8) VOH CC VDDP − − V IOH ≥ IOHmax VDDP − − V IOH ≥ IOHnom9) VDDP VDDP - 1.0 - 0.4 Data Sheet 6) + 0.3 − -0.3 6) 89 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 15 DC Characteristics for Lower Voltage Range (cont’d) Parameter Symbol Values Min. Output Low Voltage8) VOL CC Typ. Unit Note / Test Condition IOL ≤ IOLmax IOL ≤ IOLnom10) Max. − − 1.0 V − − 0.4 V 1) Because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the normal value. For a list of affected pins refer to the pin definitions table in chapter 2. 2) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions. 3) If the input voltage exceeds the respective supply voltage due to ground bouncing (VIN < VSS) or supply ripple (VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to the definition of the overload coupling factor KOV. 4) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation which applies for maximum temperature. 5) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN <= VIL for a pullup; VPIN >= VIH for a pulldown. 6) These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose IO pins. 7) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN >= VIH for a pullup; VPIN <= VIL for a pulldown. 8) The maximum deliverable output current of a port driver depends on the selected output driver mode. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is determined by the external circuit. 9) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS, VOH->VDDP). However, only the levels for nominal output currents are verified. 10) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS, VOH->VDDP). However, only the levels for nominal output currents are verified. Data Sheet 90 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.2.3 Power Consumption The power consumed by the XC238xA depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. The power consumption specified here consists of two components: • • The switching current IS depends on the device activity The leakage current ILK depends on the device temperature To determine the actual power consumption, always both components, switching current IS and leakage current ILK must be added: IDDP = IS + ILK. Note: The power consumption values are not subject to production test. They are verified by design/characterization. To determine the total power consumption for dimensioning the external power supply, also the pad driver currents must be considered. The given power consumption parameters and their values refer to specific operating conditions: • • Active mode: Regular operation, i.e. peripherals are active, code execution out of Flash. Stopover mode: Crystal oscillator and PLL stopped, Flash switched off, clock in domain DMP_1 stopped. Note: The maximum values cover the complete specified operating range of all manufactured devices. The typical values refer to average devices under typical conditions, such as nominal supply voltage, room temperature, application-oriented activity. After a power reset, the decoupling capacitors for VDDIM and VDDI1 are charged with the maximum possible current. For additional information, please refer to Section 5.2, Thermal Considerations. Note: Operating Conditions apply. Table 16 Parameter Switching Power Consumption Symbol ISACT Power supply current (active) with all peripherals CC active and EVVRs on Values Unit Note / Test Condition 10 + 1.0 x mA 2)3) 2.0 mA Min. Typ. Max. − 10 + 0.6 x 0.7 fSYS1) Power supply current in ISSO CC − stopover mode, EVVRs on fSYS1) 1) fSYS in MHz. Data Sheet 91 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 2) The pad supply voltage pins (VDDPB) provide the input current for the on-chip EVVRs and the current consumed by the pin output drivers. A small current is consumed because the drivers input stages are switched. In Fast Startup Mode (with the Flash modules deactivated), the typical current is reduced to 3 + 0.6 x fSYS. 3) Please consider the additional conditions described in section "Active Mode Power Supply Current". Active Mode Power Supply Current The actual power supply current in active mode not only depends on the system frequency but also on the configuration of the XC238xA’s subsystem. Besides the power consumed by the device logic the power supply pins also provide the current that flows through the pin output drivers. A small current is consumed because the drivers’ input stages are switched. The IO power domains can be supplied separately. Power domain A (VDDPA) supplies the A/D converters and Port 6. Power domain B (VDDPB) supplies the on-chip EVVRs and all other ports. During operation domain A draws a maximum current of 1.5 mA for each active A/D converter module from VDDPA. In Fast Startup Mode (with the Flash modules deactivated), the typical current is reduced to (3 + 0.6×fSYS) mA. Data Sheet 92 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters IS [mA] 100 ISACTmax 90 80 70 ISACTtyp 60 50 40 30 20 10 20 40 60 80 fSYS [MHz] MC_XC2XM_IS Figure 14 Supply Current in Active Mode as a Function of Frequency Note: Operating Conditions apply. Data Sheet 93 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 17 Leakage Power Consumption Parameter Leakage supply current (DMP_1 powered)1) Symbol ILK1 CC Values Unit Note / Test Condition 0.05 mA 0.5 1.3 mA − 2.1 6.2 mA − 4.4 13.7 mA TJ= 25 °C1) TJ= 85 °C1) TJ= 125 °C1) TJ= 150 °C1) Min. Typ. Max. − 0.03 − 1) All inputs (including pins configured as inputs) are set at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP and all outputs (including pins configured as outputs) are disconnected. Note: A fraction of the leakage current flows through domain DMP_A (pin VDDPA). This current can be calculated as 7 000 × e-α, with α = 5 000 / (273 + 1.3×TJ). For TJ = 150°C, this results in a current of 160 μA. The leakage power consumption can be calculated according to the following formulas: ILK0 = 500 000 × e-α, with α = 3 000 / (273 + B×TJ) Parameter B must be replaced by • • 1.0 for typical values 1.6 for maximum values ILK1 = 600 000 × e-α, with α = 5 000 / (273 + B×TJ) Parameter B must be replaced by • • 1.0 for typical values 1.3 for maximum values Data Sheet 94 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters ILK [mA] 14 ILK1max 12 10 8 6 ILK1typ 4 2 -50 0 100 50 125 150 TJ [°C] MC_XY_ILKN Figure 15 Leakage Supply Current as a Function of Temperature Data Sheet 95 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.3 Analog/Digital Converter Parameters These parameters describe the conditions for optimum ADC performance. Note: Operating Conditions apply. Table 18 ADC Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Switched capacitance at an analog input CAINSW − 4 5 pF not subject to production test1) CAINT − 10 12 pF not subject to production test1) 7 9 pF not subject to production test1) CC Total capacitance at an analog input CC Switched capacitance at the reference input CC CAREFSW − Total capacitance at the reference input CAREFT − 13 15 pF not subject to production test1) Differential Non-Linearity Error |EADNL| CC − 0.8 1.0 LSB not subject to production test Gain Error |EAGAIN| − CC 0.4 0.8 LSB not subject to production test Integral Non-Linearity |EAINL| CC − 0.8 1.2 LSB not subject to production test Offset Error |EAOFF| CC − 0.5 0.8 LSB not subject to production test Analog clock frequency fADCI SR 0.5 − 20 MHz Upper voltage range 0.5 − 16.5 MHz Lower voltage range CC Input resistance of the selected analog channel RAIN CC − − 2 kOh m not subject to production test1) Input resistance of the reference input RAREF − − 2 kOh m not subject to production test1) Data Sheet CC 96 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 18 ADC Parameters (cont’d) Parameter Symbol Values Min. Unit Typ. Max. Broken wire detection delay against VAGND2) tBWG CC − − 50 3) Broken wire detection delay against VAREF2) tBWR CC − − 50 4) Conversion time for 8-bit result2) tc8 CC (11 + STC) x tADCI + 2 x tSYS Conversion time for 10-bit tc10 CC result2) (13 + STC) x tADCI + 2 x tSYS Total Unadjusted Error − 1 2 LSB Wakeup time from analog tWAF CC − powerdown, fast mode2) − 4 μs Wakeup time from analog tWAS CC − powerdown, slow mode2) − 15 μs − 1.5 V Analog reference ground |TUE| CC VAGND SR Note / Test Condition VSS 5) - 0.05 Analog input voltage range VAIN SR VAGND − VAREF V 6) Analog reference voltage VAREF − VDDPA V 5) SR VAGND + 1.0 + 0.05 1) These parameter values cover the complete operating range. Under relaxed operating conditions (room temperature, nominal supply voltage) the typical values can be used for calculation. 2) This parameter includes the sample time (also the additional sample time specified by STC), the time to determine the digital result and the time to load the result register with the conversion result. Values for the basic clock tADCI depend on programming. 3) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 500 µs. Result below 10% (66H). 4) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10 µs. This function is influenced by leakage current, in particular at high temperature. Result above 80% (332H). 5) TUE is tested at VAREF = VDDPA = 5.0 V, VAGND = 0 V. It is verified by design for all other voltages within the defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the measurement time. 6) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. Data Sheet 97 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters RSource V AIN R AIN, On C AINT - C AINS C Ext A/D Converter CAINS MCS05570 Figure 16 Data Sheet Equivalent Circuitry for Analog Inputs 98 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Sample time and conversion time of the XC238xA’s A/D converters are programmable. The timing above can be calculated using Table 19. The limit values for fADCI must not be exceeded when selecting the prescaler value. Table 19 A/D Converter Computation Table GLOBCTR.5-0 (DIVA) A/D Converter Analog Clock fADCI INPCRx.7-0 (STC) 000000B fSYS fSYS / 2 fSYS / 3 fSYS / (DIVA+1) fSYS / 63 fSYS / 64 00H 000001B 000010B : 111110B 111111B 01H 02H : FEH FFH Sample Time1) tS tADCI × 2 tADCI × 3 tADCI × 4 tADCI × (STC+2) tADCI × 256 tADCI × 257 1) The selected sample time is doubled if broken wire detection is active (due to the presampling phase). Converter Timing Example A: Assumptions: Analog clock Sample time fSYS fADCI tS = 80 MHz (i.e. tSYS = 12.5 ns), DIVA = 03H, STC = 00H = fSYS / 4 = 20 MHz, i.e. tADCI = 50 ns = tADCI × 2 = 100 ns Conversion 10-bit: tC10 = 13 × tADCI + 2 × tSYS = 13 × 50 ns + 2 × 12.5 ns = 0.675 μs Conversion 8-bit: tC8 = 11 × tADCI + 2 × tSYS = 11 × 50 ns + 2 × 12.5 ns = 0.575 μs Converter Timing Example B: Assumptions: Analog clock Sample time fSYS fADCI tS = 40 MHz (i.e. tSYS = 25 ns), DIVA = 02H, STC = 03H = fSYS / 3 = 13.3 MHz, i.e. tADCI = 75 ns = tADCI × 5 = 375 ns Conversion 10-bit: tC10 = 16 × tADCI + 2 × tSYS = 16 × 75 ns + 2 × 25 ns = 1.25 μs Conversion 8-bit: tC8 Data Sheet = 14 × tADCI + 2 × tSYS = 14 × 75 ns + 2 × 25 ns = 1.10 μs 99 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.4 System Parameters The following parameters specify several aspects which are important when integrating the XC238xA into an application system. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 20 Various System Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition ΔTJ ≤ 10 °C Short-term deviation of internal clock source frequency1) ΔfINT CC -1 − 1 % Internal clock source frequency fINT CC 4.8 5.0 5.2 MHz Wakeup clock source frequency2) fWU CC 400 − 700 kHz FREQSEL= 00 210 − 390 kHz FREQSEL= 01 140 − 260 kHz FREQSEL= 10 110 − 200 kHz FREQSEL= 11 2.2 2.7 ms fWU = 500 kHz − 12 / μs VLV VLV V 5) Startup time from poweron with code execution from Flash tSPO CC 1.8 Startup time from stopover tSSO CC 11 / fWU3) mode with code execution from PSRAM Core voltage (PVC) supervision level VPVC CC VLV Supply watchdog (SWD) supervision level VSWD - 0.03 CC fWU3) + 0.07 4) VLV VLV VLV V Lower voltage range5) VLV VLV VLV V Upper voltage range5) - 0.106) - 0.15 + 0.15 + 0.15 1) The short-term frequency deviation refers to a timeframe of a few hours and is measured relative to the current frequency at the beginning of the respective timeframe. This parameter is useful to determine a time span for re-triggering a LIN synchronization. 2) This parameter is tested for the fastest and the slowest selection. The medium selections are not subject to production test - verified by design/characterization Data Sheet 100 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 3) fWU in MHz 4) This value includes a hysteresis of approximately 50 mV for rising voltage. 5) VLV = selected SWD voltage level 6) The limit VLV - 0.10 V is valid for the OK1 level. The limit for the OK2 level is VLV - 0.15 V. Conditions for tSPO Timing Measurement The time required for the transition from Power-On to Base mode is called tSPO. It is measured under the following conditions: Precondition: The pad supply is valid, i.e. VDDPB is above 3.0 V and remains above 3.0 V even though the XC238xA is starting up. No debugger is attached. Start condition: Power-on reset is removed (PORST = 1). End condition: External pin toggle caused by first user instruction executed from FLASH after startup. Conditions for tSSO Timing Measurement The time required for the transition from Stopover to Stopover Waked-Up mode is called tSSO. It is measured under the following conditions: Precondition: The Stopover mode has been entered using the procedure defined in the Programmer’s Guide. Start condition: Pin toggle on ESR pin triggering the startup sequence. End condition: External pin toggle caused by first user instruction executed from PSRAM after startup. Coding of bit fields LEVxV in SWD and PVC Configuration Registers Table 21 Coding of bit fields LEVxV in Register SWDCON0 Code Default Voltage Level 0000B 2.9 V 0001B 3.0 V 0010B 3.1 V 0011B 3.2 V 0100B 3.3 V 0101B 3.4 V 0110B 3.6 V 0111B 4.0 V 1000B 4.2 V Data Sheet Notes1) LEV1V: reset request 101 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 21 Coding of bit fields LEVxV in Register SWDCON0 (cont’d) Code Default Voltage Level Notes1) 1001B 4.5 V LEV2V: no request 1010B 4.6 V 1011B 4.7 V 1100B 4.8 V 1101B 4.9 V 1110B 5.0 V 1111B 5.5 V 1) The indicated default levels are selected automatically after a power reset. Table 22 Coding of Bitfields LEVxV in Registers PVCyCONz Notes1) Code Default Voltage Level 000B 0.95 V 001B 1.05 V 010B 1.15 V 011B 1.25 V 100B 1.35 V LEV1V: reset request 101B 1.45 V LEV2V: interrupt request2) 110B 1.55 V 111B 1.65 V 1) The indicated default levels are selected automatically after a power reset. 2) Due to variations of the tolerance of both the Embedded Voltage Regulators (EVR) and the PVC levels, this interrupt can be triggered inadvertently, even though the core voltage is within the normal range. It is, therefore, recommended not to use the this warning level. Data Sheet 102 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.5 Flash Memory Parameters The XC238xA is delivered with all Flash sectors erased and with no protection installed. The data retention time of the XC238xA’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 23 Flash Parameters Parameter Symbol Values Min. Unit Typ. Max. NPP SR − − 41) − − 12) Flash erase endurance for NSEC SR 10 security pages − − Flash wait states3) NWSFLAS 1 − − 2 − − 3 − − 4 − Parallel Flash module program/erase limit depending on Flash read activity H SR NFL_RD ≤ 1, fSYS ≤ 80 MHz NFL_RD > 1 cycle tRET ≥ 20 years s fSYS ≤ 8 MHz fSYS ≤ 13 MHz fSYS ≤ 17 MHz fSYS > 17 MHz − 4) Erase time per sector/page tER CC − 7 8.0 ms Programming time per page tPR CC − 34) 3.5 ms Data retention time tRET CC 20 − − year s Drain disturb limit NDD SR 32 − − cycle s Data Sheet 103 Note / Test Condition NEr ≤ 1 000 cycles V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 23 Flash Parameters (cont’d) Parameter Number of erase cycles Symbol NEr SR Values Unit Note / Test Condition Min. Typ. Max. − − 15 000 cycle tRET ≥ 5 years; s Valid for up to 64 userselected sectors (data storage) − − 1 000 cycle tRET ≥ 20 years s 1) All Flash module(s) can be erased/programmed while code is executed and/or data is read from only one Flash module or from PSRAM. The Flash module that delivers code/data can, of course, not be erased/programmed. 2) Flash module 3 can be erased/programmed while code is executed and/or data is read from any other Flash module. 3) Value of IMB_IMBCTRL.WSFLASH. 4) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few system clock cycles. This increases the stated durations noticably only at extremely low system clock frequencies. Access to the XC238xA Flash modules is controlled by the IMB. Built-in prefetch mechanisms optimize the performance for sequential access. Flash access waitstates only affect non-sequential access. Due to prefetch mechanisms, the performance for sequential access (depending on the software structure) is only partially influenced by waitstates. Data Sheet 104 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.6 AC Parameters These parameters describe the dynamic behavior of the XC238xA. 4.6.1 Testing Waveforms These values are used for characterization and production testing (except pin XTAL1). Output delay Output delay Hold time Hold time 0.8 V DDP 0.7 V DDP Input Signal (driven by tester) 0.3 V DDP 0.2 V DDP Output Signal (measured) Output timings refer to the rising edge of CLKOUT. Input timings are calculated from the time, when the input signal reaches V IH or V IL, respectively. MCD05556C Figure 17 Input Output Waveforms VLoad + 0.1 V Timing Reference Points V Load - 0.1 V V OH - 0.1 V V OL + 0.1 V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded V OH /V OL level occurs (IOH / IOL = 20 mA). MCA05565 Figure 18 Data Sheet Floating Waveforms 105 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.6.2 Definition of Internal Timing The internal operation of the XC238xA is controlled by the internal system clock fSYS. Because the system clock signal fSYS can be generated from a number of internal and external sources using different mechanisms, the duration of the system clock periods (TCSs) and their variation (as well as the derived external timing) depend on the mechanism used to generate fSYS. This must be considered when calculating the timing for the XC238xA. Phase Locked Loop Operation (1:N) fI N f SYS TCS Direct Clock Drive (1:1) fI N f SYS TCS Prescaler Operation (N:1) fI N f SYS TCS M C_XC2X_CLOCKGEN Figure 19 Generation Mechanisms for the System Clock Note: The example of PLL operation shown in Figure 19 uses a PLL factor of 1:4; the example of prescaler operation uses a divider factor of 2:1. The specification of the external timing (AC Characteristics) depends on the period of the system clock (TCS). Data Sheet 106 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Direct Drive When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is derived directly from the input clock signal CLKIN1: fSYS = fIN. The frequency of fSYS is the same as the frequency of fIN. In this case the high and low times of fSYS are determined by the duty cycle of the input clock fIN. Selecting Bypass Operation from the XTAL11) input and using a divider factor of 1 results in a similar configuration. Prescaler Operation When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 1B), the system clock is derived either from the crystal oscillator (input clock signal XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1): fSYS = fOSC / K1. If a divider factor of 1 is selected, the frequency of fSYS equals the frequency of fOSC. In this case the high and low times of fSYS are determined by the duty cycle of the input clock fOSC (external or internal). The lowest system clock frequency results from selecting the maximum value for the divider factor K1: fSYS = fOSC / 1024. 4.6.2.1 Phase Locked Loop (PLL) When PLL operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B), the on-chip phase locked loop is enabled and provides the system clock. The PLL multiplies the input frequency by the factor F (fSYS = fIN × F). F is calculated from the input divider P (= PDIV+1), the multiplication factor N (= NDIV+1), and the output divider K2 (= K2DIV+1): (F = N / (P × K2)). The input clock can be derived either from an external source at XTAL1 or from the onchip clock source. The PLL circuit synchronizes the system clock to the input clock. This synchronization is performed smoothly so that the system clock frequency does not change abruptly. Adjustment to the input clock continuously changes the frequency of fSYS so that it is locked to fIN. The slight variation causes a jitter of fSYS which in turn affects the duration of individual TCSs. 1) Voltages on XTAL1 must comply to the core supply voltage VDDIM. Data Sheet 107 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the minimum TCS possible under the given circumstances. The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or oscillator), the accumulated jitter is limited. This means that the relative deviation for periods of more than one TCS is lower than for a single TCS (see formulas and Figure 20). This is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO output clock is divided by the output prescaler K2 to generate the system clock signal fSYS. The number of VCO cycles is K2 × T, where T is the number of consecutive fSYS cycles (TCS). The maximum accumulated jitter (long-term jitter) DTmax is defined by: DTmax [ns] = ±(220 / (K2 × fSYS) + 4.3) This maximum value is applicable, if either the number of clock cycles T > (fSYS / 1.2) or the prescaler value K2 > 17. In all other cases for a timeframe of T × TCS the accumulated jitter DT is determined by: DT [ns] = DTmax × [(1 - 0.058 × K2) × (T - 1) / (0.83 × fSYS - 1) + 0.058 × K2] fSYS in [MHz] in all formulas. Example, for a period of 3 TCSs @ 33 MHz and K2 = 4: Dmax = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!) D3 = 5.97 × [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4] = 5.97 × [0.768 × 2 / 26.39 + 0.232] = 1.7 ns Example, for a period of 3 TCSs @ 33 MHz and K2 = 2: Dmax = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!) D3 = 7.63 × [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2] = 7.63 × [0.884 × 2 / 26.39 + 0.116] = 1.4 ns Data Sheet 108 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Acc. jitter DT ns ±9 fSYS = 33 MHz fSYS = 66 MHz fVCO = 66 MHz ±8 ±7 f VCO = 132 MHz ±6 ±5 ±4 ±3 ±2 ±1 0 Cycles T 1 20 40 60 80 100 MC_XC2X_JITTER Figure 20 Approximated Accumulated PLL Jitter Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF. The maximum peak-to-peak noise on the pad supply voltage (measured between VDDPB pin 100 and VSS pin 1) is limited to a peak-to-peak voltage of VPP = 50 mV. This can be achieved by appropriate blocking of the supply voltage as close as possible to the supply pins and using PCB supply and ground planes. Data Sheet 109 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters PLL frequency band selection Different frequency bands can be selected for the VCO so that the operation of the PLL can be adjusted to a wide range of input and output frequencies: Table 24 System PLL Parameters Parameter Symbol Values Min. Unit Typ. Max. − 110 Note / Test Condition VCO output frequency (VCO controlled) fVCO CC 50 − 160 MHz VCOSEL = 01B VCO output frequency (VCO free-running) fVCO CC 10 − 40 MHz VCOSEL = 00B 20 − 80 MHz VCOSEL = 01B 4.6.2.2 100 MHz VCOSEL = 00B Wakeup Clock When wakeup operation is selected (SYSCON0.CLKSEL = 00B), the system clock is derived from the low-frequency wakeup clock source: fSYS = fWU. In this mode, a basic functionality can be maintained without requiring an external clock source and while minimizing the power consumption. 4.6.2.3 Selecting and Changing the Operating Frequency When selecting a clock source and the clock generation method, the required parameters must be carefully written to the respective bit fields, to avoid unintended intermediate states. Many applications change the frequency of the system clock (fSYS) during operation in order to optimize system performance and power consumption. Changing the operating frequency also changes the switching currents, which influences the power supply. To ensure proper operation of the on-chip EVRs while they generate the core voltage, the operating frequency shall only be changed in certain steps. This prevents overshoots and undershoots of the supply voltage. To avoid the indicated problems, recommended sequences are provided which ensure the intended operation of the clock system interacting with the power system. Please refer to the Programmer’s Guide. Data Sheet 110 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.6.3 External Clock Input Parameters These parameters specify the external clock generation for the XC238xA. The clock can be generated in two ways: • • By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2 By supplying an external clock signal – This clock signal can be supplied either to pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain) If connected to CLKIN1, the input signal must reach the defined input levels VIL and VIH. If connected to XTAL1, a minimum amplitude VAX1 (peak-to-peak voltage) is sufficient for the operation of the on-chip oscillator. Note: The given clock timing parameters (t1 … t4) are only valid for an external clock input signal. Note: Operating Conditions apply. Table 25 External Clock Input Characteristics Parameter Symbol Values Min. Oscillator frequency XTAL1 input current absolute value XTAL11) Note / Test Condition Typ. Max. fOSC SR 4 − 40 MHz Input = clock signal 4 − 16 MHz Input = crystal or ceramic resonator − − 20 μA 6 − − ns 6 − − ns − − 8 ns − − 8 ns 0.3 x − − V 4 to 16 MHz − − V 16 to 25 MHz − − V 25 to 40 MHz − 1.7 V 2) |IIL| CC t1 SR Input clock low time t2 SR t3 SR Input clock rise time Input clock fall time t4 SR Input voltage amplitude on VAX1 SR Input clock high time Unit VDDIM 0.4 x VDDIM 0.5 x VDDIM Input voltage range limits for signal on XTAL1 Data Sheet VIX1 SR -1.7 + VDDIM 111 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 1) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by VIX1. 2) Overload conditions must not occur on pin XTAL1. Note: For crystal or ceramic resonator operation, it is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for oscillator operation. The manufacturers of crystals and ceramic resonators offer an oscillator evaluation service. This evaluation checks the crystal/resonator specification limits to ensure a reliable oscillator operation. t1 VOFF t3 0.9 V AX1 0.1 V AX1 VAX1 t2 t4 tOSC = 1/fOSC MC_ EXTCLOCK Figure 21 Data Sheet External Clock Drive XTAL1 112 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.6.4 Pad Properties The output pad drivers of the XC238xA can operate in several user-selectable modes. Strong driver mode allows controlling external components requiring higher currents such as power bridges or LEDs. Reducing the driving power of an output pad reduces electromagnetic emissions (EME). In strong driver mode, selecting a slower edge reduces EME. The dynamic behavior, i.e. the rise time and fall time, depends on the applied external capacitance that must be charged and discharged. Timing values are given for a capacitance of 20 pF, unless otherwise noted. In general, the performance of a pad driver depends on the available supply voltage VDDP. The following table lists the pad parameters. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Data Sheet 113 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 26 is valid under the following conditions: VDDP ≥ 4.5 V; VDDPtyp = 5 V; VDDP ≤ 5.5 V; CL ≥ 20 pF; CL ≤ 100 pF; Table 26 Standard Pad Parameters for Upper Voltage Range Parameter Symbol Maximum output driver current (absolute value)1) IOmax Nominal output driver current (absolute value) IOnom CC CC Rise and Fall times (10% - tRF CC 90%) Values Unit Note / Test Condition Min. Typ. Max. − − 10 mA Strong driver − − 4.0 mA Medium driver − − 0.5 mA Weak driver − − 2.5 mA Strong driver − − 1.0 mA Medium driver − − 0.1 mA Weak driver − − 4.2 + 0.14 x ns Strong driver; Sharp edge − − 11.6 + ns 0.22 x Strong driver; Medium edge − − − − CL CL 20.6 + ns 0.22 x Strong driver; Slow edge CL 23 + 0.6 x ns Medium driver ns Weak driver CL − − 212 + 1.9 x CL 1) The total output current that may be drawn at a given time must be limited to protect the supply rails from damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and ΣIOH) must remain below 50 mA. Data Sheet 114 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 27 is valid under the following conditions: VDDP ≥ 3.0 V; VDDPtyp = 3.3 V; VDDP ≤ 4.5 V; CL ≥ 20 pF; CL ≤ 100 pF; Table 27 Standard Pad Parameters for Lower Voltage Range Parameter Symbol Maximum output driver current (absolute value)1) IOmax Nominal output driver current (absolute value) IOnom CC CC Rise and Fall times (10% - tRF CC 90%) Values Unit Note / Test Condition Min. Typ. Max. − − 10 mA Strong driver − − 2.5 mA Medium driver − − 0.5 mA Weak driver − − 2.5 mA Strong driver − − 1.0 mA Medium driver − − 0.1 mA Weak driver − − 6.2 + 0.24 x ns Strong driver; Sharp edge − − ns Strong driver; Medium edge − − ns Strong driver; Slow edge − − ns Medium driver ns Weak driver CL 24 + 0.3 x CL 34 + 0.3 x CL 37 + 0.65 x CL − − 500 + 2.5 x CL 1) The total output current that may be drawn at a given time must be limited to protect the supply rails from damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and ΣIOH) must remain below 50 mA. Data Sheet 115 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.6.5 External Bus Timing The following parameters specify the behavior of the XC238xA bus interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Bus Interface Performance Limits The output frequency at the bus interface pins is limited by the performance of the output drivers. The fast clock driver (used for CLKOUT) can drive 80-MHz signals, the standard drivers can drive 40-MHz signals Therefore, the speed of the EBC must be limited, either by limiting the system frequency to fSYS ≤ 80 MHz or by adding waitstates so that signal transitions have a minimum distance of 12.5 ns. For a description of the bus protocol and the programming of its variable timing parameters, please refer to the User’s Manual. Table 28 EBC Parameters Parameter Symbol 1) t5 CC t6 CC t7 CC t8 CC t9 CC CLKOUT Cycle Time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time Values Min. Typ. Unit Max. − 1 / fSYS − 2 − 2 − − − − 3 − − 3 Note / Test Condition ns − ns 1) The CLKOUT cycle time is influenced by PLL jitter. For longer periods the relative deviation decreases (see PLL deviation formula). t9 t5 t6 t7 t8 CLKOUT MC_X_EBCCLKOUT Figure 22 Data Sheet CLKOUT Signal Timing 116 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Note: The term CLKOUT refers to the reference clock output signal which is generated by selecting fSYS as the source signal for the clock output signal EXTCLK on pin P2.8 and by enabling the high-speed clock driver on this pin. Variable Memory Cycles External bus cycles of the XC238xA are executed in five consecutive cycle phases (AB, C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles to the respective external module (memory, peripheral, etc.). The duration of the access phase can optionally be controlled by the external module using the READY handshake input. This table provides a summary of the phases and the ranges for their length. Table 29 Programmable Bus Cycle Phases (see timing diagrams) Bus Cycle Phase Parameter Valid Values Unit Address setup phase, the standard duration of this tpAB phase (1 … 2 TCS) can be extended by 0 … 3 TCS if the address window is changed 1 … 2 (5) TCS Command delay phase tpC 0…3 TCS Write Data setup/MUX Tristate phase tpD 0…1 TCS Access phase tpE 1 … 32 TCS Address/Write Data hold phase tpF 0…3 TCS Note: The bandwidth of a parameter (from minimum to maximum value) covers the whole operating range (temperature, voltage) as well as process variations. Within a given device, however, this bandwidth is smaller than the specified range. This is also due to interdependencies between certain parameters. Some of these interdependencies are described in additional notes (see standard timing). Note: Operating Conditions apply; CL = 20 pF. Data Sheet 117 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 30 EBC External Bus Timing for Upper Voltage Range Parameter Symbol Values Unit Min. Typ. Max. Output valid delay for RD, t10 CC WR(L/H) − 7 13 ns t11 CC − 7 14 ns Address output valid delay t12 CC for A23 ... A0 − 8 14 ns Address output valid delay t13 CC for AD15 ... AD0 (MUX mode) − 8 15 ns t14 CC Data output valid delay for t15 CC − 7 13 ns − 8 15 ns Data output valid delay for t16 CC D15 ... D0 (write data, DEMUX mode) − 8 15 ns t20 CC -2 6 8 ns Output hold time for BHE, t21 CC ALE -2 6 10 ns Address output hold time for AD15 ... AD0 t23 CC -3 6 8 ns Output hold time for CS t24 CC t25 CC -3 6 11 ns -3 6 8 ns Input setup time for t30 SR READY, D15 ... D0, AD15 ... AD0 25 15 − ns t31 SR Input hold time READY, D15 ... D0, AD15 ... AD01) 0 -7 − ns Output valid delay for BHE, ALE Output valid delay for CS Note / Test Condition AD15 ... AD0 (write data, MUX mode) Output hold time for RD, WR(L/H) Data output hold time for D15 ... D0 and AD15 ... AD0 1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can change after the rising edge of RD. Data Sheet 118 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 31 EBC External Bus Timing for Lower Voltage Range Parameter Symbol Values Unit Min. Typ. Max. Output valid delay for RD, t10 CC WR(L/H) − 11 20 ns t11 CC − 10 21 ns Address output valid delay t12 CC for A23 ... A0 − 11 22 ns Address output valid delay t13 CC for AD15 ... AD0 (MUX mode) − 10 22 ns t14 CC Data output valid delay for t15 CC − 10 13 ns − 10 22 ns Data output valid delay for t16 CC D15 ... D0 (write data, DEMUX mode) − 10 22 ns t20 CC -2 8 10 ns Output hold time for BHE, t21 CC ALE -2 8 10 ns Address output hold time for AD15 ... AD0 t23 CC -3 8 10 ns Output hold time for CS t24 CC t25 CC -3 8 11 ns -3 8 10 ns Input setup time for t30 SR READY, D15 ... D0, AD15 ... AD0 29 17 − ns t31 SR Input hold time READY, D15 ... D0, AD15 ... AD01) 0 -9 − ns Output valid delay for BHE, ALE Output valid delay for CS Note / Test Condition AD15 ... AD0 (write data, MUX mode) Output hold time for RD, WR(L/H) Data output hold time for D15 ... D0 and AD15 ... AD0 1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can change after the rising edge of RD. Data Sheet 119 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters tpAB tpC tpD tpE tpF CLKOUT t21 t11 ALE t11/ t12/t14 A23-A16, BHE, CSx t24 High Address t20 t10 RD WR(L/H) t31 t13 AD15-AD0 (read) AD15-AD0 (write) t23 Low Address t30 Data In t13 t15 Low Address t25 Data Out MC_X_EBCMUX Figure 23 Data Sheet Multiplexed Bus Cycle 120 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters tpAB tpC tpD tpE tpF CLKOUT t21 t11 ALE t11/ t12/t14 t24 A23-A0, BHE, CSx Address t20 t10 RD WR(L/H) t31 t30 D15-D0 (read) Data In t16 D15-D0 (write) t25 Data Out MC_X_EBCDEMUX Figure 24 Data Sheet Demultiplexed Bus Cycle 121 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.6.5.1 Bus Cycle Control with the READY Input The duration of an external bus cycle can be controlled by the external circuit using the READY input signal. The polarity of this input signal can be selected. Synchronous READY permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal CLKOUT. An asynchronous READY signal puts no timing constraints on the input signal but incurs a minimum of one waitstate due to the additional synchronization stage. The minimum duration of an asynchronous READY signal for safe synchronization is one CLKOUT period plus the input setup time. An active READY signal can be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the next bus cycle is controlled by READY, an active READY signal must be disabled before the first valid sample point in the next bus cycle. This sample point depends on the programmed phases of the next cycle. Data Sheet 122 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters tpD tpE tpRDY tpF CLKOUT t10 t20 RD, WR t31 t30 D15-D0 (read) Data In t25 D15-D0 (write) Data Out t31 t30 READY Synchronous READY Asynchron. Not Rdy t31 t30 t31 t30 READY t31 t30 Not Rdy READY MC_X_EBCREADY Figure 25 READY Timing Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”) a READY-controlled waitstate is inserted (tpRDY), sampling the READY input active at the indicated sampling point (“Ready”) terminates the currently running bus cycle. Note the different sampling points for synchronous and asynchronous READY. This example uses one mandatory waitstate (see tpE) before the READY input value is used. Data Sheet 123 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.6.5.2 External Bus Arbitration If the arbitration signals are enabled, the XC238xA makes its external resources available in response to an arbitration request. Note: Operating Conditions apply. Table 32 Bus Arbitration Timing for Upper Voltage Range Parameter Symbol Values Min. Typ. Unit Max. Input setup time HOLD input t40 SR 23 – ns Output delay rising edge HLDA, BREQ t41 CC -1 13 ns Output delay falling edge HLDA t42 CC -2 14 ns Table 33 Note / Test Condition Bus Arbitration Timing for Lower Voltage Range Parameter Symbol Values Max. Unit Note / Test Condition Input setup time HOLD input t40 SR 28 – ns Output delay rising edge HLDA, BREQ t41 CC -1 19 ns Output delay falling edge HLDA t42 CC -2 21 ns Min. Data Sheet 124 Typ. V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters CLKOUT t40 HOLD t42 HLDA BREQ 2) t10/t14 CSx, RD, WR(L/H) 3) Addr, Data, BHE 1) Figure 26 MC_X_EBCARBREL External Bus Arbitration, Releasing the Bus Notes 1. The XC238xA completes the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to get active. 3. The control outputs will be resistive high (pull-up) after being driven inactive (ALE will be low). Data Sheet 125 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 3) CLKOUT t40 HOLD t41 HLDA t41 BREQ 1) t10/t14 CSx, RD, WR(L/H) 2) t11/ t12/t13/t15/ t16 Addr, Data, BHE MC_X_EBCARBREG Figure 27 External Bus Arbitration, Regaining the Bus Notes 1. This is the last chance for BREQ to trigger the indicated regain sequence. Even if BREQ is activated earlier, the regain sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the XC238xA requesting the bus. 2. The control outputs will be resistive high (pull-up) before being driven inactive (ALE will be low). 3. The next XC238xA-driven bus cycle may start here. Data Sheet 126 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.6.6 Synchronous Serial Interface Timing The following parameters are applicable for a USIC channel operated in SSC mode. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply; CL = 20 pF. Table 34 USIC SSC Master Mode Timing for Upper Voltage Range Parameter Symbol Values Unit Min. Typ. Max. Slave select output SELO t1 CC active to first SCLKOUT transmit edge tSYS − − ns Slave select output SELO t2 CC inactive after last SCLKOUT receive edge tSYS − − ns t3 CC -6 − 9 ns Receive data input setup t4 SR time to SCLKOUT receive edge 31 − − ns t5 SR -4 − − ns Data output DOUT valid time Data input DX0 hold time from SCLKOUT receive edge - 8 1) - 6 1) Note / Test Condition 1) tSYS = 1 / fSYS Table 35 USIC SSC Master Mode Timing for Lower Voltage Range Parameter Symbol Values Unit Min. Typ. Max. Slave select output SELO t1 CC active to first SCLKOUT transmit edge tSYS − − ns Slave select output SELO t2 CC inactive after last SCLKOUT receive edge tSYS − − ns -7 − 11 ns Data output DOUT valid time Data Sheet t3 CC - 10 1) - 9 1) 127 Note / Test Condition V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 35 USIC SSC Master Mode Timing for Lower Voltage Range (cont’d) Parameter Symbol Values Unit Min. Typ. Max. Receive data input setup t4 SR time to SCLKOUT receive edge 40 − − ns t5 SR -5 − − ns Data input DX0 hold time from SCLKOUT receive edge Note / Test Condition 1) tSYS = 1 / fSYS Table 36 USIC SSC Slave Mode Timing for Upper Voltage Range Parameter Symbol Values Unit Min. Typ. Max. t10 SR 7 − − ns Select input DX2 hold after t11 SR last clock input DX1 receive edge1) 7 − − ns Receive data input setup time to shift clock receive edge1) t12 SR 7 − − ns Data input DX0 hold time from clock input DX1 receive edge1) t13 SR 5 − − ns Data output DOUT valid time t14 CC 7 − 33 ns Select input DX2 setup to first clock input DX1 transmit edge1) Note / Test Condition 1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0). Data Sheet 128 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 37 USIC SSC Slave Mode Timing for Lower Voltage Range Parameter Symbol Values Unit Min. Typ. Max. t10 SR 7 − − ns Select input DX2 hold after t11 SR last clock input DX1 receive edge1) 7 − − ns Receive data input setup time to shift clock receive edge1) t12 SR 7 − − ns Data input DX0 hold time from clock input DX1 receive edge1) t13 SR 5 − − ns Data output DOUT valid time t14 CC 8 − 41 ns Select input DX2 setup to first clock input DX1 transmit edge1) Note / Test Condition 1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0). Data Sheet 129 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Master Mode Timing t1 Select Output SELOx t2 Inactive Inactive Active Clock Output SCLKOUT Receive Edge First Transmit Edge Last Receive Edge Transmit Edge t3 t3 Data Output DOUT t4 Data Input DX0 t4 t5 Data valid t5 Data valid Slave Mode Timing t10 Select Input DX2 Clock Input DX1 t11 Inactive Inactive Active Receive Edge First Transmit Edge t12 Data Input DX0 t12 t13 Data valid t 14 Last Receive Edge Transmit Edge t 13 Data valid t14 Data Output DOUT Transmit Edge: with this clock edge, transmit data is shifted to transmit data output. Receive Edge: with this clock edge, receive data at receive data input is latched . Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal. USIC_SSC_TMGX.VSD Figure 28 USIC - SSC Master/Slave Mode Timing Note: This timing diagram shows a standard configuration where the slave select signal is low-active and the serial clock signal is not shifted and not inverted. Data Sheet 130 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters 4.6.7 Debug Interface Timing The debugger can communicate with the XC238xA either via the 2-pin DAP interface or via the standard JTAG interface. Debug via DAP The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply; CL= 20 pF. Table 38 DAP Interface Timing for Upper Voltage Range Parameter DAP0 clock period DAP0 high time DAP0 low time DAP0 clock rise time DAP0 clock fall time DAP1 setup to DAP0 rising edge Symbol t11 SR t12 SR t13 SR t14 SR t15 SR t16 SR Values Unit Note / Test Condition Min. Typ. Max. 251) − − ns 8 − − ns 8 − − ns − − 4 ns − − 4 ns 6 − − ns pad_type= stan dard DAP1 hold after DAP0 rising edge t17 SR 6 − − ns pad_type= stan dard DAP1 valid per DAP0 clock period2) t19 CC 17 20 − ns pad_type= stan dard 1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS. 2) The Host has to find a suitable sampling point by analyzing the sync telegram response. Data Sheet 131 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 39 DAP Interface Timing for Lower Voltage Range Parameter Symbol t11 SR t12 SR t13 SR t14 SR t15 SR t16 SR DAP0 clock period DAP0 high time DAP0 low time DAP0 clock rise time DAP0 clock fall time DAP1 setup to DAP0 rising edge Values Unit Note / Test Condition Min. Typ. Max. 251) − − ns 8 − − ns 8 − − ns − − 4 ns − − 4 ns 6 − − ns pad_type= stan dard DAP1 hold after DAP0 rising edge t17 SR 6 − − ns pad_type= stan dard DAP1 valid per DAP0 clock period2) t19 CC 12 17 − ns pad_type= stan dard 1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS. 2) The Host has to find a suitable sampling point by analyzing the sync telegram response. t 11 0.9 VDDP 0.5 VDDP t12 t15 t13 t 14 0.1 VDDP MC_DAP0 Figure 29 Data Sheet Test Clock Timing (DAP0) 132 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters DAP0 t1 6 t1 7 DAP1 MC_ DAP1_RX Figure 30 DAP Timing Host to Device t1 1 DAP1 t1 9 MC_ DAP1_TX Figure 31 DAP Timing Device to Host Note: The transmission timing is determined by the receiving debugger by evaluating the sync-request synchronization pattern telegram. Data Sheet 133 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Debug via JTAG The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply; CL= 20 pF. Table 40 JTAG Interface Timing for Upper Voltage Range Parameter Symbol Values Min. TCK clock period TCK high time t1 SR t2 SR t3 SR t4 SR t5 SR t6 SR Unit Typ. Max. 50 − − ns 16 − − ns 1) 16 − − ns − − 8 ns − − 8 ns 6 − − ns t7 SR 6 − − ns TDO valid from TCK falling t8 CC edge (propagation delay)3) − 25 29 ns TDO high impedance to valid output from TCK falling edge4)3) t9 CC − 25 29 ns TDO valid output to high impedance from TCK falling edge3) t10 CC − 25 29 ns TDO hold after TCK falling t18 CC edge3) 5 − − ns TCK low time TCK clock rise time TCK clock fall time TDI/TMS setup to TCK rising edge TDI/TMS hold after TCK rising edge Note / Test Condition 2) 1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS. 2) Under typical conditions, the interface can operate at transfer rates up to 20 MHz. 3) The falling edge on TCK is used to generate the TDO timing. 4) The setup time for TDO is given implicitly by the TCK cycle time. Data Sheet 134 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters Table 41 JTAG Interface Timing for Lower Voltage Range Parameter Symbol Values Unit Min. Typ. Max. 501) − − ns 16 − − ns 16 − − ns − t1 SR t2 SR t3 SR t4 SR t5 SR t6 SR − 8 ns − − 8 ns 6 − − ns t7 SR 6 − − ns TDO valid from TCK falling t8 CC edge (propagation delay)3) − 32 36 ns TDO high impedance to valid output from TCK falling edge4)3) t9 CC − 32 36 ns TDO valid output to high impedance from TCK falling edge3) t10 CC − 32 36 ns TDO hold after TCK falling t18 CC edge3) 5 − − ns TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time TDI/TMS setup to TCK rising edge TDI/TMS hold after TCK rising edge Note / Test Condition 2) 1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS. 2) Under typical conditions, the interface can operate at transfer rates up to 20 MHz. 3) The falling edge on TCK is used to generate the TDO timing. 4) The setup time for TDO is given implicitly by the TCK cycle time. Data Sheet 135 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Electrical Parameters t1 0.9 VDDP 0.5 VDDP t2 t5 t3 0.1 VDDP t4 MC_JTAG_TCK Figure 32 Test Clock Timing (TCK) TCK t6 t7 t6 t7 TMS TDI t9 t8 t10 TDO MC_JTAG Figure 33 Data Sheet JTAG Timing 136 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Package and Reliability 5 Package and Reliability The XC2000 Family devices use the package type PG-LQFP (Plastic Green - Low Profile Quad Flat Package). The following specifications must be regarded to ensure proper integration of the XC238xA in its target environment. 5.1 Packaging These parameters specify the packaging rather than the silicon. Table 42 Package Parameters (PG-LQFP-144-13/-23) Parameter Symbol Limit Values Min. Unit Notes Max. Exposed Pad Dimension Ex × Ey – 6.5 × 6.5 mm – Power Dissipation PDISS RΘJA – 1.0 W – – 43 K/W No thermal via1) 34 K/W 4-layer, no pad2) 21 K/W 4-layer, pad3) Thermal resistance Junction-Ambient 1) Device mounted on a 2-layer JEDEC board (according to JESD 51-3) or a 4-layer board without thermal vias; exposed pad not soldered. 2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not soldered. 3) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered to the board. Note: To improve the EMC behavior, it is recommended to connect the exposed pad to the board ground, independent of the thermal requirements. Board layout examples are given in an application note. Package Compatibility Considerations The XC238xA is a member of the XC2000 Family of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies. Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pin-count but for different device types. In particular, the size of the Exposed Pad (if present) may vary. If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration. Data Sheet 137 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Package and Reliability H 0.5 0.6 ±0.15 0.08 C 144x COPLANARITY 17.5 7˚ MAX. +0.05 0.15 -0 .06 1.6 MAX. 0.1±0.05 STAND OFF 1.4 ±0.05 Package Outlines C SEATING PLANE 0.22 ±0.05 0.08 M A-B D C 144x 22 20 Bottom View 0.2 A-B D 144x 1) 0.2 A-B D H 4x Ex Ey 22 B 20 A 1) D 144 144 1 1 Index Marking Exposed Diepad 1) Does not include plastic or metal protrusion of 0.25 max. per side Figure 34 Index Marking PG-LQFP-144-4, -13-PO V08 PG-LQFP-144-13/-23 (Plastic Green Thin Quad Flat Package) All dimensions in mm. You can find complete information about Infineon packages, packing and marking in our Infineon Internet Page “Packages”: http://www.infineon.com/packages Data Sheet 138 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Package and Reliability 5.2 Thermal Considerations When operating the XC238xA in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated depends on the package and its integration into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 150 °C. The difference between junction temperature and ambient temperature is determined by ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA The internal power consumption is defined as PINT = VDDP × IDDP (switching current and leakage current). The static external power consumption caused by the output drivers is defined as PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL) The dynamic external power consumption caused by the output drivers (PIODYN) depends on the capacitive load connected to the respective pins and their switching frequencies. If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation: • • • • Reduce VDDP, if possible in the system Reduce the system frequency Reduce the number of output pins Reduce the load on active output drivers Data Sheet 139 V2.12, 2014-06 XC2385A, XC2387A XC2000 Family / Base Line Package and Reliability 5.3 Quality Declarations The operation lifetime of the XC238xA depends on the applied temperature profile in the application. For a typical example, please refer to Table 44; for other profiles, please contact your Infineon counterpart to calculate the specific lifetime within your application. Table 43 Quality Parameters Parameter Symbol Operation lifetime Table 44 Unit Note / Test Condition 20 a See Table 44 and Table 45 − 2 000 V EIA/JESD22A114-B − 3 − JEDEC J-STD-020C Typ. Max. − − − MSL CC − tOP CC ESD susceptibility VHBM according to Human Body SR Model (HBM) Moisture sensitivity level Values Min. Typical Usage Temperature Profile Operating Time (Sum = 20 years) Operating Temperat. Notes 1 200 h TJ = 150°C TJ = 125°C TJ = 110°C TJ = 100°C TJ = 0…10°C, …, Normal operation 3 600 h 7 200 h 12 000 h 7 × 21 600 h Table 45 Normal operation Normal operation Normal operation Power reduction 60…70°C Long Time Storage Temperature Profile Operating Time (Sum = 20 years) Operating Temperat. Notes 2 000 h Normal operation 151 200 h TJ = 150°C TJ = 125°C TJ = 110°C TJ ≤ 150°C Data Sheet 140 16 000 h 6 000 h Normal operation Normal operation No operation V2.12, 2014-06 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG