82C86H ® CMOS Octal Bus Transceiver June 2004 Features Description • Full Eight Bit Bi-Directional Bus Interface The Intersil 82C86H is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C86H provides a full eight-bit bi-directional bus interface in a 20 lead package. The Transmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C86H has gated inputs, eliminating the need for pull-up/pull-down resistors and reducing overall system operating power dissipation. • Industry Standard 8286 Compatible Pinout • High Drive Capability - B Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA - A Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA • Three-State Outputs • Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max. • Gated Inputs - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors Ordering Information PART NUMBER • Single 5V Power Supply 8MHz • Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA ID82C86H PACKAGE TEMP. RANGE PKG DWG. # 20 Ld CERDIP -40oC to +85oC F20.3 • Operating Temperature Range - ID82C86H . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Pinout 82C86H (CERDIP) TOP VIEW TRUTH TABLE T OE A B X H Hi-Z Hi-Z A0 1 20 VCC H L I O A1 2 19 B0 L L O I A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 OE 9 12 B7 GND 10 11 T H L I O X Hi-Z = Logic One = Logic Zero = Input Mode = Output Mode = Don’t Care = High Impedance PIN NAMES PIN DESCRIPTION A0-A7 Local Bus Data I/O Pins B0-B7 System Bus Data I/O Pins T OE Transmit Control Input Active Low Output Enable CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2004. All Rights Reserved 1 FN2977.2 82C86H Functional Diagram Decoupling Capacitors B0 The transient current required to charge and discharge the 300pF load capacitance specified in the 82C86H/87H data sheet is determined by: A1 B1 I = C L ( dv ⁄ dt ) A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A0 (EQ. 1) Assuming that all outputs change state at the same time and that dv/dt is constant; ( VCC × 80% ) I = C L ------------------------------------tR ⁄ tF (EQ. 2) where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight outputs. I = ( 80 × 300 × 10 – 12 ) × ( 5.0V × 0.8 ) ⁄ ( 20 × 10 –9 ) (EQ. 3) = 480mA OE T VCC VCC P Gated Inputs P N During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between VCC and GND when the signal is at or near the input switching threshold. Additionally, if the driving signal becomes high impedance (“float” condition), it could create an indeterminate logic state at the inputs and cause a disruption in device operation. STB P INTERNAL DATA DATA IN N N FIGURE 1. 82C82/83H VCC The Intersil 82C8X series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for the 82C86H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power supply pins by turning off the upper P-channel and lower N-channel (See Figures 1 and 2). No current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level internal to the device. P OE P INTERNAL DATA DATA IN VCC N P N D.C. input voltage levels can also cause an increase in ICC if these input levels approach the minimum VIH or maximum VIL conditions. This is due to the operation of the input circuitry in its linear operating region (partially conducting state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the transparent mode (STB = logic one). ICC remains below the maximum ICC standby specification of 10µA during the time inputs are disabled, thereby greatly reducing the average power dissipation of the 82C8X series devices. N FIGURE 2. 82C86H/87H GATED INPUTS This current spike may cause a large negative voltage spike on VCC which could cause improper operation of the device. To filter out this noise, it is recommended that a 0.1µF ceramic disc capacitor be placed between VCC and GND at each device, with placement being as near to the device as possible. 2 82C86H Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) Operating Conditions CERDIP Package . . . . . . . . . . . . . . . . 70 16 Maximum Storage Temperature Range . . . . . . . . . -65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to +85oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications VCC = 5.0V ± 10%; TA = -40oC to +85oC SYMBOL VIH PARAMETER Logical One Input Voltage MAX UNITS 2.0 - V C82C86H, I82C86H V M82C86H (Note 1) 2.2 VIL Logical Zero Input Voltage VOH Logical One Output Voltage - 0.8 TEST CONDITIONS V B Outputs 3.0 V IOH = -8mA A Outputs 3.0 V IOH = -4mA VCC -0.4 V IOH = -100µA A or B Outputs VOL MIN Logical Zero Output Voltage B Outputs 0.45 V IOL = 20mA A Outputs 0.45 V IOL = 12mA II Input Leakage Current -10.0 10.0 µA VIN = GND or VCC DIP Pins 9, 11 IO Output Leakage Current -10.0 10.0 µA VO = GND or VCC, OE Š Š≥ VCC -0.5V DIP Pins 1 - 8, 12 - 19 VIN = VCC or GND, VCC = 5.5V, Outputs Open ICCSB Standby Power Supply Current - 10 µA ICCOP Operating Power Supply Current - 1 mA/MHz TA = +25oC, Typical (See Note 2) NOTES: 1. VIH is measured by applying a pulse of magnitude = VIH(MIN) to one data input at a time and checking the corresponding device output for a valid logical “1” during valid input high time. Control pins (T, OE) are tested separately with all device data input pins at VCC -0.4 2. Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0µs read/write cycle time = 1mA). Capacitance SYMBOL CIN TA = +25oC PARAMETER TYPICAL UNITS B Inputs 18 pF A Inputs 14 pF TEST CONDITIONS Input Capacitance 3 Freq = 1MHz, all measurements are referenced to device GND 82C86H AC Electrical Specifications VCC = 5.0V ± 10%; Freq = 1MHz: TA = -40oC to +85oC SYMBOL (1) PARAMETER TIVOV MIN MAX UNITS Input to Output Delay TEST CONDITIONS Notes 1, 2 Inverting 5 30 ns Non-Inverting 5 32 ns (2) TEHTV Transmit/Receive Hold Time 5 - ns Notes 1, 2 (3) TTVEL Transmit/Receive Setup Time 10 - ns Notes 1, 2 (4) TEHOZ Output Disable Time 5 30 ns Notes 1, 2 (5) TELOV Output Enable Time 10 50 ns Notes 1, 2 (6) TR, TF Input Rise/Fall Times - 20 ns Notes 1, 2 (7) TEHEL Minimum Output Enable High Time Note 3 82C86H 30 - ns 82C86H-5 35 - ns NOTES: 1. All AC parameters tested as per test circuits and definitions in timing waveforms and test load circuits. Input rise and fall times are driven at 1ns/V. 2. Input test signals must switch between VIL - 0.4V and VIH +0.4V. 3. A system limitation only when changing direction. Not a measured parameter. Timing Waveform TR, TF (6) INPUTS 2.0V 0.8V TEHEL (7) OE (4) TEHOZ (1) TIVOV TELOV (5) VOH -0.1V OUTPUTS VOL +0.1V TEHTV (2) T NOTE: All timing measurements are made at 1.5V unless otherwise noted. 4 3.0V 0.45V TTVEL (3) 82C86H Test Load Circuits A SIDE OUTPUTS TIVOV LOAD CIRCUIT TELOV OUTPUT HIGH ENABLE LOAD CIRCUIT TELOV OUTPUT LOW ENABLE LOAD CIRCUIT 1.5V 1.5V 2.36V 160Ω TEST POINT OUTPUT 100pF (SEE NOTE) 375Ω 2.36V 91Ω TEST POINT OUTPUT TEHOZ OUTPUT LOW/HIGH DISABLE LOAD CIRCUIT TEST POINT OUTPUT 100pF (SEE NOTE) 160Ω 100pF (SEE NOTE) TEST POINT OUTPUT 50pF (SEE NOTE) B SIDE OUTPUTS TIVOV LOAD CIRCUIT TELOV OUTPUT HIGH ENABLE LOAD CIRCUIT TELOV OUTPUT LOW ENABLE LOAD CIRCUIT 1.5V 1.5V 2.27V 91Ω OUTPUT 180Ω TEST POINT 300pF (SEE NOTE) OUTPUT TEHOZ OUTPUT LOW/HIGH DISABLE LOAD CIRCUIT 2.27V 51Ω TEST POINT OUTPUT 300pF (SEE NOTE) 300pF (SEE NOTE) NOTE: Includes jig and stray capacitance. Die Characteristics DIE DIMENSIONS: 138.6 x 155.5 x 19 ± 1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ 5 91Ω TEST POINT OUTPUT 50pF (SEE NOTE) TEST POINT 82C86H Metallization Mask Layout 82C86H A2 A1 A0 VCC B0 B1 B2 A3 B3 A4 B4 A5 B5 A6 A7 OE GND T B7 B6 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6