AK8858

[AK8858]
AK8858
PS/SD Multi Format Video Decoder
Overview
The AK8858 is a single-chip digital video decoder for composite, s-video, 525i/625i component and 525p/625p
component video signals. Its output data is in YCbCr and RGB format. Its pixel clock is generated internally and
synchronized with the input signal. Microprocessor access is via I2C interface.
Features
■ Decodes composite and S-Video signals NTSC/ PAL-B, D, G, H, I, N, Nc, M, 60 /SECAM
■ Decode 525i / 625i YPbPr component video signals
■ Decode 525p / 625p YPbPr component video signals
■ 10 input channel
■ 10-bit 54MHz ADC 2 channel
■ Internally built PLL
■ Internal analog bandwidth filter
■ Programmable Gain Amp (PGA) (-3.25dB~10dB)
■ Adaptive automatic Gain Control (AGC)
■ Auto Color Control (Composite and S-Video signals)
■ Image adjustment (Contrast, Brightness, Saturation, HUE, Sharpness)
■ Automatic input signal detection (NTSC/ PAL/ SECAM detect、Interlace/ Progressive detect)
■ Adaptive 2-D Y/C separation
■ Output data format
YCbCr 4:2:2 or RGB 8:8:8
■ Output interface
(YCbCr)
Interlace: ITU-R BT.656 (8bit 27MHz) and 16bit 13.5MHz with EAV/ SAV
Progressive: 16bit 27MHz and 8bit 54MHz with EAV/ SAV
(RGB)
Interlace: 8bit:8bit:8bit 13.5MHz with EAV/ SAV
Progressive: 8bit:8bit:8bit 27MHz with EAV/ SAV
*EAV/ SAV output can be disabled via register
■ HD, VD, DVALID and FIELD (VD, DVALID, FIELD can be select up to 2 output via register setting)
■ Closed Caption / WSS / CGMS-A signal decoding (output via register).
■ Macrovision signal detection (Rovi certification)
■ I2C control
■ Powerdown function
■ Internal VREF
■ Core supply voltage: 1.70∼2.00V
■ I/O power supply: 1.70∼3.60V
■ Operating temperature: −40°C∼105°C
■ 80-pin LQFP package (12.0mm x 12.0mm)
(Notice) This device is protected by U.S. patent number 6,600,873 and other intellectual property rights.
MS1230-E-01
2011/7
-1-
[AK8858]
Features
[1] Functional block diagram................................................................................................................................................ 6
[2] Pin assignment................................................................................................................................................................. 7
[3] Pin function description .................................................................................................................................................. 8
[3.1] Pin function................................................................................................................................................................ 8
[3.2] Output pin state ....................................................................................................................................................... 11
[4] Electrical specifications ................................................................................................................................................ 11
[4.1] Absolute maximum ratings .................................................................................................................................... 11
[4.2] Recommended operating conditions .................................................................................................................... 11
[4.3] DC characteristics ................................................................................................................................................... 12
[4.4] Analog characteristics ............................................................................................................................................ 12
[4.4.1] Input Range ....................................................................................................................................................... 12
[4.4.2] AAF (Anti-Aliasing Filter) ................................................................................................................................. 12
[4.4.3] Analog PGA ....................................................................................................................................................... 12
[4.4.4] ADC .................................................................................................................................................................... 13
[4.4.5] Current consumption ....................................................................................................................................... 13
[4.4.6] Crystal circuit block.......................................................................................................................................... 14
[5] AC Timing ....................................................................................................................................................................... 15
[5.1] Clock input............................................................................................................................................................... 15
[5.2] Clock output (DTCLK output) ................................................................................................................................. 15
[5.3] Output data timing................................................................................................................................................... 16
[5.4] Reset pulse .............................................................................................................................................................. 16
[5.5] Power-down release sequence .............................................................................................................................. 17
[5.6] Power-on sequence................................................................................................................................................. 18
[5.7] I2C bus input timing ................................................................................................................................................ 19
[5.7.1] Timing 1 ............................................................................................................................................................. 19
[5.7.2] Timing 2 ............................................................................................................................................................. 19
[6] Functional overview....................................................................................................................................................... 20
[7] Functional description................................................................................................................................................... 21
[7.1] Analog circuit description ...................................................................................................................................... 21
[7.1.1] CVBS signal decoding...................................................................................................................................... 22
[7.1.2] S(Y/C) video signal decoding........................................................................................................................... 22
[7.1.3] 525i/625i YPbPr component video signal decoding ...................................................................................... 22
[7.1.4] 525p/625p YPbPr component video signal decoding .................................................................................... 22
[7.2] Analog Interface ...................................................................................................................................................... 23
[7.3] Input Clock mode .................................................................................................................................................... 23
[7.4] Analog clamp circuit ............................................................................................................................................... 24
[7.5] Input video signal categorization........................................................................................................................... 27
MS1230-E-01
2011/7
-2-
[AK8858]
[7.6] Auto detection mode of input signal ..................................................................................................................... 29
[7.7] Auto detection restriction of input signal.............................................................................................................. 30
[7.8] Output data blanking interval ................................................................................................................................. 31
[7.9] Output data code Min/Max setting ......................................................................................................................... 32
[7.10] Output Pin state..................................................................................................................................................... 32
[7.11] Slice function ......................................................................................................................................................... 33
[7.12] VBI period decode data......................................................................................................................................... 34
[7.13] VLOCK mechanism ............................................................................................................................................... 34
[7.14] Adjustment of Y and C timing .............................................................................................................................. 35
[7.15] Adjustment of active video start position ........................................................................................................... 35
[7.16] PGA......................................................................................................................................................................... 36
[7.17] AGC (Auto Gain Control) ...................................................................................................................................... 37
[7.18] ACC (Auto Color Control) ..................................................................................................................................... 38
[7.19] Y/C separation ....................................................................................................................................................... 38
[7.20] C Filter .................................................................................................................................................................... 39
[7.21] Clock generation ................................................................................................................................................... 40
[7.21.1] Line-locked clock mode ................................................................................................................................. 40
[7.21.2] Frame-locked mode ........................................................................................................................................ 40
[7.21.3] Fixed-clock mode............................................................................................................................................ 40
[7.21.4] Auto transition mode ...................................................................................................................................... 40
[7.22] Digital Pixel Interpolar........................................................................................................................................... 41
[7.23] Phase correction ................................................................................................................................................... 41
[7.24] No-signal output .................................................................................................................................................... 41
[7.25] Output data format ................................................................................................................................................ 42
[7.25.1] YCbCr 8bit output format ............................................................................................................................... 42
[7.25.2] YCbCr 16bit output format ............................................................................................................................. 42
[7.25.3] RGB 24bit output format ................................................................................................................................ 43
[7.26] Output Interface..................................................................................................................................................... 44
[7.26.1] Interface with EAV/SAV .................................................................................................................................. 44
[7.26.2] Interface used timing signal........................................................................................................................... 48
[7.27] Sync separation, sync detection, black-level detection and digital pedestal clamp ....................................... 52
[7.28] Color killer.............................................................................................................................................................. 53
[7.29] Image quality adjustment ..................................................................................................................................... 54
[7.29.1] Contrast adjustment ....................................................................................................................................... 54
[7.29.2] Brightness adjustment ................................................................................................................................... 54
[7.29.3] Color saturation adjustment .......................................................................................................................... 55
[7.29.4] HUE adjustment .............................................................................................................................................. 55
[7.29.5] Sharpness adjustment ................................................................................................................................... 56
[7.29.6] Luminance bandwidth adjustment ................................................................................................................ 57
MS1230-E-01
2011/7
-3-
[AK8858]
[7.29.7] Sepia output .................................................................................................................................................... 57
[7.29.8] U/ V Filter ......................................................................................................................................................... 58
[7.30] VBI information decoding ..................................................................................................................................... 59
[7.31] Internal status indicators Register....................................................................................................................... 60
[7.31.1] No signal detect .............................................................................................................................................. 60
[7.31.2] VLOCK status.................................................................................................................................................. 60
[7.31.3] Interlace Status ............................................................................................................................................... 60
[7.31.4] Status of color killer operation ...................................................................................................................... 60
[7.31.5] Status of clock mode ...................................................................................................................................... 60
[7.31.6] Luminance over flow ...................................................................................................................................... 60
[7.31.7] Chrominance over flow .................................................................................................................................. 61
[7.31.8] Field status ...................................................................................................................................................... 61
[7.31.9] AGC status ...................................................................................................................................................... 61
[7.32] Macrovision signal detection ............................................................................................................................... 61
[7.32.1] Macrovision Color Stripe Cancel................................................................................................................... 61
[7.33] Auto detection result of input video signal ......................................................................................................... 62
[8] Device control interface ................................................................................................................................................ 63
[8.1] I2C bus SLAVE Address ......................................................................................................................................... 63
[8.2] I2C control sequence .............................................................................................................................................. 63
[8.2.1] Write sequence ................................................................................................................................................. 63
[8.2.2] Read sequence.................................................................................................................................................. 63
[9] Register Definitions ....................................................................................................................................................... 64
[9.1] Register setting overview ....................................................................................................................................... 65
[9.1.1] Input Channel Select Register (R/W) [Sub Address 0x00]............................................................................. 65
[9.1.2] Clamp Control 1 Register (R/W) [Sub Address 0x01] .................................................................................... 66
[9.1.3] Clamp Control 2 Register (R/W) [Sub Address 0x02] .................................................................................... 67
[9.1.4] Miscellaneous Setting Register (R/W) [Sub Address 0x03] .......................................................................... 68
[9.1.5] Input Video Standard Register (R/W) [Sub Address 0x04] ............................................................................ 69
[9.1.6] Output Format Register (R/W) [Sub Address 0x05] ....................................................................................... 70
[9.1.7] NDMODE Register (R/W) [Sub Address 0x06] ................................................................................................ 71
[9.1.8] Output Control Register (R/W) [Sub Address 0x07] ...................................................................................... 72
[9.1.9] Output Data Start and Delay Control Register (R/W) [Sub Address 0x08]................................................... 73
[9.1.10] Output Data Format Register (R/W) [Sub Address 0x09] ............................................................................ 74
[9.1.11] AGC & ACC Control Register (R/W) [Sub Address 0x0A] ........................................................................... 75
[9.1.12] Control 0 Register (R/W) [Sub Address 0x0B].............................................................................................. 76
[9.1.13] Control 1 Register (R/W) [Sub Address 0x0C].............................................................................................. 77
[9.1.14] Control 2 Register (R/W) [Sub Address 0x0D].............................................................................................. 78
[9.1.15] PGA1 Control Register (R/W) [Sub Address 0x0E] ...................................................................................... 79
[9.1.16]PGA2 Control Register (R/W) [Sub Address 0x0F] ....................................................................................... 79
MS1230-E-01
2011/7
-4-
[AK8858]
[9.1.17] Pedestal Level Control Register (R/W) [Sub Address 0x10] ....................................................................... 80
[9.1.18] Color Killer Control Register (R/W) [Sub Address 0x11] ............................................................................. 81
[9.1.19] Contrast Control Register (R/W) [Sub Address 0x12] ................................................................................. 82
[9.1.20]Brightness Control Register (R/W) [Sub Address 0x13]............................................................................... 82
[9.1.21] Image Control Register (R/W) [Sub Address 0x14]...................................................................................... 83
[9.1.22] Saturation / U Tone Control Register (R/W) [Sub Address 0x15] ............................................................... 84
[9.1.23] V Tone Control Register (R/W) [Sub Address 0x16] .................................................................................... 84
[9.1.24] HUE Control Register (R/W) [Sub Address 0x17]......................................................................................... 85
[9.1.25] High Slice Data Set Register (R/W) [Sub Address 0x18] ............................................................................. 85
[9.1.26] Low Slice Data Set Register (R/W) [Sub Address 0x19] .............................................................................. 85
[9.1.27] Request VBI Information Register (R/W) [Sub Address 0x1A].................................................................... 86
[9.1.28] Sub Address 0x1B~0x21 “Reserved Register (R/W)” .................................................................................. 87
[9.1.29] Status 1 Register (R) [Sub Address 0x22] .................................................................................................... 87
[9.1.30] Status 2 Register (R) [Sub Address 0x23] .................................................................................................... 88
[9.1.31] Macrovision Status Register (R) [Sub Address 0x24] ................................................................................. 89
[9.1.32] Input Video Status Register (R) [Sub Address 0x25] ................................................................................... 90
[9.1.33] Closed Caption1 Register (R) [Sub Address 0x26] ...................................................................................... 91
[9.1.34] Closed Caption2 Register (R) [Sub Address 0x27] ...................................................................................... 91
[9.1.35] WSS 1 Register (R) [Sub Address 0x28] ....................................................................................................... 91
[9.1.36] WSS 2 Register (R) [Sub Address 0x29] ....................................................................................................... 91
[9.1.37.] Extended Data 1 Register (R) [Sub Address 0x2A] ..................................................................................... 91
[9.1.38.] Extended Data 2 Register (R) [Sub Address 0x2B]..................................................................................... 91
[9.1.39] VBID 1 Register (R) [Sub Address 0x2C] ...................................................................................................... 91
[9.1.40] VBID 2 Register (R) [Sub Address 0x2D] ...................................................................................................... 91
[9.1.41] Device and Revision ID Register (R) [Sub Address 0x2E]........................................................................... 92
[10] System connection example....................................................................................................................................... 93
[11] Package ........................................................................................................................................................................ 94
[12] Marking ......................................................................................................................................................................... 95
[13] Revision history ........................................................................................................................................................... 96
MS1230-E-01
2011/7
-5-
[AK8858]
[1] Functional block diagram
TEST0 TEST1
XTI
XTO
SELA SDA
Test Logic
AIN1
AIN2
AIN6
HD
VD_FLD
AIN4
AIN5
VBI
Decoding
Sync
Separation
AIN3
OE
Microprocessor
Interface
Timing Controller
Digital PLL
Clock Module
SCL PDN RSTN
CLAMP
AAF
APGA1
MUX
AIN7
CLAMP
SH
AIN9
CLAMP
Luminance
Process
DPGA1
Decimation
Filter
AAF
AIN8
10-bit
ADC1
APGA2
AAF
10-bit
ADC2
YC
Separation
U Process
YUV
to
RGB
DPGA2
V Process
Output
Buffer
DVAL_FLD
NSIG
DTCLK
DATA[23:0]
AIN10
Reference
ATIO
VRP
VCOM VRN
AVDD AVSS DVDD DVSS PVDD1 PVDD2
IREF
MS1230-E-01
2011/7
-6-
[AK8858]
[2] Pin assignment
DATA0
PVDD1
DVAL_FLD
HD
VD_FLD
TEST0
DVSS
TEST1
OE
NSIG
PDN
RSTN
PVDD2
SCL
SDA
AVDD
SELA
XTI
XTO
AVSS
80-pin LQFP package (12.0mm x 12.0mm)
AVSS
DVSS
AIN1
AVDD
DVDD
DATA1
AIN2
AVSS
AIN3
DATA2
DATA3
DATA4
AVDD
AIN4
PVDD1
DVSS
ATIO
AIN5
VCOM
DATA5
DATA6
DATA7
AIN6
AVSS
PVDD1
DTCLK
IREF
AVDD
DVSS
DATA8
AIN7
VRP
AIN8
DATA9
DATA10
DATA11
VRN
AIN9
DATA12
DVDD
MS1230-E-01
DVSS
PVDD1
DATA13
DATA14
DATA15
PVDD1
DATA17
DATA16
DVSS
DATA18
DATA20
DATA19
DATA21
DATA22
DATA23
DVSS
PVDD1
AVDD
AVSS
AIN10
1
2011/7
-7-
[AK8858]
[3] Pin function description
[3.1] Pin function
Pin
Symbol
No.
1
AVSS
P/S I/O
A
Functional Description
G
Analog ground pin.
Analog video signal input pin.Connect via 0.033μF capacitor and voltage-split
2
AIN10
A
I
ting resistors. If not used, connect to NC.
3
AVDD
A
P
Analog power supply pin.
4
DVSS
D
G
Digital ground pin.
5
PVDD1 P1 P
I/O power supply pin.
O
DATA output pin. Used as output pin in RGB 8:8:8 output.(*1)
6
DATA23 P1
(I/O) If test mode, it is I/O pin.
O
DATA output pin. Used as output pin in RGB 8:8:8 output.(*1)
7
DATA22 P1
(I/O) If test mode, it is I/O pin.
O
DATA output pin. Used as output pin in RGB 8:8:8 output.(*1)
8
DATA21 P1
(I/O) If test mode, it is I/O pin.
O
DATA output pin. Used as output pin in RGB 8:8:8 output.(*1)
9
DATA20 P1
(I/O) If test mode, it is I/O pin.
O
DATA output pin. Used as output pin in RGB 8:8:8 output.(*1)
10 DATA19 P1
(I/O) If test mode, it is I/O pin.
O
DATA output pin. Used as output pin in RGB 8:8:8 output.(*1)
11 DATA18 P1
(I/O) If test mode, it is I/O pin.
12 DVSS
D
G
Digital ground pin.
13 PVDD1 P1 P
I/O power supply pin.
O
DATA output pin. Used as output pin in RGB 8:8:8 output.(*1)
14 DATA17 P1
(I/O) If test mode, it is I/O pin.
O
DATA output pin. Used as output pin in RGB 8:8:8 output.(*1)
15 DATA16 P1
(I/O) If test mode, it is I/O pin.
DATA output pin. Used as output pin in 16-bit output and RGB 8:8:8 output
O
16 DATA15 P1
mode.(*1)
(I/O)
If test mode, it is I/O pin.
DATA output pin. Used as output pin in 16-bit output and RGB 8:8:8 output
O
17 DATA14 P1
mode.(*1)
(I/O)
If test mode, it is I/O pin.
DATA output pin. Used as output pin in 16-bit output and RGB 8:8:8 output
O
18 DATA13 P1
mode.(*1)
(I/O)
If test mode, it is I/O pin.
19 DVSS
D
G
Digital ground pin.
20 PVDD1 P1 P
I/O power supply pin.
21 DVDD
D
P
Digital power supply pin.
DATA output pin. Used as output pin in 16-bit output and RGB 8:8:8 output
O
22 DATA12 P1
mode.(*1)
(I/O)
If test mode, it is I/O pin.
DATA output pin. Used as output pin in 16-bit output and RGB 8:8:8 output
O
23 DATA11 P1
mode.(*1)
(I/O)
If test mode, it is I/O pin.
DATA output pin. Used as output pin in 16-bit output and RGB 8:8:8 output
O
24 DATA10 P1
mode.(*1)
(I/O)
If test mode, it is I/O pin.
DATA output pin. Used as output pin in 16-bit output and RGB 8:8:8 output
25 DATA9
P1 O
mode.(*1)
DATA output pin. Used as output pin in 16-bit output and RGB 8:8:8 output
26 DATA8
P1 O
mode.(*1)
[Power supply] A: AVDD, D: DVDD, P1: PVDD1, P2: PVDD2
[Input/Output] I: intput pin, O: output pin, I/O: input/output pin, P: power supply pin, G: ground connection pin
(*1)
See {[3.2] Output pin state} for relation of output to OE/PDN and RSTN pin status.
MS1230-E-01
2011/7
-8-
[AK8858]
Pin
No.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
P/S I/O
DVSS
DTCLK
PVDD1
DATA7
DATA6
DATA5
DVSS
PVDD1
DATA4
DATA3
DATA2
DATA1
DVDD
DVSS
PVDD1
DATA0
D
P1
P1
P1
P1
P1
D
P1
P1
P1
P1
P1
D
D
P1
P1
Functional Description
G
O
P
O
O
O
G
P
O
O
O
O
P
G
P
O
Digital ground pin.
Data clock output pin.(*1)
I/O power supply pin.
DATA output pin.(*1)
DATA output pin.(*1)
DATA output pin.(*1)
Digital ground pin.
I/O power supply pin.
DATA output pin.(*1)
DATA output pin.(*1)
DATA output pin.(*1)
DATA output pin.(*1)
Digital power supply pin.
Digital ground pin.
I/O power supply pin.
DATA output pin.(*1)
DVALID/ FIELD signal output pin.
O
DVALID signal output / FIELD signal output can be selected by register
43 DVAL_FLD P1
(I/O) setting.(*1)
If test mode, it is I/O pin.
VD/ FIELD signal output pin
O
44 VD_FLD
P1
VD signal output / FIELD signal output can be selected by register setting.(*1)
(I/O)
If test mode, it is I/O pin.
O
HD signal output pin.(*1)
45 HD
P1
(I/O) If test mode, it is I/O pin.
46 DVSS
D
G
Digital ground pin.
47 TEST0
P2 I
Pin for test mode setting. Connect to DVSS.
48 TEST1
P2 I
Pin for test mode setting. Connect to DVSS.
Shows status of synchronization with input signal
49 NSIG
P2 O
Low: Signal present (synchronized).
High: Signal not present or not synchronized.(*1)
Output Enable pin.
Low: Digital output pin in Hi-z output mode.
50 OE
P2 I
High: Data output mode.
Hi-z input to OE pin is prohibited.
51 PVDD2
P2 P
Microprocessor I/F power supply pin.
Reset signal input pin. Hi-z input is prohibited.
52 RSTN
P2 I
Low: Reset.
High: Normal operation.
Power-down control pin. Hi-z input is prohibited.
53 PDN
P2 I
Low: Power-down.
High: Normal operation.
I2C data pin. Connect to PVDD2 via a pull-up register.
54 SDA
P2 I/O
Hi-z input possible when PDN=L.
I2C clock input pin. Connect to PVDD2 via a pull-up register.
55 SCL
P2 I
Hi-z input possible when PDN=L.
I2C bus address selector pin.
56 SELA
P2 I
PVDD2 connection: Slave address [0x8A]
DVSS connection: Slave address [0x88]
57 AVDD
A
P
Analog power supply pin.
[Power supply] A: AVDD, D: DVDD, P1: PVDD1, P2: PVDD2
[Input/Output] I: intput pin, O: output pin, I/O: input/output pin, P: power supply pin, G: ground connection pin
(*1)
See {[3.2] Output pin state} for relation of output to OE/PDN and RSTN pin status.
MS1230-E-01
2011/7
-9-
[AK8858]
Pin
Symbol P/S I/O Functional Description
No.
Crystal connection pin. Use 24.576 MHz crystal.
58 XTO
A
O
When PDN=L, output level is AVSS.
If crystal is not used, connect to NC or AVSS.
Crystal connection pin. Use 24.576 MHz crystal resonator.
59 XTI
A
I
For input from 24.576 MHz crystal oscillator, use this pin.
60 AVSS
A
G
Analog ground pin.
61 AVSS
A
G
Analog ground pin.
Analog video signal input pin.Connect via 0.033μF capacitor and voltage-splitting
62 AIN1
A
I
resistors. If not used, connect to NC.
63 AVDD
A
P
Analog power supply pin.
Analog video signal input pin.Connect via 0.033μF capacitor and voltage-splitting
64 AIN2
A
I
resistors. If not used, connect to NC.
65 AVSS
A
G
Analog ground pin.
Analog video signal input pin.Connect via 0.033μF capacitor and voltage-splitting
66 AIN3
A
I
resistors. If not used, connect to NC.
67 AVDD
A
P
Analog power supply pin.
Analog video signal input pin.Connect via 0.033μF capacitor and voltage-splitting
68 AIN4
A
I
resistors. If not used, connect to NC.
69 ATIO
A
I/O Aanalog test pin. For normal operation, connect to AVSS.
Analog video signal input pin.Connect via 0.033μF capacitor and voltage-splitting
70 AIN5
A
I
resistors. If not used, connect to NC.
Common internal voltage for AD converter.
71 VCOM A
O
Connect to AVSS via 0.1uF ceramic capacitor (±10%).
Analog video signal input pin.Connect via 0.033μF capacitor and voltage-splitting
72 AIN6
A
I
resistors. If not used, connect to NC.
73 AVSS
A
G
Analog ground pin.
Analog circuit reference current setting pin.
74 IREF
A
O
Connect to AVSS via 6.8KΩ (±1% accuracy) resistor.
75 AVDD
A
P
Analog power supply pin.
Analog video signal input pin.Connect via 0.033μF capacitor and voltage-splitting
76 AIN7
A
I
resistors. If not used, connect to NC.
Internal reference positive voltage pin for AD converter.
77 VRP
A
O
Connect to AVSS via 0.1uF ceramic capacitor (±10%).
Analog video signal input pin.Connect via 0.033μF capacitor and voltage-splitting
78 AIN8
A
I
resistors. If not used, connect to NC.
Internal reference negative voltage pin for AD converter.
79 VRN
A
O
Connect to AVSS via 0.1uF ceramic capacitor (±10%).
Analog video signal input pin.
80 AIN9
A
I
Connect via 0.033 µF capacitor and voltage-splitting resistors as shown in page 107.
If it is not used, connect to NC.
[Power supply] A: AVDD, D: DVDD, P1: PVDD1, P2: PVDD2
[Input/Output] I: intput pin, O: output pin, I/O: input/output pin, P: power supply pin, G: ground connection pin
(*1)
See {[3.2] Output pin state} for relation of output to OE/PDN and RSTN pin status.
MS1230-E-01
2011/7
- 10 -
[AK8858]
[3.2] Output pin state
Relation of output to OE/PDN and RSTN pin status.
OE
L
H
PDN
x
L
H
H
RSTN
x
L
H
DATA[23:0], DTCLK, HD, VD_FLD, DVAL_FLD
Hi-Z output
L output
L output
DOUT
(x: Don’t care, DOUT:
State of DATA pin except for RGB 8:8:8 format output
YCbCr8bit output
DATA[23:16]
DATA[15:8]
DATA[7:0]
Low output
Low output
DOUT
YCbCr16bit output
DATA[23:16]
DATA[15:8]
Low output
DOUT
NSIG
L output
L output
L output
DOUT
Data output)
DATA[7:0]
DOUT
(DOUT: Data output)
In the absence of AIN signal input, output will be black data (Y=0x10, Cb/Cr=0x80).
(Blueback output can be obtained by register setting).
*(Sub Address: 0x0D [3:2])
[4] Electrical specifications
[4.1] Absolute maximum ratings
Parameter
Min
Max
Supply voltage
DVDD, AVDD
−0.3
2.2
PVDD1, PVDD2
−0.3
4.2
Analog input pin voltage A (VinA)
−0.3
AVDD + 0.3 (≤ 2.2)
Digital input pin voltage P1 (VioP1)
−0.3 PVDD1 + 0.3 (≤ 4.2)
Digital output pin voltage P2 (VioP2)
−0.3 PVDD2 + 0.3 (≤ 4.2)
Input pin current (IIn)
−10
10
Storage temperature
−40
150
(*1)
DTCLK, DATA [23:0], HD, VD_FLD, DVAL_FLD
(*2)
OE, SELA, PDN, RSTN, SDA, SCL, NSIG, TEST0, TEST1
Unit
V
V
V
V
V
mA
°C
Notes
(*1)
(*2)
Power supply pin is not included
The above supply voltages are referenced to ground pins (DVSS=AVSS) at 0V (Reference Voltage).
All power supply grounds (AVSS, DVSS) should be at the same electric potential.
If digital output pins are connected to data bus, the data bus operating voltage should be in the same range as
shown above from the digital output pin.
The setting other than above may cause the eternal destruction to the deivce.
Normal operational is not guaranteed for the above setting.
[4.2] Recommended operating conditions
Parameter
Min
Typ
Max
Unit
Condition
Analog supply voltage (AVDD)
1.70
1.80
2.00
V
AVDD = DVDD
Digital supply voltage (DVDD)
MPU I/F supply voltage (PVDD1)
PVDD1 ≥ DVDD
1.70
1.80
3.60
V
Data output i/F supply voltage (PVDD2)
PVDD2 ≥ DVDD
Operating temperature (Ta)
−40
85
°C
The above supply voltages are referenced to ground pins (DVSS=AVSS) at 0V (Reference Voltage).
All power supply grounds (AVSS, DVSS) should be at the same electric potential.
MS1230-E-01
2011/7
- 11 -
[AK8858]
[4.3] DC characteristics
(Ta: −40°C∼85°C / DVDD=AVDD=1.7V∼2.0V / PVDD1=DVDD∼3.6V / PVDD2=DVDD∼3.6V)
Parameter
Symbol
Min
Typ
Max
Units
Condition
Digital P2 input high voltage(*1)
VPIH
Digital P2 input low voltage(*1)
VPIL
XTI input high voltage
VXIH
XTI input low voltage
Digital input leak current
Digital P1 output high voltage
Digital P1 output low voltage
Digital P1 output Hi-z leak current
(*2)
PVDD2<2.7V
0.7PVDD2
V
PVDD2≥2.7V
0.2PVDD2
V
PVDD2<2.7V
0.3PVDD2
V
PVDD2≥2.7V
0.8AVDD
0.2AVDD
IL
±10
VOH1
(*2)
V
VXIL
(*1)
(*2)
0.8PVDD2
uA
0.7PVDD1
V
IOH1 = −600uA
IOL1 = 1mA
VOL1
0.3PVDD1
V
HIL
±10
uA
NSIG output high voltage
VOH2
NSIG output low voltage
VOL2
I2C(SDA)L output
VOLC
0.7PVDD2
V
IOH2 = −600uA
0.3PVDD2
V
IOL2 = 1mA
0.4
0.2 PVDD2
(*1) Collective term for SDA, SCL, SELA, OE, PDN, RSTN, TEST0 and TEST1 pins.
(*2) Collective term for DTCLK, DATA [23:0], HD, VD_FLD and DVAL_FLD pins.
V
IOLC = 3mA
PVDD2≥2.0V
PVDD2<2.0V
[4.4] Analog characteristics
(AVDD=1.8V, Ta=25˚C)
[4.4.1] Input Range
Parameter
Input range
Symbol
VIMX
[4.4.2] AAF (Anti-Aliasing Filter)
Parameter
Symbol
Min
0
Min
Pass band ripple
Gp
−1
Stop band blocking
Gs
20
[4.4.3] Analog PGA
Parameter
Resolution
Minimum gain
Maximum gain
Gain step
Typ
Typ
Max
0.60
Max
Units
+1
dB
30
Units
Vpp
Condition
Progressive signal: ∼12MHz
Interlace signal: ∼6MHz
Progressive signal: 54MHz
Interlace signal: 27MHz
dB
Symbol
RES
GMN
GMX
GST
Min
2.75
MS1230-E-01
Condition
Typ
2
-3
6
3
Max
3.25
Units
bit
dB
dB
dB
2011/7
- 12 -
[AK8858]
[4.4.4] ADC
Parameter
Resolution
Symbol
RES
Operating clock frequency
Min
FS
Intergral nonlinearity
Differential nonlinearity
Max
Units
bit
MHz
27
INL
DNL
±1.0
±0.5
SN
53
dB
SND
52
dB
IFGM
VCOM
VRP
VRN
0.96
1.26
0.66
S/N
S/(N+D)
Full scale Gain matching
ADC internal common voltage
ADC internal positive VREF
ADC internal negative VREF
*Fin = AIN input signal frequency
Typ
10
54
±2.0
±1.0
Condition
Progressive decode : Y signal
Interlace decode : Y signal
Progressive decode : PbPr signal
LSB
LSB
5
Fin=1MHz*, FS=54MHz,
PGA GAIN default setting
Fin=1MHz*, FS=54MHz
PGA GAIN default setting
%
V
V
V
[4.4.5] Current consumption
Parameter
(Active mode)
Total
Symbol
IDD
Min
(AVDD = DVDD = PVDD1 = PVDD2 = 1.8V, Ta = −40∼85˚C)
Typ
Max
Units
Condition
Analog block
AIDD
Digital block
DIDD
110
68
60
35
28
I/O block
PIDD
14
151
mA
mA
mA
mA
mA
mA
ADC 3ch operational(*1)
ADC 3ch operational(*1)
YC: ADC 2ch operational(*2)
CVBS: ADC 1ch operational(*2)
(*1)
With crystal connected
Load condition: CL=15pF
(Power down mode)
Total
SIDD
≤1
100
uA
PDN=L(DVSS)(*3)
Analog block
ASIDD
≤1
uA
Digital block
DSIDD
≤1
uA
I/O block
PSIDD
≤1
uA
(*1)
Progressive YPbPr signal decode
(*2)
Reference value
(*3)
OE pin and RSTN pin must always be brought to the voltage polarity to be used or to ground level
MS1230-E-01
2011/7
- 13 -
[AK8858]
[4.4.6] Crystal circuit block
Parameter
Symbol Min
Typ
Max Units
Notes
Frequency
f0
24.576
MHz
Frequency tolerance
Δf / f
±100 ppm
Load capacitance
CL
15
pF
(*1)
Effective equivalent resistance
Re
100
Ω
Crystal parallel capacitance
CO
0.9
pF
XTI terminal external connection load capacitance
CXI
22
pF
CL=15pF
XTO terminal external connection load capacitance
CXO
22
pF
CL=15pF
(*1)
Effective equivalent resistance generally may be taken as Re = {R1 x (1+CO/CL)2}. (R1 is the crystal series
equivalent resistance)
Example connection
AK8858 internal circuit
Rf
XTI pin
XTO pin
External circuit
Rd
CXI = 22pF
(*2)
(* 2)
CXO = 22pF
Determine need for and appropriate value of limiting resistance (Rd) in accordance with the crystal
specifications.
MS1230-E-01
2011/7
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[AK8858]
[5] AC Timing
(1.70≤DVDD≤2.00, DVDD≤PVDD1≤3.60, DVDD≤PVDD2≤3.60)
(Ta = −40∼85˚C, Load condition: CL=15pF)
[5.1] Clock input
fCLK
tCLKL
tCLKH
0.8AVDD
0.5AVDD
0.2AVDD
Parameter
Input CLK
CLK pulse width H
CLK pulse widthL
Frequency tolerance
Symbol
fCLK
tCLKH
tCLKL
Min
Typ
24.576
Max
16
16
Units
MHz
nsec
±100
ppm
[5.2] Clock output (DTCLK output)
fDTCLK
0.5PVDD1
Parameter
Symbol
Min
Typ
Max
Units
13.5
DTCLK
fDTCLK
27
MHz
54
MS1230-E-01
Condition
(Interlace) 16bit YCbCr output
(Interlace) RGB output
(Interlace) 8bit YCbCr output
(Progressive) 16bit YCbCr output
(Progressive) RGB output
(Progressive) 8bit YCbCr output
2011/7
- 15 -
[AK8858]
[5.3] Output data timing
0.5PVDD1
DTCLK(*1)
tDS
tDH
0.5PVDD1
Output Data
(*2)
Parameter
Symbol
Min
Typ
Max
Units
20
Output Data Setup Time
tDS
nsec
10
5
20
Output Data Hold Time
tDH
nsec
10
5
(*1)
(*2)
Condition
(Interlace) 16bit YCbCr output
(Interlace) RGB output
(Interlace) 8bit YCbCr output
(Progressive) 16bit YCbCr output
(Progressive) RGB output
(Progressive) 8bit YCbCr output
(Interlace) 16bit YCbCr output
(Interlace) RGB output
(Interlace) 8bit YCbCr output
(Progressive) 16bit YCbCr output
(Progressive) RGB output
(Progressive) 8bit YCbCr output
It is possible to invert the polarity of DTCLK by setting register. (Sub Address: 0x07[7]).
Output Data is general term of DATA [23:0], HD, VD_FLD and DVAL_FLD.
[5.4] Reset pulse
tRST/ tRJCT
RSTN
Parameter
RSTN pulse width
Symbol
tRST
RSTN pulse eject
tRJCT
MS1230-E-01
Min
500
Typ
Max
50
Units
nsec
2011/7
- 16 -
[AK8858]
[5.5] Power-down release sequence
Reset must be applied after PDN release (PDN=Hi).
RESh
Don’t
Care
RSTN
PDN
VIH
DVSS
Parameter
Symbol
Min
RESh
5
Reset width after PDN release
VIH
Typ
Max
Units
ms
To perform power-down, all control signals must always be brought to the voltage polarity to be used or to
ground level.
AVDD/ DVDD
PVDD1/ PVDD2
PDN
RSTN
XTI
VCOM,VRP,VRN
5 ms (max) to stable
crystal oscillation*
PDN release
RESh: 5mS (min)
MS1230-E-01
*Reference Value
2011/7
- 17 -
[AK8858]
[5.6] Power-on sequence
PWUPTIME
AVDD/ DVDD
PVDD1/ PVDD2
RESh
VIH
PDN
VIH
RSTN
Parameter
POWERUP TIME
Reset width after PDN release
Symbol
PWUPTIME
RESh
Min
5
Typ
Max
100
Units
msec
At power-on, PDN must be set to ground level (PDN=Low).
AVDD/DVDD/PVDD1/PVDD2 should be raised at power-on less than 100msec.
After PDN release, RSTN must stay on Low level more than 5msec.
MS1230-E-01
2011/7
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[AK8858]
[5.7] I2C bus input timing
[5.7.1] Timing 1
tBUF tHD : STA
tR
tF
tSU : STO
VIH
SDA
VIL
tF
tR
VIH
SCL
VIL
tLOW
tSU : STA
Parameter
Symbol
Min
tBUF
1.3
usec
tHD:STA
0.6
usec
Clock Pulse Low Time
tLOW
1.3
usec
Input Signal Rise Time
tR
300
nsec
Input Signal Fall Time
tF
300
nsec
Bus Free Time
Hold Time (Start Condition)
Max
Units
Setup Time(Start Condition)
tSU:STA
0.6
usec
Setup Time(Stop Condition)
tSU:STO
0.6
usec
*The timing relating to the I2C bus is as stipulated by the I2C bus specification, and not determined by the
device itself. For details, see I2C bus specification.
[5.7.2] Timing 2
tHD : DAT
VIH
SDA
VIL
tHIGH
VIH
SCL
VIL
TSU : DAT
Parameter
Data Setup Time
Data Hold Time
Clock Pulse High Time
(*1)
(*2)
Symbol
Min
tSU:DAT
100(*1)
tHD:DAT
0.0
tHIGH
0.6
Max
Units
nsec
0.9
(*2)
usec
usec
If I2C is used in standard mode, tSU:DAT≥250ns is required.
This condition must be met if the AK8858 is used with a bus that does not extend tLOW (to use tLOW at
minimum specification).
MS1230-E-01
2011/7
- 19 -
[AK8858]
[6] Functional overview
The following key functions are characteristic of the AK8858 and its operational performance.
(1) It accepts composite video signal (CVBS), S-video and component YPbPr input with 10 input pins available
for this purpose.The decode signal is selected via register setting.
(2) It contains an internal analog band limiting filter (anti-aliasing) in front of the AD converter input.
(3) Its analog circuit clamps the input signal to the sync tip (analog sync tip clamp). Its digital circuit clamps the
digitized input data to the pedestal level (digital pedestal clamp).
(4) It has auto detection mode via register setting which automatically recognizes the input signal category.
(5) Its adaptive AGC function enables measurement of the input signal size and determination of the input
signal level.
(6) Its ACC function enables measurement of the input signal color burst size and determination of the
appropriate color burst level.
(7) It performs adaptive two-dimensional Y/C separation, in which its phase detector selects the best correlation
from among vertical, horizontal, and diagonal samples and optimum Y/C separation mode.
(8) Its digital pixel spacing adjustor can align vertical positions by vertical pixel positioning.
(9) Its operated in line-locked, frame-locked, or fixed clock mode with automatic transition and optimum mode
selection by automatic scanning.
(10) In PAL-B, D, G, H, I and N decoding, it can perform phase-difference correction for each line.
(11) Its output interface is ITU-R BT.656 (EAV/SAV) compliant. For connection of devices having no ITU-R
BT.656 interface, it shows the active video region by HD/ VD/ DVALID/ FIELD signal output.
(12) Its output data format is in YCbCr format and RGB (8:8:8) format.
(13) It judges the chroma signal quality from the color burst of the input signal, and can apply color kill if the
signal quality is judged insufficient. It can also apply color kill if the color decode PLL clock control.
(14) Its image quality adjustment function includes contrast, brightness, hue, color saturation, and sharpness
adjustment.
(15) Its luminance and color signal band limiting filter are adjustable via register setting.
(16) It can decode conflated closed caption data, WSS signals, VBID(CGMS-A) and write them separately to
the storage register.
(17) Its enables Macrovision signal type notification, in cases where the Macrovision signal is included in the
decoded data.
MS1230-E-01
2011/7
- 20 -
[AK8858]
[7] Functional description
[7.1] Analog circuit description
Analog circuit block is shown below.
XTI
XTO
Clock
Module
PLL Feed-back
Information
AIN1
AIN2
AIN3
CLAMP
AAF
CLAMP
AAF
PGA1
10-bit
ADC1
10bit
PGA2
10-bit
ADC2
10bit
AIN4
AIN5
AIN6
MUX
MUX
AIN7
AIN8
CLAMP
AAF
AIN9
AIN10
VREF
VRP VCOM VRN IREF
When decode YPbPr component video signal, Pb/Pr signal is converted to digital data by PGA2 and ADC2
after the data was sampled at sample hold circuit.
Time sharing operational status of ADC and PGA is shown below (PGA2 and ADC2 is shown as VPGA2,
VADC2, VPGA3 and VADC3).
XTI
XTO
Clock
Module
PLL Feed-back
Information
AIN1
AIN2
AIN3
CLAMP
PGA1
10-bit
ADC1
10bit
AAF
CLAMP
AAF
VPGA2
10-bit
VADC2
10bit
CLAMP
AAF
VPGA3
10-bit
VADC3
10bit
AIN4
AIN5
AIN6
MUX
AIN7
AIN8
AIN9
AIN10
VREF
VRP VCOM VRN IREF
MS1230-E-01
2011/7
- 21 -
[AK8858]
[7.1.1] CVBS signal decoding
The data is converted to digital at PGA1 and ADC1. Sampling clock is 27MHz.
The characteristics of internal analog limiting filter (anti-aliasing), which is in front of the AD converter input, are
as follows: ±1dB (∼6MHz), −30dB (27MHz)
[7.1.2] S(Y/C) video signal decoding
Y signal data is converted to digital at PGA1 and ADC1. Sampling clock is 27MHz.
C signal data is converted to digital at PGA2 and ADC2. Sampling clock is 27MHz.
The characteristics of internal analog limiting filter (anti-aliasing), which is in front of the AD converter input, are
as follows: ±1dB (∼6MHz), −30dB (27MHz)
[7.1.3] 525i/625i YPbPr component video signal decoding
Y signal data is converted to digital at PGA1 and ADC1. Sampling clock is 27MHz.
Pb signal data is converted to digital at VPGA2 and VADC2. Sampling clock is 27MHz.
Pr signal data is converted to digital at VPGA3 and VADC3. Sampling clock is 27MHz.
The characteristics of internal analog limiting filter (anti-aliasing), which is in front of the AD converter input, are
as follows: ±1dB (∼6MHz), −30dB (27MHz)
AAF Chracteristic (except Progressive)
[7.1.4] 525p/625p YPbPr component video signal decoding
Y signal data is converted to digital at PGA1 and ADC1. Sampling clock is 54MHz.
Pb signal data is converted to digital at VPGA2 and VADC2. Sampling clock is 27MHz.
Pr signal data is converted to digital at VPGA3 and VADC3. Sampling clock is 27MHz.
The characteristics of internal analog limiting filter (anti-aliasing), which is in front of the AD converter input, are
as follows: ±1dB (∼12MHz), −30dB (54MHz)
AAF Chracteristic (Progressive)
MS1230-E-01
2011/7
- 22 -
[AK8858]
[7.2] Analog Interface
The AK8858 accepts composite video signal (CVBS), S(Y/C) video signal, YPbPr component video signal
(D1/D2) input with 10 input pins available for this purpose.
Sub Address:0x00
bit 7
bit 6
CLKMOD
SELSRC1
Default Value
0
0
bit 5
SELSRC0
bit 4
ADC3SEL
bit 3
ADC2SEL
bit 2
ADC1SEL2
Default Value:0x00
bit 1
bit 0
ADC1SEL1
ADC1SEL0
0
0
0
0
0
0
The connection settings are shown below.
ADC1SEL[2:0]-bit: Input selection for ADC1. (for CVBS or Y)
Setting
ADC1 Input
000
AIN1
001
AIN2
010
AIN3
011
AIN4
100
AIN5
101
AIN6
ADC2SEL-bit: Input selection for ADC2 (VADC2). (for C or Pb)
Setting
ADC2 Input
0
AIN7
1
AIN8
ADC3SEL-bit: Input selection for ADC3 (VADC2). (for Pr)
Setting
ADC3 Input
0
AIN9
1
AIN10
SELSRC[1:0]-bit: Decode signal type setting bit.
Setting
Input signal
00
Composite (CVBS) video signal
01
S-Video signal
10
Component video signal
11
Analog power-down (CLAMP, AAF, PGA, ADC is power-down)
[7.3] Input Clock mode
CLKMOD-bit: Input clock setting bit.
Setting
Input clock
0
For crystal
1
External clock input (clock generator)
MS1230-E-01
2011/7
- 23 -
[AK8858]
[7.4] Analog clamp circuit
The analog circuit of the AK8858 clamps the input signal to the reference level. The way to clamp the input
signal is as follows.
The clamp timing pulse, with its origin at the falling edge of the internally synchronized and separated sync
signal, is generated at approximately the central position of the sync signal.
Input signal
Composite (CVBS)
video signal
S(Y/C) video
signal
Component video
signal
Clamp Level
Clamp pulse position
Sync tip level
Sync tip
Y signal
C signal
Y signal
Sync tip level
Pedestal level
Sync tip level
Pb signal
Pedestal level
Pr signal
Pedestal level
Sync tip
Sync tip of Y
Sync tip
Clamp timing is performs by sync tip clamp or
backporch clamp.
If Pb and Pr signal have sync signl, set clamp timing to
backporch clamp.
Clamp Timing Pulse
Y
Analog sync tip clamp
CVBS
C
Analog sync tip clamp
Analog middle clamp
Y
Y
Analog sync tip clamp
Pb
Analog sync tip clamp
Pb
Analog middle clamp
Pr
Analog backporch clamp
Pr
Analog middle clamp
Analog backporch clamp
MS1230-E-01
2011/7
- 24 -
[AK8858]
Additionary, the AK8858 can change the position, width and current value of clamp pulse via register Clamp
Control 1 Register (R/W) [Sub Address 0x01] and Clamp Control 2 Register (R/W) [Sub Address 0x02].
Sub Address: 0x01
bit 7
bit 6
CLPCLPWIDTH1
WIDTH0
Default Value
0
0
Sub Address: 0x02
bit 7
bit 6
Reserved
Reserved
Default Value
0
0
bit 5
CLPSTAT1
bit 4
CLPSTAT0
0
0
bit 3
Reserved
0
bit 2
BCLPSTAT2
Default Value: 0x00
bit 1
bit 0
BCLPBCLPSTAT1
STAT0
0
0
0
bit 5
Reserved
bit 4
YPBPRCP
bit 3
UDG1
bit 2
UDG0
Default Value: 0x01
bit 1
bit 0
CLPG1
CLPG0
0
0
0
0
0
1
BCLPSTAT[2:0]-bit: Set the position of analog backporch clamp pulse.
Setting
Clamp position
000
Same position with “CLPSTAT” setting
001
(1/128)H delay from “CLPSTAT” setting
010
(2/128)H delay from “CLPSTAT” setting
011
(3/128)H delay from “CLPSTAT” setting
100
(4/128)H advance from “CLPSTAT” setting
101
(3/128)H advance from “CLPSTAT” setting
110
(2/128)H advance from “CLPSTAT” setting
111
(1/128)H advance from “CLPSTAT” setting
Notes
Set only the position of analog backporch clamp pulse.
CLPSTAT[1:0]-bit: Set the position of clamp pulse.
Setting
Clamp position
Sync tip/ middle/ bottom clamp: Center of horizontal sync
00
Backporch clamp: Center of backporch interval
01
(1/128)H delay
10
(2/128)H advance
11
(1/128)H advance
The positions of all clamp pulse are changed.
Notes
CLPWIDTH[1:0]-bit: Set the clamp pulse width. Pulse width is change according to sampling clock units.
Setting
Clamp width
Notes
00
7 clock
Clock units
01
15 clock
525i, 625i: 27MHz
10
31 clock
525p, 625p: 54MHz
11
63 clock
The width of all clamp pulse is changed.
YPBPRCP-bit: Set the clamp position of PbPr signal of YPbPR component video signal.
Setting
Clamp position
0
Sync tip timing
1
Backporch timing
MS1230-E-01
Notes
2011/7
- 25 -
[AK8858]
The relation between CLPSTAT and BCLPSTAT is shown as follows.
Clamp Timing Pulse
CLPWIDTH[1:0]
CLPSTAT[1:0] = 00
CLPSTAT[1:0] = 01
1/128H delay
Sync tip / middle clamp
CLPSTAT[1:0] = 11
1/128H advance
CLPSTAT[1:0] = 10
2/128H advance
CLPWIDTH[1:0]
CLPSTAT[1:0] = 00
BCLPSTAT[2:0] = 000
CLPSTAT[1:0] =10
BCLPSTAT[2:0] = 000
2/128H advance
CLPSTAT[1:0] =10
BCLPSTAT[2:0] = 111
3/128H advance
CLPSTAT[1:0] =00
BCLPSTAT[2:0] = 110
2/128H advance
Back porch clamp
Clamp current value setting
CLPG[1:0]: Set the current value of fine clamp in analog block.
Setting
Clamp current value
Notes
00
Min.
Middle 1 = (Min. x 3 times)
01
Middle 1 (Default)
Middle 2 = (Min. x 5 times)
10
Middle 2
Max. = (Min. x 7 times)
11
Max.
UDG[1:0]: Set the current value of rough clamp in analog block.
Setting
Clamp current value
Notes
00
Min. (Default)
Middle 1 = (Min. x 2 times)
01
Middle 1
Middle 2 = (Min. x 3 times)
10
Middle 2
Max. = (Min. x 4 times)
11
Max.
Its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp).
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[AK8858]
[7.5] Input video signal categorization
Set the input video signal.
Composite (CVBS) video signal, S-Video signal, and Component video signal can be select via register Input
Channel Select Register (R/W) [Sub Address 0x00].
When decode composite (CVBS) video signal and S-Video signal, it is necessary to set subcarrier frequency,
color encode format, line frequency, and Setup ON/OFF of input signal via register Input Video Standard
Register (R/W) [Sub Address 0x04].
When decode component video signal, it is necessary to set line frequency and Setup ON/OFF. It is also
necessary to set sync signal and signal ratio of input video signal via register Miscellaneous Setting Register
(R/W) [Sub Address 0x03].
Sub Address: 0x04
bit 7
bit 6
AUTODET
SETUP
Default Value
0
0
Sub Address: 0x03
bit 7
bit 6
VERTS
CSCAN
Default Value
0
0
bit 5
BW
bit 4
VLF
bit 3
VCEN1
bit 2
VCEN0
Default Value:0x00
bit 1
bit 0
VSCF1
VCSF0
0
0
0
0
0
0
bit 5
Reserved
bit 4
CMPSEL
bit 3
Reserved
bit 2
CSCL
Default Value: 0x00
bit 1
bit 0
CSSL
Reserved
0
0
0
0
0
0
VCSF[1:0]-bit: Setting for subcarrier frequency of input signal.
Setting
Subcarrier frequency
Formats
00
3.57954545 MHz
NTSC
01
3.57561149 MHz
PAL-M
10
3.58205625 MHz
PAN-Nc
11
4.43361875 MHz
PAL-B,D,G,H,I,N, NTSC-4.43, PAL60, SECAM*
*For SECAM input signal, set VCSF[1:0] to 11.
For component video signal input, VCSF[1:0] setting is not necessary.
VCEN[1:0]-bit: Setting for color encode format of input signal.
Setting
Color encode format
Notes
00
NTSC
01
PAL
10
SECAM
In case of YPbPr, SECAM is prohibited.
11
Reserved
For component video signal input, VCEN[1:0] setting is not necessary.
VLF-bit: Setting for line frequency of each input frame.
Setting
Number of lines
Notes
0
525
NTSC-M, J, NTSC-4.43, PAL-M, PAL-60
1
625
PAL-B, D, G, H, I, N, Nc, SECAM
BW-bit: Setting for decoding of input signal as monochrome signal (monochrome mode)
Setting
Signal type
Notes
0
Not monochrome (monochrome mode OFF)
1
Decode as monochrome signal (monochrome mode ON)
In the monochrome mode (BW=1), the input signal is treated as a monochrome signal, and all sampling data
digitized the AD converter passes through the luminance process and is processed as luminance signal, and
the CbCr code is output as 0x80 regardless of the input.
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[AK8858]
SETUP-bit: Setting for presence or absence of input signal SETUP.
Setting
ON/OFF
Notes
0
Setup absent
With the Setup present setting,
the luminance and color signals are processed as follows:
Yout = (YIN-7.5IRE)/0.925
Uout = UIN/0.925, Vout = VIN/0.925
YOUT: Y after setup
1
Setup present
YIN: Y before setup
UOUT: U after setup
UIN: U before setup
VOUT: V after setup
VIN: V before setup
In auto detection mode, the default setting of Setup processing via register STUPATOFF-bit of Control 2
Register (R/W) [Sub Address 0x0D]-bit6 is shows as follows.
Register setting
Setup-bit
STUPATOFF-bit
0
NTSC-M,J
0
PAL-B,D,G,H,I,N
1
PAL-Nc , 60
0
1
SECAM
1
0
0
PAL-M
1
NTSC-4.43
0
1
1
In case of YPbPr signal input, auto Setup processing is not performed.
Detected signal
Setup present/ absent
Setup absent
Setup absent
Setup present
Setup present
Setup present
Setup absent
Setup present
Setup present
AUTODET-bit: Settings for auto detection of input signal (auto detetction mode)
Setting
ON/OFF
Notes
0
OFF
Manual setting
1
ON
CSSL-bit: Settings for sync and video signal ratio of input signal.
Setting
S/V ratio
0
300/700
1
286/714
Only available when component input signal is selected.
CSCL-bit: Settings for color level of component input signal.
Setting
Video level
0
700mV
1
714mV
Only available when component input signal is selected.
Notes
EIA-770.2
EIA-770.1
Notes
EIA-770.2
EIA-770.1
CMPSEL-bit: Interlace and Progressive setting for YPbPr component input signal.
Setting
YPbPr component video signal
0
Interlace (525i/ 625i)
1
Progressive (525P/ 625P)
VERTS-bit: Select of VLOCK or Direct Lock
Setting
SYNC mechanism
0
VLOCK mechanism
1
Direct LOCK mechanism
MS1230-E-01
Notes
2011/7
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[AK8858]
[7.6] Auto detection mode of input signal
The video input signal can be automatically detected (auto detection mode) via register.
Settings for auto detection of input signal (auto detetction mode)
Name
Setting
ON/OFF
0
OFF(Manual setting)
AUTODET
1
ON
Sub Address: 0x04 [7]
Notes
The auto detetction recognizes the following parameters (AUTODET-bit=1).
Number of lines per frame:
525/626
Subcarrier frequency:
3.57954545 (MHz)
3.57561149 (MHz)
3.58205625 (MHz)
4.43361875 (MHz)
Color encoding formats:
NTSC/PAL/SECAM
Progressive setting:
Interlace / Progressive
Monochrome signal*:
Not monochrome/monochrome.
*Note: Automatic monochrome detection is active if the color kill setting is ON.
The detected result of auto detetction mode is reflected to Input Video Status Register. The input signal status
can be recognized by reading this register.
bit 7
FIXED
bit 6
UNDEF
bit 5
ST_BW
bit 4
ST_VLF
bit 3
ST_VCEN1
bit 2
ST_VCEN0
bit 1
ST_VSCF1
Sub Address: 0x25
bit 0
ST_VCSF0
In addition, auto detetction function of the input signal is recognized by the changing of internal status.
If FIXED-bit changed from 0 to 1, the detetction is completed. During FIXED-bit is 0, the AK8858 may attempt
to recognize the input signal and the output code during this period cannot be trusted. If the AK8858 cannot
recognize the input signal, UNDEF-bit is changed from 0 to 1 to indicate the status of the input signal.
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[AK8858]
[7.7] Auto detection restriction of input signal
In auto detection mode, the candidates for detection can be limited via register NDMODE Register.
Sub Address:0x06
bit 7
bit 6
ND625L
ND525L
Default Value
0
0
bit 5
NDPAL60
bit 4
NDNTSC443
bit 3
Reserved
bit 2
NDSECAM
Default Value: 0x00
bit 1
bit 0
NDPALNC
NDPALM
0
0
0
0
0
0
In making the above register settings, the following restrictions apply.
1. Setting both NDNTSC443-bit and NDPAL60-bit to 1 is prohibited.
2. Setting both ND525L-bit and ND625L-bit to 1 is prohibited.
3. To limit candidate formats, it is necessary to have the auto detetction mode OFF while first setting the
register to non-limited signal status and next the NDMODE settings, and then setting the auto
detetction mode to ON.
Set auto detection mode to OFF
Set Input Video Standard Register to non-limited signal status
Enter NDMODE Register Settings
Set auto detection mode to ON
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[AK8858]
[7.8] Output data blanking interval
Setting vertical blanking intervals.
VBIL[2:0]-bit
525/625
Vertical blanking interval
525i
Line1∼Line20 and Line263.5∼Line283.5
625i
Line623.5∼Line24.5 and Line311∼Line336
001
525p
Line1∼Line43
625p
Line 621∼Line625 and Line1∼Line45
525i
Line1∼Line21 and Line263.5∼Line284.5
625i
Line623.5∼Line25.5 and Line311∼Line337
010
525p
Line1∼Line44
625p
Line 621∼Line625 and Line1∼Line46
525i
Line1∼Line22 and Line263.5∼Line285.5
625i
Line623.5∼Line26.5 and Line311∼Line338
011
525p
Line1∼Line45
625p
Line 621∼Line625 and Line1∼Line47
525i
Line1∼Line19 and Line263.5∼Line282.5
625i
Line623.5∼Line23.5 and Line311∼Line335
000
525p
Line1∼Line42
625p
Line 621∼Line625 and Line1∼Line44
525i
Line1∼Line16 and Line263.5∼Line279.5
625i
Line623.5∼Line20.5 and Line311∼Line332
101
525p
Line1∼Line39
625p
Line 621∼Line625 and Line1∼Line41
525i
Line1∼Line17 and Line263.5∼Line280.5
625i
Line623.5∼Line21.5 and Line311∼Line333
110
525p
Line1∼Line40
625p
Line 621∼Line625 and Line1∼Line42
525i
Line1∼Line18 and Line263.5∼Line281.5
625i
Line623.5∼Line22.5 and Line311∼Line334
111
525p
Line1∼Line41
625p
Line 621∼Line625 and Line1∼Line43
100
Reserved
Reserved
As indicated in this table, the default values are:
(525i) Line1∼Line19 and Line263.5∼Line282.5
(625i) Line623.5∼Line23.5 and Line311∼Line335
(525P) Line1∼Line42
(625P) Line 621∼Line625 and Line1∼Line44
The other specific values are set by entering the difference from these default values.
MS1230-E-01
Sub Address: 0x05[2:0]
Notes
+1Line
+2Lines
+3Lines
Default
-3Lines
-2Lines
-1Line
2011/7
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[AK8858]
[7.9] Output data code Min/Max setting
LIMIT601-bit: Setting for output data code Min/Max
Sub Address: 0x05[3]
LIMIT601-bit
EAVSAV-bit
Notes
Output data code Min∼Max
Y: 1∼254
0
Cb, Cr: 1∼254
R, G, B: 1∼254
(*1)
0
Y: 0∼255
1
Cb, Cr: 0∼255
R, G, B: 0∼255
Y: 16∼235
(*2)
1
X
Cb, Cr: 16∼240
R, G, B: 16∼235
All internal calculating operations are made with Min = 1, Max = 254.
(*1)
In case of LIMIT601-bit =0, the output code Min and Max values is set according to EAVSAV-bit status.
(*2)
In case of LIMIT601-bit =1, codes 1∼15 and 236∼254 are respectively clipped to 16,235(Cb, Cr is 240).
[7.10] Output Pin state
DATA[23:0], HD, VD_FLD, DVAL_FLD and NSIG pins can be Low output by register.
Sub Address: 0x07 [4:0]
Name
DL
VDFL
DVALFL
NL
HL
Setting
Definition
[0]
Normal output
[1]
[D23: D0] pin output fixed at low
[0]
Normal output
[1]
VDFL pin output fixed at low
[0]
Normal output
[1]
DVALFL pin output fixed at low
[0]
Normal output
[1]
NL pin output fixed at low
[0]
Normal output
[1]
HL pin output fixed at low
備考
Default: Normal output
Default: Normal output
Default: Normal output
Default: Normal output
Default: Normal output
OE, PDN and RSTN pins are prior to these register.
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[AK8858]
[7.11] Slice function
The results of VBI slicing by the AK8858 slicing function are output as ITU-R BT.601 digital data. The VBI
interval is set via VBIL[2:0]-bits. VBI slicing is performed in the luminance in the luminance signal processing
path, so that the Cb/Cr value of the effective line 601 output code is output at the same level as the
corresponding luminance signal.
Setting for slice level
Name
Sub Address: 0x05 [5]
Definition
[0]: 25IRE
[1]: 50IRE
SLLVL
Hi/Low Slice Data Set Register of output data, as follows.
Setting for higher of two values resulting from slicing
Sub Address: 0x18
Name
Definition
H0
~
H7
Default: 0xEB(235)
Note that a setting of 0x00 or 0xFF corresponds to a special 601 code.
Setting for lower of two values resulting from slicing
Name
L0
~
L7
Sub Address: 0x19
Definition
Default: 0x10(16)
Note that a setting of 0x00 or 0xFF corresponds to a special 601 code.
* (mV)
NTSC/PAL
601 Code
714/700
235
100% White
357/350
127
50IRE threshold with setting
SLLVL=[1]
180/175
63
25IRE threshold with setting
SLLVL=[0]
L
`````
L
Cb/Y
````
``````
L
L
Cr/Y
H
H
Cb/Y
````
``````
H
H
Cr/Y
L
L: Value set by Low Slice Data
Set Register
H: Value set by High Slice Data
Set Register
```````
*Threshold values (mV) are approximate
High/Low conversion is performed for either the Cb/Y or the Cr/Y combination. The above figure is an example
of the conversion points for Cb/Y.
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[AK8858]
[7.12] VBI period decode data
The AK8858 decode data during VBI period can be selected via register.
Settings for decode data in the VBI period
Setting
Name
Decode data
value
VBIDEC0
~
VBIDEC1
[00]
Black level output
[01]
Monochrome mode
[10]
Sliced data output
[11]
Reserved
Sub Address: 0x05 [7:6]
Notes
Y = 0x10
Cb/Cr = 0x80
Y = data converted to 601 level
Cb/Cr = 0x80
Y/Cb/Cr = value corresponding to slice level
(Value set at Hi/Low Slice Data Set Register)
Reserved
Note: (525i) Lne1~Line9 and Line263.5~Line272.5
(625i) Line623.5~Line6.5 and Line311~Line388
(525p) Line1~Line18
(625p) Line621~Line10
During the above period, these values are unaffected by the VBIDEC[1:0]-bits setting.
The output code during this period is black level code (Y=0x10, Cb/Cr=0x80).
[7.13] VLOCK mechanism
The AK8858 synchronizes internal operation with the input signal frame structure. If, for example, the frame
structure of the input signal comprises 524 lines, the internal operation will have structure of 524 lines per frame.
This mechanism is termed the VLOCK mechanism. If an input signal changes from a structure of 525 lines per
frame to one of 524 lines per frame, internal operation will change accordingly, and the VLOCK mechanism will
go to UnLock via a pull-in process. In such case, the UnLock status can be confirmed via the control register
[VLOCK-bit*]. Note that the time required for locking of the VLOCK mechanism upon channel or other input
signal switching will be about 4 frames (*Sub-address:0x22-“bit1”)
Furthermore, the AK8858 synchronizes internal operation with the vertical SYNC of the input signal. This
mechanism is termed the direct LOCK mechanism.
Setting for Vertical SYNC mechanism
Sub Address: 0x03 [7]
Name
Definition
VERTS
Vertical SYNC mechanism
[0]: VLOCK mechanism
[1]: Direct LOCK mechanism
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[AK8858]
[7.14] Adjustment of Y and C timing
Adjustment of the position between Y and C signal
Sub Address: 0x08 [2:0]
Notes
YCDELAY[2:0]-bit
Y and C timing
001
Y advance 1 sample toward Cb, Cr.
010
Y advance 2 sample toward Cb, Cr.
011
Y advance 3 sample toward Cb, Cr.
000
No delay and advance.
101
Y delay 3 sample toward Cb, Cr.
110
Y delay 2 sample toward Cb, Cr.
111
Y delay 1 sample toward Cb, Cr.
100
Reserved
Note: 1sample of Interlace output is about 74ns / 1 sample of progressive output is about 37ns.
Default
Relation between Y and C timing regardless the above setting is shown as follows.
YCDELAY[2:0] = [000]
Cb0 Y0
Cr0
Y1
Cb1 Y2
Cr1
Y3
Cb2 Y4
Cr2
Y5
Y/C default
YCDELAY[2:0] = [111]
Cb0 Y857 Cr0
Y0
Cb1 Y1
Cr1
Y2
Cb2 Y3
Cr2
Y4
1sample delay
YCDELAY[2:0] = [001]
Cb0 Y1
Y2
Cb1 Y3
Cr1
Y4
Cb2 Y5
Cr2
Y6
1sample adv.
Cr0
DTCLK
[7.15] Adjustment of active video start position
Adjustment of the active video start position
ACTSTA[2:0]-bit
001
010
011
000
101
110
111
100
Line and active video start
525 Line
124th sample
625 Line
134th sample
525 Line
125th sample
625 Line
135th sample
525 Line
126th sample
625 Line
136th sample
525 Line
123th sample
625 Line
133th sample
525 Line
120th sample
625 Line
130th sample
525 Line
121th sample
625 Line
131th sample
525 Line
122th sample
625 Line
132th sample
Reserved
Sub Address: 0x08 [6:4]
Notes
D1 decode: 74ns delay
D2 decode: 37ns delay
D1 decode: 148ns delay
D2 decode: 74ns delay
D1 decode: 222ns delay
D2 decode: 111ns delay
Default(Normal position)
D1 decode: 222ns advance
D2 decode: 111ns advance
D1 decode: 148ns advance
D2 decode: 74ns advance
D1 decode: 74ns advance
D2 decode: 37ns advance
Reserved
MS1230-E-01
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[AK8858]
With the default value, the start position is as follows (with ITU-R BT.601 format compliance).
OH
OH
122sample(525Line)
Active video start
132sample(625Line)
Active video start
[7.16] PGA
The AK8858 analog PGA and digital PGA are built internally.
The analog PGA value can be set in range of -3dB to 6dB, and the gain step is 3dB/step.
The digital PGA value can be set in range -0.25dB to 4dB, and the gain step is not log scale.
Digital PGA gain equation:
⎛ (5 × PGA) + 497 ⎞
⎟
512
⎝
⎠
Gain(dB) = 20 LOG⎜
*PGA: PGA1 or PGA2 register value (Decimal)
Default gain setting is 0x54(HEX)=1.3dB. (Analog:0dB + Digital:1.3dB)
At the default setting, when the composite video signal input with 0.5Vpp is input to the AIN pin, the decode
gain setting is set to appropriate range.
PGA1 is used for CVBS and Y signals gain processing.
Setting for PGA1 value
Name
Definition
DPGA1_0
~
DPGA1_5
Digital PGA1 gain setting.
PGA gain is set by above equation.
APGA1_0
~
APGA1_1
Analog PGA1 gain setting.
[00]: −3dB
[01]: 0dB
[10]: +3dB
[11]: +6dB
PGA2 is used for C, Pb, and Pr signals gain processing.
Setting for PGA2 value
Name
DPGA2_0
~
DPGA2_5
APGA2_0
~
APGA2_1
Sub Address: 0x0E [7:0]
Sub Address: 0x0F [7:0]
Definition
Digital PGA2 gain setting.
PGA gain is set by above equation.
Analog PGA2 gain setting.
[00]: −3dB
[01]: 0dB
[10]: +3dB
[11]: +6dB
This register also can be used to read the current setting of the AGC setting.
If AGC is enable, the Gain1/2 Control Register[7:0]-bit setting value has no effect.
If AGC is disable, the Gain1/2 Control Register setting can be manually entered.
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[AK8858]
[7.17] AGC (Auto Gain Control)
The AGC function amplifies the input signal to the appropriate size and enables input to the AD converter. The
AGC function in the AK8858 is adaptive, and thus includes peak AGC as well as sync AGC.
The AGC of the AK8858 measures the size of the input signal (i.e. the difference between the sync tip and
pedestal levels), and adjusts the PGA value to bring the sync signal level to 286mV/300mV (525/625).
Peak AGC is effective for input signals in which the sync signal level is appropriate and only the active video
signal is large.
In case of component video signal and S-Video signal inputs, AGC are adjust by Y sync level.
When AGC function is enables, the setting values of AGC can be read via register Gain Control Register.
Settings for AGC time constant
AGCT[1:0]-bit
Time constant
00
Disable
01
Fast
10
Middle
11
Slow
T is the time constant.
Settings for AGC non-sensing range
AGCC[1:0]-bit
00
01
10
11
Settings for freezing AGC function
AGCFRZ-bit
0
1
Sub Address: 0x0A [1:0]
Notes
AGC OFF, PGA register enabled.
T= 1Field
T= 7Fields
T= 29Fields
Non-sensing range
±2LSB
±3LSB
±4LSB
None
AGC status
Non-frozen
Frozen
Settings for selection of quick or slow transition between peak and sync AGC
AGCTL-bit
AGC transition
0
Quick
1
Slow
MS1230-E-01
Sub Address: 0x0A [3:2]
Notes
Sub Address: 0x0A [4]
Notes
Sub Address: 0x0B [0]
Notes
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[AK8858]
[7.18] ACC (Auto Color Control)
The ACC of the AK8858 measures the level of the input signal color burst and adjusts to the appropriate level.
The ACC is not applicable to SECAM, and YPbPr input signals.
The ACC and Color saturation functions operate independently. If ACC is enabled, the color saturation
adjustment is applied to the signal that has been adjusted to the appropriate level by the ACC.
Settings for ACC time constant
ACCT[1:0]-bit
00
01
10
11
Sub Address: 0x0A [6:5]
Time constant
Disable
Fast
Middle
Slow
Settings for freezing ACC function
ACCFRZ-bit
0
1
Notes
ACC OFF
T= 2Fields
T= 8Fields
T= 30Fields
Sub Address: 0x0A [7]
Notes
ACC status
Non-frozen
Frozen
[7.19] Y/C separation
The adaptive two-dimensional Y/C separation of the AK8858 utilizes a co-relation detector to select the
best-correlated direction from among vertical, horizontal, and diagonal samples, and selects the optimum Y/C
separation mode.
For NTSC-4.43, PAL-60, and SECAM inputs, the Y/C separation is one-dimensional only, regardless of the
setting.
Setting for Y/C separation
Name
YCSEP0
~
YCSEP1
Sub Address: 0x0C [1:0]
Setting Value
YC separation mode
[00]
Adaptive
[01]
1-D
[10]
2-D
[11]
Reserved
Notes
1-D (BPF)
(NTSC-M,J, PAL-M): 3 Line 2-D
(PAL-B,D,G,H,I,N,Nc): 5 Line 2-D
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[AK8858]
[7.20] C Filter
The bandwidth of the C filter can be set via register, as follows.
Settings for C filter bandwidth, for input signal with 3.58 MHz subcarrier wave.
C358FIL[1:0] -bit C filter bandwidth
Notes
00
Narrow
01
Medium
NTSC-M,J , PAL-M , PAL-Nc
10
Wide
11
Reserved
Sub Address: 0x0B [2:1]
Settings for C filter bandwidth, for input signal with 4.43 MHz subcarrier wave.
Sub Address: 0x0B [4:3]
C443FIL[1:0] -bit C filter bandwidth
Notes
00
Narrow
01
Medium
PAL-B,D,G,H,I,N , NTSC-4.43 , PAL-60
10
Wide
11
Reserved
*Note: No bandwidth selection is possible for SECAM input.
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[AK8858]
[7.21] Clock generation
The AK8858 operates in the following three clock modes:
1. Line-locked clock mode.
2. Frame-locked clock mode
3. Fixed clock mode
The clock mode can be set via register.
[7.21.1] Line-locked clock mode
The “line-locked clock” is generated by PLL using horizontal sync signal within the input signal. If no input
signal is present, the AK8858 will switch from this mode to fixed-clock mode.
[7.21.2] Frame-locked mode
The “frame-locked clock” is generated by PLL using vertical sync signal within the input signal. If no signal is
present, the AK8858 will switch from this mode to fixed-clock mode.
[7.21.3] Fixed-clock mode
No PLL control is applied in this mode, which is enabled only when either it is set via the register or no input
signal is present. The sampling clock in this mode is 27MHz or 54MHz. In this mode, data capture cannot be
performed in EAV (end of active video), and must be performed in SAV (start of active video) format. The
number of pixels per line is not guarantee in this mode, but data guarantee is performed in the interval from
SAV to EAV.
In the line-locked and frame-locked clock modes, the clock is synchronized with the input signal and the output
is ITU-R BT.656 compliant. It should be noted that ITU-R BT.656 compliant output may not be possible with
low-quality input signals.
It should be noted that in the fixed-clock mode the sample number will be insufficient for ITU-R BT.656
compliance, due to non-synchronization of the input data.
[7.21.4] Auto transition mode
The AK8858 transition function automatically switches among the above modes and selects the optimum one,
and when no input signal is present, it switches to the fixed-clock mode.
Settings for selection of clock generation mode.
CLKMODE[1:0]-bit
Clock generation mode
00
Automatic
01
Line-locked
10
Frame-locked
11
Fixed-clock
MS1230-E-01
Sub Address 0x0C [7:6]
Notes
2011/7
- 40 -
[AK8858]
[7.22] Digital Pixel Interpolar
The digital pixel interpolar of the AK8858 aligns vertical pixel positions in both frame-lock and fixed-clock
operating modes. The pixel interpolar can be set to ON or OFF via register. With a register setting of AUTO, the
pixel interpolar is OFF or ON depending on the clock mode, as follows.
Line-locked clock mode
Frame-locked clock mode
Fixed-clock mode
Settings for pixel interpolar operation
INTPOL[1:0]-bit
Interpolar operation
00
Auto
01
ON
10
OFF
11
Reserved
OFF
ON
ON
Sub Address: 0x0C [5:4]
Notes
Dependent on clock mode
[7.23] Phase correction
In PAL-B, D, G, H, I, N, Nc, 60, and M decoding, the AK8858 performs phase correction for each line. With this
function ON, color averaging is performed for each line. In the adaptive phase correction mode, interline phase
correlation is sampled and color averaging is performed for correlated samples.
Interline color averaging is also performed in NTSC-M and J decoding.
No phase correction or color averaging is performed in SECAM decoding.
Settings for phase correction
DPAL[1:0]-bit
00
01
10
11
Status
Adaptive phase correction mode
Phase correction ON
Phase correction OFF
Reserved
Sub Address: 0x0D [1:0]
Notes
[7.24] No-signal output
If no input signal is found (as shown by control bit NOSIG-bit), the output signal is black-level, blue-level
(blueback), or input-state (sandstorm), depending on the register setting.
Settings for output signals for no input signal
NSIGMD [1:0]-bit
Output
00
Black-level
01
Blue-level (blueback)
10
Input-state (sandstorm)
11
Reserved
MS1230-E-01
Sub Address: 0x0D [3:2]
Notes
2011/7
- 41 -
[AK8858]
[7.25] Output data format
AK8858 output YCbCr or RGB data.
Output format
bit
8bit
YCbCr
16bit
RGB
24bit
Settings for YCbCr output data width
Name
Definition
Notes
[0]: 8bit
ODFMT
Sub Address: 0x09 [0]
If RGBCNV = [1], output data is 24bit.
[1]: 16bit
Settings for RGB output
Sub Address: 0x09 [2]
Name
Definition
Notes
RGBCNV
[0]: YCbCr
[1]: RGB
If RGBCNV = [1], output data is 24bit.
[7.25.1] YCbCr 8bit output format
Interlace
DTCLK
(27MHz)
DATA[7:0]
・・・
Cbn
Y2n
Crn
Y2n+1 Cbn+1 Y2n+2 Crn+1 Y2n+3 Cbn+2 Y2n+4 Crn+2
・・・
・・・
Cbn
Y2n
Crn
Y2n+1 Cbn+1 Y2n+2 Crn+1 Y2n+3 Cbn+2 Y2n+4 Crn+2
・・・
Progressive
DTCLK
(54MHz)
DATA[7:0]
DATA[23:8] is low output.
[7.25.2] YCbCr 16bit output format
Interlace
DTCLK
(13.5MHz)
Data[7:0]
Y0
Y1
Y2
Y3
Y4
Y5
・・・
Y2n
Data[15:8]
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
・・・
Cbn
Data[7:0]
Y0
Y1
Y2
Y3
Y4
Y5
・・・
Y2n
Data[15:8]
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
・・・
Cbn
Y2n+1 Y2n+2 Y2n+3 Y2n+4 Y2n+5
Crn
・・・
Cbn+1 Crn+1 Cbn+2 Crn+2
・・・
Y2n+1 Y2n+2 Y2n+3 Y2n+4 Y2n+5
・・・
Progressive
DTCLK
(27MHz)
Crn
Cbn+1 Crn+1 Cbn+2 Crn+2
・・・
DATA[23:16] is low output.
MS1230-E-01
2011/7
- 42 -
[AK8858]
[7.25.3] RGB 24bit output format
Interlace
DTCLK
(13.5MHz)
Data[7:0]
G0
G1
G2
G3
G4
G5
・・・
Gn
Gn+1
Gn+2
Gn+3
Gn+4
Gn+5
・・・
Data[15:8]
B0
B1
B2
B3
B4
B5
・・・
Bn
Bn+1
Bn+2
Bn+3
Bn+4
Bn+5
・・・
Data[23:16]
R0
R1
R2
R3
R4
R5
・・・
Rn
Rn+1
Rn+2
Rn+3
Rn+4
Rn+5
・・・
Data[7:0]
G0
G1
G2
G3
G4
G5
・・・
Gn
Gn+1
Gn+2
Gn+3
Gn+4
Gn+5
・・・
Data[15:8]
B0
B1
B2
B3
B4
B5
・・・
Bn
Bn+1
Bn+2
Bn+3
Bn+4
Bn+5
・・・
Data[23:16]
R0
R1
R2
R3
R4
R5
・・・
Rn
Rn+1
Rn+2
Rn+3
Rn+4
Rn+5
・・・
Progressive
DTCLK
(27MHz)
MS1230-E-01
2011/7
- 43 -
[AK8858]
[7.26] Output Interface
[7.26.1] Interface with EAV/SAV
SYNC code is output with the output data.
[7.26.1.1] EAV/ SAV code
Those code succeeding 0xFF – 0x00 – 0x00 which are fed as input data become EAV/SAV codes.
EAV/SAV codes have following meanings, started with MSB.
Bit Number
MSB
LSB
WORD
VALUE
7
6
5
4
3
2
1
0
0
0xFF
1
1
1
1
1
1
1
1
1
0x00
0
0
0
0
0
0
0
0
2
0x00
0
0
0
0
0
0
0
0
3
0xXX (EAV/ SAV)
1
F
V
H
P3
P2
P1
P0
F=0: Field1
F=1: Field2
*In case of Progressive (525P/ 625P) output, F-bit output is always 0.
V=0: Exept for Field Blanking
V=1: Field Blanking
H=0: SAV
H=1: EAV
P3, P2, P1, P0: Protection bit
Following is a relation between protection bit and F/V/H-bit.
F
V
H
P3
P2
P1
P0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
0
1
0
0
0
1
1
1
1
0
1
1
0
1
0
Reference standards
Input format
525i
625i
525p
625p
Reference
ITU-R.BT656
ITU-R.BT656
SMPTE 293M
ITU-R. BT1358
MS1230-E-01
2011/7
- 44 -
[AK8858]
[7.26.1.2] EAV/SAV code position
YCbCr 8bit 525Line
Cb
Y
Cr
Y
359 718 359 719
YCbCr 8bit 625Line
Cb
Y
Cr
Y
359 718 359 719
YCbCr 16bit 525Line
Y
Y
Y
718
719
720
0xFF
Cb
360
0xFF
Y
720
0x00
Cr
360
0x00
Y
721
EAV
Cb
360
0xFF
Y
720
0x00
Cr
360
0x00
Y
721
EAV
Y
721
0x00
…
Cb
428
0xFF
Y
856
0x00
Cr
428
0x00
Y
857
SAV
Cb
0
Y
0
Cr
0
Y
1
…
Cb
431
0xFF
Y
862
0x00
Cr
431
0x00
Y
863
SAV
Cb
0
Y
0
Cr
0
Y
1
Y
722
0x00
Y
723
EAV
…
Y
854
0xFF
Y
855
0x00
Y
856
0x00
Y
857
SAV
Y
0
Y
1
Y
722
0x00
Y
723
EAV
…
Y
860
0xFF
Y
861
0x00
Y
862
0x00
Y
863
SAV
Y
0
Y
1
Only Y signal with EAV/SAV
YCbCr 16bit 625Line
Y
Y
Y
718
719
720
0xFF
Y
721
0x00
Only Y signal with EAV/SAV
RGB 24bit 525Line
RGB
RGB
RGB
718
719
720
0xFF
RGB
721
0x00
RGB
722
0x00
RGB
723
EAV
…
RGB
854
0xFF
RGB
855
0x00
RGB
856
0x00
RGB
857
SAV
RGB
0
RGB
1
RGB
722
0x00
RGB
723
EAV
…
RGB
860
0xFF
RGB
861
0x00
RGB
862
0x00
RGB
863
SAV
RGB
0
RGB
1
All of RGB signal with EAV/SAV
RGB 24bit 625Line
RGB
RGB
RGB
718
719
720
0xFF
RGB
721
0x00
All of RGB signal with EAV/SAV
MS1230-E-01
2011/7
- 45 -
[AK8858]
[7.26.1.3] F-bit, V-bit
Code relation between F-bit in EAV/SAV and line number.
F-bit
525i
625i
0
Line4~Line265
Line266~Line525
Line1~Line3
Line1~Line312
1
525P/625P
F-bit = 0
Line313~Line625
Code relation between V-bit in EAV/SAV and line number.
Interlace
Name
Sub Address: 0x05 [4]
Setting
[0]
BT. 656-3
TRSVSEL [1]
BT. 656-4 or
SMPTE125M
Not affected by VBIL[2:0]-bit
525i
625i
V-bit=0
V-bit=1
Line10~Line263
Line273~Line525
Line1~Line9
Line264~Line272
Line20~Line263
Line283~Line525
Line1~Line19
Line264~Line282
V-bit=0
V-bit=1
Line23~Line310
Line336~Line623
Line1~Line22
Line311~Line335
Line624~Line625
Progressive
Name
Sub Address: 0x05 [4]
Setting
[0]
SMPTE293M
or
TRSVSEL
EIA-770.2-A
[1]
EIA-770.2-C
Not affected by VBIL[2:0]-bit
525p
625p
V-bit=0
V-bit=1
Line43~Line525
Line1~Line42
Line46~Line525
V-bit=0
V-bit=1
Line45~Line620
Line1~Line44
Line621~Line625
Line1~Line45
[7.26.1.4] exclude EAV/SAV flag
Sub Address: 0x09 [3]
Name
Definition
[0]: Output data with EAV/SAV flag.
EAVSAV
[1]: Output data without EAV/SAV flag.
If LIMIT601*= [0], output code range are 0∼255 (*Sub Address: 0x05 [3])
MS1230-E-01
2011/7
- 46 -
[AK8858]
[7.26.1.5] Operating used EAV/SAV
[7.26.1.5.1] Line-locked and frame-locked clock modes
In both of these modes, the output data are compliant with ITU-R BT.656 (525i/625i), SMPTE293M (525p), and
ITU-R. BT1358 (625p), which is requires the following samples and line numbers.
- Number of samples for 1 line:
858 samples (525i/525) / 864 samples (625i/625p)
- Number of lines for 1 frame:
525 lines / 625 lines
It may not be possible, however to meet these requirement if the input signal quality is poor.
[Line drop/repeat processing]
A line drop or a line repeat will result in output signal with 524/624 or 526/626 lines per frame respectively.
Line drop/repeat processing may be performed at any line in the frame.
[Pixel drop/repeat processing]
A pixel drop or a pixel repeat will result in output signals less or more than the required 858/864 samples in
the last line of the frame or field respectively.
Note: In the event of output-stage buffer failure, line drop/repeat processing will be performed even if the
register is for pixel drop/ repeat processing.
Line or pixel drop/repeat
ERRHND-bit
00
01
10
11
Sub Address: 0x0D [5:4]
Notes
Default
Processing mode
Line Drop / Line Repeat
Pixel Drop / Pixel Repeat by Field
Pixel Drop / Pixel Repeat by Frame
Reserved
[7.26.1.5.2] Fixed clock mode
In fixed-clock mode, operation is at an internally generated 27 MHz clock, from a 24.576 MHz input clock. The
output signal is therefore not synchronized with the input signal, and thus not ITU-R BT.656 compliant. Data is
output in SAV format. As shown in the following figure, EAV is guaranteed for 720 pixels from SAV, but the
number of pixels from EAV to SAV is not.
SAV
EAV
720 pixels
858 / 864 ( NTSC / PAL ) pixels ± α
MS1230-E-01
2011/7
- 47 -
[AK8858]
[7.26.2] Interface used timing signal
For connection with devices having no ITU-R BT.656 interface, the AK8858 DVALID signal output identifies the
active video interval by remaining low throughout that period, as shown in the following figure.
In RGB output mode, it is suggest to use this interface when output the valid data
[7.26.2.1] HD pin output
AK8858 output HD signal for horizontal synchronization.
Pin name
Interlace /
Progressive
Interlace
HD
Progressive
525-Line
625-Line
Low for 4.7us at
15.734 kHz interval.
Low for 2.35us at
31.468 kHz interval.
Low for 4.7us at
15.625 kHz interval.
Low for 2.35us at
31.250 kHz interval.
[7.26.2.2] VD_FLD or DVAL_FLD pin output
AK8858 output VD, FIELD and DVALID signal.
Pin name
Interlace /
Progressive
Interlace
VD_FLD
Progressive
Interlace
DVAL_FLD
Progressive
Output
525-Line
625-Line
FIELD
Low output at Line4~Line6 or
Low output at Line1~Line3.5 or
Line266.5~Line269.5
Line313.5~Line315
ODD-Field: Low, EVEN-Field: High
VD
Low output at Line7~Line12
FIELD
Toggle by each flame
DVALID
Low during active video interval
FIELD
ODD-Field: Low,
DVALID
Low during active video interval
FIELD
Toggle by each flame
VD
Select output from VD_FLD pin
Low output at Line1~Line5
EVEN-Field: High
Sub Address: 0x07 [5]
Name
Definition
VDFSEL
[0]: VD
[1]: FIELD
Notes
Select output from DVAL_FLD pin
Sub Address: 0x07 [6]
Name
Definition
Notes
DVALFSEL
[0]: DVALID
[1]: FIELD
MS1230-E-01
2011/7
- 48 -
[AK8858]
[7.26.2.3] Position of HD, VD and FIELD
[7.26.2.3.1] 525Line Interlace
523
524
525
1
2
3
4
5
6
7
8
9
10
11
269
270
271
272
273
274
3
4
5
6
7
8
316
317
318
319
320
321
Input
Video
HD
VD
FIELD
2nd Field
261
262
263
264
265
1st Field
266
267
268
Input
Video
HD
VD
FIELD
1st Field
2nd Field
If 262 or 263 line signal input, FIELD signali is toggled.
[7.26.2.3.2] 625Line Interlace
Input
Video
620
621
622
623
624
625
1
2
HD
VD
FIELD
2nd Field
Input
Video
308
309
310
311
312
1st Field
313
314
315
HD
VD
FIELD
1st Field
2nd Field
If 312 or 313 line signal input, FIELD signali is toggled.
MS1230-E-01
2011/7
- 49 -
[AK8858]
[7.26.2.3.3] 525Line Progressive
Input
Video
1
2
6
7
8
…
11
12
13
…
41
42
43
625
1
2
3
4
5
6
…
43
44
45
…
HD
VD
FIELD
FIELD signal is toggled.
[7.26.2.3.4] 625Line Progressive
Input
Video
621
622
…
HD
VD
FIELD
FIELD signal is toggled.
[7.26.2.4] Position of HD, DVALID and EAV/SAV code
DTCLK
HD
DVALID
DATA [7:0]
FF
00
00
SAV Cb0
Y0
Cr0
Y1
Cb1
HD
Y2
Cr1
FF
00
ACT
00
EAV
FF
ACTEND
ACTSTRT
Input signal
525Line
625Line
YCbCr 8bit
HD
(CLK)
128
ACTSTRT
(CLK)
244
ACT
(CLK)
1440
ACTEND
(CLK)
32
YCbCr 16bit
64
122
720
16
RGB 24bit
64
122
720
16
YCbCr 8bit
128
264
1440
24
YCbCr 16bit
64
132
720
12
RGB 24bit
64
132
720
12
bit
MS1230-E-01
Notes
1CLK = DTCLK rate
2011/7
- 50 -
[AK8858]
[7.26.2.5] Pin polarity
Sub Address: 0x0B [7:5]
Register
Name
Pin name
Signal
HDP
HD
VD_FP
VD_FLD
DVAL_FP
DVAL_FLD
Setting
[0]
[1]
HD
Active Low
Active High
VD
Active Low
Active High
Low: Odd-Field
High: Even-Field
Active Low
Low: Even-Field
High: Odd-Field
Active High
Low: Odd-Field
High: Even-Field
Low: Even-Field
High: Odd-Field
Field
DVALID
Field
DTCLK polarity
Sub Address: 0x07 [7]
Name
Definition
CLKINV
[0]: Normal output ( rise edge to data)
[1]: Inverted( fall edge to data)
[7.26.2.6] Timing signal on fixed clock mode
DTCLK
HD
DVALID
DATA [7:0]
FF
00
00
SAV Cb0
Y0
HD
Cr0
Y1
Cb1
Y2
ACT
Cr1
FF
00
00
EAV
FF
ACTEND
ACTSTRT
Fixed
Not fixed
MS1230-E-01
2011/7
- 51 -
[AK8858]
[7.27] Sync separation, sync detection, black-level detection and digital pedestal clamp
The AK8858 performs sync separation and sync detection on the digitized input signal, uses the detected sync
signal as the timing reference for the decoding process, and calculates the phase error from the separated sync
signal and applies it to control of the sampling clock.
The digitally converted input signal is clamped in the digital signal processing block. The internal clamp position
depends on the input signal type (either 286 mV sync or 300 mV sync), but pedestal position is output as code
16 (8-Bit, ITU-R BT.601) for both types. The digital pedestal clamp function can adjust the time constant and
set the coring level.
Black-level tuning can be performed in the sync separation block. The black-level fine-tuning band, which is
10 bits wide before REC 601 conversion, can be adjusted -8~+7 LSB in 1-LSB steps, with one step resulting in
a change of about 0.4 LSB in the output code
Settings for digital pedestal clamp time constant
DPCT[1:0]-bit
Transition time constant
00
Fast
01
Middle
10
Slow
11
Disable
Sub Address: 0x10 [5:4]
Notes
Digital pedestal clamp OFF
Settings for digital clamp pedestal coring level
DPCC[1:0]-bit
Transition time constant (bit)
00
±1bit
01
±2bit
10
±3bit
11
Non-coring
Sub Address: 0x10 [7:6]
Notes
Settings for black-level fine tuning
Sub Address: 0x10 [3:0]
BKLVL[3:0]-bit
Code adjustment of black level
Approx. change in 601 level (LSB)
0001
+1
+0.4LSB
0010
+2
+0.8LSB
0011
+3
+1.2LSB
0100
+4
+1.6LSB
0101
+5
+2.0LSB
0110
+6
+2.4LSB
0111
+7
+2.8LSB
0000
Default
None
1000
-8
-3.2LSB
1001
-7
-2.8LSB
1010
-6
-2.4LSB
1011
-5
-2.0LSB
1100
-4
-1.6LSB
1101
-3
-1.2LSB
1110
-2
-0.8LSB
1111
-1
-0.4LSB
The black level is adjusted upward or downward by the value of the setting, which must be in 2’s-complement
form. Black-level adjustment is also enabled during the vertical blanking interval.
MS1230-E-01
2011/7
- 52 -
[AK8858]
[7.28] Color killer
In CVBS or S-video input, the chroma signal quality of the input signal is determined by comparison of its color
burst level against the threshold setting in the color killer control register. If the level is below the threshold, the
color killer is activated, resulting in processing of the input as a monochrome signal and thus with CbCr data
fixed at 0x80. Depending on the register setting, the color killer may also be activated by failure of the color
decode PLL lock.
Settings for color killer ON and OFF
COLKILL-bit
0
1
Sub Address: 0x11 [7]
Notes
Enable
Disable
Settings for color killer activation
CKILSEL-bit
Condition for activation
0
Burst level below threshold setting in CKLVL[3:0]-bits
Burst level below threshold setting in CKLVL[3:0]-bits, or
1
Failure of color decode PLL lock
For threshold setting
Sub Address: 0x11 [6]
Notes
Sub Address: 0x11 [3:0]
Name
Definition
CKLVL0
~
CKLVL3
[CKLVL3 : CKLVL0 ]
[0000]: −29.7dB
[0001]: −28.4dB
[0010]: −27.2dB
[0011]: −26.2dB
[0100]: −25.3dB
[0101]: −24.5dB
[0110]: −23.7dB
[0111]: −23.0dB
[1000]: −22.4dB (Default)
[1001]: −21.8dB
[1010]: −21.2dB
[1011]: −20.7dB
[1100]: −20.2dB
[1101]: −19.7dB
[1110]: −19.3dB
[1111]: −18.9dB
Used for threshold setting with SECAM input.
Sub Address: 0x11 [5:4]
Name
Definition
CKSCM0
~
CKSCM1
[CKSCM1 : CKSCM0 ]
[00]: {CKLVL[3:0]}
[01]: {0, CKLVL[3:1]} (1bit shift)
[10]: {0, 0, CKLVL[3:2]} (2bit shift)
[11]: Reserved
MS1230-E-01
2011/7
- 53 -
[AK8858]
[7.29] Image quality adjustment
Image quality adjustments consist of contrast, brightness, color saturation, and hue adjustment.
[7.29.1] Contrast adjustment
Setting for contrast adjustment inclination
Register
Sub Address: 0x12 [7:0]
Definition
[CONTSEL-bit =[0]*]
YOUT = (CONT / 128) x ( YIN - 128) +128
[CONTSEL-bit =[1]*]
YOUT = (CONT / 128) X YIN
CONT0
~
CONT7
YOUT: Contrast obtained by the calculation
YIN: Contrast before the calculation
CONT: Contrast gain factor (register setting value)
The gain factor can be set in the range {0~ (255 / 128)} in 1/128 step.
Default setting value is 0x80.
As the register setting shown in the above table, contrast adjustment inclination can be selected between 50%
and 0%.
Setting for contrast adjustment inclination
Sub Address: 0x0D [7]
Register
Definition
CONTSEL
[0]: 50%
[1]: 0%
[7.29.2] Brightness adjustment
Setting for brightness adjustment
Name
Sub Address: 0x13 [7:0]
Definition
YOUT = YIN + BR
BR0
~
BR7
YOUT: Brightness obtained by the calculation
YIN: Brightness before the calculation
BR: Brightness gain factor (register setting value)
The gain factor can be set in the range {-128 ~ 127} in 1 step.
The setting is in 2’s complement.
Settings for brightness and contrast adjustment status (ON/OFF) during VBI
Register
Status during VBI
VBIIMGCTL
[0]: Disable
[1]: Enable
MS1230-E-01
Sub Address: 0x14 [7]
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[AK8858]
[7.29.3] Color saturation adjustment
In composite (CVBS) or S-Video signals mode, saturation adjustment involves multiplication of the color signal
by the gain factor setting in this register. The calculated result is U/V demodulated.
In YPbPr mode, U and V value can be adjusted indivisually.
Sub Address: 0x15 [7:0]
Name
Definition
[composite (CVBS) or S-Video signals]
COUT = (SAT / 128) X CIN
COUT: C signal after calculation
CIN: C signal before calculation
SAT: Satulation factor (register setting value)
SAT0
~
SAT7
UTONE0
~
UTONE7
[Component video signal]
UOUT = (UTONE / 128) X UIN
UOUT: U signal after calculation
UIN: U signal before calculation
UTONE: Satulation factor (register setting value)
The gain factor can be set in the range 0 to 255/128, in steps of 1/128.
The default value is 0x80.
Sub Address: 0x16 [7:0]
Name
VTONE0
~
VTONE7
Definition
[Component video signal]
VOUT = (VTONE / 128) X VIN
VOUT: V signal after calculation
VIN: V signal before calculation
VTONE: Satulation factor (register setting value)
The gain factor can be set in the range 0 to 255/128, in steps of 1/128.
The default value is 0x80.
(Notice)
If component mode, UTONE and VTONE default value should be changed to following parameter.
UTONE [7:0] =0x70
VTONE [7:0] =0x9D
[7.29.4] HUE adjustment
Setting for HUE adjustment
Sub Address: 0x17 [7:0]
Name
Definition
HUE0
The phase rotation can be set in the range of ±45° in 1/256step (about 0.35step).
~
The setting is in 2’s complement.
HUE 7
HUE adjustment only valid for composite (CVBS) and S-Video signals input.
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[AK8858]
[7.29.5] Sharpness adjustment
Sharpness adjustment is performed on the luminance signal. The filter characteristic is shown in the following
diagram. A sharp image can be obtained by selection of the filter with the appropriate characteristics.
SHARP[1:0]-bit
Y Signal (before)
SHCORE[1:0]-bit
Filter
Coring
Y Signal (after)
Delay
Settings for filter characteristics selection
SHARP[1:0]-bit
Filter characteristics
00
No filtering
01
Min
10
Middle
11
Max
Settings for coring level after sharpness filtering
SHCORE[1:0]-bit
Coring level (LSB)
[00]
No coring
[01]
±1LSB
[10]
±2LSB
[11]
±3LSB
Sub Address: 0x14 [1:0]
Notes
Filter disabled
Sub Address: 0x14 [3:2]
Notes
Settings apply only to
filtered signal.
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[AK8858]
[7.29.6] Luminance bandwidth adjustment
Luminance bandwidth adjustment can be performed for MPEG compression etc. The band-limiting filters for
pre-compression limiting can be selected by the following register settings. Without these filters, the frequency
response of the luminance signal is determined by the decimation filter.
Settings for luminance bandwidth filter
LUMFIL [1:0]-bit
Filter characteristic
No filter
00
No bandwidth limit
01
Narrow
10
Mid
11
Wide
Sub Address: 0x14 [5:4]
Notes
Decimation filter characteristic
-3dB at 6.29MHz
-3dB at 2.94MHz
-3dB at 3.30MHz
-3dB at 4.00MHz
Luminance signal decimation filter
Luminance bandwidth filter
For 525/626p input signal, the bandwidth for each filter characteristic is expands about 2 times.
[7.29.7] Sepia output
Sepia-colored output of the decoded signal can be obtained by the following register setting.
Settings for sepia output of decoded signal
SEPIA –bit
Output
[0]
Normal output
[1]
Sepia output
MS1230-E-01
Sub Address: 0x14 [6]
Notes
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[AK8858]
[7.29.8] U/ V Filter
U/V signal bandwidth can be set via register
[Composite (CVBS) and S-Video signal input]
Setting for U/ V filter characteristic
UVFILSEL0–bit
U/V filter bandwidth
0
Wide
1
Narrow
[YPbPr signal input]
Setting for U/ V filter characteristic
UVFILSEL[1:0] -bit
U/V filter bandwidth
00
Middle 1
01
Middle 2
10
Wide 2
11
Narrow 2
Sub Address: 0x0C [2]
Notes
Sub Address: 0x0C [3:2]
Range
Narrow 2 < Middle 1 < Middle 2 < Wide 2
For 525/626p input signal, the bandwidth for each filter characteristic is expands about 2 times.
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[AK8858]
[7.30] VBI information decoding
The AK8858 decodes closed-caption, closed-caption-extended, VBID(CGMS), and WSS signals on the vertical
blanking signal, and writes the decoded data into a storage register. The AK8858 reads each data bit in
Request VBI Information register (Sub Address 0x1A [3:0]) as a decoding request and thereupon enters a data
wait state. Data detection and decoding to the storage register are then performed which indicates the
presence or absence of data at STATUS 2 register (Sub Address 0x23 [3:0]) for host. The host can therefore
determine the stored values by reading the respective storage registers. The value in each storage register is
retained until a new value is written in by data renewal. For VBID data (CGMS-A), the CRCC code is decoded
and only the arithmetic result is stored in the register.
Signal
Line Number
Notes
Closed Caption
Line21
525i
Closed Caption Extended Data
Line284
Line20 / 283
Line20 / 333
Line41
Line23
Line43
525i
525i
625i
525p
625i
625p
VBID
WSS
Following are store registers. (Sub Address: 0x26 ~ 0x2D)
Closed Caption 1 Register, Closed Caption 2 Register, WSS 1 Register, WSS 2 Register,
Extended Data 1 Register, Extended Data 2 Register, VBID 1 Register and VBID 2 Register
Reading data flow chart
START
[Request VBI Information Register]
xxRQ-bit = 1
(Decode request)
[Status 2 Register] Read
(Confirm decode ending)
No
Request bit
=1?
YES
Data Register
Reading
END
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[AK8858]
[7.31] Internal status indicators Register
[7.31.1] No signal detect
Indicates presence or absence of signal
Name
NOSIG
Sub Address: 0x22 [0]
Setting
Definition
Notes
[0]
Signal detected
[1]
No signal detected
[7.31.2] VLOCK status
Indicates status of VLOCK
Name
VLOCK
Sub Address: 0x22 [1]
Setting
Definition
Notes
[0]
Synchronized
[1]
Not synchronized
[7.31.3] Interlace Status
Indicate interlace or not of input video signal
Name
FRMSTD
Sub Address: 0x22 [2]
Setting
Definition
Notes
[0]
525/625 interlace
[1]
not 525/625 interlace
[7.31.4] Status of color killer operation
Indicates status of color killer
Name
COLKILON
Sub Address: 0x22 [3]
Setting
Definition
Notes
[0]
Not color killer operation
[1]
Color killer operation
[7.31.5] Status of clock mode
Indicates status of clock modeko
Name
SCLKMODE0
~
SCLKMODE1
Sub Address: 0x22 [5:4]
Setting
Definition
Notes
[00]
Fixed clock operation
[01]
Line lock clocked operation
[10]
Frame lock clocked operation
[11]
Reserved
[7.31.6] Luminance over flow
Indicates status of luminance decode result after passage through AGC block
Name
PKWHITE
Setting
Definition
[0]
Normal
[1]
Overflow
MS1230-E-01
Sub Address: 0x22 [6]
Notes
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[AK8858]
[7.31.7] Chrominance over flow
Indicates status of color decode result after passage through ACC block
Name
OVCOL
Setting
Definition
[0]
Normal
[1]
Overflow
[7.31.8] Field status
Indicates decoding signal field status
Name
REALFLD
AGCSTS
Notes
Sub Address: 0x23 [4]
Setting
Definition
[0]
EVEN field
[1]
ODD field
[7.31.9] AGC status
Indicates status of adaptive AGC
Name
Sub Address: 0x22 [7]
Notes
Sub Address: 0x23 [5]
Setting
Definition
[0]
Sync AGC operation
[1]
Peak AGC operation
Notes
[7.32] Macrovision signal detection
The AK8858 can detect a decode signal contains Macrovision signal.
The detection result can be confirmed via register.
Indicate signal contains Macrovision signal
Name
Sub Address: 0x24 [2:0]
Definition
0: No Macrovision AGC process detected
1: Macrovision AGC process detected
0: No Color Stripe Process detected
CSDET
1: Color Stripe Process detected
0: Color Stripe Type 2 in input signal
CSTYPE
1: Color Stripe Type 3 in input signal
If detect macrovision signal on progressive decoding, AGCDET-bit = [1].
AGCDET
[7.32.1] Macrovision Color Stripe Cancel
This function is cancellor for macrovision color stripe.
Set CSCAN bit to [1] only when Sub=Address 0x04[7:0] is [XXX00000] setting.
Set CSCAN bit to [0] when Sub=Address 0x04[7:0] is not [XXX00000] setting.
(X: Don’t care)
Sub Address: 0x03 [6]
Color stripe cancel
Name
Definition
CSCAN
Set to [1] only when Sub=Address 0x04[7:0] is [XXX00000] setting.
Set to [0] when Sub=Address 0x04[7:0] is not [XXX00000] setting.
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[AK8858]
[7.33] Auto detection result of input video signal
In auto detection mode, the result can be acknowledged by reading the following register.
Indicates result and status of auto detection mode
Name
ST_VSCF0
~
ST_VSCF1
ST_VCEN0
~
ST_VCEN1
ST_VLF
ST_BW
UNDEF
FIXED
Sub Address: 0x25 [7:0]
Definition
(CVBS or S-video signal decoding)
Input video signal subcarrier frequency indicator
[ ST_VSCF1 : ST_VSCF0 ] ( MHz )
[00]: 3.57954545 (NTSC-M,J)
[01]: 3.57561149 (PAL-M)
[10]: 3.58205625 (PAL-Nc)
[11]: 4.43361875 (PAL-B,D,G,H,I,N,60 , NTSC-4.43, SECAM)
(Component signal decoding)
Interlace or Progressive indicator
[00]: Interlace
[01]: Progressive
[10]: Reserved
[11]: Reserved
Input signal color encode format indicator
[ST_VCEN1 : ST_VCEN0]
[00]: NTSC
[01]: PAL
[10]: SECAM
[11]: Component setting*
Input signal line number indicator
[0]: 525-Line (NTSC-M,J , NTSC-4.43 , PAL-M,60)
[1]: 625-Line (PAL-B,D,G,H,I,N,Nc , SECAM)
Input signal monochrome indicator*
[0]: Not monochrome
[1]: Monochrome
Input signal detection indicator
[0]: Input signal detected
[1]: Input signal not detected
Input signal detection process status
[0]: Detection process in progress
[1]: Detection process completed
*Monochrome auto detection is enabled if the color killer setting is ON (COLKILL-bit = [1]).
* ST_VCEN[1:0] is [11] when Sub-Address 0x00[6:5] is set to [10] (Component video input).
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[8] Device control interface
The AK8858 is controlled via I2C bus control interface, as described below.
[8.1] I2C bus SLAVE Address
Slave Address
SELA pin status MSB
LSB
Pulldown [Low] 1
0 0 0 1 0 0 R/W
Pullup [High]
1
0 0 0 1 0 1 R/W
[8.2] I2C control sequence
[8.2.1] Write sequence
After receiving a write-mode slave address first byte, the AK8858 receives the sub-address in the second byte
and data in the subsequent bytes. The write sequence may be single-byte or multi-byte.
(a) Single-byte write sequence
S
Slave Address
w
8-bit
A
Sub Address
A
Data
A
1-bit
8-bit
1-bit
8-bit
1-bit
(b) Multi-byte writes sequence (Sequential Write Operation)
Slave
Sub
A
S
w A
Data(n)
A
Address
Address(n)
8-bit
1-bit 8-bit
1-bit 8-bit
1-bit
Data
(n+1)
8-bit
Data
(n+m)
8-bit
A
1-bit
‘’’’’’’
Stp
A
stp
1-bit
[8.2.2] Read sequence
After receiving a read-mode slave address as first byte, the AK8858 sends data in the second and subsequent
bytes.
Slave
Sub
Slave
A rS
S
w A
R A Data1 A Data2 A Data3
A
Address
Address(n)
Address
‘’’‘’
8-bit
1
8-bit
1
8-bit
1
8-bit
1
8-bit
1
8-bit
1
’‘’’’’‘’’
‘’‘
Data n
!A
8-bit
1
stp
S : Start Condition
rS : repeated Start Condition
A : Acknowledge (SDA Low )
!A : Not Acknowledge (SDA High)
stp : Stop Condition
R/W 1 : Read 0 : Write
: Received from master device (normally microprocessor)
: Output by slave device (AK8858)
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[AK8858]
[9] Register Definitions
SubAddress
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
∼
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
~
0x3F
Register
Default
R/W
Function
Input Channel Select Regsiter
Clamp Control 1
Clamp Control 2
Miscellaneous Setting
Input Video Standard
Output Format
NDMODE
Output Control
Output Data Start andDelay Control
Output Data Format(YUV/RGB)
AGC & ACC Control
Control 0
Control 1
Control 2
PGA1 Control
PGA2 Control
Pedestal Level Control
Color Killer Control
Contrast Control
Brightness Control
Image Control
Saturation / U Tone Control
V Tone Control
HUE Control
High Slice Data Set
Low Slice Data Set
Request VBI Information
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x54
0x54
0x00
0x08
0x80
0x00
0x00
0x80
0x80
0x00
0xEB
0x10
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Input channel setting
Clamp pulse setting register 1
Clamp pulse setting register 2
Input video signal setting
Output format setting
Auto detection limit setting
Output pin status setting
Output data timing setting
Output data format setting
AGC and ACC setting
Control register type
Control register type
Control register type
PGA1 gain setting
PGA2 gain setting
Pedestal level adjustment
Color killer setting
Contrast adjustment
Brightness adjustment
Image control setting
Saturation (Y) / Color (U)control
Color (V) control
Hue adjustment
VBI Slice Data High setting
VBI Slice Data Low setting
VBI interval decode request setting
Reserved
0x00
-
Reserved register
Status 1 Register
Status 2 Register
Macrovision Status Register
Input Video Status Register
Closed Caption 1 Register
Closed Caption 2 Register
WSS 1 Register
WSS 2 Register
Extended Data 1 Register
Extended Data 2 Register
VBID 1 Register
VBID 2 Register
Device and Revision ID
0x3A
R
R
R
R
R
R
R
R
R
R
R
R
R
Internal status indicator
Internal status indicator
Input Macrovision signal indicator
Input signal detection indicator
Closed caption data indicator
Closed caption data indicator
WSS data indicator
WSS data indicator
CC-Extended data indicator
CC-Extended data indicator
VBID data indicator
VBID data indicator
Device ID / Revision ID
Reserved
0x00
-
Reserved register
For all other registers, write-in is prohibited.
For all reserved registers, write-in must be limited to the default value.
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[9.1] Register setting overview
[9.1.1] Input Channel Select Register (R/W) [Sub Address 0x00]
Input signal channel selection and clock mode selection register.
Sub Address: 0x00
bit 7
bit 6
CLKMOD
SELSRC1
Default Value
0
0
bit 5
SELSRC0
bit 4
ADC3SEL
bit 3
ADC2SEL
bit 2
ADC1SEL2
Default Value: 0x00
bit 1
bit 0
ADC1SEL1
ADC1SEL0
0
0
0
0
0
Input Channel Select Register
BIT
Register Name
R/W
bit 0
~
bit 2
ADC1SEL0
~
ADC1SEL2
ADC 1 Select
R/W
bit 3
ADC2SEL
ADC 2 Select
R/W
bit 4
ADC3SEL
ADC 3 Select
R/W
bit 5
~
bit 6
SELSRC0
~
SELSRC1
Select Source
R/C
bit 7
CLKMOD
Clock Mode
R/W
0
Definition
ADC1 input signal selection
000: AIN1
001: AIN2
010: AIN3
011: AIN4
100: AIN5
101: AIN6
Virtual ADC2 input signal selection
0: AIN7
1: AIN8
Virtual ADC3 input signal selection
0: AIN9
1: AIN10
Decode signal selection
00: Composite (CVBS)
01: S-Video
10: Component (YPbPr)
11: No input signal (Analog block is powerdown)
Clock mode selection
0: For crystal
1: External clock input (clock generator etc.)
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[9.1.2] Clamp Control 1 Register (R/W) [Sub Address 0x01]
Clamp pulse setting.
Sub Address: 0x01
bit 7
bit 6
CLPCLPWIDTH1
WIDTH0
Default Value
0
0
bit 5
CLPSTAT1
bit 4
CLPSTAT0
0
0
Clamp Control 1 Register
BIT Register Name
R/W
bit 0
~
bit 2
BCLPSTAT0
~
BCLPSTAT2
Back Porch
Clamp Start
R/W
bit 3
Reserved
Reserved
R/W
bit 4
~
bit 5
CLPSTAT0
~
CLPSTAT1
Clamp Start
R/W
bit 6
~
bit 7
CLPWIDTH0
~
CLPWIDTH1
Clamp Pulse
Width
R/W
bit 3
Reserved
0
bit 2
BCLPSTAT2
Default Value: 0x00
bit 1
bit 0
BCLPBCLPSTAT1
STAT0
0
0
0
Definition
Backporch clamp start position setting.
The default position is at the center of Sync signal.
[ BCLPSTAT2 : BCLPSTAT0 ]
[000]: Same position as default “CLPSTAT”
[001]: (1/128)H delay from “CLPSTAT”
[010]: (2/128)H delay from “CLPSTAT”
[011]: (3/128)H delay from “CLPSTAT”
[100]: (4/128)H advance from “CLPSTAT”
[101]: (3/128)H advance from “CLPSTAT”
[110]: (2/128)H advance from “CLPSTAT”
[111]: (1/128)H advance from “CLPSTAT”
Reserved
Clamp pulse start position setting.
The default position is at the center of horizontal Sync signal.
[ CLPSTAT1 : CLPSTAT0 ]
[00]: Center of horizontal sync (default position)
[01]: (1/128)H delay
[10]: (2/128)H advance
[11]: (1/128)H advance
Clamp pulse width setting.
Pulse width is change according to sampling clock units.
[ CLPWIDTH1 : CLPWIDTH0 ]
[00]: 7-clk
[01]: 15-clk
[10]: 31-clk
[11]: 63-clk
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[AK8858]
[9.1.3] Clamp Control 2 Register (R/W) [Sub Address 0x02]
Clamp pulse control setting.
Sub Address: 0x02
bit 7
bit 6
Reserved
Reserved
Default Value
0
0
bit 5
Reserved
bit 4
YPBPRCP
bit 3
UDG1
bit 2
UDG0
Default Value: 0x01
bit 1
bit 0
CLPG1
CLPG0
0
0
0
0
0
Clamp Control 2 Register
BIT
Register Name
R/W
bit 0
~
bit 1
CLPG0
~
CLPG1
Clamp Gain
R/W
bit 2
~
bit 3
UDG0
~
UDG1
Up Down Gain
R/W
bit 4
YPBPRCP
YPbPr Clamp
R/W
bit 5
~
bit 7
Reserved
Reserved
R/W
1
Definition
Current value of fine clamp in analog circuit setting
CLPG[1:0]
00: Min
01: Middle 1 (default)
10: Middle 2
11: Max
Current value of rough clamp in analog circuit setting
[ UDG1 : UDG0 ]
00: Min (default)
01: Middle 1
10: Middle 2
11: Max
Clamp position of PbPr signal input setting
0: YPbPr sync tip timing
1: Y sync tip timing / PbPr backporch
Reserved
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[9.1.4] Miscellaneous Setting Register (R/W) [Sub Address 0x03]
Sub Address: 0x03
bit 7
bit 6
VERTS
CSCAN
Default Value
0
0
bit 5
Reserved
bit 4
CMPSEL
bit 3
CSCL
bit 2
CSSL
Default Value: 0x00
bit 1
bit 0
Reserved
Reserved
0
0
0
0
0
Miscellaneous Setting Register
BIT
Register Name
R/W
Definition
R/W
Reserved
bit 0
~
bit 1
Reserved
bit 2
CSSL
bit 3
CSCL
bit 4
CMPSEL
Component
Signal Select
R/W
bit 5
Reserved
Reserved
R/W
bit 6
CSCAN
Color stripe
cancel
R/W
bit 7
VERTS
Vertical
SYNC way
R/W
Reserved
Component
Signal
Sync Level
Component
Signal
Color Level
R/W
R/W
0
YPbPr signal sync / luminance ratio level setting
0: 300/700
1: 286/714
Color (PbPr) signal level setting
0: 700mV
1: 714mV
Component signal input, interlace / progressive setting
(auto detection mode is disable).
0: Interlace (525i/625i)
1: Progressive (525p/625p)
Reserved
Color stripe cancel operation
Set to [1] only when Sub=Address 0x04[7:0] is [XXX00000]
Set to [0] when Sub=Address 0x04[7:0] is not [XXX00000]
Vertical sync mechanism setting
0: VLOCK mechanism
1: Direct lock mechanism
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[9.1.5] Input Video Standard Register (R/W) [Sub Address 0x04]
Input signal setting.
Sub Address: 0x04
bit 7
bit 6
AUTODET
SETUP
Default Value
0
0
bit 5
BW
bit 4
VLF
bit 3
VCEN1
bit 2
VCEN0
Default Value: 0x00
bit 1
bit 0
VSCF1
VCSF0
0
0
0
0
0
Input Video Standard Register
BIT
Register Name
R/W
bit 0
~
bit 1
VSCF0
~
VSCF1
Video
Sub-Carrier Frequency
R/W
bit 2
~
bit 3
VCEN0
~
VCEN1
Video Color Encode
R/W
bit 4
VLF
Video Line Frequency
R/W
bit 5
BW
Black & White
R/W
bit 6
SETUP
Setup
R/W
bit 7
AUTODET
Video Standard
Auto Detect
R/W
0
Definition
Input video signal subcarrier frequency setting
[VSCF1:VSCF0]
00: 3.57954545 MHz (NTSC)
01: 3.57561149 MHz (PAL-M)
10: 3.58205625 MHz (PAL-Nc)
11: 4.43361875 MHz (PAL-B,D,G,H,I,N)*
Input signal color encode format setting
[VCEN1:VCEN0]
00: NTSC
01: PAL
10: SECAM
11: Reserved (prohibited)
Input signal line frequency setting
0: 525
1: 625
Monochrome mode (ON/OFF) setting *2
[0] : Monochrome mode OFF
[1] : Monochrome mode ON
Setup process setting
[0] : Process as input signal with no setup
[1] : Process as input signal with setup
Input signal auto detection setting
[0]: OFF (auto detection disabled; set manually)
[1]: ON (auto detection enabled)
* For SECAM input signal,change VSCF[1:0] setting to [11]
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[AK8858]
[9.1.6] Output Format Register (R/W) [Sub Address 0x05]
Output data format setting.
Sub Address: 0x05
bit 7
bit 6
VBIDEC1
VBIDEC0
Default Value
0
0
bit 5
SLLVL
bit 4
TRSVSEL
bit 3
601LIMIT
bit 2
VBIL2
Default Value: 0x00
bit 1
bit 0
VBIL1
VBIL0
0
0
0
0
0
Output Format Register
BIT
Register Name
bit 0
~
bit 2
bit 3
VBIL0
~
VBIL2
R/W
Vertical
Blanking
Interval Length
R/W
601LIMIT
601 Output Limit
R/W
bit 4
TRSVSEL
Time
Reference
Signal
V Select
R/W
bit 5
SLLVL
Slice Level
R/W
bit 6
~
bit 7
VBIDEC0
~
VBIDEC1
VBI Decode
R/W
0
Definition
Vertical blanking interval length setting,
entered as difference from the default settings
The default settings are:
(525i) Line1~Line19 and Line263.5~Line282.5
(625i) Line623.5~Line23.5 and Line311~Line335
(525p) Line1~Line42
(625p) Line 621~Line625 and Line1~Line44
Examples of lengthening and shortening:
If lengthened 1 line, the interval becomes
(525i) Line1~Line20 and Line263.5~Line283.5
(625i) Line623.5~Line24.5 and Line311~Line336
(525p) Line1~Line43
(625p) Line 621~Line625 and Line1~Line45
If shortened 1 line, the interval becomes
(525i) Line1~Line18 and Line263.5~Line281.5
(625i) Line623.5~Line22.5 and Line311~Line334
(525p) Line1~Line41
(625p) Line 621~Line625 and Line1~Line43
[ VBIL2 : VBIL0 ]
[001]: VBI lengthened 1 line
[010]: VBI lengthened 2 lines
[011]: VBI lengthened 3 lines
[000]: Default
[101]: VBI shortened 3 lines
[110]: VBI shortened 2 lines
[111]: VBI shortened 1 line
[100]: Reserved
Output data code limit (Min-Max) setting
0: 1-254 (Y/CbCr)
1: 16-235 (Y), 16-240 (Cb/Cr)
Setting of lines for “Time reference signal”
V-bit value change in ITU-R BT.656 format
0: ITU-R Bt.656-3
1: ITU-R Bt.656-4 and SMPTE125M
Slice level setting
0: Slice level approx. 25 IRE
1: Slice level approx. 50 IRE
Setting for type of data output during interval
set in Vertical Blanking Interval register *
[ VBIDEC1: VBIDEC0 ]
[00]: Black level data output
[01]: Monochrome data output
[10]: Slice result data output
[11]: Reserved
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[AK8858]
[9.1.7] NDMODE Register (R/W) [Sub Address 0x06]
Limiting auto input video signal detection candidates register setting
Sub Address: 0x06
bit 7
bit 6
ND625L
ND525L
Default Value
0
0
bit 5
NDPAL60
bit 4
NDNTSC443
bit 3
Reserved
bit 2
NDSECAM
Default Value: 0x00
bit 1
bit 0
NDPALNC
NDPALM
0
0
0
0
0
NDMODE Register
BIT
Register Name
R/W
bit 0
NDPALM
No Detect PAL-M
R/W
bit 1
NOPALNC
No Detect PAL-NC
R/W
bit 2
NDSECAM
No Detect SECAM
R/W
bit 3
Reserved
Reserved
R/W
bit 4
NDNTSC443
No Detect NTSC-4.43
R/W
bit 5
NDPAL60
No Detect PAL60
R/W
bit 6
ND525L
No Detect 525 Line
R/W
bit 7
ND625L
No Detect 625 Line
R/W
0
Definition
0: PAL-M candidate
1: PAL-M non-candidate
0: PAL-Nc candidate
1: PAL-Nc non-candidate
0: SECAM candidate
1: SECAM non-candidate
Reserved
0: NTSC-4.43 candidate
1: NTSC-4.43 non-candidate
0: PAL-60 candidate
1: PAL-60 non-candidate
0: 525 line candidate
1: 525 line non-candidate
0: 625 line candidate
1: 625 line non-candidate
In making the above register settings, the following restrictions apply,
1. Setting both NDNTSC443(bit 4) and NDPAL60(bit 5) to [1] (High) is prohibited.
2. Setting both ND525L(bit 6) and ND625L(bit 7) to [1] (High) is prohibited.
3. To limit candidate formats, it is necessary to have the auto detection mode OFF while first setting the
register to non-limited signal status and next the NDMODE settings, and then setting the auto detection
mode to ON.
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[AK8858]
[9.1.8] Output Control Register (R/W) [Sub Address 0x07]
Output pin status register setting.
Sub Address: 0x07
bit 7
bit 6
CLKINV
DVALFSEL
Default Value
0
0
bit 5
VDFSEL
bit 4
HL
bit 3
NL
bit 2
DVALFL
Default Value: 0x00
bit 1
bit 0
VDFL
DL
0
0
0
0
0
Output Control Register
BIT Register Name
R/W
bit 0
DL
Data Output Low bit
bit 1
VDFL
bit 2
DVALFL
bit 3
NL
NSIG Output Low bit
R/W
bit 4
HL
HD Output Low bit
R/W
bit 5
VDFSEL
VD_FLD Select bit
R/W
bit 6
DVALFSEL
DVAL_FLD Select bit
R/W
bit 7
CLKINV
Clock Invert Setting
R/W
VD_FLD
Output Low bit
DVAL_FLD
Output Low bit
R/W
R/W
R/W
0
Definition
0: Normal output
1: [D17: D0] pin output fixed at Low
0: Normal output
1: VD_FLD pin output fixed at Low
0: Normal output
1: DVAL_FLD pin output fixed at Low
0: Normal output
1: NSIG pin output fixed at Low
0: Normal output
1: HD pin output fixed at Low
0: VD signal output
1: FIELD signal output
0: DVALID signal output
1: FIELD signal output
0: Normal output (write in data at rising edge)
1: Data and clock reversed (write in data at falling edge)
Note: Output control via pins OE, PDN, and RSTN takes priority, regardless of the above settings.
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[AK8858]
[9.1.9] Output Data Start and Delay Control Register (R/W) [Sub Address 0x08]
Ouput data timing setting register.
Sub Address: 0x08
bit 7
bit 6
Reserved ACTSTAT2
Default Value
0
0
bit 5
ACTSTAT1
bit 4
ACTSTAT0
bit 3
Reserved
bit 2
YCDELAY2
Default Value: 0x00
bit 1
bit 0
YCDELAY1 YCDELAY0
0
0
0
0
0
Output Data Start and Delay Control Register
BIT Register Name
R/W
bit 0
~
bit 2
YCDEALY0
~
YCDELAY2
YC Delay
Control
R/W
bit 3
Reserved
Reserved
R/W
0
Definition
Adjustment of Y and C timing.
In D1 decode, delay or advance 1 sample unit is about 74ns
In D2 decode, delay or advance 1 sample unit is about 37ns.
YCDELAY[2:0]
[001]: Y advance 1-sample toward C.
[010]: Y advance 2-sample toward C.
[011]: Y advance 3-sample toward C.
[000]: No Delay and advance.
[101]: Y delay 3-sample toward C.
[110]: Y delay 2-sample toward C.
[111]: Y delay 1-sample toward C.
[100]: Reserved
Reserved
Fine-tuning video data decode start position
In D1 decode, delay or advance 1 sample unit is about 74ns
In D2 decode, delay or advance 1 sample unit is about 37ns.
bit 4
~
bit 6
ACTSTA0
~
ACTSTA2
Active Video
Start Control
R/W
bit 7
Reserved
Reserved
R/W
ACTSTA[2:0]
[001]: 1-sample delay
[010]: 2-sample delay
[011]: 3-sample delay
[000]: Normal start position
[101]: 3-sample advance
[110]: 2-sample advance
[111]: 1-sample advance
[100]: Reserved
Reserved
MS1230-E-01
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[AK8858]
[9.1.10] Output Data Format Register (R/W) [Sub Address 0x09]
Output data format setting register.
Sub Address: 0x09
bit 7
bit 6
Reserved
Reserved
Default Value
0
0
bit 5
Reserved
bit 4
Reserved
bit 3
EAVSAV
bit 2
RGBO
Default Value: 0x00
bit 1
bit 0
Reserved
ODFMT
0
0
0
0
0
Output Data Format Register
BIT
Register Name
R/W
bit 0
ODFMT
Output Data
Format
R/W
bit 1
Reserved
Reserved
R/W
bit 2
RGBO
RGB Convert
R/W
bit 3
EAVSAV
EAVSAV Disable
R/W
bit 4
~
bit 7
Reserved
Reserved
R/W
0
Definition
YCbCr output bit-width setting
0: 8-bit output
1: 16-bit output
Reserved
RGB convert output selection:
0: YCbCr data is output
1: RGB data is output
EAV/SAV output (ON/OFF) setting.
0: EAV/SAV ON
EAV/SAV is superimposed to Y or R/G/B data.
1: EAV/SAV OFF
Reserved
MS1230-E-01
2011/7
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[AK8858]
[9.1.11] AGC & ACC Control Register (R/W) [Sub Address 0x0A]
AGC and ACC setting register.
Sub Address: 0x0A
bit 7
bit 6
ACCFRZ
ACC1
Default Value
0
0
bit 5
ACC0
bit 4
AGCFRZ
bit 3
AGCC1
bit 2
AGCC0
Default Value: 0x00
bit 1
bit 0
AGCT1
AGCT0
0
0
0
0
0
AGC & ACC Control Register
BIT
Register Name
R/W
bit 0
~
bit 1
AGCT0
~
AGCT1
AGC Time Constance
R/W
bit 2
~
bit 3
AGCC0
~
AGCC1
AGC Coring Control
R/W
bit 4
AGCFRZ
AGC Freeze
R/W
bit 5
~
bit 6
ACCT0
~
ACCT1
ACC Time Constance
R/W
bit 7
ACCFRZ
ACC Freeze
R/W
MS1230-E-01
0
Definition
AGC time constant (T) setting
(if disabled, PGA can be set manually).
AGCT[1:0]
00: Disable
01: Fast [T = 1Filed]
10: Middle [T = 7Filed]
11: Slow [T = 28Filed]
AGC non-sensing bandwidth (LSB) setting
AGCC[1:0]
00: ±2 LSB
01: ±3 LSB
10: ±4 LSB
11: No non-sensing band
AGC freeze function (ON/OFF) setting
(AGC set values are saved during freeze)
0: Non-frozen
1: Frozen
ACC time constant (T) setting
ACCT[1: 0]
00: Disable
01: Fast [T = 2Fields]
10: Middle [T =8Fields]
11: Slow [T = 30Fields]
ACC freeze function (ON/OFF) setting
(ACC set values are saved during freeze)
0: Non-frozen
1: Frozen
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[AK8858]
[9.1.12] Control 0 Register (R/W) [Sub Address 0x0B]
Sub Address: 0x0B
bit 7
bit 6
DVAL_FP
VD_FP
Default Value
0
0
bit 5
HDP
bit 4
C443FIL1
bit 3
C443FIL0
bit 2
C358FIL1
Default Value: 0x00
bit 1
bit 0
C358FIL0
AGCTL
0
0
0
0
0
Control 0 Register
BIT
Register Name
R/W
bit 0
AGCTL
AGC Transition Level
R/W
bit 1
~
bit 2
C358FIL0
~
C358FIL1
C Filter 358 Select
R/W
bit 3
~
bit 4
C443FIL0
~
C443FIL1
C Filter 443 Select
R/W
bit 5
HDP
HD pin Polarity
R/W
bit 6
bit 7
VD_FP
DVAL_FP
VD_F Pin Polarity
DVAL_FLD pin Polarity
R/W
R/W
MS1230-E-01
0
Definition
Transition speed setting,
between peak AGC and sync AGC
0: QUICK
1: SLOW
C-filter bandwidth setting,
for 3.58 MHz subcarrier system signal
C358FIL[1:0]
00: Narrow
01: Middle
10: Wide
11: Reserved
C-filter bandwidth setting,
for 4.43 MHz subcarrier system signal
C443FIL[1:0]
00: Narrow
01: Middle
10: Wide
11: Reserved
HD signal polarity setting
0: ACTIVE LOW
1: ACTIV HIGH
VD_FLD pin output signal polarity setting
If VD signal is output
0: ACTIVE LOW
1: ACTVIE HIGH
If FIELD signal is output
0: LOW=ODD / HIGH=EVEN
1: LOW=EVEN / HIGH=ODD
DVAL_FLD pin output signal polarity setting
If DVALID signal is output
0: ACTIVE LOW
1: ACTVIE HIGH
If FIELD signal is output
0: LOW=ODD / HIGH=EVEN
1: LOW=EVEN / HIGH=ODD
2011/7
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[AK8858]
[9.1.13] Control 1 Register (R/W) [Sub Address 0x0C]
Sub Address: 0x0C
bit 7
bit 6
CLKMODE1
CLKMODE0
Default Value
0
0
bit 5
INTPOL1
bit 4
INTPOL0
bit 3
UVFILSEL1
bit 2
UVFILSEL0
Default Value: 0x00
bit 1
bit 0
YCSEP1 YCSEP0
0
0
0
0
0
Control 1 Register
BIT
Register Name
R/W
bit 0
~
bit 1
YCSEP0
~
YCSEP1
YC Separation
Control
R/W
bit 2
~
bit 3
UVFILSEL0
~
UVFILSEL1
UV Filter Select
R/W
bit 4
~
bit 5
INTPOL0
~
INTPOL1
Interpolator Mode
Select
R/W
bit 6
~
bit 7
CLKMODE0
~
CLKMODE1
Clock Mode Select
R/W
MS1230-E-01
0
Definition
Y/C separation setting YCSEP[1:0]
00: Adaptive Y/C separation
01: 1-dimensional Y/C separation
10: 2-dimensional Y/C separation
11: Reserved
UV filter setting
(CVBS or S-video input)
UVFILSEL0
0: Wide 1
1 Narrow 1
(YPbPr input)
00: Middle 1
01: Middle 2
10: Wide 2
11: Narrow 2
Pixel interpolator setting
INTPOL[1:0]
00: Auto
01: ON
10: OFF
11: Reserved
Clock mode setting
CLKMODE[1:0]
00: Automatic transition mode
01: Line-locked clock mode
10: Frame-locked clock mode
11: Fixed-clock mode
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[AK8858]
[9.1.14] Control 2 Register (R/W) [Sub Address 0x0D]
Sub Address: 0x0D
bit 7
bit 6
CONTSEL
STUPATOFF
Default Value
0
0
bit 5
ERRHND1
bit 4
ERRHND0
bit 3
NSIGMD1
bit 2
NSIGMD0
0
0
0
0
Control 2 Register
BIT Register Name
R/W
bit 0
~
bit 1
DPAL0
~
DPAL1
Deluxe PAL
R/W
bit 2
~
bit 3
NSIGMD0
~
NSIGMD1
NSIG mode
select
R/W
bit 4
~
bit 5
ERRHND0
~
ERRHDN1
656 Error
Handling
R/W
bit 6
STUPATOFF
Setup
Auto Control Off
R/W
bit 7
CONTSEL
Contrast Select
R/W
Default Value: 0x00
bit 1
bit 0
DPAL1
DPAL0
0
0
Definition
Setting for color averaging (PAL phase correction block)
Also applicable to NTSC.
DPAL[1:0]
00: Adaptive phase correction ON
01: Phase correction ON
10: Phase correction OFF
11: Reserved
Setting for output on no-signal detection
NSIGMD[1:0]
00: Black-level output (Y=0x10/CbCr=0x80)
01: Blue-level (Blueback) output (Y=0x29/Cb=0xF0/Cr=0x6E)
10: Input status (sandstorm) output
11: Reserved
Setting for processing if ITU-R Bt.656
output is not possible
ERRHND[1:0]
00: Line drop or repeat
01: Pixel drop or repeat, in final line of field
10: Line drop or repeat, in final line of frame
11: Reserved
Setup auto switching setting (ON/OFF)
in auto signal detection mode
0: Auto setup switching ON
1: Auto setup switching OFF
Contrast selector
0: 50%
1: 0%
MS1230-E-01
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[AK8858]
[9.1.15] PGA1 Control Register (R/W) [Sub Address 0x0E]
PGA1 gain control register setting.
Sub Address: 0x0E
bit 7
bit 6
APGA1_1
APGA1_0
Default Value
0
1
BIT
Register Name
bit 0
~
bit 5
DPGA1_0
~
DPGA1_5
bit 6
~
bit 7
APGA1_0
~
APGA1_1
bit 5
DPGA1_5
bit 4
DPGA1_4
bit 3
DPGA1_3
bit 2
DPGA1_2
Default Value: 0x54
bit 1
bit 0
DPGA1_1
DPGA1_0
0
1
0
1
0
Digital PGA1 Control
Analog PGA1 Control
0
R/W
Definition
R/W
Digital PGA1 gain setting.
PGA gain is set by following equation.
R/W
Analog PGA1 gain setting.
[00]: −3dB
[01]: 0dB
[10]: +3dB
[11]: +6dB
Digital PGA gain equation:
⎛ (5 × PGA) + 497 ⎞
⎟
512
⎝
⎠
Gain(dB) = 20 LOG⎜
*PGA: PGA1 or PGA2 register value (Decimal)
Default gain setting is 0x54(HEX)=1.3dB. (Analog:0dB + Digital:1.3dB)
[9.1.16]PGA2 Control Register (R/W) [Sub Address 0x0F]
PGA2 gain control register setting.
Sub Address: 0x0F
bit 7
bit 6
APGA2_1
APGA2_0
Default Value
0
1
BIT
Register Name
bit 0
~
bit 5
DPGA2_0
~
DPGA2_5
bit 6
~
bit 7
APGA2_0
~
APGA2_1
bit 5
DPGA2_5
bit 4
DPGA2_4
bit 3
DPGA2_3
bit 2
DPGA2_2
Default Value: 0x54
bit 1
bit 0
DPGA2_1
DPGA2_0
0
1
0
1
0
Digital PGA1 Control
Analog PGA1 Control
0
R/W
Definition
R/W
Digital PGA2 gain setting.
PGA gain is set by above equation.
R/W
Analog PGA2 gain setting.
[00]: −3dB
[01]: 0dB
[10]: +3dB
[11]: +6dB
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[AK8858]
[9.1.17] Pedestal Level Control Register (R/W) [Sub Address 0x10]
Pedestal level control register setting.
Sub Address: 0x10
bit 7
bit 6
DPCC1
DPCC0
Default Value
0
0
bit 5
DPCT1
bit 4
DPCT0
bit 3
BKLVL3
bit 2
BKLVL2
Default Value: 0x00
bit 1
bit 0
BKLVL1
BKLVL0
0
0
0
0
0
Pedestal Level Control Register
BIT
Register Name
R/W
bit 0
~
bit 3
BKLVL0
~
BKLVL3
Black Level
R/W
bit 4
~
bit 5
DPCT0
~
DPCT1
Digital Pedestal
Clamp Control
R/W
bit 6
~
bit 7
DPCC0
~
DPCC1
Digital Pedestal
Clamp Coring
R/W
0
Definition
Setting for change from current pedestal level
by adding to or subtracting from black level
BKLVL[3 : 0]
0001: Add 1
0010: Add 2
0011: Add 3
0100: Add 4
0101: Add 5
0110: Add 6
0111: Add 7
0000: Default
1000: Subtract 8
1001: Subtract 7
1010: Subtract 6
1011: Subtract 5
1100: Subtract 4
1101: Subtract 3
1110: Subtract 2
1111: Subtract 1
Time-constant setting for digital pedestal clamp
DPCT[1:0]
00: Fast
01: Middle
10: Slow
11: Disable
Non-sensing bandwidth setting for
digital pedestal clamp
DPCC[1: 0]
00: +/-1bit
01: +/-2bit
10: +/-3bit
11: No non-sensing band
MS1230-E-01
2011/7
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[AK8858]
[9.1.18] Color Killer Control Register (R/W) [Sub Address 0x11]
Color killer register.
Sub Address: 0x11
bit 7
bit 6
COLKIL
CKILSEL
Default Value
0
0
bit 5
CKSCM1
bit 4
CKSCM0
bit 3
CKLVL3
bit 2
CKLVL2
Default Value: 0x08
bit 1
bit 0
CKLVL1
CKLVL0
0
0
1
0
0
Color Killer Control Register
BIT
Register Name
R/W
Definition
0
bit 0
~
bit 3
CKLVL0
~
CKLVL3
Color Killer
Level
R/W
Burst level setting for color killer activation
Default value, approx. −23 dB.
bit 4
~
bit 5
CKSCM0
~
CKSCM1
Color Killer
Lever for SECAM
R/W
Burst level setting for color killer activation in
SECAM mode Adds 2 bits to CKLVL[3:0]
bit 6
CKILSEL
Color Killer
Select
R/W
bit 7
COLKIL
Color Killer
Set
R/W
MS1230-E-01
Color killer operational mode setting
0: Activation when burst color level is below
than CKLVL[3:0]-bit threshold setting.
1: Activation when burst color level is below
than CKLVL[3:0]-bit threshold setting
or color decode PLL lock fails.
Color killer ON/OFF setting
0: Enable
1: Disable
2011/7
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[AK8858]
[9.1.19] Contrast Control Register (R/W) [Sub Address 0x12]
Contrast adjustment setting register.
Sub Address: 0x12
bit 7
bit 6
CONT7
CONT6
Default Value
1
0
bit 5
CONT5
bit 4
CONT4
bit 3
CONT3
bit 2
CONT2
Default Value: 0x80
bit 1
bit 0
CONT1
CONT0
0
0
0
0
0
Contrast Control Register
BIT
Register Name
bit 0
~
bit 7
CONT0
~
CONT7
Contrast Control
0
R/W
Definition
R/W
Register for contrast adjustment in steps of 1/128
in range 1~255/128 from default value of 0x80
[9.1.20]Brightness Control Register (R/W) [Sub Address 0x13]
Brightness adjustment setting register
Sub Address: 0x13
bit 7
bit 6
BR7
BR6
Default Value
0
0
bit 5
BR5
bit 4
BR4
bit 3
BR3
bit 2
BR2
bit 1
BR1
0
0
0
0
0
Brightness Control Register
BIT
Register Name
bit 0
~
bit 7
BR0
~
BR7
Brightness
Control
Default Value: 0x00
bit 0
BR0
0
R/W
Definition
R/W
Register for brightness adjustment in steps of
1 by 8-bit code setting in 2’s complement
MS1230-E-01
2011/7
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[AK8858]
[9.1.21] Image Control Register (R/W) [Sub Address 0x14]
Sharpness control, Luminance bandwidth filter control, Sepia color output setting and VBI interval setting
register.
Sub Address: 0x14
bit 7
bit 6
VBIIMGCTL
SEPIA
Default Value
0
0
bit 5
LUMFIL1
bit 4
LUMFIL0
bit 3
SCCORE1
bit 2
SHCORE0
Default Value: 0x00
bit 1
bit 0
SHARP1
SHARP0
0
0
0
0
0
Image Control Register
BIT
Register Name
R/W
bit 0
~
bit 1
SHARP0
~
SHARP1
Sharpness Control
R/W
bit 2
~
bit 3
SHCORE0
~
SHCORE1
Sharpness Coring
R/W
bit 4
~
bit 5
LUMFIL0
~
LUMFIL1
Luminance Filter
R/W
bit 6
SEPIA
Sepia Output
R/W
bit 7
VBIIMGCTL
VBI Image Control
R/W
0
Definition
Sharpness control (filter effect) setting
SHARP[1: 0]
00: No filtering
01: Min effect
10: Middle effect
11: Max effect
Setting for level of coring after passage
through sharpness filter
SHCORE[1:0]
00: No coring
01: ±1LSB
10: ±2LSB
11: ±3LSB
Setting for luminance band limit filter
LUMFIL[1:0]
00: No filtering
01: Narrow
10: Mid
11: WIDE
Setting (ON/OFF) for sepia coloring of decode results
0: Normal output
1: Sepia output
Setting (ON/OFF) for image adjustment
during brightness and contrast adjustment VBI
0: Image adjustment inactive during VBI
1: Image adjustment active during VBI
MS1230-E-01
2011/7
- 83 -
[AK8858]
[9.1.22] Saturation / U Tone Control Register (R/W) [Sub Address 0x15]
Saturation adjustment registers setting.
If YPbPr signal input, U tone level adjustment register setting.
Sub Address: 0x15
bit 7
bit 6
SAT7
SAT6
UTONE7
UTONE6
Default Value
1
0
bit 5
SAT5
UTONE5
bit 4
SAT4
UTONE4
bit 3
SAT3
UTONE3
bit 2
SAT2
UTONE2
Default Value: 0x80
bit 1
bit 0
SAT1
SAT0
UTONE1
UTONE0
0
0
0
0
0
Saturation / U TONE Control Register
BIT Register Name
R/W
Definition
0
bit 0
~
bit 7
SAT0
~
SAT7
Saturation Control
R/W
Register for saturation level adjustment in steps of 1/128
in range 1~255/128 from default value of 0x80
(CVBS or S-video input)
bit 0
~
bit 7
UTONE0
~
UTONE7
U Tone Control
R/W
Register for U tone level adjustment in steps of 1/128
in range 1~255/128 from default value of 0x80
(YPbPr input)
If component mode, UTONE default value should be changed to following parameter.
UTONE [7:0] =0x70
[9.1.23] V Tone Control Register (R/W) [Sub Address 0x16]
YPbPr signal input, V tone level adjustment register setting.
Sub Address: 0x16
bit 7
bit 6
VTONE7
VTONE6
Default Value
1
0
bit 5
VTONE5
bit 4
VTONE4
bit 3
VTONE3
bit 2
VTONE2
Default Value: 0x80
bit 1
bit 0
VTONE1
VTONE0
0
0
0
0
0
V TONE Control Register
BIT
Register Name
bit 0
~
bit 7
VTONE0
~
VTONE7
V Tone Control
0
R/W
Definition
R/W
Register for V tone level adjustment in steps of 1/128
in range 1~255/128 from default value of 0x80
(YPbPr or RGB input)
If component mode, VTONE default value should be changed to following parameter.
VTONE [7:0] =0x9D
MS1230-E-01
2011/7
- 84 -
[AK8858]
[9.1.24] HUE Control Register (R/W) [Sub Address 0x17]
HUE adjustment register setting.
Sub Address: 0x17
bit 7
bit 6
HUE7
HUE6
Default Value
0
0
bit 5
HUE5
bit 4
HUE4
bit 3
HUE3
bit 2
HUE2
bit 1
HUE1
0
0
0
0
0
HUE Control Register
BIT
Register Name
bit 0
~
bit 7
HUE0
~
HUE7
HUE Control
Default Value: 0x00
bit 0
HUE0
0
R/W
Definition
R/W
Register for hue adjustment in steps of 1/256
in range ±45° in 2’s complement
[9.1.25] High Slice Data Set Register (R/W) [Sub Address 0x18]
Sub Address: 0x18
bit 7
bit 6
H7
H6
Default Value
1
1
bit 5
H5
bit 4
H4
bit 3
H3
bit 2
H2
bit 1
H1
1
0
1
0
1
High Slice Data Set Register
Register
BIT
Name
bit 0 H0
High Data
~
~
0~7 Set
bit 7 H7
Default Value: 0xEB
bit 0
H0
1
R/W
Definition
R/W
Register for setting sliced data from VBI slicer to High value.
Important: Corresponds to 601 special code if set to 0x00 or 0xFF
[9.1.26] Low Slice Data Set Register (R/W) [Sub Address 0x19]
Sub Address: 0x19
bit 7
bit 6
L7
L6
Default Value
0
0
Low Slice Data Set Register
Register
BIT
Name
bit 0 L0
Low Data
~
~
0~7 Set
bit 7 L7
bit 5
L5
bit 4
L4
bit 3
L3
bit 2
L2
bit 1
L1
0
1
0
0
0
Default Value: 0x10
bit 0
L0
0
R/W
Definition
R/W
Register for setting sliced data from VBI slicer to Low value.
Important: Corresponds to 601 special code if set to 0x00 or 0xFF
MS1230-E-01
2011/7
- 85 -
[AK8858]
[9.1.27] Request VBI Information Register (R/W) [Sub Address 0x1A]
Request decode data during VBI interval setting register.
Sub Address: 0x1A
bit 7
bit 6
Reserved
Reserved
Default Value
0
0
bit 5
Reserved
bit 4
Reserved
bit 3
WSSRQ
bit 2
VBIDRQ
Default Value: 0x00
bit 1
bit 0
EXTRQ
CCRQ
0
0
0
0
0
Request VBI Information Register
BIT Register Name
R/W
bit 0
CCRQ
Closed Caption
Decode Request
R/W
bit 1
EXTRQ
Extended Data
Decode Request
R/W
bit 2
VBIDRQ
VBID Decode Request
R/W
bit 3
WSSRQ
WSS Decode Request
R/W
bit 4
~
bit 7
Reserved
Reserved
R/W
0
Definition
Setting (ON/OFF) for closed caption decode request
0: No request (OFF)
1: Request (ON)
Setting (ON/OFF) for Extended Data decode request
0: No request (OFF)
1: Request (ON)
Setting (ON/OFF) for VBID decode request
0: No request (OFF)
1: Request (ON)
Setting (ON/OFF) for WSS decode request
0: No request (OFF)
1: Request (ON)
Reserved
MS1230-E-01
2011/7
- 86 -
[AK8858]
[9.1.28] Sub Address 0x1B~0x21 “Reserved Register (R/W)”
Reserved register.
[9.1.29] Status 1 Register (R) [Sub Address 0x22]
The AK8858 internal status register.
bit 7
OVCOL
bit 6
PKWHITE
bit 5
SCLKMOD1
bit 4
SCLKMOD0
Status 1 Register
BIT Register Name
R/W
bit 0
NOSIG
No Signal
R
bit 1
VLOCK
VLOCK
R
bit 2
FRMSTD
Frame Standard
R
bit 3
COLKILON
Color Killer ON
R
bit 4
~
bit 5
SCLKMOD0
~
SCLKMOD1
Clock Mode
R
bit 6
PKWHITE
Peak White Detection
R
bit 7
OVCOL
Over Color Level
R
bit 3
COLKLON
bit 2
FRMSTD
Sub Address: 0x22
bit 1
bit 0
VLOCK
NOSIG
Definition
Input signal indicator
0: Input signal present
1: Input signal absent
Input signal VLOCK synchronization status indicator
0: Input signal synchronized
1: Input signal non-synchronized
Input signal interlace status indicator
0: Input signal 525/625 interlaced
1: Input signal not 525/625 interlaced
Color killer status indicator
0: Color killer not operation
1: Color killer operation
In component decode mode, this bit is always 0.
Clock mode indicator
SCLKMOD[1:0]
00: Fixed-clock mode
01: Line-locked clock mode
10: Frame-locked clock mode
11: Reserved
Luminance decode result flow status indicator,
after passage through AGC block
0: Normal
1: Overflow
Color decode result flow status indicator,
after passage through ACC block
0: Normal
1: Overflow (excessive color signal input)
MS1230-E-01
2011/7
- 87 -
[AK8858]
[9.1.30] Status 2 Register (R) [Sub Address 0x23]
The AK8858 internal status register.
bit 7
Reserved
bit 6
Reserved
bit 5
AGSTS
bit 4
REALFLD
Status 2 Register
BIT
Register Name
bit 3
WSSDET
R/W
bit 0
CCDET
Closed Caption Detect
R
bit 1
EXTDET
Extended Data Detect
R
bit 2
VBIDDET
VBID Data Detect
R
bit 3
WSSDET
WSS Data Detect
R
bit 4
REALFLD
Real Filed
R
bit 5
AGCSTS
AGC Status bit
R
bit 6
~
bit 7
Reserved
Reserved
R
MS1230-E-01
bit 2
VBIDDET
Sub Address: 0x23
bit 1
bit 0
EXTDET
CCDET
Definition
Indicator for presence of decoded data
in Closed Caption 1/2 Register
0: No closed caption data present
1: Closed caption Data present
Indicator for presence of decoded data
in Extended Data 1/2 Register
0: No extended data present
1: Extended data present
Indicator for presence of decoded data
in VBID 1/2 Register
0: No VBID data present
1: VBID data present
Indicator for presence of decoded data
in WSS 1/2 Register
0: No WSS data present
1: WSS data present
Input signal field status (even/odd) indicator
0: EVEN field
1: ODD field
AGC status indicator
0: Sync AGC active
1: Peak AGC active
Reserved
2011/7
- 88 -
[AK8858]
[9.1.31] Macrovision Status Register (R) [Sub Address 0x24]
Macrovision signal status register.
bit 7
Reserved
bit 6
Reserved
bit 5
Reserved
Macrovision Status Register
Register
BIT
Name
R/W
bit 0
AGCDET
AGC Process
Detect
R
bit 1
CSDET
Color Stripe
Detect
R
bit 2
CSTYPE
Color Stripe
Type
R
bit 3
~
bit 7
Reserved
Reserved
R
bit 4
Reserved
bit 3
Reserved
bit 2
CSTYPE
Sub Address: 0x24
bit 1
bit 0
CSDET
AGCDET
Definition
Indicator for presence of Macrovision AGC in input signal
0: No Macrovision AGC present
1: Macrovision AGC present
Indicator for presence of Macrovision Color Stripe in input signal
0: No Color Stripe present
1: Color Stripe present
Indicator for type of Color Stripe included in input signal
0: Color Stripe Type 2
1: Color Stripe Type 3
Reserved
MS1230-E-01
2011/7
- 89 -
[AK8858]
[9.1.32] Input Video Status Register (R) [Sub Address 0x25]
Input video status register for auto detection mode.
bit 7
FIXED
bit 6
UNDEF
bit 5
ST_BW
Input Video Status Register
BIT
Register Name
bit 4
ST_VLF
bit 3
ST_VCEN1
R/W
bit 2
ST_VCEN0
bit 1
ST_VSCF1
Sub Address: 0x25
bit 0
ST_VCSF0
Definition
Input video signal subcarrier frequency indicator
For CVBS and S (Y/C) signal decode results
shows as follows:
ST_VSCF[1:0]
00: 3.57954545 MHz
bit 0 ST_VSCF0
Status of
01: 3.57561149 MHz
R
~
~
Video Sub-Carrier
10: 3.58205625 MHz
bit 1 ST_VSCF1
Frequency
11: 4.43361475 MHz (SECAM detected result)
For D1/D2 signal decode results shows as follows
(this result also apply if auto detection mode is OFF)
00: D1
01: D2
10/11: Reserved
Input signal color encode format indicator
ST_VCEN[1:0]
bit 2 ST_VCEN0
Status of Video
00: NTSC
~
~
R
Color Encode
01: PAL
bit 3 ST_VCEN1
10: SECAM
[11]: Component setting*
Input signal line number indicator
Status of Video
bit 4 ST_VLF
R
0: 525 line
Line Frequency
1: 625 line
Input signal monochrome indicator
bit 5 ST_BW
Status of B/W
R
0: Not monochrome
1: Monochrome
Input signal detection indicator
bit 6 UNDEF
Un-Define
R
0: Input signal detected
1: Input signal not detected
Input signal detection process status
Input Video
bit 7 FIXED
R
0: Detection process in progress
Standard Fixed
1: Detection process completed
* ST_VCEN[1:0] is [11] when Sub-Address 0x00[6:5] is set to [10] (Component video input).
MS1230-E-01
2011/7
- 90 -
[AK8858]
[9.1.33] Closed Caption1 Register (R) [Sub Address 0x26]
Closed Caption data storage register
bit 7
CC7
bit 6
CC6
bit 5
CC5
bit 4
CC4
bit 3
CC3
bit 2
CC2
Sub Address: 0x26
bit 0
CC0
bit 1
CC1
[9.1.34] Closed Caption2 Register (R) [Sub Address 0x27]
Closed Caption data storage register
bit 7
CC15
bit 6
CC14
bit 5
CC13
bit 4
CC12
bit 2
CC10
Sub Address: 0x27
bit 1
bit 0
CC9
CC8
bit 2
WSS1-2
Sub Address: 0x28
bit 1
bit 0
WSS1-1
WSS1-0
bit 3
CC11
[9.1.35] WSS 1 Register (R) [Sub Address 0x28]
WSS data storage register
bit 7
WSS2-7
bit 6
WSS2-6
bit 5
WSS2-5
bit 4
WSS2-4
bit 3
WSS1-3
[9.1.36] WSS 2 Register (R) [Sub Address 0x29]
WSS data storage register
bit 7
Reserved
bit 6
Reserved
bit 5
WSS4-13
bit 4
WSS4-12
bit 3
WSS4-11
bit 2
WSS3-10
Sub Address: 0x29
bit 1
bit 0
WSS3-9 WSS3-8
[9.1.37.] Extended Data 1 Register (R) [Sub Address 0x2A]
Closed Caption Extended data storage register
bit 7
EXT7
bit 6
EXT6
bit 5
EXT5
bit 4
EXT4
bit 3
EXT3
bit 2
EXT2
Sub Address: 0x2A
bit 1
bit 0
EXT1
EXT0
[9.1.38.] Extended Data 2 Register (R) [Sub Address 0x2B]
Closed Caption Extended data storage register
bit 7
EXT15
bit 6
EXT14
bit 5
EXT13
bit 4
EXT12
bit 3
EXT11
bit 2
EXT10
Sub Address: 0x2B
bit 1
bit 0
EXT9
EXT8
bit 2
VBID4
Sub Address: 0x2C
bit 1
bit 0
VBID5
VBID6
[9.1.39] VBID 1 Register (R) [Sub Address 0x2C]
VBID data storage register
bit 7
Reserved
bit 6
Reserved
bit 5
VBID1
bit 4
VBID2
bit 3
VBID3
[9.1.40] VBID 2 Register (R) [Sub Address 0x2D]
VBID data storage register
bit 7
VBID7
bit 6
VBID8
bit 5
VBID9
bit 4
VBID10
bit 3
VBID11
MS1230-E-01
bit 2
VBID12
bit 1
VBID13
Sub Address: 0x2D
bit 0
VBID14
2011/7
- 91 -
[AK8858]
[9.1.41] Device and Revision ID Register (R) [Sub Address 0x2E]
Device ID and Revision indicator
Device ID: [0x3A]
Revision ID: Initially 0x00; revision number changes only when control software should be modified.
bit 7
bit 6
REV1
REV0
Default Value
0
0
bit 5
DEVID5
bit 4
DEVID4
bit 3
DEVID3
bit 2
DEVID2
bit 1
DEVID1
1
1
1
0
1
Device and Revision ID Register
BIT
Register Name
bit 0
DEVID0
~
~
Device ID
bit 5
DEVID1
bit 6
REV0
Revision ID
~
~
bit 7
REV1
Sub Address: 0x2E
bit 0
DEVID0
R/W
Definition
R
Device ID indicator (0x3A)
R
Revision ID indicator (initially 0x00)
MS1230-E-01
0
2011/7
- 92 -
[AK8858]
[10] System connection example
PVDD2
Pull up
Micro Processor
2
(I C Controller)
SELA
SDA SCL RSTN PDN OE
NSIG
DATA[23:0]
Video IN
0.033uF
47Ω
DTCLK
AIN1~10
DVAL_FLD
30Ω
VD_FLD
HD
IREF
VRP
VCOM
VRN
TEST0
TEST1
ATIO
0.1uF 0.1uF 0.1uF
6.8kΩ
AK8858
PVDD1
PVDD1
0.1uF
XTI
22pF
10uF
DVSS
24.576MHz
PVDD 2
XTO
22pF
PVDD2
0.1uF
10uF
DVSS
DVDD
AVDD
DVDD
AVDD
0.1uF
0.1uF
10uF
10uF
DVSS
AVSS
Analog GND
MS1230-E-01
Digital GND
2011/7
- 93 -
[AK8858]
[11] Package
80-pin LQFP
14.00 ± 0.20
12.00 ± 0.20
41
60
40
12.00 ± 0.20
80
1
0.50
20
0.20±0.10
0.08
M
0°~10°
1.85 MAX
1.25TYP
21
1.40 ± 0.20
14.00 ± 0.20
61
S
-0.10
0.10
+0.15
0.50 ±0.20
0.10
-0.05
0.125
+0.10
S
MS1230-E-01
2011/7
- 94 -
[AK8858]
[12] Marking
AKM
AK8858VQ
XXXXXXX
AKM: AKM Logo
AK8858VQ: Marketing Code
XXXXXXX (7 digits): Date Code
MS1230-E-01
2011/7
- 95 -
[AK8858]
[13] Revision history
<MS1230-E-00 Æ MS1230-E-01>
[Writeing error, P.27]
−Before
Sub Address: 0x03
bit 7
bit 6
Reserved
Reserved
Default Value
0
0
−After
Sub Address: 0x03
bit 7
bit 6
VERTS
CSCAN
Default Value
0
0
bit 5
Reserved
bit 4
Reserved
bit 3
Reserved
bit 2
CSCL
Default Value: 0x00
bit 1
bit 0
CSSL
Reserved
0
0
0
0
0
0
bit 5
Reserved
bit 4
CMPSEL
bit 3
Reserved
bit 2
CSCL
Default Value: 0x00
bit 1
bit 0
CSSL
Reserved
0
0
0
0
0
0
[Writeing error, P.32]
−Before
DATA[23:0], HD, VD_FLD, DVAL_FLD and NSIG pins can be Low output by register.
Sub Address: 0x17 [4:0]
−After
DATA[23:0], HD, VD_FLD, DVAL_FLD and NSIG pins can be Low output by register.
Sub Address: 0x07 [4:0]
[Writeing error, P.41]
−Before
Settings for output signals for no input signal
Sub Address: 0x07 [3:2]
−After
Settings for output signals for no input signal
Sub Address: 0x0D [3:2]
MS1230-E-01
2011/7
- 96 -
[AK8858]
[Writeing error, P.54]
−Before
Name
Definition
YOUT = YIN + BR
BR0
~
BR7
YOUT: Brightness obtained by the calculation
YIN: Brightness before the calculation
BR: Brightness gain factor (register setting value)
The gain factor can be set in the range {-128 ~ 126} in 1 step.
The setting is in 2’s complement.
−After
Name
Definition
YOUT = YIN + BR
BR0
~
BR7
YOUT: Brightness obtained by the calculation
YIN: Brightness before the calculation
BR: Brightness gain factor (register setting value)
The gain factor can be set in the range {-128 ~ 127} in 1 step.
The setting is in 2’s complement.
[Writeing error, P.62, 90]
−Before
Input signal color encode format indicator
[ST_VCEN1 : ST_VCEN0]
ST_VCEN0
[00]: NTSC
~
[01]: PAL
ST_VCEN1
[10]: SECAM
[11]: Reserved
−After
Input signal color encode format indicator
[ST_VCEN1 : ST_VCEN0]
ST_VCEN0
[00]: NTSC
~
[01]: PAL
ST_VCEN1
[10]: SECAM
[11]: Component setting*
* ST_VCEN[1:0] is [11] when Sub-Address 0x00[6:5] is set to [10] (Component video input).
MS1230-E-01
2011/7
- 97 -
[AK8858]
[Spec. revise, P.61]
−Before
This function is cancellor for macrovision color stripe. Set CSCAN bit to [1].
Color stripe cancel
Sub Address: 0x03 [6]
Name
Definition
CSCAN
[0]: Color stripe on screen (Cancel function is not operated)
[1]: No Color stripe on screen (Cancel function is operated)
−After
This function is cancellor for macrovision color stripe.
Set CSCAN bit to [1] only when Sub=Address 0x04[7:0] is [XXX00000] setting.
Set CSCAN bit to [0] when Sub=Address 0x04[7:0] is not [XXX00000] setting.
(X: Don’t care)
Sub Address: 0x03 [6]
Color stripe cancel
Name
Definition
CSCAN
Set to [1] only when Sub=Address 0x04[7:0] is [XXX00000] setting.
Set to [0] when Sub=Address 0x04[7:0] is not [XXX00000] setting.
[Spec. revise, P.68]
−Before
bit 6
CSCAN
Color stripe
cancel
R/W
Color stripe cancel operation*
0: not operated
1: operated
−After
bit 6
CSCAN
Color stripe
cancel
R/W
Color stripe cancel operation
Set to [1] only when Sub=Address 0x04[7:0] is [XXX00000]
Set to [0] when Sub=Address 0x04[7:0] is not [XXX00000]
MS1230-E-01
2011/7
- 98 -
[AK8858]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of
Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the
products.
• Descriptions of external circuits, application circuits, software and other related information contained in
this document are provided only to illustrate the operation and application examples of the
semiconductor products. You are fully responsible for the incorporation of these external circuits,
application circuits, software and other related information in the design of your equipments. Asahi
Kasei Microdevices Corporation (AKM) assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of
any patent, intellectual property, or other rights in the application or use of such information contained
herein.
• Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety,
life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for
such use, except for the use approved with the express written consent by Representative Director of
AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
• It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for
and hold AKM harmless from any and all claims arising from the use of said product in the absence of
such notification.
MS1230-E-01
2011/7
- 99 -
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