AK8137A

AK8137A
Low Power
Multiclock Generator with XO
AK8137A
Features
Description
25MHz Crystal Input
One 25MHz-Reference Output
Selectable Clock out Frequencies:
- 100, 133, 166, 200MHz
- 96MHz
- 100MHz
- 25MHｚ
Low Jitter Performance
- Cycle to Cycle Jitter:
85 psec at CPU_C
125 psec at SATA_C
250 psec at UBS_C
Low Current Consumption:
37mA (Typ.) at 3.3V
Supply Voltage:
3.0 – 3.6V
Operating Temperature Range:
-20 to +85℃
Package:
20-pin SSOP (Lead free, Halogen free)
The AK8137A is a member of AKM’s low power
multi clock generator family designed for a feature
rich DTV or STB, requiring a range of system
clocks with high performance. The AK8137A
generates different frequency clocks from a 25
MHz crystal oscillator and provides them to up to
four outputs configured by pin-setting. PLL in
AK8137A are derived from AKM’s
long-term-experienced clock device technology,
and enable clock output to perform low jitter and to
operate with very low current consumption. The
AK8137A is available in a 20-pin SSOP package.
Applications
Set-Top-Boxes
Block Diagram
VDD
XI
Crystal
Oscillator
PLL1
SATA_Cp
SATA_Cn
XO
PLL2
USB_Cp
USB_Cn
PLL3
CPU_Cp
CPU_Cn
PDCLKN
REFOUT
FSA
VREF
FSB
GND
AK8137A Multi Clock Generator
MS1109_E_02
February-10
-1-
AK8137A
Pin Descriptions
Package: 20-Pin SSOP(Top View)
XI
1
20
GND3
2
19
VDD3
USB_Cp
3
18
REFOUT
USB_Cn
4
17
GND4
VDD2
5
16
PDCLKN
GND2
6
15
FSA
CPU_Cp
7
14
SATA_Cn
CPU_Cn
8
13
SATA_Cp
FSB
9
12
VDD1
10
11
GND1
VREF
Pin
Name
Pin
No.
XO
Pin
Type
Description
1
XI
AI
Crystal connection, Connect to 25.000MHz crystal
2
GND3
PWR
3
USB_Cp
DO
4
USB_Cn
DO
5
VDD2
PWR
Power Supply 2
6
GND2
PWR
Ground 2
7
CPU_Cp
DO
8
CPU_Cn
DO
9
FSB
DI
10
VREF
AO
11
GND1
PWR
Ground 1
12
VDD１
PWR
Power Supply 1
13
SATA_Cp
DO
14
SATA_Cn
DO
15
FSA
DI
Ground 3
96MHz Clock output for USB
Clock output for CPU
See Table 1 for its selectable frequency
CPU Clock select
360ｋΩ internal pull-up.
VREF Pin. Connect 1uF capacitor.
100MHz Clock output for SATA
CPU Clock select
360ｋΩ internal pull-up.
Clock Output Control
16
PDCLKN
DI
H: Power Down Disable, L: Power Down Enable
500ｋΩ internal pull-up.
17
GND4
PWR
18
REFOUT
DO
19
VDD3
PWR
20
XO
AO
Ground4
Reference Clock Output 25.000MHz Crystal
Power Supply 3
Crystal connection, Connect to 25.000MHz crystal
Ordering Information
Part Number
Marking
Shipping
Packaging
Package
Temperature
Range
AK8137A
813７A
Tape and Reel
20-pin SSOP
-20 to 85 ℃
February-10
MS1109_E_02
-2-
AK8137A
Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted
Items
Symbol
Supply voltage
(1)
Ratings
Unit
V
VDD
-0.3 to 4.6
Input voltage
Vin
VSS-0.3 to VDD+0.3
V
Input current (any pins except supplies)
IIN
±10
mA
Tstg
-55 to 130
°C
Storage temperature
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating
conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
ESD Sensitive Device
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and
installation procedures can cause damage. AKM recommends that this device is handled with
appropriate precautions.
Recommended Operation Conditions
Parameter
Operating temperature
Supply voltage
(1)
Symbol
Conditions
Ta
VDD
Output Load Capacitance
CL
Output Load Capacitance
Cpl
Min
Typ
Max
Unit
85
°C
3.3
3.6
V
2
pF
25
pF
-20
Pin: VDD1,VDD2,VDD3
3.0
Pin: Diff CLK pins
See Figure.1
Pin: REFOUT
Note:
(1) Power to VDD1, VDD2 , VDD3 requires to be supplied from a single source.
power supply line should be installed close to each VDD pin.
MS1109_E_02
A decoupling capacitor for
February-10
-3-
AK8137A
DC Characteristics
All specifications at VDD: over 3.0 to 3.6V, Ta:
Parameter
-20 to +85℃, 25MHz Crystal, unless otherwise noted
Conditions
Symbol
High Level Input Voltage
VIH
Pin: FSA,FSB,PDCLKN
Low Level Input Voltage
VIL
Pin: FSA,FSB,PDCLKN
IL
Pin: FSA,FSB,PDCLKN
Input Current
High Level Output
Voltage
VOH
Low level Output
Voltage
VOL
Pin:
REFOUT
IOH=-4mA
Pin:
Vref
Current Consumption 1
IDD1
Current Consumption 2
IDD2
Current Consumption 3
IDDPD
Pin: VREF
MAX
0.7VDD
Unit
V
-20
0.3VDD
V
+10
μA
0.8VDD
V
REFOUT
TA=25℃,3.3V
VREF Voltage
TYP
IOL=+4mA
Pin: Diff CLK pins
Output impedance
MIN
0.2VDD
V
14
20
26
Ω
0.72
0.8
0.88
V
No load
Clock out selection by note (1)
VDD=3.3V, Ta=25℃
37
mA
48
mA
On load (2)
Clock out selection by note (1)
VDD=3.3V, Ta=25℃
PDCLKN=”L”
Ta=25℃
(1)CPU_Cp/n:200MHz, USB_Cp/n:96MHz,
50
250
μA
SATA_Cp/n: 100MHz
(2)Diff CLK pins: Figure1, REFOUT:Cpl=25pF
February-10
MS1109_E_02
-4-
AK8137A
AC Characteristics
All specifications at VDD: over 3.0 to 3.6V, Ta: over -20 to +85℃, 25MHz Crystal, unless otherwise noted
Parameter
Symbol
Crystal Clock Frequency
F_osc
Conditions
MIN
Pin: XI,XO
Cycle to Cycle Jitter 1
Jit_cycle-cycle1
Pin: CPU_Cp, CPU_Cn
Cycle to Cycle Jitter 2
Jit_cycle-cycle2
Pin: USB_Cp, USB_Cn
(1)(2)
Cycle to Cycle Jitter 3
Jit_cycle-cycle3
Pin: SATA_Cp,SATA_Cn
DtyCyc
Pin: Diff CLK Pins
Figure.3
Pin: REFOUT
(1)(2)
ps
-250
+250
ps
-125
+125
ps
(2)
(3)
45
50
55
%
40
50
60
%
8.0
V/ns
20
%
Slew_rise_fall
Diff CLK Pins
Slew rate matching
Slew_ver
Diff CLK Pins
(2)
Figure.2
Differential output swing
V_swing
Diff CLK Pins
(2)
Figure.3
300
Crossing point voltage
V_cross
Diff CLK Pins
(2)
Figure.2
300
Variation of
V_cross_delta
Diff CLK Pins
(2)
Diff CLK Pins
(2)
(2)
Figure.2
V_max
MHz
+85
Output Clock Slew Rate
Maximim output voltage
Unit
-85
(2)
Vcr
MAX
25.000
(1)(2)
Output Clock Duty
Cycle
TYP
Figure3
2.5
mV
550
mV
Figure.2
140
mV
Figure.2
1.15
V
Minimum output voltage
V_min
Diff CLK Pins
Output Clock Rise Time
T_rise
Pin: REFOUT
(3 )
2.5
5.0
ns
Output Clock Fall Time
T_fall
Pin: REFOUT
(3 )
2.5
5.0
ns
T_dis
Pin: CLK Pins
300
ms
Output disable Time
(4)
-0.3
V
Power-up Time1
(4)
T_put1
Pin: CLK Pins
150
ms
Power-up Time2
(5)
T_put2
Pin: CLK Pins
150
ms
(1) 1000 sampling or more
(2) Measured with load condition shown in Figure.1
(3) Measured with load capacitance of 25pF
(4) Refer to Figure.5 on Power down sequence
(5) Refer to Figure.4 on Power On Reset sequence
MS1109_E_02
February-10
-5-
AK8137A
3.3V
<5inch
T-Line
Z=50Ω
30Ω+/-5%
Rs
Measure point
PLL
2pF
Core
T-Line
Z=50Ω
Vref
2pF
Figure.1 Diff Clocks Load condition
V_max=1.15V
XXX_Cp
V_cross_max=550mV
V_cross
V_cross_min=300mV
XXX_Cn
V_min=-0.3V
XXX_Cp
V_cross_delta_max=140mV
V_cross_delta
XXX_Cn
XXX_Cn
Slew_rise SE(Avg)
+75mV
Slew_fall SE(Avg)
+75mV
V_cross(Avg)
-75mV
-75mV
XXX_Cp
Figure.2 Single ended (SE) measurement waveforms
February-10
MS1109_E_02
-6-
AK8137A
Period
-DtyCyc
0.0V
Diff clock
+DtyCyc
Slew_fall
Slew_rise
+150mV
0.0V
V_swing
0.0V
-150mV
Diff clock
Figure.3 Differential (DIFF) measurement waveforms
MS1109_E_02
February-10
-7-
AK8137A
Functional Description
Power On Reset
AK8137A has the POR(Power On Reset) circuit. In power up, the POR works and the register is set to the
initial value and all clock output becomes enable without glitch.
Note1) The assumption power start time to reach 90 % of VDD is within 20 ms.
Note2) The first register setting should be done after the 150 ms elapse after the power on.
VDD1/2/3
VDD*0.9
POR
(Internal signal)
XXX_Cp/REFOUT
XXX_Cn
Max:20ms
Min:150ms
Figure.4 Recommend Power On Reset Sequence
Power down Control
When the PDCLKN is “L”, CPU_Cp/Cn, USB_Cp/Cn and SATA_Cp/Cn clocks are forced to “L”. When it
is “H”, they are activated.
< 300ns
PDCLKN
XXX_Cp
XXX_Cn
PDCLKN
< 150ms
XXX_Cp
XXX_Cn
Figure.5 Power Down Sequence
February-10
MS1109_E_02
-8-
AK8137A
Output clock frequency selection
The AK8137A generates a range of low-jitter and hi-accuracy clock frequencies with three built-in PLLs
and provides four assigned outputs. A frequency selection at assigned output pin is configured by
pin-setting of FSA and FSB.
The selectable frequency is shown in Table 1..
Table 1: Clock output Frequency
FSB
L
L
H
H
FSA
L
H
L
H
CPU_C Frequency (MHz)
100
133
166
200
MS1109_E_02
February-10
-9-
AK8137A
Package Information
+0.10
-0.05
0.50±0.20
• 20SSOP Mechanical data
+0.30
-0.10
0.15
6.5
11
4.40±0.20
6.40±0.30
20
1
10
0.10
M
0゜～10゜
0.22±0.10
0.65
0.45MAX
S
1.15±0.10
0.10
0.10±0.10
S
• Marking
20
11
b
8137A
XXXXX
AKM
c
a:
b:
c:
d
#1 Pin Index
Part number
Date code (5 digits)
(1)
Product Family Logo
d
a
10
1
• RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
February-10
MS1109_E_02
- 10 -
AK8137A
IMPORTANT NOTICE
l These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi
Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
l AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the
application or use of any information contained herein.
l Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
l AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life
support, or other hazard related device or system Note2), and AKM assumes no responsibility for such use,
except for the use approved with the express written consent by Representative Director of AKM. As used
here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage
to person or property.
l It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions,
and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless
from any and all claims arising from the use of said product in the absence of such notification.
Asahi Kasei EMD Corporation has changed its company name to Asahi Kasei
Asahi Kasei EMD Corporation has changed its company name to Asahi Kasei
Microdevices Corporation (AKM) effective 1st April 2009.
Microdevices Corporation (AKM) effective 1st April 2009.
It
released before
before the
the date
date
It is
is noted
noted the
the documents
documents according
according to
to this
this product,
product, which
which was
was released
of
1st
April
2009,
shall
include
the
old
company
name
as
Asahi
Kasei
EMD
Corporation
of 1st April 2009, shall include the old company name as Asahi Kasei EMD Corporation
(AKEMD). These documents will be continuously valid by interpreting the old company
(AKEMD).
documents
be Microdevices
continuously valid
by interpreting
name to the These
new one
as Asahi will
Kasei
Corporation
(AKM). the old company
Further information of this company name change, contact AKM’s sales person or
AKM’s authorized distributor.
MS1109_E_02
February-10
- 11 -