AK8142

ASAHI KASEI EMD CORPORATION
Programmable
Clock Generator
AK8142
Features
Description
•
Supply Voltage:
3.0 – 3.6V(Main)
1.8 – 3.3V(Interface)
•
Low Current Consumption:
5.0mA (Typ.)
•
Crystal Unit Oscillation:
The AK8142 is a programmable clock generator IC
with an integrated Fractional N PLL. Highly accurate
clocks can be output from an external master clock or
a crystal unit.
Applications
16.0MHz – 32.0MHz
•
•
•
•
•
•
Input Frequency:
2.0MHz – 67.0MHz
Output Frequency:
4.0MHz – 200MHz
Low Jitter Performance:
15 ps (Typ.) Period 1σ
Operating Temperature Range:
-30 to +85℃
I2C Interface:
Package:
16-pin TSSOP
•
General purpose clock generator
Block Diagram
VDD
REFOUTEN[1:0]
XOUT
REFOUT
Crystal
OSC
XIN
(EXTIN)
CKOFF[0]
MDIV
ODIVPG[3:0]
MDIVC[3:0]
MDIVPG[2:0]
OUTC[2:0]
Phase
Charge
Comparator
Pump
FSEL
A0
A1
VCO
ODIV
CKOUT
CKOFF[1]
SDA
SCL
RESET
LPF
CKOUTEN[1:0]
NDIV
Control 1
Register0
FRAC[17:0]
⊿∑
INT[6:0]
Modulator
GND
AK8142 Register Programmable Clock Generator
MS0932-E-01
Jan-09
1
The brand name
of AKEMD’s IC’s
AK8142
PIN DESCRIPTION
1:XIN
16:XOUT
2:RESET
15:A0
3:FSET
14:A1
4:VDD1
13:GND3
5:GND1
12:VDD3
6:GND2
11:SDA
7:VDD2
10:SCL
8:CKOUT
9:REFOUT
Package: 16-Pin TSSOP ( Top View)
Pin No.
Pin
Name
Pin
Type
1
XIN
IN
2
RESET
IN
3
FSEL
IN
4
5
6
VDD1
GND1
GND2
----
7
VDD2
--
8
9
10
11
CKOUT
REFOUT
SCL
SDA
OUT
OUT
IN
IN / OUT
12
VDD3
--
13
14
15
GND3
A1
A0
-IN
IN
16
XOUT
IN
Description
Crystal connection.
Please input external clock to XIN when the external clock is
used.
Reset signal input pin. High pulse reset the register and digital
part of PLL.
Hi: Reset Lo: Normal operation
Frequency setting register bank selection pin.
Hi: Register bank1 Lo: Register bank0
Valid when CTLFSEL=”1” of Register F7.
3.3V power supply for PLL core.
Ground 1.
Ground 2.
Power supply for clock output buffer.
1.8V or 3.3V can be used.
Clock output.
PLL reference clock output.
Serial interface clock input.
Serial data input and output pin. Open drain.
Power supply for serial interface.
1.8V or 3.3V can be used.
Ground 3.
Device address setting pin.
Device address setting pin.
Crystal connection.
Please keep this pin open if the external clock is input to XIN
pin.
Ordering Information
Part Number
Marking
Shipping Packaging
Package
Temperature
Range
AK8142
8142
Tape and Reel
16-pin TSSOP
-30 to 85 ℃
Jan-09
MS0932-E-01
-2-
The brand name
of AKEMD’s IC’s
AK8142
Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted
Items
Supply Voltage
(1)
Symbol
Ratings
Unit
VDD
-0.3 to 4.6
V
Vin
VSS-0.3 to VDD+0.3
V
IIN
±10
mA
Tstg
-55 to 130
°C
Input Voltage
Input Current (any pins except supplies)
Storage Temperature
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated
under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating conditions for
extended periods may affect device reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
ESD Sensitive Device
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and installation
procedures can cause damage. AKEMD recommends that this device is handled with appropriate
precautions.
Recommended Operation Conditions
Parameter
Operating Temperature
Supply Voltage
Symbol
Conditions
Min
Typ
Max
Unit
85
°C
Ta
-30
VDD1
3.0
3.3
3.6
V
1.7
1.8
VDD1
V
24.0
32.0
MHz
67.0
MHz
70
%
VDD2
VDD3
Input Clock Frequency1
Fin1
Quartz Oscillator input
16.0
Input Clock Frequency2
Fin2
External input, >0.8Vpp
2.0
External input
30
Input Clock Duty Cycle
50
Pin: CKOUT
Cp1
Output Load Capacitance
Cp2
4MHz – 100MHz
15
100MHz – 150MHz
10
150MHz – 200MHz
8
Pin: REFOUT
2MHz – 67.0MHz
MS0932-E-01
25
pF
pF
Jan-09
-3-
The brand name
of AKEMD’s IC’s
AK8142
DC Characteristics
All specifications at VDD1: 3.3V, VDD2/VDD3: 1.8V, Ta: -30 to +85℃, unless otherwise noted
Parameter
Symbol
High level input voltage1
VIH1
Low level input voltage1
High level input voltage2
Low level input voltage2
VIL1
(1)
(1)
Input Current
FSEL,
Max
0.7VDD1
Unit
V
0.3VDD1
0.7VDD3
V
V
VIL2
VOH1
Low level output voltage1
VOL1
Low level output voltage2
VOL2
Power down current
A1,
Typ
Pin: SCL, SDA
IL
(2), (3)
Pin: A0,
RESET
Min
VIH2
High level output voltage1
Current Consumption
Conditions
Pin: A0, A1, FSEL,
RESET
REFOUT, CLKOUT
IOH= -4mA
REFOUT, CLKOUT
IOL = +4mA
Pin: SDA
-10
0.3VDD3
V
+10
µA
0.8VDD2
V
IOL = +3mA, Open Drain
0.2VDD2
V
0.4
V
IDD1
No load, VDD1
3.5
mA
IDD2
No load, VDD2
0.95
mA
IDD3
No load, VDD3
0.05
mA
Ipd
OE=”L”
FSEL=”L” or open
0
10
μA
(1) Do not exceed the voltage VDD3.
(2) External clock mode.(SCL=H, SDA=H), No load.
(3) XIN = 16MHz, CKOUT = 24.5759989MHz.
Register: FF=03hex, FE=74hex, FD=BChex, FC=25hex, FB=32hex, FA=61hex
Jan-09
MS0932-E-01
-4-
The brand name
of AKEMD’s IC’s
AK8142
AC Characteristics
All specifications at VDD1: 3.3V, VDD2/VDD3: 1.8V, Ta: -30 to +85℃, unless otherwise noted
Parameter
Symbol
Phase Comparison Period
VCO Frequency
(1)
Output Clock Frequency
(3)
Output Clock Duty Cycle
(4)(7)
Output Clock Fall Time
Output Clock Jitter
Output Lock Time
(4)(7)
(6)
(4)(7)
(4)(7)
MIN
TYP
2
(2)
Output Clock Rise Time
Conditions
trise
tfall
CKOUT
100
CKOUT, Divided
CKOUT, not Divided
(5)
REFOUT
CKOUT, Divided
CKOUT, not Divided
REFOUT, 0.2VDD to 0.8VDD
2MHz – 66.0MHz
CKOUT, 0.2VDD to 0.8VDD
4MHz – 100MHz
CKOUT, 0.2VDD to 0.8VDD
100MHz – 150MHz
CKOUT, 0.2VDD to 0.8VDD
150MHz – 200MHz
REFOUT, 0.2VDD to 0.8VDD
2MHz – 66.0MHz
CKOUT, 0.2VDD to 0.8VDD
4MHz – 100MHz
CKOUT, 0.2VDD to 0.8VDD
100MHz – 150MHz
CKOUT, 0.2VDD to 0.8VDD
150MHz – 200MHz
4.0
100
40
45
30
MAX
Unit
4
MHz
MHz
50
50
50
100
200
60
55
70
MHz
MHz
3.0
ns
3.0
ns
2.5
ns
2.0
Ns
3.0
Ns
3.0
Ns
2.5
ns
2.0
ns
%
Jit
CKOUT, Period, 1σ
15
ps
tlock
CKOUT, Power-up
1
ms
(1) Phase Comparison Frequency = Input frequency / MDIV value. Refer to register address FA.
(2) VCO Frequency = Phase Comparison Frequency x NDIV value. Refer to register address FC.
(3) Refer to register address FB.
(4) With the load capacitance specified by the recommended operation conditions.
(5) Quartz oscillator input or external clock input with 50% duty.
(6) The time that output reaches the target frequency within accuracy of ±0.1% from the point that the FSEL is
switched.
(7) Design value
MS0932-E-01
Jan-09
-5-
The brand name
of AKEMD’s IC’s
AK8142
Serial interface (I2C:slave mode) AC Characteristics
All specifications at VDD1: 3.3V, VDD2/VDD3: 1.8V, Ta: -30 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
MAX
Unit
400
kHz
SCL clock frequency
fSCL
SCL Clock Low Period
tLOW
4.7
us
SCL Clock High Period
tHIGH
4.0
us
Pulse width of spikes which must
be suppressed
SLC Low to SDA Data Out
tI
100
ns
3.5
us
tAA
0.1
tBUF
4.7
us
Start Condition Hold Time
tHD.STA
4.0
us
Start Condition Setup Time
(for a Repeated Start condition)
tSU.STA
4.7
ms
Data in Hold Time
tHD.DAT
0
us
Data in Setup Time
tSU.DAT
200
ns
Bus free time between a STOP
and START condition
SDA and SCL Rise Time
tR
(*)
1.0
us
SDA and SCL Fall Time
tF
(*]
0.3
us
Stop Condition Setup Time
Data Out Hold Time
tSU.STO
4.0
us
tDH
100
ns
(*) Design value.
tF
tR
SCL (IN)
tSU.STA
tLOW
tHIGH
tHD.DAT
tHD.STA
tSU.STO
tSU.DAT
SDA (IN)
tAA
tDH
tBUF
SDA (OUT)
Jan-09
MS0932-E-01
-6-
The brand name
of AKEMD’s IC’s
AK8142
Function Description
I2C interface
Read/Write performance of I2C interface is expressed below. The device address #1 of AK8142 is fixed
as ”1010”. The device address #2 is set by A0, A1 pins.
Device address of AK8142
1
0
1
0
Device Adress#1
1
A1 A0 R/W
Device Adress#2
Byte wtire operation
Byte write operation is described below. Data must be sent after sending 8 bits address and receiving ACK.
Byte write
SDA
1 0 1 0
S
T
A
R
T
Device
Address
-1
0
Device R A
Address / C
W K
-2
Address
(MSB First)
A
C
K
Data
(MSB First)
A S
C T
K O
P
Page write operation
Page write operation is described below. Only lower 4 bits of address are valid. Upper 4 bits are fixed as
“1111”. Therefore the address which is written after “1111 1111” becomes “1111 0000”.
Page write
1 0 1 0
SDA
S
T
A
R
T
Device
Address
-1
・・・・
0
Device R A
Address / C
W K
-2
Address
(MSB First)
A
C
K
Data
A
C
K
(Address)
Data
(Address+1)
A
C
K
A
C
K
Data
(Address+n)
A S
C T
K O
P
Current address read
Current address read operation is described below. The data that is read by this operation is obtained as
“last accessed address + 1”. Therefore, It is consequent to return “0000 0000” after accessing the address
“0000 1111”.
Current address read
SDA
1 0 1 0
S
T
A
R
T
Device
Address
-1
1
Device R A
Address / C
W K
-2
Data
(MSB First)
N
O
A
C
K
S
T
O
P
MS0932-E-01
Jan-09
-7-
The brand name
of AKEMD’s IC’s
AK8142
Random read
Random read operation is described below. It is necessary to operate “dummy write” before sending read
command. Dummy write is to send the address to read.
Random read
SDA
1 0 1 0
S
T
A
R
T
Device
Address
-1
0
Device R A
Address / C
W K
-2
1 0 1 0
Address
(MSB First)
A S
C T
K A
R
T
Device
Address
-1
1
Device R A
Address / C
W K
-2
Data
(MSB First)
N
O
A
C
K
S
T
O
P
Dummy Write
Sequential read
Sequential read operation is described below. It is possible to read next address sequentially by sending
ACK instead of stop condition.
Sequential read
SDA ・・・・
・・・・
1
Device R A
Address / C
W K
-2
Data (MSB First)
(Address)
A
C
K
Data (MSB First)
(Address+1)
A
C
K
A
C
K
Data (MSB First)
(Address+n)
N
O
A
C
K
S
T
O
P
Change data
Change data operation is described below. It is available when SCL is Low.
Change data
SCL
SDA
DATA STABLE
DATA
CHANGE
Start / Stop timing
Start / Stop timing is described below. The sequence is started when SDA goes from high to low during
SCL is high. The sequence is stopped when SDA goes from low to high during SCL is high.
Start / Stop timing
SCL
SDA
START
STOP
Jan-09
MS0932-E-01
-8-
The brand name
of AKEMD’s IC’s
AK8142
Register map
Zero is returned when “– “ bits are read.
FA – FF has 2 dimensions which are selectable by BANK bit.
Bottom part: Reset value
*note The power-on-reset does not reset “SFTRST” of register F7.
Address
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
~
F1
D7
D6
D5
D4
D3
D2
D1
D0
Note
–
–
–
–
–
–
FRAC[17]
FRAC[16]
0
0
Sigma-Delta
fraction
FRAC[15]
FRAC[14]
FRAC[13]
FRAC[12]
FRAC[11]
FRAC[10]
FRAC[9]
FRAC[8]
0
0
0
0
0
0
0
0
FRAC[7]
FRAC[6]
FRAC[5]
FRAC[4]
FRAC[3]
FRAC[2]
FRAC[1]
FRAC[0]
0
0
0
0
0
0
0
0
–
INT[6]
INT[5]
INT[4]
INT[3]
INT[2]
INT[1]
INT[0]
0
1
0
0
0
0
0
–
OUTC[2]
OUTC[1]
OUTC[0]
ODIVPG[3]
ODIVPG[2]
ODIVPG[1]
ODIVPG[0]
1
1
1
0
1
1
1
MDIVC[3]
MDIVC[2]
MDIVC[1]
MDIVC[0]
MDIVP[3]
MDIVP[2]
MDIVP[1]
MDIVP[0]
0
1
1
0
0
0
0
1
–
–
–
–
RSRV
RSRV
RSRV
RSRV
0
1
0
1
RSRV
RSRV
RSRV
RSRV
0
0
0
0
CKOFF[0]
RSRV
PD
SFTRST
–
BANK
–
BANKWR
–
CTLFSEL
–
CKOFF[1]
0
0
0
0
0
0
0
0
–
–
–
–
CKOUTEN[1]
REFOTEN[0]
REFOTEN[1]
REFOTEN[0]
0
0
0
0
–
–
DUMON
DITHER
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Sigma-Delta
integer
OUTDIV
MDIV
Reserve
Reserve
RESET
BANK
OUTBUF
Sigma-Delta
Test
Test
Test
Registers F1 to F4 are for test purpose only. Do not access these registers.
MS0932-E-01
Jan-09
-9-
The brand name
of AKEMD’s IC’s
AK8142
Register definitions
Refer “Frequency setting procedure” on page 15 for details.
Address FF, FE, FD
D7
Address
FF
D6
D5
D4
D3
D2
D1
D0
FRAC[17]
FRAC[16]
FE
FRAC[15]
FRAC[14]
FRAC[13]
FRAC[12]
FRAC[11]
FRAC[10]
FRAC[9]
FRAC[8]
FRAC[7]
FRAC[6]
FRAC[5]
FRAC[4]
FRAC[3]
FRAC[2]
FRAC[1]
FRAC[0]
FD
FRAC[17:0]
FRACTIONAL N fractional part settings
FRAC[17:0]
01 1111 1111 1111 1111
01 1111 1111 1111 1110
01 0000 0000 0000 0000
00 0000 0000 0000 0001
00 0000 0000 0000 0000
11 1111 1111 1111 1111
11 1111 1111 1111 1110
11 0000 0000 0000 0000
10 0000 0000 0000 0001
10 0000 0000 0000 0000
A value
+131071
+131070
+65536
+1
0
-1
-2
-65536
-131071
-131072
Decimal fraction
0.49999619..
0.25
0.00000381..
0
-0.00000381..
-0.25
-0.49999619..
-0.5
18
Fractional part of N is expressed by A/2 . Here, the numerator A is defined by FRAC bits. FRAC is
17
17
treated as 2’s Complement which is able to set from -2 up to +2 . Consequently, it is possible to set
from -0.5 to +0.5 for fractional part of N.
FRAC[17:0] settings are updated after writing register FF. Setting procedure should be 1.FD, 2.FE
and then 3.FF.
Address FC
Address
FC
INT[5:0]
D7
-
D6
INT[6]
D5
INT[5]
D4
INT[4]
D3
INT[3]
D2
INT[2]
D1
INT[1]
D0
INT[0]
FRACTIONAL N integral part settings
INT[6:0]
000 0000 - 001 1000
001 1001
001 1010
Integral value
Prohibited
25
26
110 0011
110 0100
110 0101 - 111 1111
99
100
Prohibited
*note Do not set any value except ”25” - ”100”.
Jan-09
MS0932-E-01
- 10 -
The brand name
of AKEMD’s IC’s
AK8142
Address FB
Address
FB
D7
D6
D5
D4
D3
D2
D1
D0
-
OUTC[2]
OUTC[1]
OUTC[0]
ODIVPG[3]
ODIVPG[2]
ODIVPG[1]
ODIVPG[0]
OUTC[2]
Programmable divider input select
0
1
OUTC[1:0]
VCO output (not divided)
VCO 1/2 output
PLL output select
OUTC[1:0]
00
01
10
11
ODIVPG[3:0]
VCO output (not divided)
VCO 1/2 output
VCO 1/4 output
VCO programmable divider output
Programmable divider control
ODIVPG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Dividing value
(Fixed output)
4
6
8
10
12
14
16
18
20
22
24
26
28
30
(Fixed output)
ODIV
SEL
VCO
PLLOut
1/2
SEL
1/2
OUTC[2]
1/4
Programmable Div.
ODIVPG[3:0]
MS0932-E-01
OUTC[1:0]
Jan-09
- 11 -
The brand name
of AKEMD’s IC’s
AK8142
Address FA
Address
FA
D7
D6
D5
D4
D3
D2
D1
D0
MDIVC[3]
MDIVC[2]
MDIVC[1]
MDIVC[0]
MDIVP[3]
MDIVP[2]
MDIVP[1]
MDIVP[0]
MDIVC[3]
Programmable divider input select
0
1
MDIVC[2]
CLKIN
CLKIN 1/2
3or4 divider select
0
1
MDIVC[1:0]
M divider dividing value settings
MDIVC[1:0]
00
01
10
11
MDIVP[3:0]
3 divider
4 divider
Dividing value
1
2
3or4
programmable
Programmable divider control
MDIVP[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Dividing value
Prohibited
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Prohibited
MDIVC[2]
MDIV
SEL
Clock In
1/2
SEL
1/2
MDIVC[3]
Phase
Comparator
1/3 or 1/4
Programmable Div.
MDIVP[3:0]
Jan-09
MDIVC[1:0]
MS0932-E-01
- 12 -
The brand name
of AKEMD’s IC’s
AK8142
Address F9, F8
Address
F9
F8
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
Reserved
Reserved
Reserved
Reserved
-
-
-
-
Reserved
Reserved
Reserved
Reserved
These registers are reserved. Set 05hex and 00hex to F9 and F8, respectively.
Address F7
Address
F7
BANK
D7
D6
D5
D4
D3
D2
D1
D0
BANK
BANKWR
CTLFSEL
CKOFF[1]
CKOFF[0]
Reserved
PD
SFTRST
Access register select for frequency settings
0
1
BANKWR
Select the BANK to write
0
1
CTLFSEL
1
Invalid
Set invalid when register is set.
Valid
Frequency selection BANK is selectable with FSEL pin.
Control REFOUT output buffer
0
1
CKOFF[0]
BANK0
BANK1
Select function for the FSEL pin
0
CKOFF[1]
BANK0
Valid when CTLFSEL=”0”
BANK1
Valid when CTLFSEL=”0”
Output enable
Output disenable (500k-ohm Pull Down)
Control PLL output buffer
0
1
Output enable
Output disenable (500k-ohm Pull Down)
Reserved
This bit is reserved. Set to “0”.
PD
Power down control
0
1
SFTRST
Power up
Power down (PLL analog part)
Output turns to “H”.
Software reset control
0
1
Reset cancel
Reset (PLL digital part and Register)
Set to “0” to cancel the software reset.
MS0932-E-01
Jan-09
- 13 -
The brand name
of AKEMD’s IC’s
AK8142
Address F6
Address
F6
D7
D6
D5
D4
D3
D2
D1
D0
―
―
―
―
CKOUTEN[1]
CKOUTEN[0]
REFOUTEN[1]
REFOUTEN[0]
CKOUTEN[1:0]
Control CKOUT buffer drivability
CKOUTEN[1:0]
00
01
10
11
REFOUTEN[1:0]
High (x3)
Middle (x2)
Middle (x2)
Low (x1)
Control REFOUT buffer drivability
REFOUTEN[1:0]
00
01
10
11
High (x3)
Middle (x2)
Middle (x2)
Low (x1)
Address F5
Address
F5
D7
D6
D5
D4
D3
D2
D1
D0
―
―
―
―
―
―
DUMON
DITHER
DUMON
Control SDM (Sigma Delta Modulator)
DUMON
0
1
DITHER
Normal mode
Bypassing SDM
Set this when using PLL with integer only.
Fractional N divider settings
DITHER
0
1
Perform as fractional part is 0.
Set this when using PLL with integer only.
Normal mode
Address F4 – F1
These registers are test propose only. Do not access these address.
Jan-09
MS0932-E-01
- 14 -
The brand name
of AKEMD’s IC’s
AK8142
Frequency setting procedure
Output frequency of CKOUT is determined by REFCLK Dividing value (MDIV), OUTPUT Dividing value (ODIV),
Fractional N Dividing value (INT,FRAC). These parameters should be set as described below.
Step1. Deciding VCO base frequency.
This frequency (fvco) is decided from Output frequency and Output dividing value (address FB).
Note: Set VCO frequency between 100MHz to 200MHz.
Set ODIV bit to “1” when output frequency exceeds 100MHz.
Step2. Deciding Phase comparison frequency.
Set M divider as this frequency becomes between 2MHz to 4MHz.
Step3. Deciding Feedback dividing value.
This value is decided by VCO frequency (fvco) and Phase comparison frequency (fcmp).
7 bits integral part and 18 bits fractional part (signed 2’s complement) is necessary to be set.
Integral part (INT)
Fractional part (FRAC)
= round ( fvco / fcmp )
18
= round ( ( fvco / fcmp ) – INT ) x 2 )
Exsample1) input 27MHz, output 123.75MHz
1.
2.
VCO frequency:
Phase comparison frequency:
3.
Feedback dividing value:
123.75MHz
ODIV = 1
3MHz
MDIV = 9
27MHz / 9 = 3MHz
41.25
INT = 41d, FRAC = 65536d
INT = round ( 123.75 / 3 ) = round ( 41.25 ) = 41d
18
FRAC = round ( ( 41.25 – 41 ) x 2 ) = 65536d
Output frequency error: 0ppm
Register settings of exsample1)
[Address]
0xF7
0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
[Value]
0x08
0x38
0x00
0x29
0x00
0x00
0x01
[Contents]
Clear SFTRST, BANK0, FSEL=Invalid, REFOUT=OFF
MDIV=9d
ODIV=1d
INT =41d
FRAC(Lower 8bits)
FRAC(Medium 8bits)
FRAC(Upper 2bits)
FRAC=655536d
Exsample2) input 16MHz, output 24.576MHz
1.
2.
VCO frequency:
Phase comparison frequency:
3.
Feedback dividing value:
147.456MHz
ODIV = 6
4MHz
MDIV = 4
16MHz / 4 = 4MHz
36.864
INT = 37d, FRAC = -35652d
INT = round ( 147.456 / 4 ) = round ( 36.864 ) = 37d
18
FRAC = round ( 36.864 – 37 ) x 2 ) = -35652d
Output frequency error: 0.043ppm (1.06Hz)
Register settings of example2)
[Address]
0xF7
0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
[Value]
0x08
0x06
0x32
0x25
0xBC
0x74
0x03
[Contents]
Clear SFTRST, BANK0, FSEL=Invalid, REFOUT=OFF
MDIV=4d
ODIV=6d
INT =37d
FRAC(Lower 8bits)
FRAC(Medium 8bits)
FRAC(Upper 2bits)
FRAC=-35652d
MS0932-E-01
Jan-09
- 15 -
The brand name
of AKEMD’s IC’s
AK8142
Power up sequence
Supplying proper voltage to the power pins.
*Note: VDD1, VDD2, VDD3 must be supplied simultaneously.
Power-on-reset is executed by setting RESET = “L” during start up.
SCL / SDA are acceptable 1ms later.
*Note: When using RESET signal, It takes 500us after releasing the RESET to accept SCL / SDA
access.
VDD1/2/3
VDD*0.9
Max:1ms
Internal Vref
Power-on-reset
Min:500us
RESET
SCL/SDA
I2C Interface input available
Reset circuit
To reset this IC, these tree methods are available.
1) Internal power-on-reset
2) Hardware reset by RESET pin
3) Software reset by “SFTSRT” of register F7
The “SFTRST” bit is not cleared by power-on-reset. It should be manually set to “0” after power-on-reset if it is necessary.
VREF
PWRON RST
Register reset
(except SFTRST bit)
SFTRST bit
SFTRST
R
RESET pin
Jan-09
MS0932-E-01
- 16 -
The brand name
of AKEMD’s IC’s
AK8142
Package Information
Mechanical data (Units:mm)
Marking
a:
#1 Pin Index
b:
Product Family Logo
c:
Part number
c:
Date code (5digits)
*)
*) AKM is the brand name of AKEMD’s IC’s.
AKM and the logo - are the brand of AKEMD’s IC’s and identify that AKEMD continues to offer the
best choice for high performance mixed-signal solution under this brand.
RoHS Compliance
All integrated circuits form Asahi Kasei EMD Corporation (AKEMD) assembled in
“lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKEMD are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
MS0932-E-01
Jan-09
- 17 -
The brand name
of AKEMD’s IC’s
AK8142
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., LTD. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for application in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
Jan-09
MS0932-E-01
- 18 -
Similar pages