VBUS051CD-HD1 www.vishay.com Vishay Semiconductors Low Capacitance, Single-Line ESD-Protection Diode FEATURES • Ultra compact LLP1006-2L package • Low package height < 0.4 mm • 1-line ESD-protection 1 2 • Low leakage current < 0.1 μA 20856 • Low load capacitance CD = 0.6 pF 20855 • ESD-protection to IEC 61000-4-2 ± 15 kV contact discharge ± 15 kV air discharge MARKING (example only) • High surge current acc. IEC 61000-4-5 IPP > 2 A XY • Soldering can be checked by standard vision inspection. No X-ray necessary 21121 • Pin plating NiPdAu (e4) no whisker growth Bar = cathode marking X = date code Y = type code (see table below) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 ORDERING INFORMATION DEVICE NAME VBUS051CD-HD1 ORDERING CODE TAPED UNITS PER REEL (8 MM TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VBUS051CD-HD1-G-08 8000 8000 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS VBUS051CD-HD1 LLP1006-2L T 0.72 mg UL 94 V-0 MSL level 1 (according J-STD-020) 260 °C/10 s at terminals ABSOLUTE MAXIMUM RATINGS VBUS051CD-HD1 PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT Peak pulse current Acc. IEC 61000-4-5; tp = 8/20 μs; single shot IPPM 2 A Peak pulse power Acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 28 W ESD immunity Operating temperature Storage temperature Contact discharge acc. IEC 61000-4-2; 10 pulses Air discharge acc. IEC 61000-4-2; 10 pulses Junction temperature ± 15 kV ± 15 kV TJ -40 to +125 °C TSTG -40 to +150 °C VESD PATENT(S): www.vishay.com/patents This Vishay product is protected by one or more United States and International patents. Rev. 1.4, 04-Feb-16 Document Number: 81195 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS051CD-HD1 www.vishay.com Vishay Semiconductors ELECTRICAL CHARACTERISTICS VBUS051CD-HD1 (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of line which can be protected Nchannel - - 1 lines Max. reverse working voltage VRWM - - 5.5 V Reverse voltage at IR = 0.1 μA pin 2 to pin 1 VR 5.5 - - V Reverse current at VR = VRWM = 5.5 V; pin 2 to pin 1 IR - < 0.01 0.1 μA at IR = 1 mA pin 2 to pin 1 VBR 6.5 7.6 8.5 V Reverse clamping voltage at IPP = 2 A; acc. IEC 61000-4-5 pin 2 to pin 1 VC - - 14 V Forward clamping voltage at IF = 2 A; acc. IEC 61000-4-5 pin 1 to pin 2 VF - - 3.5 V at VR = 0 V; f = 1 MHz pin 2 to pin 1 CD - 0.6 0.8 pF Protection paths Reverse stand-off voltage Reverse breakdown voltage Capacitance APPLICATION NOTE The VBUS051CD-HD1 is an ESD-protection device with the characteristic of a Z-diode with a high ESD-immunity and a very low capacitance which makes it usable for high frequency applications like USB2.0 or HDMI. With the VBUS051CD-HD1 one high speed data line can be protected against transient voltage signals like ESD (Electro Static Discharge). Connected to the data line (pin 2) and to ground (pin 1) negative transients will be clamped close below the ground level while positive transients will be clamped clos above the 5.5 V working range. The clamping behaviour of the VBUS051CD-HD1 is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications running up to 5 V. TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 120 % Rise time = 0.7 ns to 1 ns 8 µs to 100 % 100 % 80 % 80 % 60 % 60 % IPPM Discharge Current IESD 100 % 53 % 40 % 27 % 20 % 20 % 0% -10 0 10 20 30 40 50 60 70 80 90 100 20557 Time (ns) Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) Rev. 1.4, 04-Feb-16 20 µs to 50 % 40 % 0% 0 20548 10 20 30 40 Time (µs) Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 Document Number: 81195 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS051CD-HD1 www.vishay.com Vishay Semiconductors 1 16 f = 1 MHz 14 0.8 12 0.7 10 0.6 8 VC (V) CD (pF) 0.9 0.5 0.4 positive surge Measured acc. IEC 61000-4-5 (8/20 µs - wave form) 6 4 0.3 VC 2 0.2 0 0.1 -2 0 negative surge -4 0 1 2 3 21897 VR (V) 21894 0 4 Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR 1 2 3 IPP (A) Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP 100 102 101 80 acc. IEC 61000-4-2 + 8 kV contact discharge VC-ESD (V) IF (mA) 1 10-1 10-2 10-3 60 40 20 10-4 0 10-5 10-6 0.4 0.6 0.8 21895 1 - 20 - 10 0 10 20 30 40 50 60 70 80 90 1.2 VF (V) 21898 Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF t (ns) Fig. 7 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 20 9 8 0 7 VC-ESD (V) VR (V) 6 5 4 3 - 20 - 40 acc. IEC 61000-4-2 - 8 kV contact discharge - 60 2 - 80 1 0 0.01 21896 0.1 1 10 100 1000 10 000 IR (µA) Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR Rev. 1.4, 04-Feb-16 - 100 - 10 0 10 20 30 40 50 60 70 80 90 21899 t (ns) Fig. 8 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) Document Number: 81195 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS051CD-HD1 www.vishay.com Vishay Semiconductors 200 acc. IEC 61000-4-2 contact discharge 150 VC-ESD (V) 100 50 VC-ESD 0 - 50 - 100 - 150 - 200 0 21900 5 10 15 20 VESD (kV) Fig. 9 - Typical Peak Clamping Voltage at ESD Contact Discharge (acc. IEC 61000-4-2) 0.25 [0.010] 0.15 [0.006] PACKAGE DIMENSIONS in millimeters (inches): LLP1006-2L 0.65 [0.026] 0.55 [0.022] Orientation identification 0.05 [0.002] 0 [0.000] 0.4 [0.016] 0.33 [0.013] 0.45 [0.018] 0.35 [0.014] 0.125 [0.005] ref. 0.55 [0.022] 0.45[0.018] 0.3 [0.012] 0.2 [0.008] 1.05 [0.041] 0.95 [0.037] 0.05 [0.002] Document no.: S8-V-3906.04-005 (4) Rev. 6 - Date: 15.July 2015 20812 Rev. 1.4, 04-Feb-16 0.25 [0.010] 1 [0.039] 0.2 [0.008] 0.5 [0.020] 0.6 [0.024] Foot print recommendation: solder resist mask solder pad 0.5 [0.020] soldermask opening ± 0.03 measured middle of the package Document Number: 81195 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS051CD-HD1 www.vishay.com Vishay Semiconductors Unreeling direction Pin 1 cathode mark Top view Pad layout - view from top seen at bottom side S8-V-3906.04-017 (4) Rev.1, Date: 28. Jan. 2010 21999 Rev. 1.4, 04-Feb-16 Document Number: 81195 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000