AK2301A

ASAHI KASEI
[AK2301A]
AK2301A
3.3V Single channel PCM CODEC LSI
FEATURE
GENERAL DESCRIPTION
♦ Single PCM CODEC and filtering system
♦ Mute function
♦ PCM interface; 14bits linear data
(16bit format, serial interface)
♦ Long Frame / Short Frame are selected
automatically
♦ PCM data rate
256kHz/512kHz
♦ Op-amp for the external gain adjustment
♦ Dual universal op-amps
♦ Single power supply voltage
+3.0~+3.6V
♦ Low power consumption
♦ Small package
The AK2301A is a single channel PCM CODEC for
speech processing 8kHz sampling PCM data by DSP.
The AK2301A interfaces with 14bit linear data (16bit
format).
It includes Band limiting filter, A/D and D/A converter,
and universal op-amps for construction of the output
filter. All functions are provided in small 24pin VSOP
package and it is good for reducing the mounting
space.
PACKAGE
♦ 24pin VSOP
Pin to pin 7.9*7.6mm
Pin pitch 0.65mm
BLOCK DIAGRAM
GST
VFTN
VFTP
AAF
A/D
AMPT
VR
VFR
CODEC
Core
SMF
PCM I/F
DX
DR
FS
BCLK
D/A
AMPR
GSR
Internal
Main Clock
TAGND
VREF
PLL
PLLC
BGREF
MUTEN
RSTN
VDD
AMP1
VSS
AMP2
TEST1
TEST2
TEST3
AK2301A
AMP1O
<MS0300-E-01>
AMP1I
1
AMP2O
AMP2I
2005/8
ASAHI KASEI
[AK2301A]
CONTENT
ITEMS
<MS0300-E-01>
PAGE
-
BLOCK DIAGRAM…………………………………… 1
-
PIN CONDITION……………………………………… 3
-
PIN FUNCTION……………………………………..
-
ABSOLUTE MAXIMUM RATINGS………………… 5
-
RECOMMENDED OPERATING CONDITON ……. 5
-
ELECTRICAL CHARACTERESTICS…………….… 5
-
PACKAGE INFORMATION……………………….… 10
-
PIN ASSIGNMENT…………………………………… 11
-
MARKINGS…………………………………….……
-
CIRCUIT DESCRIPTIONS………………………...… 12
-
FUNCTIONAL DESCLIPTIONS………………..…… 13
-
PCM CODEC………………………...…………
-
PCM INTERFACE………………………..……… 14
-
LongFrame/ShortFrame…....………….……… 14
-
MUTE……………………………………………
-
RESET SEQUENCE………………………..…… 17
-
Universal op-amps………………………..……. 18
-
APPLICATION CIRCUIT EXAMPLE ……………… 19
2
4
11
13
16
2005/8
ASAHI KASEI
[AK2301A]
PIN CONDITIONS
Pin#
AC load
(MAX.)
I/O
Pin type
VFTN
VFTP
I
I
Analog
Analog
GST
O
Analog
50pF
GSR
O
Analog
40pF
8
9
VFR
I
Analog
VR
O
Analog
6
19
5
3
2
4
23
22
18
VDD
VSS
FS
BCLK
DX
DR
MUTEN
RSTN
I
I
O
I
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
VREF
O
Analog
PLLC
O
Analog
TAGND
O
Analog
AMP2I
AMP1I
I
I
Analog
Analog
AMP1O
O
Analog
40pF
AMP2O
O
Analog
40pF
15
16
14
7
Name
DC load
(MIN.)
AC load(*1)
8kΩ
40pF
50pF
21
24
1
Analog
ground
Hi-Z
- External
capacitance
1.0uF or more
- External
capacitance
0.33uF±40%
( Includes
temperature
characteristic)
- External
capacitance
1.0uF or more
- 150uA load max
17
10
Remarks
AC load(*1)
10kΩ(*2)
AC load(*1)
8kΩ
20
11
12
13
Output
status
(mute)
AC load(*1)
8kΩ
AC load(*1)
8kΩ
- Tie to the VSS
- Tie to the VSS
- Tie to the VSS
*1)AC load is a load against AGND. This value includes a feedback resistance of input/output op-amps.
Test1
Tset2
Test3
<MS0300-E-01>
I
I
I
CMOS
CMOS
CMOS
3
2005/8
ASAHI KASEI
[AK2301A]
PIN FUNCTION
Pin types
NIN:
Normal input
AIN:
Analog input
Pin# Name
15
VFTN
16
14
VFTP
GST
7
GSR
8
9
6
VFR
VR
VDD
19
5
VSS
FS
3
BCLK
2
DX
4
DR
23
MUTEN
22
RSTN
18
VREF
20
PLLC
17
TAGND
TOUT: Try state output
AOUT: Analog output
PWR: Power / Ground
Type
Function
AIN Negative analog onput of transmit OP amp.
Diffelential or signal amplifire is composed with the VFTP and the exernal
registers. Transmit gain is defined by the ratio of the external registers.
AIN Positive analog input of the transmit OP amp.
AOUT Output of the transmit OP amp.
The external feedback resister is connected between this pin and VFTP.
AOUT Output of the receive OP amp.
Receive gain is defined by the ratio of the external registers.
The differential output can be composed with using the VR.
AIN Negative analog input of the receive OP amp.
AOUT Analog output of the D/A converter equivalent to the received PCM code.
PWR Positive supply voltage
+3.3V supply
PWR Ground (0V)
NIN Frame sync input
This clock is input for the internal PLL which generates the internal system
clocks. FS must be 8kHz clock which synchronized with BCLK and do not
stop feeding. *
NIN Bit clock of PCM data interface
This clock defines the input/output timing of DX and RX.
The frequency of BCLK should be 256kHz or 512kHz and do not stop
feeding. *
TOUT Serial output of PCM data
The PCM data is synchronized with BCLK. This output remains in the high
impedance except for the period in which PCM data is transmitted.
NIN Serial input of PCM data
The PCM data is synchronized with BCLK.
NIN Mute setting pin
“L” level forces both A/D, D/A output to mute state.
NIN Reset signal input pin
Reset operation starts by low input. This pin is used for the initialization at
the power up.Please use MUTEN pin together to avoid the popping sound
output until the LSI finish the initialization after the power up. (Refer to P.13)
AOUT Analog ground output
External capacitance (1.0µF or more) should be connected between this pin
and VSS. Please do not connect external load to this pin.
AOUT PLL loop filter output
External capacitance (0.33µF±40%: Includes temperature characteristic)
should be connected between this pin and VSS.
AIN Analog ground output for transmit OP amp
150µA load max. External capacitance (1.0µF or more) should be connected
between this pin and VSS. This pin is used as an analog ground for transmit
OP amp (AMPT).
AIN Negative input of the universal OP amp
12
AMP1I
11
AMP2I
13
AMP1O
AOUT Output of the universal OP amp
10
AMP2O
21
TEST1
NIN Test pins (“H”=test mode)
24
TEST2
Please tie to VSS
1
TEST3
*) When stop the BCLK and FS, please set RSTN=“L”.
<MS0300-E-01>
4
2005/8
ASAHI KASEI
[AK2301A]
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
min
Power supply voltage
Analog/Digital power supply
VDD
-0.3
Digital input voltage
VTD
-0.3
Analog input voltage
VTA
-0.3
Input current (except power supply pins)
IIN
-10
Storage temperature
Tstg
-55
Warning: Exceeding absolute maximum ratings may cause permanent damage.
Normal operation is not guaranteed at these extremes.
max
Units
4.6
VDD+0.3
VDD+0.3
10
125
V
V
V
mA
℃
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power supply voltage
VDD
Analog/Digital power supply
Ambient operating temperature
Ta
Frame sync frequency *)
FS
Note) All voltages reference to ground: VSS = 0V
*) All the characteristics of the CODEC is defined by 8kHz FS.
min
3.0
typ
3.3
max
3.6
Units
V
-40
-1.0%
8
85
+1.0%
℃
kHz
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, guaranteed for VDD = +3.3V±0.3V, Ta = -40~+85℃, FS=8kHz, VSS=0V
DC Characteristics
Parameter
Power Consumption
BCLK=512kHz
Symbol
PDD1
Output high voltage
VOH
IOH=-1.6mA
Output low voltage
VOL
IOL=1.6mA
Input high voltage
VIH
Input low voltage
VIL
Input leakage current
ILL
-10
Analog ground output
VRG
1.4
Conditions
All putput unloaded
*1)
typ
10
Max
Unit
15
mA
0.8VDD
V
0.4
0.7VDD
Output leakage current ILT
Tri-state mode
*1) [email protected] input, [email protected] Code input
<MS0300-E-01>
min
5
-10
V
V
1.5
0.3VDD
V
+10
uA
1.6
V
+10
uA
2005/8
ASAHI KASEI
[AK2301A]
PCM INTERFACE (Long Frame, Short Frame)
All timing parameters of the output pins are measured at VOH = 0.8VDD and VOL = 0.4V. Input pins are
measured at VIH = 0.7VDD and VIL = 0.3VDD.
AC Characteristics
Parameter
Symbol
Min
Typ
FS Frequency
fPF
-1.0%
8
BCLK Frequency
fPB
-
32FS/
64FS
-
kHz
1.563
1.953
2.344
us
0.781
0.977
1.172
us
40
ns
BCLK Pulse width (High/Low) (BCLK=32xFS=256kHz)
BCLK Pulse width (High/Low) (BCLK=64xFS=512kHz)
Rising/Falling Time: (BCLK,FS, DX,DR)
tWBH
tWBL
tWBH
tWBL
tRB
tFB
Max
Unit Ref Fig
+1.0% kHz
Hold Time: BCLK Low to FS High
tHBF
60
ns
Setup Time: FS High to BCLK Low
tSFB
60
ns
Setup Time: DR to BCLK Low
tSDB
60
ns
Hold Time: BCLK Low to DR
tHBD
60
ns
Delay Time: BCLK High to DX valid
Note1)
tDBD
0
60
ns
Delay Time: BCLK High to DX High-Z
Note1)
tDZC
0
60
ns
Hold Time: 2 period of BCLK Low to FS Low
tHBFL
60
Delay Time: FS or BCLK High, whichever is later,to DX valid
注1)
tDZFL
FS Pulse Width Low
tWFSL
1
BCLK
Hold Time: BCLK Low to FS Low
tHBFS
60
ns
Setup Time: FS Low to BCLK Low
tSFBS
60
ns
Fig1,2
Long Frame
nd
ns
60
ns
Fig1
Short Frame
Fig2
Note1) Measured with 50pF load capacitance and 0.2mA drive.
<MS0300-E-01>
6
2005/8
ASAHI KASEI
[AK2301A]
Interface Timing
tFB
tRB tBD
tBD
1/fPB
BCLK
tSFB
FS
tHBF
tHBFL
tDZFL
tDBD
DX
MS
B
DR
MS
B
2
3
4
6
7
14
5
6
7
14
tHBD
tSDB
2
tDZC
5
3
4
FS
1/fPF
tWFSL
図1. Long Frame
tFB
tRB
tBD
tBD
1/fPB
BCLK
tSFB
FS
tHBF
DX
tHBFS
tSFBS
tDBD
MS
B
tDBD
2
3
4
tSDB
DR
MS
B
2
3
tDZC
5
6
7
14
5
6
7
14
tHBD
4
図2. Short Frame
<MS0300-E-01>
7
2005/8
ASAHI KASEI
[AK2301A]
CODEC
* The receive and transmit op-amp’s characteristics are measured at the 0dB gain.
The frequency specifications when FS deviation from 8kHz are as follows:
UsedFS
× noted frequency specification = Effective frequency specification
8k[Hz]
Absolute Gain
Parameter
Analog input level
Absolute transmit gain
Maximum overload level
Analog output level
Absolute receive gain
Maximum overload level
VFTP,VFTN
→
DX
Frequency response
Parameter
Transmit Frequency response
(A→D)
VFTP,VFTN →
DX
Receive Frequency response
(D→A)
DR → VR
DR
→
VR
Conditions
[email protected] input
min
-0.6
3.14dBm0
[email protected] input
-0.6
3.14dBm0
Conditions
Relative to:
0.05kHz
[email protected]
0.06kHz
0.2kHz
0.3~3.0kHz
3.4kHz
4.0kHz
Relative to:
0~3.0kHz
[email protected]
3.4kHz
4.0kHz
typ
0.531
-
0.762
0.531
-
0.762
max
0.6
0.6
min
30
26
0
-0.15
0
14
-0.15
-0.8
14
typ
-
-
-
-
-
-
-
-
-
max
-
-
1.8
0.15
0.8
-
0.15
0.8
-
min
typ
max
Unit
Vrms
dB
Vrms
Vrms
dB
Vrms
Unit
dB
dB
Distortion
Parameter
Transmit signal to Distortion
(A→D)
VFTP,VFTN → DX
Receive signal to Distortion
(D→A)
DR → VR
<MS0300-E-01>
Conditions
Unit
1020Hz Tone
0dBm0
70
75
-
dB
0dBm0
70
75
-
dB
C-message
1020Hz Tone
C-message
8
2005/8
ASAHI KASEI
[AK2301A]
Noise
min
typ
max
Units
C-message
-
8
13
dBrnC0
C-message
-
5
10
dBrnC0
-
55
-
dB
-
55
-
dB
min
typ
max
Units
-
-
-75
dB
-
-
-75
dB
Transmit op-amp characteristics: AMPT
Parameter
Conditions
Load resistance
AC load, Including feedback resistance
Load capacitance
min
10
-
typ
-
-
max
-
50
Units
kΩ
pF
Gain
-12
-
6
dB
min
typ
max
Units
Output voltage (AGND level) PCM +0 code input
-
1.5
-
V
Load resistance
Load capacitance
8
-
-
-
-
40
kΩ
pF
min
8
-
typ
-
-
max
-
40
Units
kΩ
pF
70
75
-
dB
-12
-
6
dB
-
2.15
-
Vp-p
min
8
-
typ
-
-
max
-
40
Units
kΩ
pF
62
87
-
dB
-12
-
6
dB
2.1
2.25
-
Vp-p
Parameter
Idle channel noise A→D (*1)
VFTP,VFTN → DX
Idle channel noise D→A(*2)
DR → VR
PSRR
Transmit path
Conditions
VDD=3.3V/±66mVop
f=0~10kHz
PSRR
VDD=3.3V/±66mVop
Receiver path
f=0~10kHz
(*1) Analog input is set to the analog ground level
(*2) Digital input is set to the +0 CODE
Crosstalk
Parameter
Transmit to receive
VFTP,VFTN → VR,GSR
Receive to transmit
DR → DX
Conditions
VFTN [email protected]
DR = 0-Code
[email protected] code level
VFTP,VFTN = 0 Vrms
Inverting amplifiers
Receive signal output characteristics: VR
Parameter
Conditions
AC load
Receive op-amp characteristics: AMPR
Parameter
Conditions
Load resistance
AC load, Including feedback resistance
Load capacitance
0dB setting, [email protected] input
SINAD
VR, GSR differential output
With C-message
Gain
Inverting amplifire
Output voltage swing
DR = 3.14dBm0 digital code input
Universal op-amp characteristics: AMP1,2
Parameter
Conditions
Load resistance
AC load, Including feedback resistance
Load capacitance
+6dB setting, [email protected] input
SINAD
5Hz~30kHz measurement
Gain
Inverting amplifier
Output voltage swing
<MS0300-E-01>
+6dB setting, [email protected] input
9
2005/8
ASAHI KASEI
[AK2301A]
PACKAGE INFORMATION
24pin VSOP
<MS0300-E-01>
10
2005/8
ASAHI KASEI
[AK2301A]
PIN ASSIGNMENT
24pin VSOP
TEST3
DX
BCLK
DR
FS
VDD
GSR
VFR
VR
AMP2O
AMP2I
AMP1I
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TEST2
MUTEN
RSTN
TEST1
PLLC
VSS
VREF
TAGND
VFTP
VFTN
GST
AMP1O
TEST1, TEST2, TEST3 are test pins.
Please tie them to the VSS.
MARKING
(1) 1pin sign
(2) Date Code: 5digit XXXXX
(3) Marketing Code: AK2301A
(4) AKM logo
(4)
(3)
AKM
AK2301A
XXXXX
(2)
(1)
<MS0300-E-01>
11
2005/8
ASAHI KASEI
[AK2301A]
CIRCUIT DESCRIPTION
BLOCK
AMPT
AMPR
AAF
CODEC
A/D
CODEC
D/A
SMF
BGREF
PCM I/F
AMP1, AMP2
<MS0300-E-01>
FUNCTION
Op-amp for input gain adjustment. This op-amp is used as an inverting or
differential amplifier. Adjusting the gain with external resistors. The resistor should
be larger than 10kΩ for the feedback resistor.
VFTN: Negative op-amp input.
VFTP: Positive op-amp input.
GST: Op-amp output.
Op-amp for output gain adjustment. This op-amp is used as an inverting amplifier.
Adjusting the gain with external resistors. The combined resistor larger than 8kΩ is
recommended for the feedback and the output load
VFR: Negative op-amp input.
GSR: Op-amp output.
VR and GSR can be used as the differential output.
Integrated anti-aliasing filter which prevents signals around the sampling rate from
folding back into the voice band. AAF is a 2nd order RC active low-pass filter.
Converts the analog signal to 14bit PCM data. The band limiting filter is also
intergrated.
Converting the 14bit PCM data from the DR to the analog signal. Output of the
D/A coverter is fed into the SMF to suppress the high frequency element.
Extracts the inband signal from D/A output. It also corrects the sinx/x effect of the
D/A output.
Provide the stable analog ground voltage using an on-chip band-gap reference
circuit which is temperature compensated. The output voltage is 1.5V for 3.3V
An external capacitor of 1.0uF or larger should be connected between VREF and
VSS to stabilize analog ground (VREF). Please do not connect external load to
this pin. TAGND pin is used as the analog ground level output for the AMPT. An
external capacitor of 1.0uF or larger should be connected between TAGND and
VSS to stabilize analog ground.
For the PCM data rate, 256kHz or 512kHz are available. The 14bit PCM data is
input/output by the 2’s compliment 16bit serial data format. Two kinds of data
format (Long Frame/Short Frame) are available. Each data format is automatically
detected by AK2301A.
PCM data is input to DR pin and output from DX pin.
Universal op-amp for the filter of the external voice path. The maximum load is 8kΩ
(including the feedback resistor and AC load). These op-amps are assumed as
using for the inverting LPF with 20kHz cut off frequency.
12
2005/8
ASAHI KASEI
[AK2301A]
FUNCTIONAL DESCRIPTIONS
PCM CODEC
- A/D
Analog input signal is converted to 14bit PCM data. The analog signal is fed to the anti-aliasing filter
(AAF) before the converting PCM data, to prevent signals around the sampling rate from folding back
into the voice band. The converted PCM data passes through the band limiting filter which Frequency
response is designated in page8, and output from the DX pin with MSB first format. It is synchronized
with rising edge of the BCLK. This PCM data is 2’s compliment 2digit data and full scale is defined as
3.14dBm0. The analog input of 0.762Vrms is converted to a digital code of 3.14dBm0.
- D/A
Input PCM data from the DR pin is through the digital filter which Frequency response is designated in page8,
and converted analog signal. This analog signal is removed the high frequency element with SMF (fc=30kHz
typ) and output from the VR pin. The input PCM data is 2’s compliment 2digit data and full scale is defined as
3.14dBm0. When the input signal is 3.14dBm0, the level of the analog output signal becomes 0.762Vrms.
- PCM digital code
The relation ship between the analog signal and the 14bit linear code.
Signal level
14bit linear CODE (MSB First)
+Full code
01 1111 1111 1111
Peak value of the PCM 0dBm0 CODEC
01 0110 0100 1010
PCM 0-CODE
00 0000 0000 0000
-Full scale
10 0000 0000 0000
<MS0300-E-01>
13
2005/8
ASAHI KASEI
[AK2301A]
PCM Data Interface
AK2301A supports the following 2 PCM data formats
- Long Frame Sync (LF)
- Short Frame Sync (SF)
PCM data is interfaced through the pin (DX, DR).
In each case, PCM data is interfaced by the 2’s compliment 2digit data with 16bit MSB first format. However,
internal CODEC is 14bit format operation, then the lowest 2bits output become to “L” level. For the input, the
lowest 2bits are ignored.
Selection of the interface format
The AK2301A automatically selects the Long Frame/Short frame by means of detecting the length frame
signal.
LONG FRAME (LF) / SHORT FRAME (SF)
-Automatic LF/SF detection
AK2301A monitors the duration of the “H” level of FS and automatically selects LF or SF interface
format.
Period of FS=”H”
Frame type
More than 2 clocks of BCLK
LF
1 clock of BCLK
SF
Timing of the interface
16bit PCM data is accommodated in 1 flame (125µs) defined by 8kHz frame sync signal. Although there are
4time slot at maximum in 8kHz frame (when BCLK = 512kHz), PCM data for AK2301A occupies first time
slot.
<MS0300-E-01>
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2005/8
ASAHI KASEI
[AK2301A]
- Frame sync signal (FS)
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface.
All the internal clock of the LSI is generated based on this FS signal.
-Bit clock (BCLK)
BCLK defines the PCM data rate. BCLK rate is 256kHz or 512kHz. This clock must be synchronized with FS.
LongFrame
FS
BCLK
DX
DR
Don’t
care
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
9
10
11
12
13
14
L
L
9
10
11
12
13
14
Don’t care
9
10
11
12
13
14
L
9
10
11
12
13
14
Don’t care
ShortFrame
FS
BCLK
DX
DR
Don’t
care
8
8
L
Important notice!
Please don’t stop feeding FS and BCLK.
Both FS and BCLK is used as the internal reference clock. LSI does not work when the FS and BCLK are not
provided.
When stop the BCLK and FS, please set RSTN=“L”.
<MS0300-E-01>
15
2005/8
ASAHI KASEI
[AK2301A]
MUTE
The output of the PCM CODEC can be muted by pin control.
MUTEN pin
MUTEN pin
Operation
DX pin
VR pin
0
Mute
High-Impedance
CODEC analog
ground
1
Normal
PCM data output
CODEC analog output
[DX pin]
When the MUTEN pin turns to “L” during the data output, the mute function becomes available at the top of
the next FS.
[VR pin]
When the MUTEN pin turns to “L”, 0 code is fed to the D/A converter and VR becomes at analog ground
level.
<MS0300-E-01>
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ASAHI KASEI
Reset and Start up sequence
[AK2301A]
Reset operation starts by low input.
This function is used for the initialization at the power up. Please use MUTEN together with RSTN to avoid the popping
sound from the output until the AK2301A moves into the stable operation.
- Start up sequence
(1) After the power on, please set the RSTN pin to low level for 10msec or more.
(2) Before the first sequence or less than 250µs after the cancellation of reset, please provide the FS and the
BCLK.
(3) Please set the MUTEN pin to low level during the period of the AK2301A’s initialization which is less than
200msec after the FS and the BCLK provided. The CODEC voice path is established by releasing the
mute function.
Less than 250usec
10msec or more
200msec or more
0.9VDD
VDD
RSTN
(1)
(2)
FS
BCLK
MUTEN
<MS0300-E-01>
(3)
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ASAHI KASEI
Universal op-amps
[AK2301A]
The op-amps for construction of the external filter.
The AMP1(2)I is negative input and the AMP1(2)O is output of the op -amp.
- Circuit example
Please design output load may become 8kΩ or more. The output load includes a feedback register and AC
load. These op-amps are assumed to be used for 20kHz max cut off frequency LPF. And please design the
gain may become –12~+6dB.
The following figure shows the circuit example.
C1
R1
AMP1(2)I
C2
C3
R2
AMP1(2)O
Load Z
Each parameter is calculated as is shown below.
LPFcut-off frequency fCL[Hz] : fCL=1/(2πR2C2)
Output load L[Ω] : L=R2Z/(R2+Z)
Gain A[dB] : A=20log(R2/R1)
HPF cut-off frequency fCH[Hz] : fCH=1/(2πR1C1)
<MS0300-E-01>
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2005/8
ASAHI KASEI
[AK2301A]
APPLICATION CIRCUIT EXAMPLES
Analog input circuit
Analog output circuit
GST
20koh
m
1uF
1uF
VR
100pF
10kohm
load
10koh
m
1uF
VFTN
40kohm
1uF
10koh
m
VFR
VFTP
100pF
40kohm
20koh
m
TAGND
1uF
100pF
GSR
10kohm
load
1uF
VSS
Power supply, PLL loop filter
capacitor and analog ground
stabilization capacitor
Universal op-amps
1uF
20koh
m
40koh
m
AMP1I
VREF
VREF
PLLC
PLL
200pF
1uF
1uF
AMP1O
VSS
10kohm
load
0.33uF
1uF
20koh
m
40koh
m
AMP2I
VSS
200pF
VDD
1uF
AMP2O
10uF
10kohm
load
<MS0300-E-01>
0.1uF
VSS
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2005/8
ASAHI KASEI
[AK2301A]
IMPORTANT NOTICE
l These products and their specifications are subject to change without notice.
Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd.
(AKM) sales office or authorized distributor concerning their current status.
l AKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
l Any export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
l AKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet very
high standards of performance and reliability.
l It is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in advance
of the above content and conditions, and the buyer or distributor agrees to assume any and
all responsibility and liability for and hold AKM harmless from any and all claims arising
from the use of said product in the absence of such notification.
<MS0300-E-01>
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2005/8
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