AK4649VN

[AK4649VN]
AK4649VN
24bit Stereo CODEC with MIC/SPK-AMP
GENERAL DESCRIPTION
The AK4649VN features a stereo CODEC with a built-in Microphone-Amplifier and Speaker-Amplifier.
Input circuits include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit, and Output
circuits include a Speaker-Amplifier. These circuits are suitable for portable application with
recording/playback function. The AK4649VN is available in 32pin QFN(5x5mm 0.5mm pitch) utilizing less
board space than competitive offerings.
FEATURES
1. Recording Function
• Stereo Single-ended input with two Selectors
• MIC Amplifier
(+29dB/+26dB/+23dB/+20dB/+16dB/+12dB/+9dB/+6dB/+3dB/0dB)
• Digital ALC (Automatic Level Control)
- Setting Range: +36dB ∼ −54dB, 0.375dB Step
- Noise Suppression
• ADC Performance: S/(N+D): 80dB, DR, S/N: 89dB (MIC-Amp=+20dB, AVDD=3.3V)
S/(N+D): 80dB, DR, S/N: 100dB (MIC-Amp=0dB, AVDD=3.3V)
• Wind-noise Reduction Filter
• 5 Band Notch Filter
• Stereo Separation Emphasis
• Digital MIC Interface
2. Playback Function
• Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
• Digital ALC (Automatic Level Control)
- Setting Range: +36dB ∼ −54dB, 0.375dB Step
- Noise Suppression
• Digital Volume Control:
- 0dB ∼ −18dB, 6dB Step & 256 Linear Step (+0dB ∼ - 48.13dB & Mute)
• Stereo Separation Emphasis
• Stereo Line Output
- S/(N+D): 87dB, S/N: 97dB
• Mono Speaker-Amp
- SPK-AMP Performance: S/(N+D): 60dB@150mW, S/N: 98dB
- BTL Output
- Output Power: 400mW@8Ω (SVDD=3.3V)
• Analog Mixing: Mono Input
3. Power Management
4. Master Clock:
(1) PLL Mode
• Frequencies: 11.2896MHz, 12MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
(2) External Clock Mode
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs
• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
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• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
6. μP I/F: 3-wire Serial, I2C Bus (Ver 1.0, 400kHz Fast-Mode)
7. Master/Slave mode
8. Audio Interface Format: MSB First, 2’s complement
• ADC: 24bit MSB justified, 16/24bit I2S
• DAC: 24bit MSB justified, 16bit LSB justified, 24bit LSB justified, 16/24bit I2S
9. Ta = −40 ∼ 85°C
10. Power Supply:
• Analog Power Supply (AVDD): 3.0 ∼ 3.6V
• Digital Power Supply (DVDD): 3.0 ∼ 3.6V
• Speaker Power Supply (SVDD): 3.0 ∼ 3.6V
11. Package : 32pin QFN, 5x5mm, 0.5mm pitch
12. Register Compatible with the AK4646
■ Block Diagram
AVDD
VSS1
VCOM
DVDD
VSS2
PMMP
MPWR/DMP
MIC Power
Supply
I2C
Control
Register
PMADL
Internal
MIC
LIN1/DMDAT
RIN1/DMCLK
CCLK/SCL
CDTIO/CAD0
PMADL or PMADR
MIC-Amp
Gain: 0/+3/+6/+9/+12/+16
+20/+23/+26/+29dB
A/D
PDN
SDTI
HPF1
PMPFIL
HPF2
BICK
LPF
LRCK
Stereo
Separation
SDTI
LIN2
External
MIC
CSN/SDA
PMADR
RIN2
PMLO
LOUT
Audio
I/F
4-band EQ
Line Out
ROUT
SDTO
ALC
1-band EQ
SDTO
PMBP
MIN
PMDAC
SPP
Speaker
PMSPK
D/A
SPN
DATT DEM
SMUTE
MCKO
PMPLL
SVDD
VSS3
PLL
MCKI
VCOC
Figure 1. Block Diagram
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■ Ordering Guide
−40 ∼ +85°C
32 pin QFN (0.5mm pitch)
Evaluation board for AK4649VN
AK4649VN
AKD4649
NC
17
BICK
20
MCKI
SDTI
21
18
SDTO
22
LRCK
MCKO
23
19
NC
24
■ Pin Layout
13
CDTIO/CAD0
LOUT
29
Top View
12
CCLK/SCL
ROUT
30
11
PDN
MIN
31
10
I2C
LIN2
32
9
VCOC
RIN1/DMCLK
8
AK4649VN
VCOM
28
7
SPN
VSS1
CSN/SDA
6
14
AVDD
27
5
SPP
MPWR/DMP
DVDD
4
15
3
26
LIN1/DMDAT
SVDD
2
VSS2
NC
16
1
25
RIN2
VSS3
Top View
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PIN/FUNCTION
No
1
2
6
AVDD
-
7
VSS1
-
8
VCOM
O
9
VCOC
O
10
I2C
I
11
PDN
I
CCLK
I
Function
Rch Analog Input 2 Pin
No Connection. No internal bonding. This pin must be connected to the ground.
Lch Analog Input Line Input 1Pin
(DMIC bit = “0”)
Digital Microphone Data Input Pin
(DMIC bit = “1”)
Rch Analog Input 1 Pin
(DMIC bit = “0”)
Digital Microphone Clock pin
(DMIC bit = “1”)
MIC Power Supply Pin for Microphone
(MPDMP bit = 0”)
MIC Power Supply pin for Digital Microphone (MPDMP bit = “1”)
Analog Power Supply Pin
This pin must be connected to VSS1 with a 0.1μF ceramic capacitor in series.
Ground 1 Pin
Common Voltage Output Pin
Bias voltage of ADC inputs and DAC outputs.
Output Pin for Loop Filter of PLL Circuit
This pin must be connected to VSS1 with one resistor and capacitor in series.
Control Mode Select Pin “H”: I2C Bus, “L”: 3-wire mode
The input circuit of the I2C pin is operated by AVDD.
Power-down & Reset
When “L”, the AK4649VN is in power-down mode and is held in reset.
The AK4649VN must be always reset upon power-up.
Control Data Clock Pin
(I2C pin = “L”)
SCL
I
Control Data Clock Pin
3
4
5
12
Pin Name
RIN2
NC
LIN1
DMDAT
RIN1
DMCLK
MPWR
DMP
I/O
I
I
I
I
O
O
O
(I2C pin = “H”)
CDTIO
I/O
Control Data Input/Output Pin
(I2C pin = “L”)
CAD0
I
Chip Address Select Pin
(I2C pin = “H”)
CSN
I
Chip Select Pin
(I2C pin = “L”)
14
SDA
I/O
Control Data Input/Output Pin
(I2C pin = “H”)
15 DVDD
Digital Power Supply Pin
16 VSS2
Ground 2 Pin
17 NC
No Connection. No internal bonding. This pin must be connected to the ground.
18 MCKI
I
External Master Clock Input Pin
19 LRCK
I/O
Input/Output Channel Clock Pin
20 BICK
I/O
Audio Serial Data Clock Pin
21 SDTI
I
Audio Serial Data Input Pin
22 SDTO
O
Audio Serial Data Output Pin
23 MCKO
O
Master Clock Output Pin
24 NC
No Connection. No internal bonding. This pin must be connected to the ground.
25 VSS3
Ground 3 Pin
26 SVDD
Speaker Amp Power Supply Pin
27 SPP
O
Speaker Amp Positive Output Pin
28 SPN
O
Speaker Amp Negative Output Pin
29 LOUT
O
Lch Analog Output Pin
30 ROUT
O
Rch Analog Output Pin
31 MIN
I
Mono Analog Signal Input Pin
32 LIN2
I
Lch Analog Input 2 pin
Note 1. All input pins except analog input pins (MIN, LIN1, RIN1, LIN1, RIN2) must not allowed to float.
13
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■ Handling of Unused Pin
The unused I/O pins must be processed appropriately as below.
Classification
Pin Name
MPWR/DMP, VCOC, SPN, SPP, ROUT, LOUT,
Analog
MIN, RIN2, LIN2, LIN1/DMDAT, RIN1/DMCLK
MCKO
Digital
MCKI
Setting
These pins must be open.
These pins must be open.
This pin must be connected to VSS2.
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=0V; Note 2)
Parameter
Symbol
min
max
Unit
Power Supplies: Analog
AVDD
4.6
V
−0.3
Digital
DVDD
4.6
V
−0.3
Speaker-Amp
SVDD
4.6
V
−0.3
Input Current, Any Pin Except Supplies
IIN
mA
±10
Analog Input Voltage (Note 4)
VINA
AVDD+0.3
V
−0.3
Digital Input Voltage (Note 5)
VIND
DVDD+0.3
V
−0.3
Ambient Temperature (powered applied)
Ta
85
−40
°C
Storage Temperature
Tstg
150
−65
°C
Maximum Power Dissipation (Note 6)
Pd1
390
mW
Note 2. All voltages are with respect to ground.
Note 3. VSS1, VSS2 and VSS3 must be connected to the same analog ground plane.
Note 4. MIN, LIN1, RIN1, LIN2 and RIN2 pins
Note 5. PDN, CSN, CCLK, CDTIO, SDTI, LRCK, BICK and MCKI pins
Note 6. In case that PCB wiring density is 200% over and surface wiring density is 50% over. This power is the
AK4649VN internal dissipation that does not include power dissipation of an externally connected speaker.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=0V; Note 2)
Parameter
Symbol
min
typ
max
Unit
Power Supplies
Analog
AVDD
3.0
3.3
3.6
V
(Note 7) Digital
DVDD
3.0
3.3
3.6
V
SPK-Amp
SVDD
3.0
3.3
3.6
V
Difference
DVDD-AVDD
+0.6
V
+0.6
V
AVDD−SVDD
Note 2. All voltages are with respect to ground.
Note 7. The power-up sequence between AVDD, DVDD and SVDD is not critical. The PDN pin must be “L” upon power
up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error.
* When DVDD is powered ON and the PDN pin is “L”, AVDD or SVDD can be powered OFF.
However, when AVDD is powered OFF, the power supply current of DVDD at power-down
mode may be increased. When the AK4649VN is changed from power down state to power
ON, the PDN pin must be “H” after all power supplies are ON.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=SVDD=3.3V; VSS1=VSS2=VSS3=0V; fs=44.1kHz, BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
typ
max
Unit
MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins
Input Resistance
20
30
40
kΩ
MGAIN3-0 bits = “0000”
-1
0
+1
dB
Gain
+19
MGAIN3-0 bits = “0001”
+20
+21
dB
+25
MGAIN3-0 bits = “0010”
+26
+27
dB
MGAIN3-0 bits = “0100”
+8
+9
+10
dB
MGAIN3-0 bits = “0101”
+15
+16
+17
dB
MGAIN3-0 bits = “0110”
+22
+23
+24
dB
MGAIN3-0 bits = “0111”
+28
+29
+30
dB
MGAIN3-0 bits = “1000”
+2
+3
+4
dB
MGAIN3-0 bits = “1001”
+5
+6
+7
dB
MGAIN3-0 bits = “1010”
+11
+12
+13
dB
MIC Power Supply: MPWR pin
Output Voltage (Note 8)
2.38
2.64
2.90
V
Load Resistance
0.5
kΩ
Load Capacitance
30
pF
ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins → ADC → IVOL, IVOL=0dB, ALC=OFF
Resolution
24
Bits
(Note 10)
0.208
0.231
0.254
Vpp
Input Voltage (Note 9)
2.08
2.31
2.54
Vpp
(Note 11)
(Note 10)
70
80
dBFS
S/(N+D) (−1dBFS)
80
dBFS
(Note 11)
(Note 10)
79
89
dB
D-Range (−60dBFS, A-weighted)
100
dB
(Note 11)
(Note 10)
79
89
dB
S/N
(A-weighted)
100
dB
(Note 11)
(Note 10)
75
90
dB
Interchannel Isolation
100
dB
(Note 11)
(Note 10)
0
0.8
dB
Interchannel Gain Mismatch
0
0.8
dB
(Note 11)
Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ)
Note 9. Input voltage is proportional to AVDD voltage. Vin = 0.07 x AVDD (typ) @MGAIN3-0 bits = “0001” (+20dB),
Vin = 0.7 x AVDD (typ) @MGAIN3-0 bits = “0000” (0dB)
Note 10. MGAIN3-0 bits = “0001” (+20dB)
Note 11. MGAIN3-0 bits = “0000” (0dB)
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Parameter
min
typ
max
Unit
DAC Characteristics:
Resolution
24
Bits
Stereo Line Output Characteristics: DAC → LOUT, ROUT pins, ALC=OFF, DVOL=OVOL=DATT=0dB,
LOVL1-0 bit = “00”, RL=10kΩ
Output Voltage (Note 12)
LOVL1-0 bit = “00”
2.08
2.31
2.54
Vpp
LOVL1-0 bit = “01”
2.62
2.91
3.20
Vpp
S/(N+D)
77
87
dBFS
(−3dBFS)
S/N
(A-weighted)
87
97
dB
Interchannel Isolation
85
100
dB
Interchannel Gain Mismatch
0
0.8
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, DVOL=OVOL=DATT=0dB, RL=8Ω, BTL
Output Voltage (Note 13)
3.18
Vpp
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
3.20
4.00
4.80
Vpp
SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW)
1.79
Vrms
SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW)
S/(N+D)
60
dB
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
20
50
dB
SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW)
20
dB
SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW)
S/N (A-weighted)
88
98
dB
Load Resistance
8
Ω
Load Capacitance
30
pF
Note 12. Output voltage is proportional to AVDD voltage. Vout = 0.7 x AVDD (typ) @LOVL1-0 bit = “00”.
Note 13. Output voltage is proportional to AVDD voltage.
In case of Full-differential (DAC Input Level = 0dBFS), Vout = 1.02 x AVDD (typ) @SPKG1-0 bits = “00”,
1.28 x AVDD (typ) @SPKG1-0 bits = “01”, 1.62 x AVDD (typ ) @ SPKG1-0 bits = “10”.
The output level is calculated by assuming that output signal is no clipped. In the actual case, output signal may
be clipped when DAC outputs 0dBFS signal. Therefore, DAC output level should be set to lower level by setting
digital volume so that Speaker-Amp output level is not clipped.
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Parameter
min
typ
max
Unit
Mono Input: MIN pin, External Resistance mode (BPM bit = “0”), External Input Resistance=33kΩ
Maximum Input Voltage (Note 14)
2.31
Vpp
Gain (Note 15)
MIN Æ LOUT/ROUT LOVL1-0 bit = “00”
-4.5
0
+4.5
dB
LOVL1-0 bit = “01”
+2
dB
LOVL1-0 bit = “10”
+4
dB
LOVL1-0 bit = “11”
+6
dB
MIN Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
-1.2
+3.3
+7.8
dB
ALC bit = “0”, SPKG1-0 bits = “01”
+5.3
dB
ALC bit = “0”, SPKG1-0 bits = “10”
+7.3
dB
ALC bit = “0”, SPKG1-0 bits = “11”
+9.3
dB
ALC bit = “1”, SPKG1-0 bits = “00”
+5.3
dB
ALC bit = “1”, SPKG1-0 bits = “01”
+7.3
dB
ALC bit = “1”, SPKG1-0 bits = “10”
+9.3
dB
ALC bit = “1”, SPKG1-0 bits = “11”
+11.3
dB
Mono Input: MIN pin, Internal Resistance Mode (BPM bit = “1”)
Input Resistance
23
33
43
kΩ
Maximum Input Voltage (Note 16)
2.31
Vpp
Gain
MIN Æ LOUT/ROUT LOVL1-0 bit = “00”
-1
0
+1
dB
LOVL1-0 bit = “01”
+2
dB
LOVL1-0 bit = “10”
+4
dB
LOVL1-0 bit = “11”
+6
dB
MIN Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
+1.3
+3.3
+5.3
dB
ALC bit = “0”, SPKG1-0 bits = “01”
+5.3
dB
ALC bit = “0”, SPKG1-0 bits = “10”
+7.3
dB
ALC bit = “0”, SPKG1-0 bits = “11”
+9.3
dB
ALC bit = “1”, SPKG1-0 bits = “00”
+5.3
dB
ALC bit = “1”, SPKG1-0 bits = “01”
+7.3
dB
ALC bit = “1”, SPKG1-0 bits = “10”
+9.3
dB
ALC bit = “1”, SPKG1-0 bits = “11”
+11.3
dB
Note 14. The Maximum input voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.7 x
AVDD x Rin / 33kΩ (typ).
Note 15. The gain is in inverse proportion to external input resistance.
Note 16. The Maximum input voltage is in proportion to AVDD. Vin = 0.7 x AVDD (typ) @ BPLVL = 0dB.
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Parameter
min
typ
max
Unit
Power Supplies:
Power Up (PDN pin = “H”)
All Circuit Power-up (Note 17)
AVDD+DVDD
12.5
19
mA
SVDD (No Load)
4.0
12
mA
Power Down (PDN pin = “L”) (Note 18)
AVDD+DVDD+SVDD
1
5
μA
Note 17. When PLL Master Mode (MCKI=12MHz), and PMADL = PMADR = PMDAC =PMPFIL = PMLO = PMSPK
= PMVCM = PMPLL = MCKO = PMBP = PMMP = M/S bits = “1”. The MPWR pin outputs 0mA. AVDD =
6.8mA (typ), DVDD = 5.7mA (typ).
Note 18. All digital input pins are fixed to DVDD or VSS2.
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FILTER CHARACTERISTICS
(Ta =25°C; AVDD=SVDD=3.0 ∼ 3.6V, DVDD =3.0 ∼ 3.6V; fs=44.1kHz; DEM=OFF)
Parameter
Symbol
min
typ
max
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 19)
PB
0
17.3
kHz
±0.16dB
19.4
kHz
−0.66dB
19.9
kHz
−1.1dB
22.1
kHz
−6.9dB
Stopband
SB
26.1
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
73
dB
Group Delay (Note 20)
GD
19
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF): HPFC1-0 bits = “00”
Frequency Response
FR
3.4
Hz
−3.0dB
10
Hz
−0.5dB
22
Hz
−0.1dB
DAC Digital Filter (LPF):
Passband (Note 19)
PB
0
20.0
kHz
±0.05dB
22.05
kHz
−6.0dB
Stopband
SB
24.1
kHz
Passband Ripple
PR
dB
±0.02
Stopband Attenuation
SA
54
dB
Group Delay (Note 20)
GD
20
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±1.0
Note 19. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=20.0kHz (@−1.0dB) is 0.454 x fs (ADC). Each response refers to that of 1kHz
Note 20. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
24-bit data of both channels from the input register to the output register of the ADC. This time includes the
group delay of the HPF. For the DAC, this time is from setting the 24-bit data of both channels from the input
register to the output of analog signal.
For the signal through the programmable filters (First HPF + First LPF + 4-band Equalizer + ALC + Equalizer),
group delay is increased 5/fs at Recording Mode or 7/fs at Playback Mode from the value above if there is no
phase change by the IIR filter.
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[AK4649VN]
DC CHARACTERISTICS
(Ta = 25°C; AVDD=SVDD=3.0 ∼ 3.6V, DVDD =3.0 ∼ 3.6V; fs=44.1kHz)
Parameter
Symbol
min
typ
max
Unit
Audio Interface & Serial µP Interface
(CDTIO/CAD0, CSN/SDA, CCLK/SCL, I2C, PDN, BICK, LRCK, SDTI, MCKI pins )
High-Level Input Voltage
VIH
70%DVDD
V
Low-Level Input Voltage
VIL
30%DVDD
V
Audio Interface & Serial µP Interface (CDTIO, SDA MCKO, BICK, LRCK, SDTO pins Output)
V
DVDD−0.2
VOH
High-Level Output Voltage
(Iout = −80μA)
Low-Level Output Voltage
V
0.2
(Except SDA pin : Iout = 80μA) VOL1
V
0.4
(SDA pin : Iout = 3mA) VOL2
Input Leakage Current
Iin
±10
μA
Digital MIC Interface (DMDAT pin Input ; DMIC bit = “1”)
High-Level Input Voltage
VIH3
65%AVDD
V
Low-Level Input Voltage
VIL3
35%AVDD
V
Digital MIC Interface (DMCLK pin Output ; DMIC bit = “1”)
High-Level Output Voltage
(Iout=−80μA)
VOH3
AVDD-0.4
V
Low-Level Output Voltage
(Iout= 80μA)
VOL3
0.4
V
Input Leakage Current
Iin
±10
μA
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[AK4649VN]
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD=SVDD=3.0 ∼ 3.6V, DVDD =3.0 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
256fs at fs=32kHz, 29.4kHz
dMCK
LRCK Output Timing
Frequency
fs
7.35
Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
256fs at fs=32kHz, 29.4kHz
dMCK
LRCK Input Timing
Frequency
fs
7.35
Duty
Duty
45
BICK Input Timing
Period
tBCK
1/(64fs)
Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
MS1506-E-00
typ
max
Unit
-
27
-
MHz
ns
ns
-
12.288
MHz
50
33
60
-
%
%
50
48
-
kHz
%
1/(32fs)
1/(64fs)
50
-
ns
ns
%
-
27
-
MHz
ns
ns
-
12.288
MHz
50
33
60
-
%
%
-
48
55
kHz
%
-
1/(32fs)
-
ns
ns
ns
2013/01
- 12 -
[AK4649VN]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
Duty
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
Duty
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs
fs
512fs
fs
1024fs
fs
Duty
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS1506-E-00
min
typ
max
Unit
7.35
45
-
48
55
kHz
%
1/(64fs)
240
240
-
1/(32fs)
-
ns
ns
ns
7.35
45
-
48
55
kHz
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
45
-
48
26
13
55
kHz
kHz
kHz
%
312.5
130
130
-
-
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
-
50
48
-
kHz
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2013/01
- 13 -
[AK4649VN]
Parameter
Symbol
min
Audio Interface Timing
Master Mode
tMBLR
−40
BICK “↓” to LRCK Edge (Note 21)
tLRD
LRCK Edge to SDTO (MSB)
−70
(Except I2S mode)
tBSD
BICK “↓” to SDTO
−70
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Slave Mode
tLRB
50
LRCK Edge to BICK “↑” (Note 21)
tBLR
50
BICK “↑” to LRCK Edge (Note 21)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Control Interface Timing (3-wire Mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTIO Setup Time
tCDS
40
CDTIO Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN Edge to CCLK “↑” (Note 22)
tCSH
50
CCLK “↑” to CSN Edge (Note 22)
tDCD
CCLK “↓” to CDTIO (at Read Command)
tCCZ
CSN “↑” to CDTIO (Hi-Z) (at Read Command)(Note 24)
Control Interface Timing (I2C Bus Mode):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 25)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive Load on Bus
Cb
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Note 21. BICK rising edge must not occur at the same time as LRCK edge.
Note 22. CCLK rising edge must not occur at the same time as CSN edge.
Note 23. I2C-bus is a trademark of NXP B.V.
Note 24. RL=1kΩ/10% change (pull-up or DVDD)
Note 25. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS1506-E-00
typ
max
Unit
-
40
70
ns
ns
-
70
-
ns
ns
ns
-
80
ns
ns
ns
-
80
-
ns
ns
ns
-
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
2013/01
- 14 -
[AK4649VN]
Parameter
Symbol
min
Digital Audio Interface Timing; CL=100pF
DMCLK Output Timing
Period
tSCK
Rising Time
tSRise
Falling Time
tSFall
Duty Cycle
dSCK
40
Audio Interface Timing
DMDAT Setup Time
tSDS
50
DMDAT Hold Time
tSDH
0
Power-down & Reset Timing
PDN Pulse Width
(Note 26)
tPD
150
PMADL or PMADR “↑” to SDTO valid (Note 27)
ADRST bit = “0”
tPDV
ADRST bit = “1”
tPDV
Note 26. The AK4649VN can be reset by the PDN pin = “L”.
Note 27. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
typ
max
Unit
1/(64fs)
50
10
10
60
ns
ns
ns
%
-
-
ns
ns
-
-
ns
1059
267
-
1/fs
1/fs
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
1/fMCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Note 28. MCKO is not available at EXT Master mode.
Figure 2. Clock Timing (PLL/EXT Master mode)
MS1506-E-00
2013/01
- 15 -
[AK4649VN]
50%DVDD
LRCK
tBLR
tBCKL
BICK
50%DVDD
tDLR
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 3. Audio Interface Timing (PLL/EXT Master mode)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 4. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin)
MS1506-E-00
2013/01
- 16 -
[AK4649VN]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tLRCKL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 5. Clock Timing (EXT Slave mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
tLRD
SDTO
MSB
50%DVDD
tSDH
tSDS
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Slave mode)
MS1506-E-00
2013/01
- 17 -
[AK4649VN]
VIH
CSN
VIL
tCSH
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
CDTIO
A6
A5
R/W
VIH
VIL
Figure 7. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
CDTIO
VIL
D2
D1
VIH
D0
VIL
Figure 8. WRITE Data Input Timing
VIH
CSN
VIL
CCLK
Clock, H or L
D3
VIL
tCCZ
tDCD
CDTIO
VIH
D2
D1
D0
Hi-Z
50%
DVDD
Figure 9. Read Data Output Timing
MS1506-E-00
2013/01
- 18 -
[AK4649VN]
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Start
Stop
Figure 10. I2C Bus Mode Timing
tSCK
65%AVDD
DMCLK
50%AVDD
35%AVDD
tSCKL
tSRise
tSFall
dSCK = 100 x tSCKL / tSCK
Figure 11. DMCLK Clock Timing
65%AVDD
DMCLK
35%AVDD
tSDS
tSDH
VIH3
DMDAT
VIL3
Figure 30. Audio Interface Timing (DCLKP bit = “1”)
65%AVDD
DMCLK
35%AVDD
tSDS
tSDH
VIH3
DMDAT
VIL3
Figure 31. Audio Interface Timing (DCLKP bit = “0”)
MS1506-E-00
2013/01
- 19 -
[AK4649VN]
PMADL bit
or
PMADR bit
tPDV
SDTO
50%DVDD
Figure 12. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 13. Power Down & Reset Timing 2
MS1506-E-00
2013/01
- 20 -
[AK4649VN]
OPERATION OVERVIEW
■ System Clock
There are the following five clock modes to interface with external devices (Table 1, Table 2).
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 29)
1
1
Table 4
Figure 14
PLL Slave Mode 1
Table 4
Figure 15
1
0
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
Figure 16
Table 4
(PLL Reference Clock: LRCK or BICK
1
0
Figure 17
pin)
EXT Slave Mode
0
0
x
Figure 18
EXT Master Mode
0
1
x
Figure 19
Note 29. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from the MCKO pin.
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
L
Selected by
PS1-0 bits
L
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL3-0 bits
Selected by
PLL3-0 bits
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK
pin)
0
L
GND
EXT Slave Mode
0
L
Selected by
PLL3-0 bits
EXT Master Mode
0
L
Selected by
PLL3-0 bits
Note 30. When PMVCM bit = M/S bit = “1” and MCKI is input, LRCK and BICK are
PMADL bit = PMADR bit = “0”.
Table 2. Clock pins state in Clock Mode
BICK pin
LRCK pin
Output
Output
(Selected by
(1fs)
BCKO bit)
Input
Input
(Selected by
(1fs)
BCKO bit)
Input
Input
(Selected by
(1fs)
BCKO bit)
Input
Input
(1fs)
(≥ 32fs)
Output
Output
(Selected by
(1fs)
BCKO bit)
output, even if PMDAC bit =
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4649VN is power-down mode (PDN pin = “L”) and exits reset state, the AK4649VN is in slave mode. After exiting
reset state, the AK4649VN goes to master mode by changing M/S bit = “1”.
When the AK4649VN is in master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The
LRCK and BICK pins of the AK4649VN must be pulled-down or pulled-up by the resistor (about 100kΩ) externally to
avoid the floating state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Slave Mode
MS1506-E-00
(default)
2013/01
- 21 -
[AK4649VN]
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, when the AK4649VN is supplied stable clocks after PLL
is powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency is changed.
1) PLL Mode Setting
R and C of
PLL
PLL Lock
Input
VCOC pin
Reference
Mode
Time
Frequency
Clock Input
R[Ω] C[F]
(max)
Pin
0
0
0
0
0
LRCK pin
1fs
6.8k
220n
160ms
1
0
0
0
1
N/A
2
0
0
1
0
BICK pin
32fs
10k
4.7n
2ms
3
0
0
1
1
BICK pin
64fs
10k
4.7n
2ms
4
0
1
0
0
MCKI pin
11.2896MHz
10k
4.7n
10ms
6
0
1
1
0
MCKI pin
12MHz
10k
4.7n
10ms
7
0
1
1
1
MCKI pin
24MHz
10k
4.7n
10ms
12
1
1
0
0
MCKI pin
13.5MHz
10k
10n
10ms
13
1
1
0
1
MCKI pin
27MHz
10k
10n
10ms
Others
Others
N/A
Note 31. R has a tolerance of ± 5%, and C has a tolerance of ± 30%.
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not Available)
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
(default)
2) Setting of sampling frequency in PLL Mode
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (Reference Clock = MCKI pin),
(N/A: Not Available)
When PLL2 bit is “0” (PLL reference clock input is LRCK or BICK pin), the sampling frequency is selected by FS3 and
FS2 bits. (Table 6).
Sampling Frequency
Range
0
0
x
0
x
(default)
7.35kHz ≤ fs ≤ 12kHz
0
1
x
1
x
12kHz < fs ≤ 24kHz
1
0
x
2
x
24kHz < fs ≤ 48kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin), (x: Don’t care, N/A: Not Available)
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
MS1506-E-00
2013/01
- 22 -
[AK4649VN]
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pin at MCKO
bit is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin goes to “L”
(Table 7).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
BICK pin
LRCK pin
MCKO bit = “0” MCKO bit = “1”
After PMPLL bit “0” → “1”
“L” Output
Invalid
“L” Output
“L” Output
PLL Unlock (except the case above)
“L” Output
Invalid
Invalid
Invalid
PLL Lock
“L” Output
Table 9
Table 10
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” →
“1”. Then, the clock selected by Table 9 is output from the MCKO pin when PLL is locked. ADC and DAC output invalid
data when the PLL is unlocked. For DAC, the output signal can be muted by writing “0” to DACL and DACS bits.
MCKO pin
MCKO bit = “0”
MCKO bit = “1”
After PMPLL bit “0” → “1”
“L” Output
Invalid
PLL Unlock (except the case above)
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
MS1506-E-00
2013/01
- 23 -
[AK4649VN]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, MCKO, BICK
and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (Table
9) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit
(Table 10).
11.2896MHz,12MHz, 13.5MHz,
24MHz, 27MHz
AK4649
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 14. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BCKO bit
BICK Output Frequency
0
32fs
(default)
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS1506-E-00
2013/01
- 24 -
[AK4649VN]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock for the
AK4649VN is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 4).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs must be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (Table 5)
11.2896MHz, 12MHz, 13.5MHz,
24MHz, 27MHz
AK4649
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 15. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS1506-E-00
2013/01
- 25 -
[AK4649VN]
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (Table 6).
AK4649
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 16. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4649
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 17 PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
The external clocks (MCKI, BICK and LRCK) must always be present whenever the ADC, DAC or Programmable Filter
is in operation (PMADL bit = “1”, PMADR bit = “1” PMDAC, or PMPFIL bit = “1”). If these clocks are not provided, the
AK4649VN may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If the external clocks are not present, the ADC, DAC and Programmable Filter should be in the power-down
mode (PMADL=PMADR=PMDAC =PMPFIL bits = “0”).
MS1506-E-00
2013/01
- 26 -
[AK4649VN]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4649VN becomes EXT mode. Master clock can directly be inputted from the MCKI pin,
without the internal PLL circuit operation. This mode is compatible with I/F of the normal audio CODEC. The clocks
required to operate this mode are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock
(MCKI) must be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of
MCKI is selected by FS1-0 bits (Table 11).
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
7.35kHz ∼ 48kHz
1
x
0
1
1024fs
7.35kHz ∼ 13kHz
2
x
1
0
512fs
7.35kHz ∼ 26kHz
3
x
1
1
256fs
7.35kHz ∼ 48kHz
Others
Others
N/A
N/A
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
(x: Don’t care, N/A: Not Available)
Mode
FS3-2 bits
FS1 bit
FS0 bit
(default)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 12.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
95dB
1024fs
96dB
Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
The external clocks (MCKI, BICK and LRCK) must always be present whenever the ADC, DAC or Programmable Filter
is in operation (PMADL bit = “1”, PMADR bit = “1”, PMDAC bit = “1” or PMPFIL bit = “1”). If these clocks are not
provided, the AK4649VN may draw excess current and it is not possible to operate properly because utilizes dynamic
refreshed logic internally. When the external clocks are not present, the ADC and DAC should be in the power-down
mode (PMADL=PMADR=PMDAC = PMPFIL bits = “0”).
AK4649
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCLK
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 18. EXT Slave Mode
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[AK4649VN]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4649VN becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from
the MCKI pin, the internal PLL circuit is not operated. The clock required to operate the AK4649VN is MCKI (256fs,
512fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits (Table 13).
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
(default)
7.35kHz ∼ 48kHz
1
x
0
1
1024fs
7.35kHz ∼ 13kHz
2
x
1
0
512fs
7.35kHz ∼ 26kHz
3
x
1
1
256fs
7.35kHz ∼ 48kHz
Table 13. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (x: Don’t care)
Mode
FS3-2 bits
FS1 bit
FS0 bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 14.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
95dB
1024fs
96dB
Table 14. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
MCKI must always be present whenever the ADC, DAC or Programmable Filter is in operation (PMADL bit = “1”,
PMADR bit = “1”, PMDAC bit = “1” or PMPFIL bit = “1”). If MCKI is not provided, the AK4649VN may draw excess
current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not
present, the ADC, DAC and Programmable Filter should be in the power-down mode (PMADL=PMADR=PMDAC=
PMPFIL bits = “0”).
AK4649
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 19. EXT Master Mode
BCKO bit
BICK Output Frequency
0
32fs
(default)
1
64fs
Table 15. BICK Output Frequency at Master Mode
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[AK4649VN]
■ System Reset
Upon power-up, the AK4649VN must be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial value. The PDN pin recommends inputting “L” at power-up.
The ADC enters an initialization cycle when the PMADL or PMADR bit is changed from “0” to “1”. The initialization
cycle time is set by ADRST bit (Table 16). During the initialization cycle, the ADC digital data outputs of both channels
are forced to a 2's complement, “0”. The ADC output reflects the analog input signal after the initialization cycle is
complete. When using a digital microphone, the initialization cycle is the same as ADC’s.
(Note) The initial data of ADC has offset data that depends on the condition of the microphone and the cut-off frequency
of HPF. If this offset is not small, make initialization cycle longer by setting ADRST bit = “0” or do not use the
initial data of ADC.
Initialization Cycle
Cycle
fs = 8kHz
fs = 16kHz
1059/fs
132.4ms
66.2ms
267/fs
33.4ms
16.7ms
Table 16. ADC Initialization Cycle
ADRST bit
0
1
fs = 44.1kHz
24ms
6.1ms
■ Audio Interface Format
Four types of data formats are available and selected by setting the DIF1-0 bits (Table 17). In all modes, the serial data is
MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK
are output from the AK4649VN in master mode, but must be input to the AK4649VN in slave mode. The SDTO is
clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”).
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO (ADC)
24bit MSB justified
24bit MSB justified
24bit MSB justified
2
I S Compatible
SDTI (DAC)
24bit LSB justified
16bit LSB justified
24bit MSB justified
2
I S Compatible
BICK
≥ 48fs
≥ 32fs
≥ 48fs
=32fs or
≥ 48fs
Figure
Figure 20
Figure 21
Figure 22
(default)
Figure 23
Table 17. Audio Interface Format
If 24-bit(16-bit) data that ADC outputs is converted to 8-bit data by removing LSB 16-bit(8-bit), “−1” at 24-bit(16-bit)
data is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted
to “−65536” at 24-bit (“−256” at 16-bit) data which is a large offset. This offset can be removed by adding the offset of
“32768” at 24-bit(“128” at 16-bit) to 24-bit(16-bit) data before converting to 8-bit data.
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[AK4649VN]
LRCK
0
1
2
8
9
10
20
21
31
0
1
2
8
9
10
20
21
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
16 15 14
Don’t Care
0
23 22
23:MSB, 0:LSB
23 22
12 11
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
12 11
1
0
Rch Data
Figure 20. Mode 0 Timing
LRCK
0
1
2
3
7
8
9
10
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
23 22 21
15 14 13 12 11 10
9
8
23 22 21
15 14 13 12 11 10
9
8
23
SDTI(i)
15 14 13
7
1
0
15 14 13
7
1
0
15
0
1
2
3
15
6
16
5
17
4
18
3
23
2
24
31
30
0
1
2
3
15
6
16
5
17
4
18
3
23
2
24
25
31
30
1
BICK(64fs)
SDTO(o)
23 22 21
SDTI(i)
Don’t Care
8
7
6
5
15
14 13 8
23 22 21
0
2
1
0
8
Don’t Care
7
6
5
15
14 13 8
23
0
2
1
0
24bit: 23:MSB, 0:LSB
16bit: 15: MSB, 0:LSB
Lch Data
Rch Data
Figure 21. Mode 1 Timing
LRCK
0
1
2
18
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
24
25
0
1
BCLK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
23
Rch Data
Figure 22. Mode 2 Timing
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[AK4649VN]
LRCK
0
1
2
3
7
8
9
10
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
8
23 22
16 15 14 13 12 11
10 9
8
23 22
16 15 14 13 12 11
10 9
8
SDTI(i)
8
23 22
16 15 14 13 12 11
10 9
8
23 22
16 15 14 13 12 11
10 9
8
0
1
2
3
19
20
21
22
23
24
25
0
1
2
3
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 23. Mode 3 Timing
■ Mono/Stereo Mode
PMADL, PMADR, PMDML and PMDMR bits set mono/stereo ADC operation. When changing ADC operation and
analog/digital microphone, PMADL, PMADR, PMDML and PMDMR bits must be set “0” at first. When PMDML or
PMDMR bit is “1”, PMADL and PMADR bits setting are ignored.
PMADL bit
0
0
1
1
PMADR bit
ADC Lch data
ADC Rch data
0
All “0”
All “0”
1
Rch Input Signal
Rch Input Signal
0
Lch Input Signal
Lch Input Signal
1
Lch Input Signal
Rch Input Signal
Table 18. Mono/Stereo ADC operation (Analog MIC)
PMDML bit
0
0
1
1
PMDMR bit
ADC Lch data
ADC Rch data
0
All “0”
All “0”
1
Rch Input Signal
Rch Input Signal
0
Lch Input Signal
Lch Input Signal
1
Lch Input Signal
Rch Input Signal
Table 19. Mono/Stereo ADC operation (Digital MIC)
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(default)
(default)
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[AK4649VN]
■ MIC/LINE Input Selector
The AK4649VN has an input selector. INL and INR bits select LIN1/LIN2 and RIN1/RIN2, respectively. When DMIC
bit = “1”, digital microphone input is selected regardless of INL and INR bits.
DMIC bit
0
1
INL bit
0
0
1
1
0
0
1
1
INR bit
Lch
Rch
0
LIN1
RIN1
1
LIN1
RIN2
0
LIN2
RIN1
1
LIN2
RIN2
0
1
Digital MIC
0
1
Table 20. MIC/Line In Path Select
(default)
■ MIC Gain Amplifier
The AK4649VN has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN3-0 bits
(Table 21). The typical input impedance is 30kΩ (typ).
MGAIN3 bit
0
0
0
0
0
0
0
0
1
1
1
MGAIN2 bit
MGAIN1 bit
MGAIN0 bit
Input Gain
0
0
0
0dB
0
0
1
+20dB
0
1
0
+26dB
0
1
1
N/A
1
0
0
+9dB
1
0
1
+16dB
1
1
0
+23dB
1
1
1
+29dB
0
0
0
+3dB
0
0
1
+6dB
0
1
0
+12dB
Others
N/A
Table 21. Input Gain (N/A: Not available)
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[AK4649VN]
■ MIC Power
When PMMP bit = “1”and MPDMP bit = “0”, the MPWR pin supplies power for the microphone. This output voltage is
typically 0.8 x AVDD and the load resistance is minimum 0.5kΩ. In case of using two sets of stereo microphone, the load
resistance is minimum 2kΩ for each channel. Any capacitor must not be connected directly to the MPWR pin (Figure 24).
PMMP bit
MPWR pin
0
Hi-Z
(default)
1
Output
Table 22. MIC Power (MPDMP bit = “0”)
MIC Power
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
Microphone
RIN2 pin
Figure 24. MIC Block Circuit
■ Digital MIC
1. Connection to Digital MIC
The AK4649VN can be connected to digital microphone by setting DMIC bit = “1”. When DMIC bit is set to “1”, the
LIN1 and RIN1 pins become DMDAT (digital microphone data input) and DMCLK (digital microphone clock supply)
pins respectively. By setting MPDMP bit = “1”, the MPWR pin becomes DMP (digital microphone power supply) pin
and can supply the power to the digital microphone (max. 4mA). When DMPE bit = “0”, the same power supply as
AVDD must be provided to the digital microphone. The Figure 25 and Figure 26 show mono/stereo connection examples.
The DMCLK signal is output from the AK4649VN, and the digital microphone outputs 1bit data, which generated by
ΔΣModulator, from DMDAT. PMDML/R bits control power up/down of the digital block (Decimation Filter and Digital
Filter). PMADL/PMADR bits settings do not affect the digital microphone power management. The DCLKE bit controls
ON/OFF of the output clock from the DMCLK pin. When the AK4649VN is powered down (PDN pin= “L”), the
DMCLK and DMDAT pin are floating state. Pull-down resistors must be connected to the DMCLK and DMDAT pin
externally to avoid floating state.
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[AK4649VN]
AK4649
AVDD
DMP
MPDMP = DMPE = “1”
VDD
DMCLK(64fs)
AMP
MCKI
PLL
100kΩ
ΔΣ
Modulator
Decimation
Filter
DMDAT
Lch
HPF1
Programmable
Filter
SDTO
ALC
R
VDD
AMP
ΔΣ
Modulator
Rch
Figure 25. Connection Example of Stereo Digital MIC (MPDMP = DMPE bits = “1”)
AVDD
AK4649
DMP
MPDMP = DMPE = “1”
VDD
DMCLK(64fs)
AMP
ΔΣ
PLL
MCKI
100kΩ
Modulator
DMDAT
Decimation
Filter
HPF1
Programmable
Filter
ALC
SDTO
R
Figure 26. Connection Example of Mono Digital MIC (MPDMP = DMPE bits = “1”)
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[AK4649VN]
2. Interface
The input data channel of the DMDAT pin is set by DCLKP bit. When DCLKP bit = “1, Lch data is input to the
Decimation Filter if DMCLK = “H”, Rch data is input if DMCLK = “L”. When DCLKP bit = “0”, Rch data is input to the
Decimation Filter if DMCLK = “H”, Lch data is input if DMCLK = “L”. The DMCLK pin outputs “L” when DCLKE bit
= “0”, and only supports 64fs. In this case, necessary clocks must be supplied to the AK4649VN for ADC operation. The
output data through “the Decimation and Digital Filters” is 24bit full scale when the 1bit data density is 0%~100%.
DCLKP bit
DMCLK = “H”
DMCLK = “L”
0
Rch
Lch
(default)
1
Lch
Rch
Figure 27. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)
DMCLK(64fs)
DMDAT (Lch)
Valid
Data
Valid
Data
Valid
Data
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 28. Data In/Output Timing with Digital MIC (DCLKP bit = “1”)
DMCLK(64fs)
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 29. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)
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[AK4649VN]
■ Digital Block
The digital block consists of the blocks shown in Figure 30. Recording path and playback path is selected by setting
ADCPF bit, PFDAC bit and PFSDO bit. (Figure 31 ~ Figure 34, Table 23)
PMADL/R bit
SDTI
ADC
1st Order
HPFAD bit
HPF1
ADCPF bit
“1”
“0”
PMPFIL bit
HPF bit
LPF bit
1st Order
HPF2
1st Order
LPF
FIL3 bit
Stereo
Separation
EQ0 bit
GN1-0 bits
Gain
Compensation
4 Band
EQ5-2 bit
EQ
ALC1/2 bits
ALC
(Volume)
1 Band
EQ1 bit
“0”
EQ
“1”
“1”
PFSDO bit
“0”
PFDAC bit
PMDAC bit
DATT
SDTO
SMUTE
DAC
(1)
(2)
(3)
(4)
ADC: Include the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”.
HPF1: Include the Digital Filter (HPF) for ADC as shown in “FILTER CHRACTERISTICS”.
DAC: Include the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”.
HPF2: High Pass Filter. Applicable for use as Wind-Noise Reduction Filter. (See “Digital Programmable Filter
Circuit”)
(5) LPF: Low Pass Filter (See “Digital Programmable Filter Circuit”)
(6) Stereo Separation: Digital Separation Emphasis Filter (See “Digital Programmable Filter Circuit”)
(7) Gain Compensation: Composed of the Equalizer (EQ0) and the Gain (0dB/+12dB/+24dB). Compensate the
frequency response and the gain after the Stereo Separation Emphasis Filter.
(8) 4 Band EQ: Applicable for use as Equalizer or Notch Filter. (See “Digital Programmable Filter Circuit”)
(9) Volume: Input Digital Volume with ALC function. (See “Input Digital Volume” and “ALC Operation”)
(10) 1 Band EQ: Applicable for use as Equalizer or Notch Filter. (See “Digital Programmable Filter Circuit”)
(11) DATT: Digital volume for playback path (See “Output Digital Volume2” )
(12) SMUTE: Digital volume with soft mute function (See “Output Digital Volume3”)
Figure 30. Digital Block Path Select
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[AK4649VN]
ADCPF bit
PFDAC bit
Mode
Recording Mode 1
1
0
Playback Mode 1
0
1
Recording Mode 2 & Playback Mode 2
x
0
(Programmable Filter Bypass Mode: PMPFIL bit = “0”)
Loopback Mode
1
1
Table 23. Recording Playback Mode (x: Don’t care)
1
0
Figure
Figure 31
Figure 32
0
Figure 33
1
Figure 34
PFSDO bit
LPF bit, HPF bit, FIL3 bit, EQ0 bit, EQ1 bit, EQ2 bit, EQ3 bit, EQ4 bit, EQ5 bit, ACL1 bit and ALC2 bit must be “0”
when changing those modes.
ADC
DAC
1st Order
1st Order
1st Order
HPF1
HPF2
LPF
SMUTE
Stereo
Separation
Gain
Compensation
4 Band
EQ
ALC
(Volume)
1 Band
EQ
DATT
Figure 31. Path at Recording Mode 1 (default)
ADC
DAC
1st Order
HPF1
SMUTE
DATT
1 Band
4 Band
ALC
EQ
EQ
(Volume)
Gain
Compensation
Stereo
Separation
1st Order
1st Order
LPF
HPF2
Figure 32. Path at Playback Mode 1
ADC
DAC
1st Order
HPF1
SMUTE
DATT
Figure 33. Path at Recording Mode 2 & Playback Mode 2
ADC
DAC
1st Order
1st Order
1st Order
HPF1
HPF2
LPF
SMUTE
Stereo
Separation
Gain
Compensation
4 Band
EQ
ALC
(Volume)
1 Band
EQ
DATT
Figure 34. Path at Loopback Mode
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[AK4649VN]
■ Digital Programmable Filter Circuit
(1) High Pass Filter (HPF2)
Normally, this HPF is used for Wind-Noise Reduction. This is composed 1st order HPF. The coefficient of HPF is set by
F1A13-0 bits and F1B13-0 bits. HPF bit controls ON/OFF of the HPF2. When the HPF2 is OFF, the audio data passes
this block by 0dB gain. The coefficient must be set when HPF bit = “0” or PMPFIL bit = “0”. The HPF2 starts operation
4/fs(max) after when HPF bit=PMPFIL bit= “1” is set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 32)
HPF: F1A[13:0] bits =A, F1B[13:0] bits =B
(MSB=F1A13, F1B13; LSB=F1A0, F1B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
The cut-off frequency must be set as below.
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
(2) Low Pass Filter (LPF)
This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF
of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when LPF bit
= “0” or PMPFIL bit = “0”. The LPF starts operation 4/fs(max) after when LPF bit =PMPFIL bit= “1” is set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 32)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F1B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency must be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
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[AK4649VN]
(3) Stereo Separation Emphasis Filter (FIL3)
FIL3 is used to emphasize the stereo separation of a stereo microphone recording data or playback data. F3A13-0 and
F3B13-0 bits set the filter coefficient of FIL3. FIL3 becomes High Pass Filter (HPF) at F3AS bit = “0”, and Low Pass
Filter (LPF) at F3AS bit = “1”. FIL3 bit controls ON/OFF of the FIL3. When Stereo Separation Emphasis Filter is OFF,
the audio data passes this block by 0dB gain. The coefficient, must be set when FIL3 bit = “0” or PMPFIL bit = “0”. The
FIL3 starts operation 4/fs(max) after when FIL3 bit= PMPFIL bit= “1” is set.
1) When FIL3 is set to “HPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 32)
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB=F3A0, F3B0)
A = 10K/20 x
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
2) When FIL3 is set to “LPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 32)
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB= F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
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(4) Gain Compensation
Gain Compensation is used to compensate the frequency response and the gain that is changed by Stereo Separation
Emphasis Filter. Gain Compensation is composed of the Equalizer (EQ0) and the Gain (0dB/+12dB/+24dB).
E0A15-0, E0B13-0 and E0C15-0 bits set the coefficient of EQ0. GN1-0 bits set the gain (Table 24). EQ0 bit controls
ON/OFF of EQ0. When EQ is OFF and the gain is 0dB, the audio data passes this block by 0dB gain. The coefficient
must be set when EQ0 bit = “0” or PMPFIL bit = “0”. EQ0 starts operation 4/fs(max) after when EQ0=PMPFIL bits =
“1” is set.
fs: Sampling frequency
fc1: Pole frequency
fc2: Zero-point frequency
K: Filter gain [dB] (Maximum +12dB)
Register setting (Note 32)
E0A[15:0] bits =A, E0B[13:0] bits =B, E0C[15:0] bits =C
(MSB=E0A15, E0B13, E0C15; LSB=E0A0, E0B0, E0C0)
A = 10K/20 x
1 + 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
,
B=
1 − 1 / tan (πfc1/fs)
,
C =10K/20 x
1 + 1 / tan (πfc1/fs)
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
Transfer function
A + Cz −1
H(z) =
1 + Bz −1
Gain[dB]
K
fc1
fc2
Frequency
Figure 35. EQ0 Frequency Response
GN1 bit
GN0 bit
Gain
0
0
0dB
(default)
0
1
+12dB
1
x
+24dB
Table 24. Gain select of gain block (x: Don’t care)
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(5) 4-band Equalizer & 1-band Equalizer after ALC
This block can be used as Equalizer or Notch Filter. 4-band Equalizer (EQ2, EQ3, EQ4 and EQ5) is selected ON/OFF
independently by EQ2, EQ3, EQ4 and EQ5 bits. The equalizer after ALC (EQ1) is controlled by EQ1 bit. When Equalizer
is OFF, the audio data passes this block by 0dB gain. E1A15-0, E1B15-0 and E1C15-0 bits set the coefficient of EQ1.
E2A15-0, E2B15-0 and E2C15-0 bits set the coefficient of EQ2. E3A15-0, E3B15-0 and E3C15-0 bits set the coefficient
of EQ3. E4A15-0, E4B15-0 and E4C15-0 bits set the coefficient of EQ4. E5A15-0, E5B15-0 and E5C15-0 bits set the
coefficient of EQ5. The EQx (x=1∼5) coefficient must be set when EQx bit = “0” or PMPFIL bit = “0”. EQ1-5 start
operation 4/fs(max) after when EQx (X=1~5) = PMPFIL bit = “1”is set.
fs: Sampling frequency
fo1 ~ fo5: Center frequency
fb1 ~ fb5: Band width where the gain is 3dB different from center frequency
K1 ~ K5: Gain (−1 ≤ Kn ≤ 3)
Register setting (Note 32)
EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3
EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4
EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15,
E5A15, E5B15, E5C15 ; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0,
E4C0, E5A0, E5B0, E5C0)
An = Kn x
tan (πfbn/fs)
2
, Bn = cos(2π fon/fs) x
1 + tan (πfbn/fs)
1 + tan (πfbn/fs)
,
Cn =
1 − tan (πfbn/fs)
1 + tan (πfbn/fs)
(n = 1, 2, 3, 4, 5)
Transfer function
H(z) = {1 + h2(z) + h3(z) + h4(z) + h5(z) } x {1+ h1(z)}
1 − z −2
hn (z) = An
1− Bnz −1− Cnz −2
(n = 1, 2, 3, 4, 5)
The center frequency must be set as below.
fon / fs < 0.497
When gain of K is set to “-1”, this equalizer becomes a notch filter. When EQ2 ∼EQ5 is used as a notch filter, central
frequency of a real notch filter deviates from the above-mentioned calculation, if its central frequency of each band is near.
The control soft that is attached to the evaluation board has functions that revises a gap of frequency and calculates the
coefficient. When its central frequency of each band is near, the central frequency should be revised and confirm the
frequency response.
Note 32. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s
complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X must be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sine bit.
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■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. When ADCPF bit is “1”, ALC
circuit operates at recording path. When ADCPF bit is “0”, ALC circuit operates at playback path. ALC1 bit controls
ON/OFF of ALC operation at recording path, and ALC2 bit controls of ON/OFF of ALC operation at playback path.
Note 33. In this section, VOL means IVL and IVR for recording path, OVL and OVR for playback path.
Note 34. In this section, ALC bit means ALC1 bit for recording path, ALC2 bit for playback path.
Note 35. In this section, REF means IREF for recording path, OREF for playback path.
1.
ALC Limiter Operation
During ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 25), the VOL value
(same value for both L and R) is attenuated automatically by the amount defined by the ALC limiter ATT step (Table 26).
The VOL is then set to the same value for both channels.
When ZELMN bit = “0” (zero cross detection is enabled), the VOL value is changed by ALC limiter operation at the
individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout
period of both ALC limiter and recovery operation (Table 27). When ALC output level exceeds full-scale at LFST bit =
“1”, VOL values are immediately (Period: 1/fs) changed in 1step(L/R common). When ALC output level is less than
full-scale, VOL values are changed at the individual zero crossing point of each channels or at the zero crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), VOL value is immediately (period: 1/fs) changed by ALC
limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is executed continuously until the input signal level becomes ALC limiter detection level (Table
25) or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the
input signal level exceeds LMTH1-0 bits.
LMTH1 bit LMTH0 bit ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level
0
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
0
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
1
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 25. ALC Limiter Detection Level / Recovery Counter Reset Level
(default)
ALC1 Limiter ATT Step
LMAT1 bit LMAT0 bit ALC1 Output ALC1 Output
≥ LMTH
≥ FS
0
0
1
1
0
1
0
1
ALC1 Output
≥ FS + 6dB
1
1
2
2
2
4
1
2
Table 26. ALC Limiter ATT Step
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1
2
4
4
ALC1 Output
≥ FS + 12dB
1
2
8
8
(default)
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2.
ZTM1 bit
ZTM0 bit
0
0
1
1
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 27. ALC Zero Crossing Timeout Period
(default)
ALC Recovery Operation
ALC recovery operation wait for the WTM2-0 bits (Table 28) to be set after completing ALC limiter operation. If the
input signal does not exceed “ALC recovery waiting counter reset level” (Table 25) during the wait time, ALC recovery
operation is executed. The VOL value is automatically incremented by RGAIN1-0 bits (Table 29) up to the set reference
level (Table 30) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 27). Then the IVL and
IVR are set to the same value for both channels. The ALC recovery operation is executed in a period set by WTM2-0 bits.
If the setting of ZTM1-0 is longer than WTM2-0 and no zero crossing occurs, the ALC recovery operation is done at a
period set by ZTM1-0 bits.
For example, when the current VOL value is 30H and RGAIN1-0 bits are set to “01”, VOL is changed to 32H by auto
limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the VOL value exceeds the
reference level (REF7-0), the VOL values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
ALC operations correspond to the impulse noise. When the impulse noise is input, the ALC recovery operation becomes
faster than a normal recovery operation. When large noise is input to a microphone instantaneously, the quality of small
level in the large noise can be improved by this fast recovery operation. The speed of first recovery operation is set by
RFST1-0 bits(Table 32)
WTM2
bit
0
0
0
0
1
1
1
1
WTM1
bit
0
0
1
1
0
0
1
1
WTM0
ALC Recovery Operation Waiting Period
bit
8kHz
16kHz
44.1kHz
0
128/fs
16ms
8ms
2.9ms
1
256/fs
32ms
16ms
5.8ms
0
512/fs
64ms
32ms
11.6ms
1
1024/fs
128ms
64ms
23.2ms
0
2048/fs
256ms
128ms
46.4ms
1
4096/fs
512ms
256ms
92.9ms
0
8192/fs
1024ms
512ms
185.8ms
1
16384/fs
2048ms
1024ms
371.5ms
Table 28. ALC Recovery Operation Waiting Period
RGAIN1 bit
0
0
1
1
RGAIN0 bit
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 29. ALC Recovery GAIN Step
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IREF7-0 bits
GAIN (dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E1H
+30.0
(default)
0.375dB
:
:
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 30. Reference Level at ALC Recovery Operation for Recoding
OREF5-0 bits
GAIN (dB)
Step
3CH
+36.0
3BH
+34.5
3AH
+33.0
:
:
28H
+6.0
(default)
1.5dB
:
:
25H
+1.5
24H
0.0
23H
-1.5
:
:
2H
-51.0
1H
-52.5
0H
-54.0
Table 31. Reference Level at ALC Recovery Operation for Playback
RFST1 bit
RFST0 bit
Recovery Speed
0
0
Quad Speed
(default)
0
1
8times
1
0
16times
1
1
N/A
Table 32. First Recovery Speed Setting (N/A: Not available)
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3.
The Volume at ALC Operation
The current volume value at ALC operation is reflected in VOL7-0 bits. It is enable to check the current volume value by
reading the register value of VOL7-0 bits. (Since data reading for I2C bus control mode is not supported, the register
values are invalid when reading the VOL7-0 bits.)
VOL7-0 bits
GAIN (dB)
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
C5H
+19.5
:
:
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 33. Value of VOL7-0 bits
4.
Example of ALC Setting
Table 34 and Table 35 show the examples of the ALC setting for recording and playback path.
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits must be the same value
or larger value than ZTM1-0 bits
Maximum gain at recovery operation
WTM2-0
IREF7-0
IVL7-0,
IVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC1
Gain of IVOL
Data
01
0
01
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
001
32ms
100
46.4ms
E1H
+30dB
E1H
+30dB
E1H
+30dB
E1H
+30dB
00
1
00
00
1
1 step
ON
1 step
4 times
Enable
Limiter ATT step
00
1 step
Fast Limiter Operation
1
ON
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 34. Example of the ALC Setting (Recording)
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Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits must be the same value
or larger value than ZTM1-0 bits
Maximum gain at recovery operation
WTM2-0
OREF5-0
OVL7-0,
OVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC2
5.
Data
01
0
01
Gain of VOL
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
001
32ms
100
46.4ms
28H
+6dB
28H
+6dB
91H
0dB
91H
0dB
00
1
00
00
1
1 step
ON
1 step
4 times
Enable
Limiter ATT step
00
1 step
Fast Limiter Operation
1
ON
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 35. Example of the ALC Setting (Playback)
Noise Suppression
The Noise Suppression is enabled when NSCE bit (Noise suppression enable bit) = “1” during ALC operation (ALC1 bit
= “1”). This function attenuates output signal level automatically when minute amount of the signal is input.
NSCE bit: Noise Suppression Enable
0: Disable (default)
1: Enable
(1)
Noise Level Suppressing Operation
The output signal (Note 36) is suppressed when the input peak level is lower than “Noise Suppression Threshold Low
Level” set by NSTHL3-0 bits (Table 36) during the waiting time set by WTM2-0 bits (Table 28).
VOL value is changed by this noise suppressing operation only at the individual zero crossing points of Lch and Rch or at
the zero crossing timeout. Noise level suppressing operation has common zero cross timeout period to ALC recovery
operation which is set by ZTM1-0 bits. (Table 27)
This operation sets the volume automatically to the reference level (Table 40) with zero cross detection in the period
which is set by ZTM1-0 bits (Table 27). It is executed in the cycle of WTM2-0 bits settings.
Note 36. When the input signal volume is smaller than the value set by NSREF7-0 bits, normal ALC recovery operation
is executed.
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NSTHL3 bit
Noise Suppression
Threshold Low Level
0
0
0
(default)
−81dB
0
0
1
−78dB
0
1
0
−75dB
0
1
1
−72dB
1
0
0
−69dB
1
0
1
−66dB
1
1
0
−63dB
1
1
1
−60dB
0
0
0
−57dB
0
0
1
−54dB
0
1
0
−51dB
Table 36. Noise Suppression Threshold Low Level
NSTHL2 bit
0
0
0
0
0
0
0
0
1
1
1
NSTHL1 bit
NSTHL0 bit
NATT1 bit
NATT0 bit
ATT STEP
0
0
1/4 (Note 37)
0
1
1/2 (Note 38) (default)
1
0
1
1
1
2
Note 37. 1step attenuated in 4 x “WTM cycles”.
Note 38. 1step attenuated in 2 x “WTM cycles”.
Table 37. Noise ATT Settings
ZTM1 bit
ZTM0 bit
0
0
1
1
0
1
0
1
Zero Cross Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 27. ALC Zero Cross Timeout Period Settings
(default)
(2) Noise Level Hold
During the waiting time set by WTM2-0 bits (Table 28), VOL values are kept when the input signal peak level is in
between the set value of NSTHH1-0 (Note 39) and Noise Suppression Threshold Low Level (Noise Suppression High
Level >input signal level ≥ Noise Suppression Threshold Low Level) therefore the output signal level does not change.
NSTHH1 bit NSTHH0 bit Noise Suppression High Level (Note 39)
0
0
NSTHL3-0 bits + 3dB
(default)
0
1
NSTHL3-0 bits + 6dB
1
0
NSTHL3-0 bits + 9dB
1
1
NSTHL3-0 bits + 12dB
Note 39. Noise Suppression Threshold Low Level (NSTHL3-0 bits) + Gain (NSTHH1-0 bits) = Noise Suppression High
Level
Table 38. Noise Suppression High Level Settings
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(3) Noise Suppression → Normal ALC Operation
During noise suppressing operation, if the input signal level exceeds Noise Suppression High Level, the operation
switches to normal ALC operation from noise suppressing or noise level hold operation. In this case, recovery speed is
faster than the normal recovery (Table 39).
However, when normal ALC operation is changed to noise suppressing operation and the internal volume is lower than
the reference value at Noise Suppression (NSREF7-0 bits), the recovery speed is the same as the ALC recovery speed
during the operation switches to normal ALC operation from noise suppressing.
NSGAIN1 bit
NSGAIN0 bit
Recovery Speed
0
0
8 step
0
1
12 step
(default)
1
0
16 step
1
1
28 step
Table 39. Fast Recovery Speed Setting from Noise Suppression to ALC Operation
NSREF7-0 bits
GAIN[dB]
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
C5H
+19.5
0.375dB
:
:
92H
+0.375
91H
0.0
(default)
90H
−0.375
:
:
2H
−53.625
1H
−54.0
0H
MUTE
Table 40. Reference Value Setting when Noise Suppression is ON
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6.
Example of registers set-up sequence of ALC1 Operation
The following registers must not be changed during ALC operation. These bits must be changed after ALC operation is
finished by ALC1 bit=ALC2 bit = “0”. All ALC outputs are “0” until manual mode starts when ALC1 bit =ALC2 bit =
“0”.
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN 1-0, REF7-0, ZELMN, RFST1-0, LFST, NSCE, NSTHL3-0,
NATT1-0, NSTHH1-0, NSGAIN1-0, NSREF7-0
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Manual Mode
ALC1 bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=06H, Data=14H
WR (IREF7-0)
(2) Addr=08H, Data=E1H
WR (IVL/R7-0)
* The value of IVOL should be
(3) Addr=09H&0CH, Data=E1H
the same or smaller than REF’s
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=28H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC1= “1”)
(5) Addr=07H, Data=21H
ALC1 Operation
Note : WR : Write
Figure 36. Registers Set-up Sequence at ALC1 Operation (recording path)
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■ Input Digital Volume (Manual Mode)
The input digital volume becomes manual mode at ALC1 bit = “0” when ADCPF bit =“1”. This mode is used in the case
shown below.
1.
2.
3.
After exiting reset state, set-up the registers for ALC operation (ZTM1-0, LMTH and etc)
When the registers for ALC operation (Limiter period, Recovery period and etc) are changed.
For example; when the change of the sampling frequency.
When IVOL is used as a manual volume control.
IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 41). The IVOL value is changed at zero crossing or
timeout. The zero crossing timeout period is set by ZTM1-0 bits. Lch and Rch volumes are set individually by IVL7-0 and
IVR7-0 bits when IVOLC bit = “0”. IVL7-0 bits control both Lch and Rch volumes together when IVOLC bit = “1”.
IVL7-0 bits
IVR7-0 bits
F1H
F0H
EFH
:
E2H
E1H
E0H
:
03H
02H
01H
00H
GAIN (dB)
Step
+36.0
+35.625
+35.25
:
+30.375
0.375dB
+30.0
+29.625
:
−53.25
−53.625
−54
MUTE
Table 41. Input Digital Volume Setting
(default)
If IVL7-0 or IVR7-0 bits are written during PMPFIL bit = “0”, IVOL operation starts with the written values after
PMPFIL bit is changed to “1”.
When writing to IVOL7-0 bits continually, take an interval of zero crossing timeout period or more. If not, the zero
crossing counter is reset at each time and the volume will not be changed. However, when writing the same register values
as the previous time, the zero crossing counter will not be reset, so that it could be written in an interval less than zero
crossing timeout.
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[AK4649VN]
■ Output Digital Volume (Manual Mode)
The ALC block becomes output digital volume (manual mode) by setting ALC2 bit to “0” when PMPFIL = PMDAC bits
= “1” and ADCPF bit is “0”. The output digital volume gain is set by the OVL7-0 bit and the OVR7-0 bit (Table 42).
When the OVOLC bit = “1”, the OVL7-0 bits control both Lch and Rch volume levels. When the OVOLC bit = “0”, the
OVL7-0 bits control Lch volume level and the OVR7-0 bits control Rch volume level. When changing the volumes, zero
cross detect is excuted for Lch and Rch individually. The OVOL value is changed at zero crossing or timeout. The zero
crossing timeout period is set by ZTM1-0 bits.
OVL7-0 bits
GAIN (dB)
Step
OVR7-0 bits
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
0.375dB
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 42. Output Digital Volume Setting
(default)
When writing to the OVL7-0 bits and OVR7-0 bit continuously, the control register should be written in an interval more
than zero crossing timeout. If not, the zero crossing counter is reset at each time and the volume will not be changed. H
However, when writing the same register values as the previous time, the zero crossing counter will not be reset, so that it
could be written in an interval less than zero crossing timeout.
■ Output Digital Volume 2
The AK4649VN has 4 steps output volume control. Lch and Rch have the same volume values, which are set by
DATT1-0 bits as shown in Table 43. This volume control is also available during ALC operation.
DATT1-0 bits
0H
1H
2H
3H
GAIN (dB)
Step
0.0
(default)
6.0dB
-6.0
-12.0
-18.1
Table 43. Output Digital Volume2 Setting
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[AK4649VN]
■ Output Digital Volume 3
The AK4649VN has a digital output volume control (256 levels, linear step, MUTE). It is processed before the DAC
block. The input data of DAC is changed from 0 to –48.13dB or MUTE. This volume has a soft transition function.
Therefore no switching noise occurs during the transition. Transition time from 0dB to MUTE is 255/fs, and each 1level
transition takes 1/fs. Volume calculating formula is shown in Table 45. This volume control is also available during ALC
operation.
DVOL7-0 bits
ATT_DATA
GAIN(dB)
FFH
FEH
FDH
:
255
254
253
:
+0
-0.034
-0.068
:
02H
2
-42.11
01H
1
-48.13
00H
-
Mute
(default)
Table 44. Output Digital Volume3 Setting
DVOL7-0 bits
GAIN (dB)
FFH
20 log10 (ATT_DATA / 255)
:
01H
00H
Mute
Table 45. Output Digital Volume 3 Formula
■ Digital HPF1
A digital High Pass Filter (HPF) is integrated for DC offset cancellation of the ADC input. The cut-off frequencies of the
HPF1 are set by HPFC1-0 bits (Table 46). It is proportional to the sampling frequency (fs) and default is 3.4Hz (@fs =
44.1kHz). HPFAD bit controls the ON/OFF of the HPF1 (Recommend HPF enable).
HPFC1 bit
HPFC0 bit
0
0
1
1
0
1
0
1
fc
fs=44.1kHz
fs=22.05kHz
3.4Hz
1.7Hz
13.6Hz
6.8Hz
108.8Hz
54.4Hz
217.6Hz
108.8Hz
Table 46. HPF1 Cut-off Frequency
MS1506-E-00
fs=8kHz
0.62Hz
2.47Hz
19.7Hz
39.5Hz
(default)
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[AK4649VN]
■ De-emphasis Filter
The AK4649VN includes a digital de-emphasis filter (tc = 50/15μs) which corresponds 3 kinds frequency (32kHz,
44kHz, 48kHz) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 47).
DEM1
0
0
1
1
DEM0
Mode
0
44.1kHz
1
OFF
(default)
0
48kHz
1
32kHz
Table 47. De-emphasis Control
■ Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit is set “1”, the output signal is attenuated to
-∞ in“ATT_DATA/fs” cycle. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation
gradually changes to 0dB in “ATT_DATA/fs” cycle. If the soft mute is cancelled within this cycle after starting an
operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for changing
the signal source without stopping the signal transmission at playback path.
S M U T E bit
A T T _D A T A
(1)
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 37. Soft Mute Function
(1) The input signal is attenuated by −∞ (“0”) during “ATT_DATA/fs” cycle (when ATT_DATA = 0dB, 255/fs =
5.7msec@fs=44.1kHz).
(2) Analog output corresponding to digital input has group delay (GD).
(3) If soft mute is cancelled before attenuating to −∞, the attenuation is discounted and returned to ATT_DATA value
within the same cycle.
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[AK4649VN]
■ Analog Mixing: Mono Input
When the PMBP bit is set to “1”, the mono input is powered-up. When the BEEPS bit is set to “1”, the input signal from
the MIN pin is output to Speaker-Amp. When the BEEPH bit is set to “1”, the input signal from the MIN pin is output to
a stereo line output amplifier. When BPM bit is set to “0”, the external resister Ri adjusts the signal level of MIN input.
When BPM bit is “0”, the external resister Ri is not needed. BPLVL2-0 bits control the MIN-Amp gain. Table 49, and
Table 50 show the typical gain example at Ri = 33kΩ This gain is in inverse proportion to Ri
BPM bit
BEEP Mode
0
External Resistance Mode
1
Internal Resistance Mode
Table 48. BEEP Mode Setting
(default)
1. External Resistance Mode (BPM bit = “0”)
MIN pin
BEEPL
LOUT/ROUT pin
Ri
BEEPS
MIN-Amp
SPP/SPN pin
Figure 38. Block Diagram of MIN pin (BPM bit =“0”)
LOVL1-0 bits
MIN → LOUT/ROUT
00
0dB
(default)
01
+2dB
10
+4dB
11
+6dB
Table 49.MIN → AOUT Output Gain (typ) at Ri = 33kΩ
MIN → SPP/SPN
ALC2 bit = “0”
ALC2 bit = “1”
+3.3dB
+5.3dB
+5.3dB
+7.3dB
+7.3dB
+9.3dB
+9.3dB
+11.3dB
Table 50.MIN → SPK Output Gain (typ) at Ri = 33kΩ
SPKG1-0 bits
00
01
10
11
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(default)
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[AK4649VN]
2. Internal Resistance Mode (BPM bit = “1”)
BPLVL2
BPLVL1
BPLVL0
BEEP Gain
0
0
0
0dB
(default)
0
0
1
−3dB
0
1
0
−6dB
0
1
1
−12dB
1
0
0
−18dB
1
0
1
−23dB
1
1
0
−29dB
1
1
1
−34dB
Table 51. BEEP Output Gain Setting (BPM bit = “1”)
MIN pin
BEEPL
LOUT/ROUT pin
BEEPS
MIN -Amp
SPP/SPN pin
Figure 39. Block Diagram of MIN pin (BPM bit =“1”)
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[AK4649VN]
■ Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ
(min.). When the PMLO bit = LOPS bit = “0”, the stereo line output enters power-down mode and the output is
pulled-down to VSS1 by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMLO bit when LOPS bit = “1”. In this case, output signal line should be
pulled-down to VSS1 by 20kΩ after AC coupled as Figure 41. Rise/Fall time is 300ms (max) at C=1μF and RL=10kΩ.
When PMLO bit = “1” and LOPS bit = “0”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
“DACL bit”
“LOVL1- bits”
LOUT pin
DAC
ROUT pin
Figure 40. Stereo Line Output
LOPS
0
1
PMLO
0
1
0
1
Mode
LOUT/ROUT pin
Power-down
Pull-down to VSS1
Normal Operation
Normal Operation
Power-save
Fall down to VSS1
Power-save
Rise up to VCOM
Table 52. Stereo Line Output Mode Select
(default)
LOVL1-0 bits
Gain
00
0dB
(default)
01
+2dB
10
+4dB
11
+6dB
Table 53. Stereo Line Output Volume Setting
LOUT
ROUT
1μF
220Ω
20kΩ
Figure 41. External Circuit for Stereo Line Output (when using Pop Noise Reduction Circuit)
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[AK4649VN]
[Stereo Line Output Control Sequence (when using Pop Noise Reduction Circuit)]
(2 )
(5 )
P M L O b it
(1 )
(3 )
(4 )
(6 )
L O P S b it
99% V C O M
L O U T , R O U T p in s
N o r m a l O u tp u t
≥ 300 m s
1% VC O M
≥ 300 m s
Figure 42. Stereo Line Output Control Sequence (when using Pop Noise Reduction Circuit)
(1) Set LOPS bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO bit = “1”. Stereo line output exits the power-down mode.
LOUT and ROUT pins rise up to 99% VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF.
(3) Set LOPS bit = “0”. After LOUT and ROUT pins rise up, stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO bit = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to 1% VCOM voltage. Fall time is 200ms (max 300ms) at C=1μF.
(6) Set LOPS bit = “0”. After LOUT and ROUT pins fall down, stereo line output exits the power-save mode
■ Speaker Output
The DAC output signal is input to the Speaker-amp as [(L+R)/2]. The Speaker-amp is mono and BTL output. The gain is
set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits.
SPKG1-0 bits
00
01
10
11
Gain
ALC2 bit = “0”
ALC2 bit = “1”
+3.3dB
+5.3dB
+5.3dB
+7.3dB
+7.3dB
+9.3dB
+9.3dB
+11.3dB
Table 54. SPK-Amp Gain
(default)
SPK-Amp Output (DAC Input=0dBFS,
AVDD=SVDD=3.3V)
SPKG1-0 bits
ALC2 bit = “0”
ALC2 bit = “1”
(LMTH1-0 bits = “00”)
00
3.37Vpp
3.17Vpp
01
4.23Vpp (Note 40)
4.00Vpp
10
5.33Vpp (Note 40)
5.04Vpp (Note 40)
11
6.71Vpp (Note 40)
6.33Vpp (Note 40)
Note 40. The output level is calculated by assuming that output signal is not clipped. In actual case, output signal may be
clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital
volume so that Speaker-Amp output level is 4.0Vpp or less and output signal is not clipped.
Table 55. SPK-Amp Output Level
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[AK4649VN]
< Speaker-Amp Control Sequence >
Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pins are in Hi-Z state.
When PMSPK bit is “1” and SPPSN bit is “0”, the Speaker-Amp enters power-save mode. In this mode, the SPP pin is
placed in Hi-Z state and the SPN pin outputs SVDD/2 voltage.
When the PMSPK bit is “1” after the PDN pin is changed from “L” to “H”, the SPP and SPN pins rise up from
power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. Because
the SPP and SPN pins rise up at power-save-mode, this mode can reduce pop noise. When the AK4646 is powered-down,
pop noise can be also reduced by first entering power-save-mode.
PMSPK
0
1
SPPSN
x
0
1
Mode
SPP
SPN
Power-down
Hi-Z
Hi-Z
Power-save
Hi-Z
SVDD/2
Normal Operation Normal Operation Normal Operation
Table 56 Speaker-Amp Mode Setting (x: Don’t care)
(default)
PMSPK bit
SPPSN bit
>1ms
SPP pin
SPN pin
Hi-Z
Hi-Z
Hi-Z
SVDD/2
SVDD/2
Hi-Z
Figure 43. Power-up/Power-down Timing for Speaker-Amp
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[AK4649VN]
■ Serial Control Interface
(1) 3-wire Serial Control Mode
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control data (MSB first, 8bits). Each bit is
clocked in on the rising edge (“↑”) of CCLK. Data writing become available on the rising edge of CSN. When reading,
the CDTIO pin will be output mode at the falling edge of 8th CCLIC and outputs D7-D0. The output finishes on the rising
edge of CSN. The CDTIO is placed in a Hi-Z state except outputting data at read operation mode. Clock speed of CCLK
is 5MHz (max). The value of internal registers are initialized by the PDN pin = “L”.
Note 41. Data reading is only available on the following addresses; 00H~11H, 24H~2BH, 30~31H. When reading the
address 12H ∼ 23H, 2C~2FH, 32H~7FH, the register values are invalid.
CSN
0
CCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
“H” or “L”
CDTIO “H” or “L”
“H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
R/W:
A6-A0:
D7-D0:
“H” or “L”
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data (Input) at Write Command
Output data (Output) at Read Command
Figure 44. Serial Control I/F Timing
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[AK4649VN]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4649VN supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins must be
connected to (DVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 45 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by START condition.
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 51). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit). This
bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits (Figure
46). If the slave address matches that of the AK4649VN, the AK4649VN generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 52). A R/W bit value of “1” indicates that the read operation is to be executed. “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4649VN. The format is MSB first, and those most
significant 2-bits are fixed to zeros (Figure 47). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 48). The AK4649VN generates an acknowledge after each byte is received. Data transfer is always
terminated by STOP condition generated by the master. LOW to HIGH transition on the SDA line while SCL is HIGH
defines STOP condition (Figure 51).
The AK4649VN can perform more than one byte write operation per sequence. After receipt of the third byte the
AK4649VN generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit
address counter is incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 4FH prior to generating stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only be changed when the clock signal on the SCL line is LOW (Figure 53) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 45. Data Transfer Sequence at I2C Bus Mode
0
0
1
0
0
1
CAD0
R/W
A2
A1
A0
D2
D1
D0
Figure 46. The First Byte
0
A6
A5
A4
A3
Figure 47. The Second Byte
D7
D6
D5
D4
D3
Figure 48. The Third Byte
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[AK4649VN]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4649VN. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 4FH prior to generating stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out.
Note 42. Data reading is only available on the following addresses; 00H~0CH, 0EH ~ 11H, 24H~2BH, 30~31H. When
reading the address 0DH, 12H ∼ 23H, 2C~2FH, 32H~7FH, the register values are invalid.
The AK4649VN supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4649VN contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4649VN generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but generates stop condition instead, the
AK4649VN ceases the transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 49. Current Address Read
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit “1”. The AK4649VN then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but generates a stop condition instead, the AK4649VN ceases the transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 50. Random Address Read
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[AK4649VN]
SDA
SCL
S
P
start condition
stop condition
Figure 51. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 52. Acknowledge (I2C Bus)
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 53. Bit Transfer (I2C Bus)
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[AK4649VN]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Output Volume Control
ALC Mode Control 3
Rch Input Volume Control
ALC LEVEL
Mode Control 3
Digital Volume Control
Power Management 3
Digital Filter Select 1
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ0-efficient 0
EQ0-efficient 1
EQ0-efficient 2
EQ0-efficient 3
EQ0-efficient 4
EQ0-efficient 5
HPF2 Co-efficient 0
HPF2 Co-efficient 1
HPF2 Co-efficient 2
HPF2 Co-efficient 3
Reserved
Reserved
Reserved
Reserved
BEEP Volume Control
Rch Output Volume Control
Digital Filter Mode
Digital MIC
BEEP/HPF Mode
Noise Suppression 1
Noise Suppression 2
Noise Suppression 3
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
D7
PMPFIL
0
SPPSN
0
PLL3
PS1
ADRST
LFST
IREF7
D6
PMVCM
0
BEEPS
LOPS
PLL2
PS0
WTM2
ALC2
IREF6
D5
PMBP
0
DACS
MGAIN1
PLL1
FS3
ZTM1
ALC1
IREF5
D4
PMSPK
0
DACL
SPKG1
PLL0
0
ZTM0
ZELMN
IREF4
D3
PMLO
M/S
MGAIN3
SPKG0
BCKO
0
WTM1
LMAT1
IREF3
D2
PMDAC
0
PMMP
BEEPL
0
FS2
WTM0
LMAT0
IREF2
D1
0
MCKO
D0
PMADL
PMPLL
MGAIN2
MGAIN0
LOVL1
DIF1
FS1
RFST1
RGAIN0
IREF1
LOVL0
DIF0
FS0
RFST0
LMTH0
IREF0
IVL7
IVL6
IVL5
IVL4
IVL3
IVL2
IVL1
IVL0
OVL7
RGAIN1
IVR7
VOL7
READ
DVOL7
IVOLC
GN1
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
F1A7
0
F1B7
0
0
0
0
0
0
OVR7
0
0
HPFC1
0
0
NSREF7
F2A7
0
F2B7
0
OVL6
LMTH1
IVR6
VOL6
0
DVOL6
0
GN0
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
F1A6
0
F1B6
0
0
0
0
0
0
OVR6
0
MPDMP
HPFC0
NSCE
0
NSREF6
F2A6
0
F2B6
0
OVL5
OREF5
IVR5
VOL5
SMUTE
DVOL5
0
LPF
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
F1A5
F1A13
F1B5
F1B13
0
0
0
0
0
OVR5
0
PMDMR
0
OVL4
OREF4
IVR4
VOL4
OVOLC
DVOL4
0
HPF
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
F1A4
F1A12
F1B4
F1B12
0
0
0
0
0
OVR4
0
PMDML
0
OVL3
OREF3
IVR3
VOL3
DATT1
DVOL3
0
EQ0
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
F1A3
F1A11
F1B3
F1B11
0
0
0
0
0
OVR3
0
DCLKE
0
OVL2
OREF2
IVR2
VOL2
DATT0
DVOL2
INR
FIL3
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
F1A2
F1A10
F1B2
F1B10
0
0
0
0
BPLVL2
OVR2
PFDAC
DMPE
0
OVL1
OREF1
IVR1
VOL1
DEM1
DVOL1
INL
0
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
F1A1
F1A9
F1B1
F1B9
0
0
0
0
BPLVL1
OVR1
ADCPF
DCLKP
0
OVL0
OREF0
IVR0
VOL0
DEM0
DVOL0
PMADR
HPFAD
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
F1A0
F1A8
F1B0
F1B8
0
0
0
0
BPLVL0
OVR0
PFSDO
DMIC
BPM
NSTHH1
NSTHH0
NSTHL3
NSTHL2
NATT1
NSREF5
F2A5
F2A13
F2B5
F2B13
NATT0
NSREF4
F2A4
F2A12
F2B4
F2B12
0
NSREF3
F2A3
F2A11
F2B3
F2B11
0
NSREF2
F2A2
F2A10
F2B2
F2B10
NSTHL1
NSGAIN1
NSTHL0
NSGAIN0
NSREF1
F2A1
F2A9
F2B1
F2B9
NSREF 0
F2A0
F2A8
F2B0
F2B8
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Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
D6
0
0
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
D5
0
0
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
D4
EQ5
0
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
D3
EQ4
0
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
Note 43. PDN pin = “L” resets the registers to their default values.
Note 44. The bits defined as 0 must contain a “0” value.
Note 45. Reading address 0DH (in I2C-bus control mode), 12H ~ 23H, 2CH ~ 2FH and 32H ~ 7FH is not possible.
Note 46. Address 0DH is a read only register. Writing access to 0DH is ignored and does not effect the operation.
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■ Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
D6
PMPFIL
PMVCM
R/W
0
R/W
0
D5
PMBP
R/W
0
D4
PMSPK
R/W
0
D3
PMLO
R/W
0
D2
PMDAC
R/W
0
D1
0
R
0
D0
PMADL
R/W
0
PMADL: MIC-Amp Lch and ADC Lch Power Management
0: Power-down (default)
1: Power-up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMDAC: DAC Power Management
0: Power-down (default)
1: Power-up
PMLO: Stereo Line Out Power Management
0: Power-down (default)
1: Power-up
PMSPK: Speaker-Amp Power Management
0: Power-down (default)
1: Power-up
PMBP: MIN Input Power Management
0: Power-down (default)
1: Power-up
Both PMDAC and PMBP bits must be set to “1” when DAC is powered-up for playback. After that, BEEPL or
BEEPS bit is used to control each path when MIN input is used.
PMVCM: VCOM Power Management
0: Power-down (default)
1: Power-up
PMPFIL: Programmable Filter Block (HPF2/LPF/FIL3/EQ/5 Band EQ/ALC) Power Management
0: Power down (default)
1: Power up
All blocks can be powered-down by writing “0” to the address “00H”, PMPLL, PMDML, PMDMR, DMPE,
PMADR and MCKO bits. In this case, register values are maintained.
PMVCM bit must be “1” when one of bocks is powered-up. PMVCM bit can only be “0” when the address “00H”
and all power management bits (PMPLL, PMMP, PMDML, PMDMR, DMPE, PMADR and MCKO) are “0”.
When using either ADC, DAC or Programmable Filter (PMADL bit = “1”, PMADR bit =”1”, PMDAC bit = “1” or
PMPFIL bit = “1”), clock must be supplied.
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Addr
01H
Register Name
Power Management 2
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
M/S
R/W
0
D2
0
R
0
D3
D2
PMMP
R/W
0
D1
MCKO
R/W
0
D0
PMPLL
R/W
0
PMPLL: PLL Power Management
0: EXT Mode and Power-Down (default)
1: PLL Mode and Power-up
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
Addr
02H
Register Name
Signal Select 1
R/W
Default
D7
SPPSN
R/W
0
D6
BEEPS
R/W
0
D5
DACS
R/W
0
D4
DACL
R/W
0
MGAIN3
R/W
0
D1
D0
MGAIN2
MGAIN0
R/W
0
R/W
1
MGAIN3-0: MIC-Amp Gain Control (Table 21)
MGAIN1 bit is D5 bit of 03H.
PMMP: MPWR pin Power Management
0: Power-down: Hi-Z (default)
1: Power-up
DACL: Switch Control from DAC to Stereo Line Output
0: OFF (default)
1: ON
When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1.
DACS: Switch Control from DAC to Speaker-Amp
0: OFF (default)
1: ON
When DACS bit is “1”, DAC output signal is input to Speaker-Amp.
BEEPS: Switch Control from MIN pin to Speaker-Amp
0: OFF (default)
1: ON
When BEEPS bit is “1”, mono signal is input to Speaker-Amp.
Set BEEP input mode by BPM bit.
SPPSN: Speaker-Amp Power-Save Mode
0: Power-Save Mode (default)
1: Normal Operation
When SPPSN bit is “0”, Speaker-Amp is on power-save mode. In this mode, the SPP pin goes to Hi-Z and
outputs SVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “L”,
Speaker-Amp is in power-down mode since PMSPK bit is “0”.
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Addr
03H
Register Name
Signal Select 2
R/W
Default
D7
0
R
0
D6
LOPS
R/W
0
D5
MGAIN1
R/W
0
D4
SPKG1
R/W
0
D3
SPKG0
R/W
0
D2
BEEPL
R/W
0
D1
LOVL1
R/W
0
D0
LOVL0
R/W
0
LOVL1-0 : Output Stereo Line Gain Select (Table 53)
Default: 00(0dB)
BEEPL: Switch Control from MIN pin to Stereo Line Output
0: OFF (default)
1: ON
When PMLO bit is “1”, BEEPL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1.
SPKG1-0: Speaker-Amp Output Gain Select (Table 54)
MGAIN1: MIC-Amp Gain Control (Table 21)
LOPS: Stereo Line Output Power-Save Mode
0: Normal Operation (default)
1: Power Save Mode
Addr
04H
Register Name
Mode Control 1
R/W
Default
D7
PLL3
R/W
0
D6
PLL2
R/W
0
D5
PLL1
R/W
0
D4
PLL0
R/W
0
D3
BCKO
R/W
0
D2
0
R
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
D4
0
R
0
D3
0
R
0
D2
FS2
R/W
0
D1
FS1
R/W
0
D0
FS0
R/W
0
DIF1-0: Audio Interface Format (Table 17)
Default: “10” (MSB)
BCKO: BICK Output Frequency Select at Master Mode (Table 10)
PLL3-0: PLL Reference Clock Select (Note 31)
Default: “0000” (LRCK pin)
Addr
05H
Register Name
Mode Control 2
R/W
Default
D7
PS1
R/W
0
D6
PS0
R/W
0
D5
FS3
R/W
0
FS3-0: Sampling Frequency Select (Table 5, Table 6) and MCKI Frequency Select (Table 11)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
PS1-0: MCKO Output Frequency Select (Table 9)
Default: “00”(256fs)
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Addr
06H
Register Name
Timer Select
R/W
Default
D7
ADRST
R/W
0
D6
WTM2
R/W
0
D5
ZTM1
R/W
0
D4
ZTM0
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
RFST1
R/W
0
D0
RFST0
R/W
0
ADRST: ADC Initialization Cycle Setting
0: 1059/fs (default)
1: 267/fs
WTM2-0: ALC Recovery Waiting Period (Table 28)
A period of recovery operation when any limiter operation does not occur during ALC operation
Default is “000” (128/fs).
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 27)
In case of the μP WRITE operation or ALC1 recovery operation, the volume is changed at zero crossing or
timeout.
RFST1-0: ALC First recovery Speed (Table 32)
Default: “00”(4times)
Addr
07H
Register Name
ALC Mode Control 1
R/W
Default
D7
LFST
R/W
0
D6
ALC2
R/W
0
D5
ALC1
R/W
0
D4
ZELMN
R/W
0
D3
LMAT1
R/W
0
D2
LMAT0
R/W
0
D1
RGAIN0
R/W
0
D0
LMTH0
R/W
0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 25)
Default: “00”
LMTH1 bit is D6 bit of 0BH.
RGAIN1-0: ALC Recovery GAIN Step (Table 29)
Default: “00”
RGAIN1 bit is D7 bit of 0BH.
LMAT1-0: ALC Limiter ATT Step (Table 26)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (default)
1: Disable
ALC1: ALC Enable for Recording
0: Recording ALC Disable (default)
1: Recording ALC Enable
ALC2: ALC Enable for Playback
0: Playback ALC Disable (default)
1: Playback ALC Enable
LFST: ALC Limiter operation when the output level exceed FS(Full-scale) level.
0: The volume is changed at zero crossing or zero crossing time out. (default)
1: When output of ALC is larger than FS, OVOL value is changed immediately (1/fs).
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Addr
08H
Register Name
ALC Mode Control 2
R/W
Default
D7
IREF7
R/W
1
D6
IREF6
R/W
1
D5
IREF5
R/W
1
D4
IREF4
R/W
0
D3
IREF3
R/W
0
D2
IREF2
R/W
0
D1
IREF1
R/W
0
D0
IREF0
R/W
1
D2
IVL2
IVR2
R/W
0
D1
IVL1
IVR1
R/W
0
D0
IVL0
IVR0
R/W
1
IREF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 30)
Default: “E1H” (+30.0dB)
Addr
09H
0CH
Register Name
Lch Input Volume Control
Rch Input Volume Control
R/W
Default
D7
IVL7
IVR7
R/W
1
D6
IVL6
IVR6
R/W
1
D5
IVL5
IVR5
R/W
1
D4
IVL4
IVR4
R/W
0
D3
IVL3
IVR3
R/W
0
IVL7-0, IVR7-0: IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 41)
Default: “E1H” (+30.0dB)
Addr
0AH
25H
Register Name
Lch Output Volume Control
Rch Output Volume Control
R/W
Default
D7
OVL7
OVR7
R/W
1
D6
OVL6
OVR6
R/W
0
D5
OVL5
OVR5
R/W
0
D4
OVL4
OVR4
R/W
1
D3
OVL3
OVR3
R/W
0
D2
OVL2
OVR2
R/W
0
D1
OVL1
OVR1
R/W
0
D0
OVL0
OVR0
R/W
1
D5
OREF5
R/W
1
D4
OREF4
R/W
0
D3
OREF3
R/W
1
D2
OREF2
R/W
0
D1
OREF1
R/W
0
D0
OREF0
R/W
0
OVL7-0, OVR7-0: Output Digital Volume (Table 42)
Default: “91H” (0dB)
Addr
0BH
Register Name
ALC Mode Control 3
R/W
Default
D7
RGAIN1
R/W
0
D6
LMTH1
R/W
0
OREF5-0: Reference value at Playback ALC Recovery Operation. 0.375dB step, 50 Level (Table 31)
Default: “28H” (+6.0dB)
LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 25)
RGAIN1: ALC Recovery GAIN Step (Table 29)
Addr
0DH
Register Name
ALC Volume
R/W
Default
D7
VOL7
R
-
D6
VOL6
R
-
D5
VOL5
R
-
D4
VOL4
R
-
D3
VOL3
R
-
D2
VOL2
R
-
D1
VOL1
R
-
D0
VOL0
R
-
VOL7-0: Current ALC volume value; 0.375dB step, 242 Level. Read operation only (Table 33)
Note 47. In 3-wire serial control mode. Register values are invalid when reading the address 0DH in I2C bus control
mode.
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Addr
0EH
Register Name
Mode Control 3
R/W
Default
D7
READ
R/W
0
D6
0
R
0
D5
SMUTE
R/W
0
D4
OVOLC
R/W
1
D3
DATT1
R/W
0
D2
DATT0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
DEM1-0: De-emphasis Frequency Select (Table 47)
Default: “01” (OFF)
DATT1-0: Output Digital Volume2; 6dB step, 4 Level (Table 43)
Default: “00H” (0.0dB)
OVOLC: Output Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When OVOLC bit = “1”, OVL7-0 bits control both Lch and Rch volume level, while register values of
OVL7-0 bits are not written to OVR7-0 bits. When OVOLC bit = “0”, OVL7-0 bits control Lch level and
OVR7-0 bits control Rch level, respectively.
SMUTE: Soft Mute Control
0: Normal Operation (default)
1: DAC outputs soft-muted
READ: Read function Enable
0: Disable (default)
1: Enable
Addr
0FH
Register Name
Digital Volume Control
R/W
Default
D7
DVOL7
R/W
1
D6
DVOL6
R/W
1
D5
DVOL5
R/W
1
D4
DVOL4
R/W
1
D3
DVOL3
R/W
1
D2
DVOL2
R/W
1
D1
DVOL1
R/W
1
D0
DVOL0
R/W
1
DVOL7-0: Output Digital Volume Control 3; Linear step (Table 43, Table 45)
Default: “FFH” (0dB)
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Addr
10H
Register Name
Power Management 3
R/W
Default
D7
IVOLC
R/W
1
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
INR
R/W
0
D1
INL
R/W
0
D0
PMADR
R/W
0
PMADR: MIC-Amp Rch, ADC Rch Power Management
0: Power down (default)
1: Power up
INL: ADC Lch Input Source Select
0: LIN1 pin (default)
1: LIN2 pin
INR: ADC Rch Input Source Select
0: RIN1 pin (default)
1: RIN2 pin
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
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Addr
11H
Register Name
Digital Filter Select 1
R/W
Default
D7
GN1
R/W
0
D6
GN0
R/W
0
D5
LPF
R/W
0
D4
HPF
R/W
0
D3
EQ0
R/W
0
D2
FIL3
R/W
0
D1
0
R
0
D0
HPFAD
R/W
1
HPFAD: HPF1 Control of ADC
0: OFF
1: ON (default)
When HPFAD bit is “1”, the settings of HPFC1-0 bits are enabled. When HPFAD bit is “0”, HPFAD block is
through (0dB).
When PMADL bit = “1” or PMADR bit = “1”, set HPFAD bit to “1”.
FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable
0: OFF (default)
1: ON
When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled.
EQ0: EQ0 (Gain Compensation Filter) Coefficient Setting Enable
0: OFF (default)
1: ON
When EQ0 bit is “1”, the settings of E0A15-0, E0B13-0 and E-C15-0 bits are enabled. When EQ0 bit is “0”,
EQ block is through (0dB).
HPF: HPF2 Coefficient Setting Enable
0: OFF (default)
1: ON
When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPF bit is “0”, HPF block
is through (0dB).
LPF: LPF Coefficient Setting Enable
0: OFF (default)
1: ON
When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are enabled. When LPF bit is “0”, LPF block
is through (0dB).
GN1-0: Gain Select at GAIN block (Table 24)
Default: “00” (0dB)
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Addr
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ0-efficient 0
EQ0-efficient 1
EQ0-efficient 2
EQ0-efficient 3
EQ0-efficient 4
EQ0-efficient 5
R/W
Default
D7
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
W
0
D6
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
W
0
D5
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
W
0
D4
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
W
0
D3
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
W
0
D2
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
W
0
D1
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
W
0
D0
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
W
0
D1
F1A1
F1A9
F1B1
F1B9
W
D0
F1A0
F1A8
F1B0
F1B8
W
F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2)
Default: “0000H”
F3AS: FIL3 (Stereo Separation Emphasis Filter) Select
0: HPF (default)
1: LPF
E0A15-0, E0B13-0, E0C15-C0: EQ (Gain Compensation Filter) Coefficient (16bit x 2 + 14bit x 1)
Default: “0000H”
Addr
1CH
1DH
1EH
1FH
Register Name
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
R/W
Default
D7
F1A7
0
F1B7
0
W
D6
F1A6
0
F1B6
0
W
D5
F1A5
F1A13
F1B5
F1B13
W
D4
F1A4
F1A12
F1B4
F1B12
W
D3
F1A3
F1A11
F1B3
F1B11
W
D2
F1A2
F1A10
F1B2
F1B10
W
F1A13-0 bits = 0x1FA9, F1B13-0 bits = 0x20AD
F1A13-0, F1B13-0: HPF2 Coefficient (14bit x 2)
Default: F1A13-0 bits = 0x1FA9, F1B13-0 bits = 0x20AD
fc = 150Hz@fs=44.1kHz
Addr
24H
Register Name
BEEP Volume Control
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
BPLVL2
R/W
0
D1
BPLVL1
R/W
0
D0
BPLVL0
R/W
0
BPLVL2-0 : BEEP Sound Output Level (Table 51)
Default: “0H”: 0dB
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Addr
26H
Register Name
Digital Filter Mode
R/W
Default
D7
0
R
0
D6
D5
0
R
0
0
R
0
D4
0
R
0
D3
0
R
0
D2
PFDAC
R/W
0
D1
ADCPF
R/W
1
D0
PFSDO
R/W
1
D3
DCLKE
R/W
0
D2
DMPE
R/W
0
D1
DCLKP
R/W
0
D0
DMIC
R/W
0
PFSDO: SDTO Output Signal Select
0: ADC (+ 1st HPF) Output
1: Programmable Filter / ALC Output (default)
ADCPF: Programmable Filter / ALC Input Signal Select
0: SDTI
1: ADC Output (default)
PFDAC: DAC Input Signal Select
0: SDTI (default)
1: Programmable Filter / ALC Output
Addr
27H
Register Name
Digital MIC
R/W
Default
D7
0
R
0
D6
D5
D4
MPDMP
PMDMR
PMDML
R/W
0
R/W
0
R/W
0
DMIC: Digital Microphone Connection Select
0: Analog Microphone (default)
1: Digital Microphone
DCLKP: Data Latching Edge Select
0: Lch data is latched on the DMCLK rising edge (“↑”). (default)
1: Lch data is latched on the DMCLK falling edge (“↓”).
DMPE: Digital Microphone Power Supply
0: Externally (the same supply as AVDD) (default)
1: DMP pin
DCLKE: DMCLK pin Output Clock Control
0: “L” Output (default)
1: 64fs Output
PMDML/R: Input Signal Select with Digital Microphone (Table 20)
Default: “00”
ADC digital block is powered-down by PMDML = PMDMR bits = “0” when selecting a digital microphone input
(DMIC bit = “1”, INL/R bits = “00”, “01” or “10”).
MPDMP: Analog / Digital Microphone Power Supply Pin Select
0: Power Supply for Analog Microphone: MPWR pin (default)
1: Power Supply for Digital Microphone: DMP pin
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Addr
28H
Register Name
BEEP/HPF Mode
R/W
Default
D7
HPFC1
R/W
0
D6
HPFC0
R\/W
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
BPM
R/W
0
BPM: BEEP Mode Setting (Table 48)
Default: “0”: External Resistance Mode
HPFC1-0: Cut-off Frequency Setting of HPF1 (ADC) (Table 46)
Default: “00” (3.4Hz @ fs = 44.1kHz)
Addr
29H
Register Name
Noise Suppression 1
R/W
Default
D7
0
R
0
D6
NSCE
R/W
0
D5
NSTHH1
R/W
0
D4
NSTHH0
R/W
1
D3
NSTHL3
R/W
0
D2
NSTHL2
R/W
0
D1
NSTHL1
R/W
0
D0
NSTHL0
R/W
0
NSTHL3-0: Noise Suppression Threshold Low Level Setting (Table 36)
Default: “0000” (-81dBFS)
NSTHH1-0: Noise Suppression Threshold High Level Setting (Table 38)
Default: “01” (NSTHL3-0 bits + 6dB)
NSCE: Noise Suppression Enable
0: Disable (default)
1: Enable
Addr
2AH
Register Name
Noise Suppression 2
R/W
Default
D7
0
R
0
D6
0
R
0
D5
NATT1
R/W
0
D4
NATT0
R/W
1
D3
0
R
0
D2
0
R
0
D1
NSGAIN1
R/W
0
D0
NSGAIN0
R/W
1
NSGAIN1-0: ALC First Recovery Speed Setting after Noise Suppression (Table 39)
Default: “01” (8 step)
NATT1-0: Noise Attenuate Step Setting (Table 37)
Default: “01” (1/2 step)
Addr
2BH
Register Name
Noise Suppression 3
R/W
Default
D7
NSREF7
R/W
1
D6
NSREF6
R/W
0
D5
NSREF5
R/W
0
D4
NSREF4
R/W
1
D3
NSREF3
R/W
0
D2
NSREF2
R/W
0
D1
NSREF1
R/W
0
D0
NSREF0
R/W
1
NSREF7-0: Reference Level Setting at Noise Suppression
0.375dB step, 242 Level (Table 40)
Default: “91H” (0dB)
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[AK4649VN]
Addr
2CH
2DH
2EH
2FH
Register Name
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
R/W
Default
D7
F2A7
0
F2B7
0
W
0
D6
F2A6
0
F2B6
0
W
0
D5
F2A5
F2A13
F2B5
F2B13
W
0
D4
F2A4
F2A12
F2B4
F2B12
W
0
D3
F2A3
F2A11
F2B3
F2B11
W
0
D2
F2A2
F2A10
F2B2
F2B10
W
0
D1
F2A1
F2A9
F2B1
F2B9
W
0
D0
F2A0
F2A8
F2B0
F2B8
W
0
D5
0
R
0
D4
EQ5
R/W
0
D3
EQ4
R/W
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
D0
EQ1
R/W
0
F2A13-0, F2B13-0: LPF Coefficient (14bit x 2)
Default: “0000H”
Addr
30H
Register Name
Digital Filter Select 2
R/W
Default
D7
0
R
0
D6
0
R
0
EQ1: Equalizer 1 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”,
EQ1 block is through (0dB).
EQ2: Equalizer 2 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ2 bit is “1”, the settings of E2A15-0, E2B15-0 and E2C15-0 bits are enabled. When EQ2 bit is “0”,
EQ2 block is through (0dB).
EQ3: Equalizer 3 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ3 bit is “1”, the settings of E3A15-0, E3B15-0 and E3C15-0 bits are enabled. When EQ3 bit is “0”,
EQ3 block is through (0dB).
EQ4: Equalizer 4 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ4 bit is “1”, the settings of E4A15-0, E4B15-0 and E4C15-0 bits are enabled. When EQ4 bit is “0”,
EQ4 block is through (0dB).
EQ5: Equalizer 5 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ5 bit is “1”, the settings of E5A15-0, E5B15-0 and E5C15-0 bits are enabled. When EQ5 bit is “0”,
EQ5 block is through (0dB).
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Addr
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
W
0
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3)
Default: “0000H”
E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3)
Default: “0000H”
E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3)
Default: “0000H”
E4A15-0, E4B15-0, E4C15-0: Equalizer 4 Coefficient (16bit x3)
Default: “0000H”
E5A15-0, E5B15-0, E5C15-0: Equalizer 5 Coefficient (16bit x3)
Default: “0000H”
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SYSTEM DESIGN
Figure 54 shows the system connection diagram. An evaluation board (AKD4649) is available for fast evaluation as well
as suggestions for peripheral circuitry.
Speaker
NC 17
MCKI 18
LRCK 19
BICK 20
SDTI 21
SDTO 22
25 VSS3
0.1μ
MCKO 23
NC 24
DSP
VSS2 16
26 SVDD
27 SPP
1μ
Line Out
28 SPN
AK4649VN
CDTIO 13
29 LOUT
Top View
CCLK 12
30 ROUT
VCOM
8
VSS1
7
AVDD
6
5
4
1
MPWR
VCOC 9
RIN1
32 LIN2
RIN2
20k
I2C 10
LIN1
20k
μP
PDN 11
31 MIN
3
1μ
NC
220
CSN 14
2
220
0.1μ
DVDD 15
Rp
Cp
0.1μ 2.2μ
10
C
C
C
Mono Input
C
C
2.2k
2.2k
2.2k
2.2k
Microphone
10μ
Power Supply
3.0 ∼ 3.6V
Analog Ground
Digital Ground
Notes:
- VSS1, VSS2 and VSS3 of the AK4649VN must be distributed separately from the ground of external
controllers.
- All digital input pins must not be left floating.
- When the AK4649VN is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK4649VN is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in
Table 4.
- When the AK4649VN is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to
“1”. Therefore, around 100kΩ pull-up resistor must be connected to LRCK and BICK pins of the AK4649VN.
Figure 54. System Connection Diagram (3-wire Serial Mode, Internal Resistance Mode; BPM bit = “1”)
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1. Grounding and Power Supply Decoupling
The AK4649VN requires careful attention to power supply and grounding arrangements. AVDD, DVDD and SVDD are
usually supplied from the system’s analog supply. If AVDD, DVDD and SVDD are supplied separately, the power-up
sequence is not critical. VSS1, VSS2 and VSS3 of the AK4649VN must be connected to the analog ground plane. System
analog ground and digital ground must be connected together near to where the supplies are brought onto the printed
circuit board. Decoupling capacitors must be as near to the AK4649VN as possible, with the small value ceramic
capacitor being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor must be
attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM
pin. All signals, especially clocks, must be kept away from the VCOM pin in order to avoid unwanted coupling into the
AK4649VN.
3. Analog Inputs
The MIC and Line inputs are single-ended. The inputs signal range scales with nominally at typ. 0.07 x AVDD Vpp (@
MGAIN = +20dB) and typ. 0.7 x AVDD Vpp (@ MGAIN = 0dB), centered around the internal common voltage (typ. 0.5
x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = 1/ (2πRC). The
AK4649VN can accept input voltages from VSS1 to AVDD.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFFFH (@24bit)
and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit). Stereo Line
Output is centered at typ. 0.5 x AVDD. The Headphone-Amp and Speaker-Amp outputs are centered at typ. 0.5 x SVDD.
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CONTROL SEQUENCE
■ Clock Set up
When ADC, DAC, Digital MIC or Programmable Filter is powered-up, the clocks must be supplied.
1. PLL Master Mode
Example:
Power Supply
PDN pin
PMVCM bit
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
(2)
(3)
(Addr:00H, D6)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:01H, D1)
PMPLL bit
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
(Addr:01H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:40H
(Addr:01H, D3)
10msec(max)
(6)
BICK pin
LRCK pin
Output
(4)Addr:01H, Data:0BH
Output
MCKO, BICK and LRCK output
10msec(max)
(8)
MCKO pin
(7)
Figure 55. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” → “H”
“L” time of 150ns or more is needed to reset the AK4649VN.
(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM must first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source, and PLL
lock time is 10ms (max).
(6) The AK4649VN starts to output the LRCK and BICK clocks after the PLL became stable. Then normal
operation starts.
(7) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from the MCKO pin after the PLL is locked if MCKO bit = “1”.
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2. PLL Slave Mode (LRCK or BICK pin)
Example:
Power Supply
PDN pin
PMVCM bit
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
(2)
(3)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(Addr:00H, D6)
PMPLL bit
(2) Addr:04H, Data:32H
Addr:05H, Data:27H
(Addr:01H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:40H
(4)
Internal Clock
(5)
(4) Addr:01H, Data:01H
Figure 56. Clock Set Up Sequence (2)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4649VN.
(2) DIF1-0, FS3-0 and PLL3-0 bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM must first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is
supplied. PLL lock time is 160ms (max) when LRCK is a PLL reference clock. And PLL lock time is 2ms (max)
when BICK is a PLL reference clock.
(5) Normal operation stats after that the PLL is locked.
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3. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Power Supply
PDN pin
PMVCM bit
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
(2)
(3)
(2)Addr:04H, Data:4AH
Addr:05H, Data:27H
(Addr:00H, D6)
(4)
MCKO bit
(Addr:01H, D1)
(3)Addr:00H, Data:40H
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
(4)Addr:01H, Data:03H
Input
10msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
BICK pin
LRCK pin
Input
BICK and LRCK input start
Figure 57. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4649VN.
(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM must first be powered up before the other block operates.
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 10ms (max).
(6) The normal clock is output from MCKO after PLL is locked.
(7) The invalid frequency is output from MCKO during this period.
(8) BICK and LRCK clocks must be synchronized with MCKO clock.
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4. EXT Slave Mode
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 1024fs
MCKO: Disable
Power Supply
PDN pin
PMVCM bit
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
(2)
(2) Addr:04H, Data:02H
Addr:05H, Data:27H
(3)
(Addr:00H, D6)
(4)
MCKI pin
Input
(3) Addr:00H, Data:40H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 58. Clock Set Up Sequence (4)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4649VN.
(2) DIF1-0 and FS1-0 bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM must first be powered up before the other block operates.
(4) Normal operation starts after the MCKI, LRCK and BICK are supplied.
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■ MIC Input Recording (Stereo)
FS3-0 bits
(Addr:05H, D5,D2-0)
X,XXX
Example:
1,111
PLL Master Mode
Audio I/F Format: MSB justified
Pre MIC Amp: +20dB
MIC Power ON
Sampling Frequency: 44.1kHz
ALC1 setting:Refer to Table 34
HPF1: fc=108.8Hz, ADRST bit = “1”
Programmable Filter OFF
(1)
MIC Control
(Addr:02H, D2-0
Addr: 03H, D5)
Timer Select
(Addr:06H)
ALC Control 2
(Addr:08H )
IVL7-0 bits
(Addr:09H)
ALC Control 3
(Addr:0BH, D7-6)
ALC Control 1
(Addr:07H)
Digital Filter Path
(Addr:26H)
Filter Select
(Addr:11H, 30H)
Filter Co-ef
(Addr:12-1FH, 28H,
32-4FH)
ALC1 State
X, XXX
0, 001
(2)
X, X...X
(1) Addr:05H, Data:27H
X, 1110000
(3)
XXH
(2) Addr:02H, Data:05H
Addr: 03H, Data: 00H
E1H
(4)
(3) Addr:06H, Data:F0H
E1H
XXH
(5)
(4) Addr:08H, Data:E1H
00
XX
(6)
(5) Addr:09H, Data:E1H
A1H
XXH
(13)
(7)
XXH
03H
(7) Addr:07H, Data:A1H
(8)
XX....X
XX....X
(8) Addr:26H, Data:03H
(9)
(9) Addr:28H, Data:80H
XX....X
XX....X
(10)
ALC1 Disable
(10) Addr:11H, Data:01H
ALC1 Enable
ALC1 Disable
PMPFIL bit
PMADL/R bit
(Addr:00H, D7, D0
Addr: 10H, D0)
SDTO pin
State
(6) Addr:0BH, Data:00H
(11) Addr:00H, Data:C1H
Addr: 10H, Data: 81H
Recording
(11)
0 data Output
267/fs or 1059/fs
(12)
Normal
Initialize
0 data output
Data Output
(12) Addr:00H, Data:40H
Addr: 10H, Data: 01H
(13) Addr:07H, Data:81H
Figure 59. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=44.1kHz. For changing the parameter of ALC, please refer to
“Figure 36. Registers Set-up Sequence at ALC1 Operation (recording path)”
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4649VN is PLL mode, MIC, ADC and Programmable
Filter must be powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC Gain (Addr = 02H, 03H)
(3) Set up ALC1 Timer and ADRST bit (Addr = 06H)
(4) Set up IREF value for ALC1 (Addr = 08H)
(5) Set up IVOL value at ALC1 operation start
(6) Set up LMTH1 and RGAIN1 bits (Addr = 0BH)
(7) Set up LFST, LMTH0, RGAIN0, LMAT1-0, ZELMN and ALC1 bits (Addr = 07H)
(8) Set up Programmable Filter Path: PFSDO = ADCPF bits = “1” (Addr = 26H)
(9) Set up Coefficient Programmable Filter (Addr = 12H ∼ 1FH, 28H, 32H ∼ 4FH)
(10) Set up of Programmable Filter ON/OFF
(11) Power Up MIC, ADC and Programmable Filter: PMADL =PMADR =PMPFIL bits = “0” →“1”
The initialization cycle time of ADC is 1059/fs=24ms @ fs=44.1kHz, ADRST bit = “0”. ADC outputs “0” data
during the initialization cycle. After the ALC1 bit is set to “1”, the ALC1 operation starts from IVOL value of
(4).
(12) Power Down MIC, ADC and Programmable Filter: PMADL =PMADR =PMPFIL bits = “1” → “0”
(13) ALC1 Disable: ALC1 bit = “1” → “0”
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■ Digital MIC Input Recording (Stereo)
FS3-0 bits
(Addr:05H, D5,D2-0)
X,XXX
1,111
Example:
(1)
Timer Select X,X...X
(Addr:06H)
ALC Control 2
(Addr:08H )
IVL7-0 bits
(Addr:09H)
ALC Control 3
(Addr:0BH, D7-6)
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 44.1kHz
Digital MIC setting:
D ata is latched on the DMCLK failing edge
Digital MIC Power Supply “Externally”
ALC1 setting:Refer to Table 34
HPF1: fc=108.8Hz, ADRST bit = “1”
Programmable Filter OFF
X, 1110000
(2)
XXH
E1H
(3)
(1) Addr:05H, Data:27H
E1H
XXH
(2) Addr:06H, Data:F0H
(4)
00
XX
(3) Addr:08H, Data:E1H
(5)
ALC Control 1
(Addr:07H)
Digital Filter Path
(Addr:26H)
Filter Select
(Addr:11H, 30H)
Filter Co-ef
(Addr:12-1FH, 28H,
32-4FH)
ALC1 State
(4) Addr:09H, Data:E1H
A1H
XXH
(6)
(14)
XXH
(5) Addr:07H, Data:A1H
03H
(7)
(6) Addr:0BH, Data:00H
XX....X
XX....X
(8)
(7) Addr:26H, Data:03H
XX....X
XX....X
(8) Addr:28H, Data:80H
(9)
ALC1 Disable
ALC1 Enable
ALC1 Disable
(9) Addr:11H, Data:01H
(10) Addr:00H, Data:C0H
PMPFIL bit
(Addr:00H, D7)
(13)
(10)
Digital MIC
0 X 00 XXXX
0 X 11 XXXX
0 X 00 XXXX
(Addr:27H)
(11)
267/fs or 1059/fs
(11) Addr:27H, Data:3BH
Recording
(12)
(12) Addr:27H, Data:0BH
SDTO pin
State
Normal
data ouput
0 data output
0 data output
(13) Addr:00H, Data:40H
(14) Addr:07H, Data:81H
Figure 60. Digital MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=44.1kHz. For changing the parameter of ALC, please refer to
“Figure 36. Registers Set-up Sequence at ALC1 Operation (recording path)”
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4649VN is PLL mode, Digital MIC and Programmable
Filter must be powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up ALC1 Timer and ADRST bit (Addr = 06H)
(3) Set up IREF value for ALC1 (Addr = 08H)
(4) Set up IVOL value at ALC1 operation start (Addr = 09H)
(5) Set up LMTH1 and RGAIN1 bits (Addr = 0BH)
(6) Set up LFST, LMTH0, RGAIN0, LMAT1-0, ZELMN and ALC1 bits (Addr = 07H)
(7) Set up Programmable Filter Path: PFSDO = ADCPF bits = “1” (Addr = 26H)
(8) Set up Coefficient of Programmable Filter (Addr = 12H ∼ 1FH, 28H, 32H ∼ 4FH)
(9) Set up Programmable Filter ON/OFF
(10) Power Up Programmable Filter: PMPFIL bit = “0” →“1”
(11) Set up & Power Up Digital MIC: PMDMR = PMDML bits = “0” →“1”
The initialization cycle time of ADC is 1059/fs=24ms @ fs=44.1kHz, .ADRST bit = “1”. ADC outputs “0” data
during initialization cycle. After the ALC1 bit is set to “1”, the ALC1 operation starts from IVOL value of (4).
(12) Power Down Digital MIC: PMDMR = PMDML bits = “1” →“0”
(13) Power Down Programmable Filter: PMPFIL bit = “1” → “0”
(14) ALC1 Disable: ALC1 bit = “1” → “0”
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■ Speaker-amp Output
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
1,111
(1)
(12)
DACS bit
(Addr:02H, D3)
(2)
SPKG1-0 bits
(Addr:03H, D4-3)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:0BH)
ALC Control 3
(Addr:07H)
OVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
00
01
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency:44.1KHz
Digital Volume: 0dB
ALC2: Enable
(3)
00H
3CH
(4)
28H
(1) Addr:05H, Data:27H
28H
(5)
(2) Addr:02H, Data:20H
00H
40H
(6)
(3) Addr:03H, Data:08H
91H
91H
(4) Addr:06H, Data:3CH
(7)
Digital Filter Path
(Addr:26H)
ALC2 State
00H
04H
(5) Addr:0BH, Data:28H
(8)
ALC2 Disable
ALC2 Disable
ALC2 Enable
(7) Addr:0AH & 0DH, Data:91H
(13)
PMPFIL bit
PMDAC bit
(6) Addr:07H, Data:40H
(8) Addr:26H, Data:04H
(Addr:00H, D2)
PMBP bit
(9) Addr:00H, Data:74H
(Addr:00H, D5)
(9)
PMSPK bit
(10) Addr:02H, Data:A0H
(Addr:00H, D4)
(10)
SPPSN bit
Playback
(Addr:02H, D7)
(11)
SPP pin
Hi-Z
Normal Output
Hi-Z
SVDD/2 Normal Output SVDD/2
Hi-Z
(11) Addr:02H, Data:20H
(12) Addr:02H, Data:00H
SPN pin
Hi-Z
(13) Addr:00H, Data:40H
Figure 61. Speaker-Amp Output Sequence
<Example>
At first, clocks must be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4649VN is PLL mode, DAC and Speaker-Amp must be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC → SPK-Amp”: DACS bit = “0” → “1”
(3) SPK-Amp gain setting: SPKG1-0 bits = “00” → “01”
(4) Set up Timer Select for ALC (Addr = 06H)
(5) Set up REF value for ALC, LMTH1 and RGAIN1 bits (Addr = 0BH)
(6) Set up LMTH0, RGAIN0, LMAT1-0, ALC2 bits (Addr = 07H)
(7) Set up the output digital volume (Addr = 0AH, 0DH).
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition. When ALC2
bit = “0”, it could be digital volume control.
(8) Set up Programmable Filter Path (PFDAC, ADCPF and PFSDO bits) (Addr = 26H)
(9) Power up DAC, MIN-Amp, Programmable Filter and Speaker:
PMDAC = PMPFIL = PMBP = PMSPK bits = “0” → “1”
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(10) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
“(9)” time depends on the time constant of external resistor and capacitor connected to the MIN pin. If
Speaker-Amp output is enabled before input of MIN-Amp becomes stable, pop noise may occur.
e.g. R=33kΩ, C=0.1μF: Recommended wait time is more than 5τ = 16.5ms.
(11) Enter Speaker-Amp Power-save-mode: SPPSN bit = “1” → “0”
(12) Disable the path of “DAC → SPK-Amp”: DACS bit = “1” → “0”
(13) Power down DAC, MIN-Amp Programmable Filter and Speaker:
PMDAC = PMPFIL = PMBP = PMSPK bits = “1” → “0”
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■Mono Signal Output from Speaker-Amp
Example:
Clocks can be stopped.
CLOCK
(1) Addr:00H, Data:70H
PMBP bit
(Addr:00H, D5)
(1)
(5)
(2) Addr:02H, Data:60H
PMSPK bit
(Addr:00H, D4)
DACS bit
(Addr:02H, D5)
" 0" or " 1"
(3) Addr:02H, Data:E0H
0
(2)
(6)
BEEPS bit
Mono Signal Output
(Addr:02H, D6)
(3)
SPPSN bit
(4) Addr:02H, Data:60H
(Addr:02H, D7)
(4)
SPP pin
SPN pin
Hi-Z
Hi-Z
Normal Output
SVDD/2
Normal Output
Hi-Z
SVDD/2
(5) Addr:00H, Data:40H
Hi-Z
(6) Addr:02H, Data:00H
Figure 62. “MIN-Amp Æ Speaker-Amp” Output Sequence
<Example>
The clocks can be stopped when only MIN-Amp and Speaker-Amp are operating.
(1) Power Up MIN-Amp and Speaker-Amp: PMBP = PMSPK bits = “0” → “1”
(2) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “0”
Enable the path of “MIN Æ SPK-Amp”: BEEPS bit = “0” → “1”
(3) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
“(3)” time depends on the time constant of external resistor and capacitor connected to MIN pin. If
Speaker-Amp output is enabled before input of MIN-Amp becomes stable, pop noise may occur.
e.g. R=33kΩ, C=0.1μF: Recommended wait time is more than 5τ = 16.5ms.
(4) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”
(5) Power Down MIN-Amp and Speaker-Amp: PMBP = PMSPK bits = “1” → “0”
(6) Disable the path of “MIN Æ SPK-Amp”: BEEPS bit = “1” → “0”
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■ Stereo Line Output
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
1,111
0,000
(1)
DACL bit
(Addr:0FH)
(10)
(1) Addr:05H, Data:27H
(2)
(Addr:02H, D4)
DVOL7-0 bits
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency:44.1KHz
Digital Volume 3: 0dB
MGAIN1=SPKG1=SPKG0=BEEPL bits = “0”
Programmable Filter OFF
(2) Addr:02H, Data:10H
FFH
FFH
(3) Addr:0FH, Data:FFH
(3)
Digital Filter Path
(Addr:26H)
00H
(4) Addr:26H, Data:00H
00H
(4)
(5) Addr:03H, Data:40H
LOPS bit
(6) Addr:00H, Data:6CH
(Addr:03H, D6)
(7)
(5)
(8)
(11)
PMDAC bit
(7) Addr:03H, Data:00H
(Addr:00H, D2)
Playback
PMBP bit
(Addr:00H, D5)
(6)
(9)
PMLO bit
(Addr:00H, D3)
LOUT pin
ROUT pin
(8) Addr:03H, Data:40H
(9) Addr:00H, Data:40H
>300 ms
Normal Output
>300 ms
(10) Addr:02H, Data:00H
(11) Addr:03H, Data:00H
Figure 63. Stereo Lineout Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4646 is PLL mode, DAC and Stereo Line-Amp must
be powered-up in consideration of PLL lock time after the sampling frequency is changed.
(2) Set up the path of “DAC Æ Stereo Line Amp”: DACL bit = “0” Æ “1”
(3) Set up the output digital volume3 (Addr = 0FH)
(4) Set up the path of Programmable Filter (PFDAC, ADCPF and PFSDO bits) (Addr = 26H)
(5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0” Æ “1”
(6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “0” → “1”
LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time to 99% VCOM
voltage is 300ms (max) at C=1μF and RL=10kΩ.
(7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit must be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation by
setting LOPS bit to “0”.
(8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1”
(9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “1” → “0”
LOUT and ROUT pins fall down to 1% VCOM voltage. Fall time is 300ms (max) at C=1μF and RL=10kΩ.
(10) Disable the path of “DAC Æ Stereo Line-Amp”: DACL bit = “1” Æ “0”
(11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit must be set to “0” after LOUT and ROUT pins fall down.
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■ Stop of Clock
Master clock can be stopped when ADC, DAC, Digital MIC and Programmable Filter are not used.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"0" or "1"
(1) (2) Addr:01H, Data:08H
(Addr:01H, D1)
External MCKI
(3)
Input
(3) Stop an external MCKI
Figure 64. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (LRCK or BICK pin)
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1)
PMPLL bit
(Addr:01H, D0)
(2)
External BICK
Input
(1) Addr:01H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 65. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
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3. PLL Slave (MCKI pin)
Example
(1)
PMPLL bit
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
(Addr:01H, D0)
(1)
MCKO bit
(1) Addr:01H, Data:00H
(Addr:01H, D1)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 66. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
4. EXT Slave Mode
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format :MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
(1)
(1) Stop the external clocks
Figure 67. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
■ Power down
Power supply current can be shut down (typ. 1μA) by stopping clocks and setting PMVCM bit = “0” after all blocks
except for VCOM are powered-down. Power supply current can be also shut down (typ. 1μA) by stopping clocks and
setting PDN pin = “L”. When PDN pin = “L”, the registers are initialized.
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PACKAGE (AK4649VN)
32pin QFN (Unit: mm)
5.0 ± 0.1
3.15 ± 0.15
17
24
A
Exposed
Pad
32
9
8
B
0.25 +0.05
-0.07
0.40 ± 0.10
25
3.15 ± 0.15
5.0 ± 0.1
16
1
C0.35
C
0.5
0.75 ± 0.05
0.08 C
Note: The exposed pad on the bottom surface of the package must be connected to the ground.
■ Material & Lead finish
Package molding compound: Epoxy
Lead frame material: Cu
Inner plating: Ni/Pd/Au-Ag
Outer plating: Ni/Pd/Au
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MARKING(AK4649VN)
4649VN
XXXX
1
“4649VN”：Market Number
XXXX：Date code (4 digit)
●：Pin #1 indication
REVISION HISTORY
Date (Y/M/D)
13/01/09
Revision
00
Reason
First Edition
Page
Contents
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IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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