INTERSIL 5962F9666301QEC

HS-26C31RH
®
Data Sheet
May 27, 2010
Radiation Hardened Quad Differential Line
Driver
The Intersil HS-26C31RH is a quad differential line driver
designed for digital data transmission over balanced lines
and meets the requirements of EIA standard RS-422.
Radiation hardened CMOS processing assures low power
consumption, high speed, and reliable operation in the most
severe radiation environments.
The HS-26C31RH accepts CMOS signal levels and converts
them to RS-422 compatible outputs. This circuit uses special
outputs that enable the drivers to power-down without loading
down the bus. Enable and disable pins allow several devices to
be connected to the same data source and addressed
independently.
Specifications
FN3401.5
Features
• Electrically Screened to SMD # 5962-96663
• QML Qualified per MIL-PRF-38535 Requirements
• 1.2 Micron Radiation Hardened CMOS
- Total Dose Up to . . . . . . . . . . . . . . . . . . . . 300kRAD(Si)
• Latchup Free
• EIA RS-422 Compatible Outputs (Except for IOS)
• CMOS Inputs
• High Impedance Outputs when Disabled or Powered
Down
• Low Power Dissipation . . . . . . . . . 2.75mW Standby (Max)
• Single 5V Supply
• Low Output Impedance . . . . . . . . . . . . . . . . . 10Ω or Less
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96663. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/military/
• Full -55°C to +125°C Military Temperature Range
Applications
• Line Transmitter for MIL-STD-1553 Serial Data Bus
Ordering Information
ORDERING
NUMBER
INTERNAL
MKT. NUMBER
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG.
DWG. #
5962F9666301QEC
HS1-26C31RH-8
Q 5962F96 6630QEC
-55 to +125
16 LD SBDIP
D16.3
5962F9666301QXC
HS9-26C31RH-8
Q 5962F96 66301QXC
-55 to +125
16 LD FLATPACK
K16.A
5962F9666301VEC
HS1-26C31RH-Q
Q 5962F96 66301VEC
-55 to +125
16 LD SBDIP
D16.3
5962F9666301VXC
HS9-26C31RH-Q
Q 5962F96 66301VXC
-55 to +125
16 LD FLATPACK
K16.A
HS1-26C31RH/PROTO
HS1-26C31RH/PROTO
HS1- 26C31RH/PROTO
-55 to +125
16 LD SBDIP
D16.3
HS9-26C31RH/PROTO
HS9-26C31RH/PROTO
HS9- 26C31RH/PROTO
-55 to +125
16 LD FLATPACK
K16.A
5962F9666301V9A
HSO-26C31RH-Q
1
-55 to +125
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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respective owners.
HS-26C31RH
Pinouts
HS1-26C31RH
(16 LD SBDIP) CDIP2-T16
TOP VIEW
HS9-26C31RH
(16 LD FLATPACK) CDFP4-F16
TOP VIEW
16 VDD
AIN
1
16
VDD
AO 2
15 DIN
AO
2
15
DIN
AO 3
14 DO
AIN 1
13 DO
ENABLE 4
BO 5
12 ENABLE
BO 6
11 CO
BIN 7
10 CO
GND 8
9 CIN
AO
3
14
DO
ENABLE
4
13
DO
BO
5
12
ENABLE
BO
6
11
CO
BIN
7
10
CO
GND
8
9
CIN
Logic Diagram
ENABLE
ENABLE
DIN
CIN
BIN
AIN
DO DO
CO CO
BO BO
AO AO
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
2
FN3401.5
May 27, 2010
HS-26C31RH
Die Characteristics
DIE DIMENSIONS:
Substrate:
96.5 mils x 195 mils x 21 mils
(2450 x 4950)
AVLSI1RA
Backside Finish:
INTERFACE MATERIALS:
Silicon
Glassivation:
ASSEMBLY RELATED INFORMATION:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 10kÅ ±1kÅ
Substrate Potential (Powered Up):
VDD
Metallization:
ADDITIONAL INFORMATION:
M1: Mo/TiW
Thickness: 5800Å
M2: Al/Si/Cu (Top)
Thickness: 10kÅ ±1kÅ
Worst Case Current Density:
<2.0x105A/cm2
Bond Pad Size:
110µmx100µm
Metallization Mask Layout
(15) DIN
(16) VDD
(1) AIN
(16) VDD
HS-26C31RH
AO (2)
(14) DO
AO (3)
(13) DO
(12) ENABLE
ENABLE (4)
3
CIN (9)
(10) CO
GND (8)
BO (6)
GND (8)
(11) CO
BIN (7)
BO (5)
FN3401.5
May 27, 2010