® CT T O D U C EM E N t R P E A ra T L e nt e OL E R EP OBS ENDED upport C om/tsc M S il.c COM chnical w.inters E R e NO ur T L or w w I act o cont -INTERS 8 8 1-8 8-Bit, 75 MSPS, Flash A/D Converter March 2003 Features • • • • Differential Linearity Error ±0.5 LSB or Less Integral Linearity Error ±0.5 LSB or Less Built-In Integral Linearity Compensation Circuit High-Speed Operation with Maximum Conversion Rate (Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MSPS • • • • • • • • Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . 17pF Wide Analog Input Bandwidth (Min for Full Scale Input) 150MHz Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.2V Low Power Consumption (Typ) . . . . . . . . . . . . . . . . . . . . . 580mW Low Error Rate Operable at 50% Clock Duty Cycle Capable of Driving 50Ω Loads Direct Replacement for CXA1386 Applications • • • • • • • HI1386 Video Digitizing RGB Graphics Processing HDTV (High Definition TV) Radar Systems Communication Systems Direct RF Down-Conversion Digital Oscilloscopes Description The HI1386 is an 8-bit, high-speed flash analog-to-digital converter IC capable of digitizing analog signals at a maximum rate of 75 MSPS. The digital I/O levels of this A/D converter are compatible with ECL 100K/10KH/10K. The HI1386 is available in the commercial and industrial temperature range and is supplied in 28 lead plastic DIP and 44 lead ceramic LCC packages. Part Number Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. HI1386JCP -20 to 75 28 Ld PDIP E28.6A-S HI1386AIL -20 to 100 44 Ld CLCC J44.B Pinouts (LSB) D0 4 26 AVEE 25 AGND AVEE 2 AVEE 3 NC 4 VRT 5 NC 6 AVEE LINV 27 VRT DGND 3 NC 28 AVEE DVEE LINV 1 DVEE 2 DGND1 HI1386 (CLCC) TOP VIEW DGND2 HI1386 (PDIP) TOP VIEW 1 44 43 42 41 40 NC 7 39 NC (LSB) D0 8 38 NC D1 5 24 VIN D1 9 37 AGND D2 6 23 AGND D2 10 36 VIN D3 7 22 VRM D3 11 35 AGND D4 12 34 VRM D5 13 33 AGND D6 14 32 VIN 21 AGND MINV 14 15 CLK CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 1 29 NC 18 19 20 21 22 23 24 25 26 27 28 AVEE 16 CLK AVEE DVEE 13 30 NC NC 17 NC 17 VRB VRB DGND 12 31 AGND DGND2 16 NC 18 AVEE CLK (MSB) D7 11 (MSB) D7 15 CLK 19 AGND MINV D6 10 DVEE 20 VIN NC D5 9 DGND1 D4 8 FN3583.5 HI1386 Functional Block Diagram MINV R1 COMPARATOR VRT R/2 R 1 R D7 (MSB) 2 R D6 63 D5 R 64 VIN R D4 65 OUTPUT D3 R 126 D2 R 127 R2 VRM ENCODE LOGIC R D1 128 R D0 (LSB) 129 R 191 R 192 VIN R 193 R 254 R 255 VRB CLK CLK R3 R/2 CLOCK DRIVER LINV 2 HI1386 Pin Descriptions PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 19, 21, 23, 25 31, 33, 35, 37 AGND - 0V Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND, DGND1, and DGND2. 18, 26, 28 27, 28, 40, 41, 44 AVEE - -5.2V Analog VEE -5.2V (Typ). Internally connected to DVEE (Resistance: 4Ω to 6Ω). Bypass with 0.1µF to AGND. 16 23 CLK I ECL EQUIVALENT CIRCUIT DESCRIPTION CLK Input. DGND, DGND1 15 22 CLK R Input Complementary to CLK. When open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation. R R R CLK CLK R DVEE R 3, 12 - DGND - 0V Digital GND (used for internal circuits and output transistors). - 5, 19 DGND1 - 0V Digital GND (used for internal circuits and output transistors). - 6, 16 DGND2 - 0V Digital GND (used for output buffers). 2, 13 4, 20 DVEE - -5.2V Digital VEE . Internally connected to AVEE (resistance: 4Ω to 6Ω). Bypass with 0.1µF to DGND 4 8 D0 O ECL DGND 5 9 D1 6 10 D2 7 11 D3 8 12 D4 9 13 D5 10 14 D6 11 15 D7 LSB of Data Outputs. External pull-down resistor is required. Data Outputs. External pull-down resistors are required. D1 DVEE 3 MSB of Data Outputs. External pull-down resistor is required. HI1386 Pin Descriptions (Continued) PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 1 3 LINV I ECL EQUIVALENT CIRCUIT DESCRIPTION Input Pin for D0 (LSB) to D6 Output Polarity Inversion (see A/D Output Code Table). Pulled low when left open. DGND, DGND1 14 21 MINV I ECL Input Pin for D7 (MSB) Output Polarity Inversion (see A/D Output Code Table). Pulled low when left open. R R 20, 24 32, 36 VIN I LINV OR MINV R DVEE R -1.3V VRT to VRB AGND VIN Analog Input Pins. These two pins must be connected externally, since they are not internally connected. See Application Note for precautions. VIN AVEE 17 26 VRB I VRM I -2V VRT Reference Voltage (Bottom). Typically -2V. Bypass with a 0.1µF and 10µF to AGND. R1 R/2 22 34 VRB/2 R COMPARATOR 1 Reference Voltage Mid Point. Can be used as a pin for integral linearity compensation. R 27 42 VRT I 0V COMPARATOR 2 R VRM COMPARATOR 127 R2 R COMPARATOR 128 R COMPARATOR 129 R COMPARATOR 130 R COMPARATOR 255 VRB R3 4 R/2 Reference Voltage (Top) Typically 0V. HI1386 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . -7V to +0.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT , VRB , VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V |VRT -VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage CLK, CLK, MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V |CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7) . . . . . . . . . . . . . . . -30mA to 0mA Thermal Resistance (Typical, Note 1) θJAoC/W θJCoC/W PDIP Package . . . . . . . . . . . . . . . . . . . 58 N/A CLCC Package . . . . . . . . . . . . . . . . . . 45 11 Maximum Junction Temperature CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC Operating Conditions Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Pulse Width of Clock tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min) tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min) Temperature Ranges (Note 4) PDIP Package (TA). . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CLCC Package (TC) . . . . . . . . . . . . . . . . . . . . . . . -20oC to100oC Supply Voltage AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNIT - 8 - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL fC = 75MHz - ±0.3 ±0.5 LSB Differential Linearity Error, DNL fC = 75MHz - ±0.3 ±0.5 LSB Signal to Noise and Distortion Ratio, SINAD Input = 1MHz, Full Scale fC = 75MHz RMS Signal = -----------------------------------------------------------------RMS Noise + Distortion Input = 18.75MHz, Full Scale fC = 75MHz - 46 - dB - 40 - dB Error Rate Input = 18.749MHz, Full Scale Error > 16 LSB, fC = 75MHz - - 10-9 TPS (Note 2) Differential Gain Error, DG - 1.0 - % Differential Phase Error, DP NTSC 40 IRE Mod. Ramp, fC = 75 MSPS Maximum Conversion Rate, fC Error Rate of 10-9 TPS (Note 2) DYNAMIC CHARACTERISTICS - 0.5 - Degree 75 - - MSPS Aperture Jitter, tAJ - 10 - ps Sampling Delay, tDS - 3.0 - ns 150 - - MHz - 17 - pF - 390 - kΩ - - 200 µA 75 110 155 Ω ANALOG INPUT Input Bandwidth VIN = 2VP-P (-3dB) Analog Input Capacitance, CIN VIN = 1V + 0.07VRMS Analog Input Resistance, RIN Input Bias Current, IIN VIN = -1V REFERENCE INPUTS Reference Resistance, RREF 5 HI1386 Electrical Specifications TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Offset Voltage EOT VRT 8 18 32 mV EOB VRB 0 10 24 mV Logic H Level, VIH -1.13 - - V Logic L Level, VIL - - -1.50 V DIGITAL INPUTS Logic H Current, IIH -0.8V is Applied to Input 0 - 50 µA Logic L Current, IIL -1.6V is Applied to Input -50 - 50 µA - 7 - pF Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH RL = 620Ω to DVEE -1.03 - - V Logic L Level, VOL RL = 620Ω to DVEE - - -1.62 V H Pulse Width of Clock, tPW1 6.6 - - ns L Pulse Width of Clock, tPW0 6.6 - - ns - 0.9 - ns TIMING CHARACTERISTICS Output Rise Time, tr RL = 620Ω to DVEE , 20% to 80% Output Fall Time, tf RL = 620Ω to DVEE , 20% to 80% Output Delay, tOD - 2.1 - ns 4.0 6.5 9.0 ns -150 -104 - mA - 580 - mW POWER SUPPLY CHARACTERISTICS Supply Current, IEE Note 3 Power Consumption, PD NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. 2 3. ( V RT -V RB ) P D = I EE • V EE + -----------------------------------R REF 4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed. Timing Diagram tDS ANALOG IN N+1 N N+2 tPW1 tPW0 CLK CLK DIGITAL OUT N-1 20% tOD 80% tr FIGURE 1. 6 N 80% N+1 20% tf HI1386 A/D OUTPUT CODE TABLE VIN (NOTE 1) MINV 1 LINV 1 STEP 0V -1V D7 0 1 D0 D7 1 0 D0 D7 0 0 D0 D7 D0 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11 0 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11 1 000 • • • • • 01 100 • • • • • 01 011 • • • • • 10 111 • • • • • 10 • • • • • • • • • • • • 127 011 • • • • • 11 111 • • • • • 11 000 • • • • • 00 100 • • • • • 00 128 100 • • • • • 00 000 • • • • • 00 111 • • • • • 11 011 • • • • • 11 • • • • • • • • • • • • 254 111 • • • • • 10 011 • • • • • 10 100 • • • • • 01 000 • • • • • 01 255 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00 -2V NOTE: 5. VRT = 0V, VRB = -2V. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7