Documentation Addendum, V2.0, Apr. 2008 TC1766 32-Bit Single-Chip Microcontroller Microcontrollers Edition 2008-04 Published by Infineon Technologies AG, 81726 München, Germany © Infineon Technologies AG 2008. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Documentation Addendum, V2.0, Apr. 2008 TC1766 32-Bit Single-Chip Microcontroller Microcontrollers TC1766 TC1766 Documentation Addendum Revision History: V2.0 2008-04 Previous Versions: V1.0, V1.1, V1.2 Page Subjects (major changes since last revision) – This is the first release that refers to the TC1766 User’s Manual V2.0, July 2007 Trademarks TriCore® is a trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Documentation Addendum V2.0, 2008-04 TC1766 Table of Contents Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 User’s Manual - System Units Part (Volume 1) . . . . . . . . . . . . . . . . . . . . 4 Page 3-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Page 6-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Page 7-34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Page 7-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Page 7-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Page 8-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Page 9-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Page 10-109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Page 11-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 User’s Manual - Peripheral Units Part (Volume 2) . . . . . . . . . . . . . . . . Page 17-37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18-34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19-69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20-39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20-68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20-113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21-29, 21-34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21-75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21-80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21-102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21-103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Documentation Addendum 1 14 14 14 15 15 15 15 15 15 15 15 15 15 16 16 17 17 17 17 17 18 18 18 18 18 18 18 18 19 V2.0, 2008-04 TC1766 Table of Contents Page 22-164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 22-228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 23-91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 24-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 24-37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 24-50, 24-51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 24-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Documentation Addendum 2 19 19 19 20 21 21 21 V2.0, 2008-04 TC1766 Introduction 1 Introduction This document describes corrections, changes, and improvements for the TC1766 User’s Manual V2.0 2007-07, the System Units (Volume 1) and the Peripheral Units (Volume 2). These changes will be included in the next update of the User’s Manual. The referenced documents to this addendum are located at the Internet page: • • www.infineon.com/tc1766 TC1766 User’s Manual System and Peripheral Units , V2.0, July 2007 Documentation Addendum 3 V2.0, 2008-04 TC1766 CONFIDENTIAL 2 User’s Manual - System Units Part (Volume 1) User’s Manual - System Units Part (Volume 1) This section describes the updates for the System Units of the User‘s Manual. Page 3-19 Section 3.2.2.5 “Setting up the PLL after Reset” must be updated. Points 1. to 7. of this section must be replaced by the following 9 points (red text indicates the changes): 1. 2. 3. 4. 5. 6. 7. 8. 9. Wait until the oscillator is running (OSC_CON.OSCR = 1) Selection of the VCO Bypass Mode (PLL_CLC.VCOBYP = 1) Selecting the VCO band by programming PLL_CON.VCOSEL Program the desired P, N and K values (PDIV, NDIV, and KDIV bit fields of register PLL_CLC) to get a temporary fCPU value which is lower than the target frequency.1) Connect the oscillator to the PLL (PLL_CLC.OSCDISC = 0) Wait until the PLL becomes locked (PLL_CLC.LOCK = 1) Disable the VCO Bypass Mode (PLL_CLC.VCOBYP = 0) Wait for typically 5ms until supply ripple caused by increased supply current is faded away. Decrease K value step by step, with wait phases in between, until the targeted fCPU is reached. Page 6-12 The first line in the description for bit field LEDAT[31:0] must be corrected into “LMB Data Bits [31:0]” instead of “LMB Bus Address Bits [31:0]“. The first line in the description for bit field LEDAT[63:32] must be corrected into “LMB Data Bits [63:32]” instead of “LMB Bus Address Bits [31:0]“. Page 7-34 The note at the end of the page must be erased: “Note: After the detection …”. Page 7-35 The second sentence of the first paragraph must be erased: “With this features, problematic …” Paragraphs 3 to 6 must be erased: “Since problematic Flash array bits …” until “… of Flash cells is close to the zero state”. 1) K value selection should result in a small change of fCPU when bypass mode is left to reduce supply ripple Documentation Addendum 4 V2.0, 2008-04 TC1766 User’s Manual - System Units Part (Volume 1) Page 7-36 The following section must be added to the top of page: 7.2.8.3 Application Hints Flash Error Handling The previous sections described shortly the functionality of “error indicating” bits in the flash status register FSR. This section gives recommendations how these should be handled by customer software. PFOPER/DFOPER “Operation Error” Fault conditions: ECC double-bit error detected in Flash microcode SRAM during a program or erase operation in PFlash or DFlash. This can be a transient event due to alpha-particles or illegal operating conditions or it is a permanent error due to a hardware defect. This situation will practically not occur. These bits can also be set in case of uncritical errors that don’t affect Flash operation. This case is much more likely than real operation errors. Attention: these bits can also be set during startup. New state: If triggered by Flash operation this is aborted, the BUSY flag is cleared and read mode is entered. Proposed handling by software: The DFOPER and PFOPER flags should be ignored for the possibility of flagging an error which is not related to a Flash write or erase operation. By checking the result of an operation (e.g. checking programmed data) a real operation error can be easily determined. When a real operation error is determined a reset should be applied before trying the operation again. Note: Even when the flag is ignored it is recommended to clear it. Otherwise all following operations — including “sleep” — could trigger an interrupt even when they are successful. VER “Verification Error” Fault conditions: This flag is a warning indication and not an error. It is set when a program or erase operation was completed but with a suboptimal result. This bit is already set when only a single bit is left over-erased or weakly programmed which would be corrected by the ECC anyhow. However excessive VER occurrence can be caused by operating the Flash out of the specified limits, e.g. incorrect voltage or temperature. A VER after programming can also be caused by programming a page whose sector was not erased correctly (e.g. aborted erase due to power failure). Under correct operating conditions a VER after programming will practically not occur. A VER after erasing is not unusual. Documentation Addendum 5 V2.0, 2008-04 TC1766 CONFIDENTIAL User’s Manual - System Units Part (Volume 1) New state: No state change. Just the bit is set. Proposed handling by software: This bit can be ignored. It should be cleared with “Clear Status” or “Reset to Read”. Inspec operation of the Flash memory must be ensured. If the application allows (timing and data logistics), a more elaborate procedure can be used to get rid of the VER situation: • • VER after program: erase the sector and program the data again. This is only recommended when there are more than 3 program VERs in the same sector. When programming the DFlash in field (EEPROM emulation) ignoring program VER is normally the best solution because its most likely cause are violated operating conditions. Take care that never a sector is programmed in which the erase was aborted. In the EEPROM emulation the algorithm must ensure this e.g. by programming a marker after finishing successfully the erase. VER after erase: the erase operation can be repeated until VER disappears. Repeating the erase more than 3 times consecutively for the same sector is not recommended. After that it is better to ignore the VER, program the data and check its readability. Again for EEPROM emulation its most likely cause are violated operating conditions. Therefore it is recommended to repeat the erase at most once or ignore it altogether. For optimizing the quality of Flash programming see the following section about handling single-bit ECC errors. Note: Even when this flag is ignored it is recommended to clear it. Otherwise all following operations — including “sleep” — could trigger an interrupt even when they are successful. PFSBER/DFSBER “Single-Bit Error” Fault conditions: When reading data or fetching code from PFlash or DFlash the ECC evaluation detected a single-bit error (“SBE”) which was corrected. This flag is a warning indication and not an error. A certain amount of single-bit errors must be expected because of known physical effects. New state: No state change. Just the bit is set. Proposed handling by software: This flag can be used to analyze the state of the Flash memory. During normal operation it should be ignored. In order to count single-bit errors it must be cleared by “Clear Status” or “Reset to Read” after each occurrence. Documentation Addendum 6 V2.0, 2008-04 TC1766 User’s Manual - System Units Part (Volume 1) Usually it is sufficient after programming data to compare the programmed data with its reference values ignoring the SBE bits. When there is a comparison error the sector is erased and programmed again. When programming the PFlash (end-of-line programming or SW updates) customers can further reduce the probability of future read errors by performing the following check after programming: • • • • • Change the read margin to “high margin 0”. Verify the data and count the number of SBEs. When the number of SBEs exceeds a certain limit (e.g. 10 in 2 MByte) the affected sectors could be erased and programmed again. Repeat the check for “high margin 1”. Each sector should be reprogrammed at most once, afterwards SBEs can be ignored. In case of EEPROM emulation using DFlash the verification of programmed data should be done with the normal read level and SBEs should be ignored. When a comparison error is found the sector can usually not be erased because it contains active data in other pages. The emulation algorithm can mark the affected page as invalid and program the data to a following page. As always the number of consecutive repetitions should be limited (e.g. to 3) as protection against violated operating conditions. To keep the EEPROM emulation alive even when wordline (two consecutive pages, even followed by odd pages) oriented fails occur (e.g. due to over-cycling) the algorithm can implement the following scheme for highest possible robustness: • • • • Before programming a page save the content of the other page on the same wordline in SRAM. Program the new page and compare the content with the reference data. This can be done with normal read margins. Ignore SBEs. If the data comparison fails program this page and the saved content of the other page to a different wordline. This procedure can be repeated if the data comparison fails again. The number of repetitions should be limited (e.g. to 3) in case the programming fails because of outof-spec operating conditions. Due to the specificity of each application the appropriate usage and implementation of these measures (together with the more elaborate VER handling) must be chosen according to the context of the application. Documentation Addendum 7 V2.0, 2008-04 TC1766 CONFIDENTIAL User’s Manual - System Units Part (Volume 1) Page 8-17 With the addition of possible memory access for OVRAM, Table 8-5 must be replaced by the below table: Table 8-5 Possible Memory Accesses Memory Bit Byte Half-word Word Double-word rmw r w r w r w r w PMI1) SPRAM ✔ ✔ – ✔ ✔ ✔ ✔ ✔ ✔ DMI1) LDRAM ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ PMU ROM – ✔ – ✔ – ✔ – ✔ – PFLASH – ✔ – ✔ – ✔ ✔ ✔ ✔ DFLASH – ✔ – ✔ – ✔ ✔ ✔ ✔ OVRAM1) – ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ PCP2) CRAM – – – – – ✔ ✔ ✔ ✔ PRAM – – – – – ✔ ✔ ✔ ✔ 1) The module also supports LMB 2-Word and 4-Word Block read and write accesses. 2) The module also supports FPI 4-Word and 8-Word Block read and write accesses. Documentation Addendum 8 V2.0, 2008-04 TC1766 User’s Manual - System Units Part (Volume 1) Page 9-47 Table 9-13 should be replaced as below: Table 9-13 Port Pin I/O P3.0 I O P3.1 I O Port 3 Functions Pin Functionality Associated Reg./ I/O Line General-purpose input P3_IN.P0 ASC0 input RXD0A General-purpose output P3_OUT.P0 Port I/O Control Select. Reg./Bit Field P3_IOCR0.PC0 Value 0XXXB 1X00B ASC0 output (Synchronous RXD0A Mode only)1) 1X01B Reserved2) – 1X11B General-purpose input P3_IN.P1 SCU input OSCBYP General-purpose output P3_OUT.P1 1X00B ASC0 output1) TXD0A 1X01B 1X10B P3_IOCR0.PC1 0XXXB 1X10B 2) P3.2 I O P3.3 I Reserved – 1X11B General-purpose input P3_IN.P2 SSC0 input (Slave Mode) SCLK0 General-purpose output P3_OUT.P2 1X00B SSC0 output (Master Mode)1) SCLK0 1X01B Reserved2) – General-purpose input P3_IN.P3 P3_IOCR0.PC2 0XXXB 1X10B 1X11B P3_IOCR0.PC3 0XXXB SSC0 input (Master Mode) MRST0 O General-purpose output P3_OUT.P3 1X00B SSC0 output (Slave Mode)1) MRST0 1X01B Reserved2) – Documentation Addendum 1X10B 9 1X11B V2.0, 2008-04 TC1766 CONFIDENTIAL Table 9-13 Port Pin I/O P3.4 I P3.6 P3.7 Port 3 Functions (cont’d) Pin Functionality Port I/O Control Select. Reg./Bit Field Value P3_IN.P4 SSC0 input (Slave Mode) MTSR0 General-purpose output P3_OUT.P4 1X00B SSC0 output (Master Mode)1) MTSR0 1X01B Reserved 2) – I General-purpose input P3_IN.P5 O General-purpose output P3_OUT.P5 1X00B SSC0 output SLSO00 1X01B SSC1 output SLSO10 1X10B SSC0 and SSC1 output SLSO00 AND SLSO103) 1X11B I General-purpose input P3_IN.P6 O General-purpose output P3_OUT.P6 SSC0 output SLSO01 1X01B SSC1 output SLSO11 1X10B SSC0 and SSC1 output SLSO01 AND SLSO113) 1X11B General-purpose input P3_IN.P7 SSC0 input SLSI0 General-purpose output P3_OUT.P7 1X00B SSC0 output SLSO02 1X01B SSC1 output SLSO12 1X10B Reserved – 1X11B I General-purpose input P3_IN.P8 O General-purpose output P3_OUT.P8 1X00B SSC0 output SLSO06 1X01B ASC1 output TXD1A 1X10B Reserved2) – 1X11B I O 2) P3.8 Associated Reg./ I/O Line General-purpose input O P3.5 User’s Manual - System Units Part (Volume 1) Documentation Addendum P3_IOCR4.PC4 0XXXB 1X10B 10 1X11B P3_IOCR4.PC5 0XXXB P3_IOCR4.PC11 x P3_IOCR4.PC7 P3_IOCR8.PC8 0XXXB 1X00B 0XXXB 0XXXB V2.0, 2008-04 TC1766 User’s Manual - System Units Part (Volume 1) Table 9-13 Port Pin I/O P3.9 I O P3.10 I O Port 3 Functions (cont’d) Pin Functionality Associated Reg./ I/O Line General-purpose input P3_IN.P9 ASC1 input RXD1A General-purpose output P3_OUT.P9 Port I/O Control Select. Reg./Bit Field Value P3_IOCR8.PC9 0XXXB 1X00B ASC1 output (Synchronous RXD1A Mode only)1) 1X01B Reserved2) – 1X11B General-purpose input P3_IN.P10 SCU input REQ0 General-purpose output P3_OUT.P10 1X00B Reserved2) – 1X01B 1X10B P3_IOCR8.PC10 0XXXB 1X10B 1X11B P3.11 I O General-purpose input P3_IN.P11 SCU input REQ1 General-purpose output P3_OUT.P11 1X00B – 1X01B 2) Reserved P3_IOCR8.PC11 0XXXB 1X10B 1X11B P3.12 I General-purpose input P3_IN.P12 P3_IOCR12.PC12 0XXXB CAN node 0 receive input 0 RXDCAN0 CAN node 1 receive input 1 O ASC0 input RXD0B General-purpose output P3_OUT.P12 1X00B ASC0 output (Synchronous RXD0B Mode only)1) 1X01B Reserved2) 1X11B Documentation Addendum – 11 1X10B V2.0, 2008-04 TC1766 CONFIDENTIAL Table 9-13 Port Pin I/O P3.13 I O P3.14 I User’s Manual - System Units Part (Volume 1) Port 3 Functions (cont’d) Pin Functionality Associated Reg./ I/O Line Port I/O Control Select. Reg./Bit Field Value General-purpose input P3_IN.P13 P3_IOCR12.PC13 General-purpose output P3_OUT.P13 1X00B CAN node 0 output TXDCAN0 1X01B ASC0 output TXD0B 1X10B Reserved2) – 1X11B General-purpose input P3_IN.P14 P3_IOCR12.PC14 0XXXB 0XXXB CAN node 1 receive input 0 RXDCAN1 CAN node 0 receive input 1 O P3.15 I O ASC1 output RXD1B General-purpose output P3_OUT.P14 1X00B ASC1 output RXD1B 1) (Synchronous Mode only) 1X01B Reserved2) – 1X11B General-purpose input P3_IN.P15 General-purpose output P3_OUT.P15 1X00B CAN node 1output RXDCAN1 1X01B ASC1 output TXD1B 1X10B Reserved2) – 1X11B 1X10B P3_IOCR12.PC15 0XXXB 1) The ALT1 and ALT2 for this pin are connected together. There are no dependencies. Either one can be chosen. 2) The port I/O control values P3_IOCRx.Py that are assigned to this reserved alternate output control selection should not be used. Otherwise, unpredictable output port line behavior may occur. 3) The AND-gate of ALT3 is located in the GPIO module. Documentation Addendum 12 V2.0, 2008-04 TC1766 User’s Manual - System Units Part (Volume 1) Page 10-109 In Table 10-15, the number of clock cycles for the stated instructions must be corrected as below: Table 10-15 Instruction Timing Instruction Number of Clock Cycles Comments Notes MCLR.PI 6 – – MSET.PI 6 – – ST.PI 4 – – XCH.PI 5 – – 11 – – PRAM Access Complex Maths MSETP.U On Page 10-111, the last row of footnote 7 must be changed to “32 x 32 bit multiply requires instruction MINIT + 4 x MSTEP.U = 1+4 x 11 = 45 cycles”. Page 11-35 The first bulleted point must be changed to “The activation of the interrupt corresponding to the current active channel 0n using the Interrupt Pointer defined in CHICR0n.INTP.”. Documentation Addendum 13 V2.0, 2008-04 TC1766 CONFIDENTIAL 3 User’s Manual - Peripheral Units Part (Volume 2) User’s Manual - Peripheral Units Part (Volume 2) This section describes the updates for the Peripheral Units of the User‘s Manual. Page 17-37 Table 17-8 should be replaced as below: Table 17-8 ASC0/ASC1 I/O Control Selection and Setup I/O Module Port Lines PISEL Register Input/Output Control Register Bits1) ASC0 P3.0/RXD0A ASC0_PISEL.RIS = 0 P3_IOCR0.PC0 = 0XXXB P3.0/RXD0A – Input P3_IOCR0.PC0 = 1X01B or Output 2) 1X10B P3.12/RXD0B ASC0_PISEL.RIS = 1 P3_IOCR12.PC12 = 0XXXB Input P3.12/RXD0B – P3_IOCR12.PC12 = 1X01B Output 2) or 1X10B P3.1/TXD0A P3_IOCR0.PC1 = 1X01Bor 1X10B – P3.13/TXD0B – ASC1 Output P3_IOCR12.PC13 = 1X10B Output P3.9/RXD1A ASC1_PISEL.RIS = 0 P3_IOCR8.PC9 = 0XXXB P3.9/RXD1A – P3_IOCR8.PC9 = 1X01Bor 1X10B Input Output 2) P3.14/RXD1B ASC1_PISEL.RIS = 1 P3_IOCR12.PC14 = 0XXXB Input P3.14/RXD1B – P3_IOCR12.PC14 = 1X01B Output 2) or 1X10B P3.8/TXD1A P3_IOCR8.PC8 = 1X10B – P3.15/TXD1B – Output P3_IOCR12.PC15 = 1X10B Output 1) For possible PCx bit field combinations, see Table 17-9. 2) Applicable in Synchronous Mode only. Page 18-16 The expression ”SLSOx” must be replaced three times by “SLSOn”. In the numbered paragraph “3.” the expression “SSSOTC.INACT“ must be changed to “SSOTC.INACT”. Documentation Addendum 14 V2.0, 2008-04 TC1766 User’s Manual - Peripheral Units Part (Volume 2) Page 18-24 The description for the Module Revision Number bit field for the ID register must be changed to ”MODREV defines the module revision number. The value of a module revision starts with 10H(first revision).” Page 18-34 The bit field description for bit TB_VALUE must begin with “Register TB stores the data value ....”. Page 18-42 The content “rw” of column “Type” in the last row of the table on top of the page for the “Reserved” bits must be changed to “r“. Page 19-4 The item “- Programmable upstream data frame length (16 or 12 bits)” must be moved from the second bullet as third item under the third bullet “Low-speed asynchronous serial reception on upstream channel”. Page 19-13 in the last bullet line on the bottom of the page “DDL” must be changed to “DCL“. Page 19-18 “DSS.DC” must be changed to “DSS.PFC“ at the first sentence of the Passive Frame Counter in Data Repetition Mode section. Page 19-19 In the paragraph above Figure 19-12 “(ENSELL=0)” must be changed to “(ENSELH=0)“. Page 19-25 In Table 19-6 column USR.URR fourth line “010B” must be changed to “011B”. Page 19-26 In the first paragraph, “OCSR.URR” must be changed to “USR.URR”. Page 19-34 In the paragraph above Figure 19-26 “ISC.SRDI and ISC.CRDI” must be changed to “ISC.SURDI and ISC.CURDI”. Figure 19-26 must be updated with the following figure (output signal on the right side): Documentation Addendum 15 V2.0, 2008-04 TC1766 CONFIDENTIAL User’s Manual - Peripheral Units Part (Volume 2) ISC ICR RDIE 2 Software ISR Clear CURDI URDI SURDI Set RDIE = 00 Data is received 01 Data is received and not equal 00 H 10 Data is received in UD 3 11 Software Set ≥1 Hardware Set RDI Receive Data Interrupt (to Int. Comp .) MCA05820a_mod Figure 19-26 Receive Data Interrupt Control Page 19-47 The paragraph on the top of the page must be changed to: “The bit fields of the Downstream Select Data Source High Register DSDSH determine the data source for each bit in shift register SRH.“ The register description table must be changed as follows: SHx (x = 0-15) [2*x+1: rw 2*x] Select Source for SRH SHx determines which data source is used for the shift register bit SRH[x] during data frame transmission. 00B SRH[x] is taken from data register DD.DDH[x]. 01B Reserved. 10B SRH[x] is taken from the ALTINH input line x. 11B SRH[x] is taken from the ALTINH input line x in inverted state. Page 19-57 n the bit description of bit CSH “SRL” must be changed to “SRH”. Documentation Addendum 16 V2.0, 2008-04 TC1766 User’s Manual - Peripheral Units Part (Volume 2) Page 19-65 The below five formulas must be changed as follows (“MSC0_FDR.STEP”): 1 n f MSC 0 = f SYS × --- with n = 1024 - MSC0_FDR.STEP (19.3) 1 Baud rate MSC 0 = f SYS × ---------------------------------------------------------------------------------2 × ( 1024 - MSC0_FDR.STEP ) (19.5) MSC0_FDR.STEP Baud rate MSC 0 = f SYS × ------------------------------------------------2 × 1024 (19.6) 1 Baud rate MSC 0 = f SYS × --------------------------------------------------------------------------------------DF × ( 1024 - MSC0_FDR.STEP ) (19.7) MSC0_FDR.STEP Baud rate MSC 0 = f SYS × ------------------------------------------------DF × 1024 (19.8) Page 19-68 In the bit description for bit SUSACK in the register description table “Indicates state of SPNDACK signal.“ must be changed to “Indicates state of SPNDACK signal. Page 19-69 The content “rw” of column “Type” in the last row of the table on top of the page for the “Reserved” bits must be changed to “r“. Page 20-39 The bulleted points of Allocation Case 1 must be changed to: • • The upper three bits of MOIPRn.MPN (MPN[7:5]) select the number k of a Message Pending Register MSPNDk in which the pending bit will be set.“. The lower five bits of MOIPRn.MPN (MPN[4:0]) select the bit position (0-31) in MSPNDk for the pending bit to be set. Page 20-50 The second sentence of paragraph 6 must be changed to “Transmit acceptance filtering evaluates TXEN1 for each message object and a message object can win transmit acceptance filtering only if its TXEN1 bit is set.” Documentation Addendum 17 V2.0, 2008-04 TC1766 CONFIDENTIAL User’s Manual - Peripheral Units Part (Volume 2) Page 20-64 The first sentence of the page must be changed to “Each of the two CAN nodes has a list that determines the allocated message objects.” Page 20-66 The first sentence of the page must be changed to “When a message object n generates an interrupt request upon the transmission or reception of a message, then the request is routed to the interrupt output line selected by the bit field MOIPRn.TXINP or MOIPRn.RXINP of the message object n.” Page 20-68 The bit field description of Message Index Mask must be replaced with “Only those bits in MSPNDk for which the corresponding Index Mask bits are set contribute to the calculation of the Message Index. Page 20-113 The content “rw” of column “Type” in the last row of the table on top of the page for the “Reserved” bits must be changed to “r“. Page 21-29, 21-34 At both pages, the first bullet paragraphs from the top of the pages should be extended at its end by the following text: “... are not taken into account, assuming the buffer size is configured correctly (see Page 21-102).” Page 21-75 In Figure 21-50, the TCDMR text within the Transmission Status/Control Registers block must be corrected to “TCMDR”. Page 21-80 The content “rw” of column “Type” in the last row of the table on top of the page for the “Reserved” bits must be changed into “r“. Page 21-102 The description of bit field BS should be extended in the following way: 1. Adding the bit field combination “1101B 14-bit offset address of Remote Window” 2. Adding the following text after bit combination 1111B: “Do not use the values 1101B, 1110B, and 1111B as buffer size BS for Small Transfer Windows.“ Documentation Addendum 18 V2.0, 2008-04 TC1766 User’s Manual - Peripheral Units Part (Volume 2) Page 21-103 The bit description of AOFF should be extended at its end by the following text: “... are not taken into account for further actions, assuming the buffer size is configured correctly (see Page 21-102).” Page 22-164 The bit description of bit PLLCTR.AEN must be changed as follows: AEN 2 rw Automatic End Mode Enable With the Automatic End Mode the compensation of input signal’s period length variation (acceleration, deceleration) is requested. 0B Automatic End Mode is disabled. 1B Automatic End Mode is enabled. Page 22-228 The content “rw” of column “Type” in the last row of the table on top of the page for the “Reserved” bits must be changed to “r“. Page 23-91 The content “rw” of column “Type” in the last row of the table on top of the page for the “Reserved” bits must be changed to “r“. Documentation Addendum 19 V2.0, 2008-04 TC1766 CONFIDENTIAL User’s Manual - Peripheral Units Part (Volume 2) Page 24-7 The ACRx.GAIN setting which corresponds to the FAINxP and FAINxN values in Table 24-1 for Differential Measurement Mode (Configuration 3) must be replaced as below: Table 24-1 Conversion Results in the Different Measurement Modes Measurements ACRx. ENP 0 Single-ended Measurement Mode (Configuration 1) ACRx. ENN FAINxP FAINxN ACRx. Conversion GAIN Results 1 “don’t care” 0 00B 3.3 0 256 01B 3.3 1 Single-ended Measurement Mode (Configuration 2) 0 0 3.3 “don’t care” 0 Documentation Addendum 1 1023 0 00B 256 768 01B 3.3 1 Differential Measurement Mode (Configuration 3) 768 0 1023 0 1.65 0 3.3 0 1.65 0 768 3.3 0 1023 3.3 1.65 768 0 1.65 1.65 0 1023 3.3 1.65 1023 20 00B 01B 256 0 V2.0, 2008-04 TC1766 User’s Manual - Peripheral Units Part (Volume 2) Page 24-37 The bit field description CRPRIO must be changed as follows: CRPRIO [17:16] rwh Conversion Request Priority This bit field determines the priority of the conversion requests if more than one channel is requested. If the dynamic priority assignment is enabled, the priority is automatically changed as a function of the gating inputs. The priority of the channels is: 00B Channel 0 before channel 1 01B Channel 1 before channel 0 10B Reserved 11B Reserved Page 24-50, 24-51 The bit field description of CRR0.AC and CRR1.AC must be changed as follows: AC [26:24] rh Addition Count With the Automatic End Mode the compensation of input signal’s period length variation (acceleration, deceleration) is requested.xxThis bit field indicates the number of additions of filter input values with remain to be executed before the next intermediate result register transfer occurs. AC is loaded with the value of FCRn.ADDL for a new addition sequence, also when writing GCR.RSTFn = 1. Page 24-60 The content “rw” of column “Type” in the last row of the table on top of the page for the “Reserved” bits must be changed to “r“. Documentation Addendum 21 V2.0, 2008-04 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG