TC1766 Documentation Addendum V1.2 (Addendum to TC1766 User's Manual V1.1)

Documentation Addendum, V1.2, Apr. 2007
TC1766
32-Bit Single-Chip Microcontroller
Microcontrollers
Edition 2007-04
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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question please contact your nearest Infineon Technologies Office.
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devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
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be endangered.
Documentation Addendum, V1.2, Apr. 2007
TC1766
32-Bit Single-Chip Microcontroller
Microcontrollers
TC1766 Documentation Addendum
Revision History:
V1.2 2007-04
Previous Version:
V1.1
Page
Subjects (major changes since last revision)
7
Figure 1-12 is updated.
8
The register long names for MMU_CON and D11 to D15 are corrected.
10
The desription for CRC generation and error checking is improved; the typo
is corrected for EICR0.REN0, EICR0.REN1, EICR1.REN2 and
EICR1.REN3
11
The typo of bit description GEEN1 is corrected.
19
The bit name and access type is corrected for bit 5 of PCP_ES register; the
instruction field definition of Table 10-12 is updated.
20
Figure 10-14 is updated; the typo in the syntax description of the ST.PI
instruction of the PCP is corrected
21
The typo in Figure 11-5 is corrected.
22
The description for Channel Reset Operation is improved.
23
The typo in Transaction Lost Interrupt section is corrected.
24
The typo in Move Engine Interrupt section is corrected.
28
The read and write access modes for address location F000 0804H of
Table 16-7 are corrected; the reserved column for address location F000
0850H to F000 08F4H of Table 16-7 are split.
30
Typo in Slave Select Output Control and the description for Slave Select
Register Update section are corrected.
32
A new note is added for SSOC and SSOTC registers; a new footnote is
added to SSOTC.LEAD, SSOTC.TRAIL and SSOTC.INACT bit
description.
33
A new paragraph is added to Receive FIFO section; the description when
LEC=111B is improved; the CAN Bus State Information is updated in Table
20-8.
34, 35, 36 The typo for number of CAN interrupt outputs is corrected.
36
MLI receive clock max. frequency is corrected.
52
The formula for the timer period is corrected.
Trademarks
TriCore® is a trademark of Infineon Technologies AG.
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TC1766
Table of Contents
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
User’s Manual - System Units Part (Volume 1) . . . . . . . . . . . . . . . . . . . . 6
Page 1-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Page 1-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Page 1-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Page 1-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Page 1-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page 1-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page 2-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page 2-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page 2-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page 2-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Page 3-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Page 4-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Page 4-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page 5-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page 5-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page 5-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page 5-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page 5-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Page 5-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Page 5-58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Page 5-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Page 6-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Page 6-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Page 6-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Page 6-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Page 6-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Page 6-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Page 7-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Page 7-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Page 7-49 to 7-51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Page 8-5 to 8-7 and 8-13 to 8-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Page 8-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Page 9-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Page 9-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Page 9-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Page 9-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Page 9-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Documentation Addendum
1
V1.2, 2007-04
TC1766
Table of Contents
Page 9-49 to 9-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Page 9-55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page 9-57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page 10-58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page 10-59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page 10-73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page 10-77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Page 10-98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Page 11-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page 11-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Page 11-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Page 11-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Page 11-79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Page 11-80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Page 11-91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Page 12-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Page 14-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Page 16-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Page 16-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Page 16-20 to 16-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Page 16-69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Page 16-79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Documentation Addendum
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V1.2, 2007-04
TC1766
Table of Contents
3
User’s Manual - Peripheral Units Part (Volume 2) . . . . . . . . . . . . . . . . 29
Page 17-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Page 18-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Page 18-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Page 18-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Page 18-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Page 18-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page 18-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page 18-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page 18-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page 18-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page 18-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page 18-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page 19-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Page 19-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Page 20-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Page 20-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Page 20-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Page 20-75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Page 20-85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Page 20-109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Page 20-116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Page 20-117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Page 20-118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Page 21-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Page 21-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Page 21-79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Page 21-108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Page 21-116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Page 21-117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Page 22-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Page 22-69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Page 22-70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Page 22-71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Page 22-74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Page 22-75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Page 22-76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Page 22-89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Page 22-90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Page 22-91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Page 22-94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Page 22-96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Page 22-97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Table of Contents
Page 22-99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Page 22-100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Page 22-101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Page 22-103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Page 22-104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Page 22-105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Page 22-106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Page 22-108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Page 22-125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Page 22-132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pages 22-173 and 22-174 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Page 22-178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Page 22-184 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Page 22-200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Page 22-205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Page 22-209 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Page 23-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Page 23-96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Page 23-97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Page 24-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Page 24-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Page 24-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Documentation Addendum
4
V1.2, 2007-04
TC1766
Introduction
1
Introduction
This document describes corrections, changes, and improvements for the two parts of
the TC1766 User’s Manual V1.1 2005-08, the System Units book (Volume 1) and the
Peripheral Units book (Volume 2). These corrections will be considered with the next
update of these User’s Manual documents.
The referenced documents to this addendum are located at the Internet page:
•
•
•
www.infineon.com/tc1766
TC1766 System Units User’s Manual (Vol.1), V1.1, Aug. 2005
TC1766 Peripheral Units User’s Manual (Vol.2), V1.1, Aug. 2005
Documentation Addendum
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V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
2
User’s Manual - System Units Part (Volume 1)
This section describes corrections for the System Units part of the User‘s Manual.
Page 1-10
The second bulleted point under Interrupt System must be corrected to “Flexible
interrupt-prioritizing scheme with 255 interrupt priority levels.”
Page 1-11
The bulleted point under Package must be corrected to “PG-LQFP-176-2 package, 0.5
mm pitch.”
Documentation Addendum
6
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 1-33
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128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P3.4/MTSR0
P3.7/SLSI0/SLSO02/SLSO12
P3.3/MRST0
P3.2/SCLK0
P3.8/SLSO06/TXD1A
P3.6/SLSO01/SLSO11/SLSO01&SLSO11
P3.5/SLSO00/SLSO10/SLSO00&SLSO10
VSS
VDDP
VDD
HDRST
PORST
NMI
BYPASS
TESTMODE
BRKIN
BRKOUT
TCK
TRST
TDO
TMS
TDI
P1.7/IN23/OUT23/OUT79
P1.6/IN22/OUT22/OUT78
P1.5/IN21/OUT21/OUT77
P1.4/IN20/EMG_IN/OUT20/OUT76
VDDOSC3
VDDOSC
VSSOSC
XTAL2
XTAL1
VSS
VDDP
VDD
P1.3/IN19/OUT19/OUT75
P1.11/IN27/IN51/SCLK1B/OUT27/OUT51
P1.10/IN26/IN50/OUT26/OUT50/SLSO17
P1.9/IN25/IN49/MRST1B/OUT25/OUT49
P1.8/IN24/IN48/MTSR1B/OUT24/OUT48
P1.2/IN18/OUT18/OUT74
P1.1/IN17/OUT17/OUT73
P1.0/IN16/OUT16/OUT72
P4.3/IN31/IN55/OUT31/OUT55/SYSCLK
N.C.
AN19
AN18
AN17
AN16
AN15
AN14
VAGND0
VAREF0
VSSM
VDDM
AN13
AN12
AN11
AN10
AN9
AN8
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VDD
VDDP
VSS
AD0EMUX2/P1.14
AD0EMUX1/P1.13
AD0EMUX0/P1.12
TCLK0A/OUT32/IN32/P2.0
SLSO13/SLSO03/OUT33/TREADY0A/IN33/P2.1
TVALID0A/OUT34/IN34/P2.2
TDATA0A/OUT35/IN35/P2.3
OUT36/RCLK0A/IN36/P2.4
RREADY0A/OUT37/IN37/P2.5
OUT38/RVALID0A/IN38/P2.6
OUT39/RDATA0A/IN39/P2.7
VSS
VDDP
VDD
VSS
OUT52/OUT28/HWCFG0/IN52/IN28/P4.0
OUT53/OUT29/HWCFG1/IN53/IN29/P4.1
OUT54/OUT30/HWCFG2/IN54/IN30/P4.2
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
OCDSDBG0/OUT40/IN40/P5.0
OCDSDBG1/OUT41/IN41/P5.1
OCDSDBG2/OUT42/IN42/P5.2
OCDSDBG3/OUT43/IN43/P5.3
OCDSDBG4/OUT44/IN44/P5.4
OCDSDBG5/OUT45/IN45/P5.5
OCDSDBG6/OUT46/IN46/P5.6
OCDSDBG7/OUT47/IN47/P5.7
TRCLK
VDD
VDDP
VSS
OCDSDBG8/TDATA1/RDATA0B/P5.8
OCDSDBG9/TVALID1/RVALID0B/P5.9
OCDSDBG10/RREADY0B/TREADY1/P5.10
OCDSDBG11/TCLK1/RCLK0B/P5.11
OCDSDBG12/TDATA0B/RDATA1/P5.12
OCDSDBG13/TVALID0B/RVALID1/P5.13
OCDSDBG14/RREADY1/TREADY0B/P5.14
OCDSDBG15/TCLK0B/RCLK1/P5.15
N.C.
VSSAF
VDDAF
VDDMF
VSSMF
VFAREF
VFAGND
AN35
AN34
AN33
AN32
AN31
AN30
AN29
AN28
AN7
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
P0.15/IN15/SWCFG15/REQ5/OUT15/OUT71
P0.14/IN14/SWCFG14/REQ4/OUT14/OUT70
P0.7/IN7/SWCFG7/REQ3/OUT7/OUT63
P0.6/IN6/SWCFG6/REQ2/OUT6/OUT62
VSS
VDDP
VDD
P0.13/IN13/SWCFG13/OUT13/OUT69
P0.12/IN12/SWCFG12/OUT12/OUT68
P0.5/IN5/SWCFG5/OUT5/OUT61
P0.4/IN4/SWCFG4/OUT4/OUT60
P2.13/SLSI1/SDI0
P2.8/SLSO04/SLSO14/EN00
P2.12/MTSR1A/SOP0B
P2.11/SCLK1A/FCLP0B
P2.10/MRST1A
P2.9/SLSO05/SLSO15/EN01
SOP0A
SON0
FCLP0A
FCLN0
VSS
VDDP
VDD
P0.11/IN11/SWCFG11/OUT11/OUT67
P0.10/IN10/SWCFG10/OUT10/OUT66
P0.9/IN9/SWCFG9/OUT9/OUT65
P0.8/IN8/SWCFG8/OUT8/OUT64
P0.3/IN3/SWCFG3/OUT3/OUT59
P0.2/IN2/SWCFG2/OUT2/OUT58
P0.1/IN1/SWCFG1/OUT1/OUT57
P0.0/IN0/SWCFG0/OUT0/OUT56
P3.11/REQ1
P3.12/RXDCAN0/RXD0B
P3.13/TXDCAN0/TXD0B
VDDFL3
VSS
VDDP
P3.9/RXD1A
P3.10/REQ0
P3.0/RXD0A
P3.1/TXD0A
P3.14/RXDCAN1/RXD1B
P3.15/TXDCAN1/TXD1B
Figure 1-12 should be replaced with the below figure:
MCP06067_c
Figure 1-12 TC1766 Pinning for PG-LQFP-176-2 Package
Page 1-44
The pad driver class of pin HDRST is “A2” instead of “A1”. The pad driver class of pin
NMI and PORST are grouped as “A2”.
Documentation Addendum
7
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 1-46
The footnotes 2 and 4 of Table 1-3 should be deleted.
Page 1-47
The following section has to be added after section 1.4.2:
1.4.3
Pull-Up/Pull-Down Behavior of the Pins
Table 1-5
List of Pull-up/Pull-down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
All GPIOs, TDI, TMS, TDO
Pull-up
HDRST
Drive-low
Pull-up
BYPASS
Pull-up
High-impedance
TRST, TCK
High-impedance
Pull-down
TRCLK
High-impedance
BRKIN, BRKOUT, TESTMODE
Pull-up
NMI, PORST
Pull-down
Page 2-13
The long register name of register MMU_CON must be changed to “MMU
Configuration Register”.
Page 2-15
The bit description of bit CPU_SRCn.TOS is wrong. For TOS = 1, the description must
be changed from “Reserved” to “Service Provider = PCP”.
Page 2-17
In Table 2-4, the register long name for D11, D12, D13, D14 and D15 must be changed
to “Data Register 11, Data Register 12, Data Register 13, Data Register 14 and Data
Register 15.
Page 2-23
The offset address for register CMP1 must be corrected in Table 2-6 from 2200H into
2280H.
Documentation Addendum
8
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 2-26
Figure 2-11 should be replaced with the below figure:
CPU
Interfac e
Program Memory
Interface (PMI)
PMEM
Tag
RAM
8 KB
ICACHE
128
16 KB
SPRAM
Data Switch
&
Data Alignment
&
Interface Control
64
To/From
CPU
PMI
Control
Registers
128
Parity
Control/Check
Slave Master
LMB Interface
64
To SCU
(PMI Memory Parity Errors)
To/From
Local Memory Bus
PMEM = Program Memory in PMI
ICACHE = Instruction Cache
SPRAM = Scratch-Pad RAM
LMB
= Local Memory Bus
CPS
= CPU Slave
MCB06078_c
Figure 2-11 PMI Block Diagram
Page 3-18
Section 3.2.2.5: Point 3) of the actions should be executed after point 5) and not after
point 2).
Page 4-25
The first sentence of Section 4.4.3 must be replaced by “Except for different connections
to serial port lines of ASC0, the bootstrap loader mode 3 is identical to bootstrap loader
mode 1.”
Documentation Addendum
9
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 4-26
The first sentence of the note at the top of the page must be extended by “For CRC
generation and error checking, the BootROM software uses the TC1766 on-chip
memory checker module with an initial value of FFFF FFFFH for the memory checker
result register before the checksum is generated.”
Page 5-18
The bit description of case “1” for EICR0.REN0 must be replaced by “ The detection of
a rising edge of IN0 generates a trigger event (INTF0 becomes set).”
Page 5-20
The bit description of case “1” for EICR0.REN1 must be replaced by “ The detection of
a rising edge of IN1 generates a trigger event (INTF1 becomes set).”
Page 5-21
The bit description of case “1” for EICR1.REN2 must be replaced by “ The detection of
a rising edge of IN2 generates a trigger event (INTF2 becomes set).”
Page 5-22
The bit description of case “1” for EICR1.REN3 must be replaced by “ The detection of
a rising edge of IN3 generates a trigger event (INTF3 becomes set).”
Documentation Addendum
10
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 5-28
The first sentence of the bit description of GEEN1 must be replaced by “Bit GEEN1
enables the generation of a trigger event for output channel 1 when the result of the
pattern detection changes.”
Page 5-48
Figure 5-11 should be replaced with the figure shown as below.The below note must be
added to the end of the last sentence of the page.
SCU
TIR
ASC0
RIR
0
1
M
U
X
ASC0_REQ
To DMA Controller
SEL0
TIR
ASC1
RIR
0
1
M
U
X
ASC1_REQ
To DMA Controller
SEL1
TIR
SSC0
RIR
0
1
M
U
X
SSC0_REQ
To DMA Controller
SEL2
TIR
SSC1
RIR
0
1
M
U
X
SSC1_REQ
To DMA Controller
SEL3
SEL0 to SEL3 are bit fields of the
DMA Request Select Register
MCA06453
Figure 5-11 DMA Request Selection Logic
Note: By default, TIR line is selected for both ASC and SSC modules. For RIR line to be
selected, SEL0.DMARS to SEL3.DMARS should be set accordingly. See DMARS
register.
Page 5-58
The bit description of ENON on the bottom of the page must be corrected to:
“1 Setting of EMSF by hardware is enabled.”
Documentation Addendum
11
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 5-64
The sentence “This bit is set with any reset.” in the description of bit PARAV must be
changed into “This bit is set after a power-on reset“.
Page 6-4
Figure 6-2 should be replaced with the below figure:
Bus Cycle
1
2
3
Transfer 1
Request/
Grant
Address
Cycle
Data
Cycle
Request/
Grant
Address
Cycle
Transfer 2
Transfer 3
Request/Grant
4
5
Data
Cycle
Address
Cycle
Data
Cycle
MCA06109_c
Figure 6-2
Basic LMB Transactions
Page 6-6
In the second paragraph of Section 6.2.3, second bulleted point, the register short name
for LMB Error Data Registers should be replaced with “LEDATL/LEDATH”.
Page 6-7
In the bit description of bit LEC, the text “When writing a 0 to LEC” must be replaced by
“When writing a 1 to LEC”.
Page 6-19
The second sentence of the first paragraph of Section 6.4.3 should be replaced with:
“The requesting FPI Bus master releases the FPI Bus for one cycle after the FPI Bus
transaction request, in order to allow the FPI Bus slave to indicate if it is ready to handle
the requested FPI Bus transaction.”
Documentation Addendum
12
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 6-20
Figure 6-7 should be replaced with the below figure:
Bus Cycle
1
2
3
Transfer 1
Request/
Grant
Address
Cycle
Data
Cycle
Request/
Grant
Address
Cycle
Transfer 2
Transfer 3
Request/Grant
4
5
Data
Cycle
Address
Cycle
Data
Cycle
MCA06109_c
Figure 6-7
Basic FPI Bus Transactions
Page 6-29
Figure 6-12 should be replaced with the below figure:
SBCU_DBCNTL
CONCOM2 CONCOM1 CONCOM0
Address 1 Trigger
Address 2 Trigger
Signal Status Trigger
Address
AND/OR Trigger
Selection
AND/OR
Selection
AND/OR
Selection
Grant Trigger
BCU
Breakpoint
Trigger
MCA06117_c
Figure 6-12 BCU Breakpoint Trigger Combination Logic
Page 7-16
In Table 7-7, 32-bit Load Page Buffer Command, the DFLASH address for DB1 AFE1
55F4H must be replaced with AFE1 55F0H in Cycle 1 and DFLASH address for DB0
AFE0 55F0H must be replaced with AFE0 55F4H in Cycle 2.
Documentation Addendum
13
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 7-41
The first paragraph of column “Description” for bit FABUSY should be changed as
follows:
“This status flag is a flag for test purposes that should not be used by software drivers.
It indicates whether any of the Flash arrays is in busy state. FABUSY is cleared by any
reset operation.”
Page 7-49 to 7-51
The following footnote 1) must be added to the following FCON bits and bit fields:
WSPFLASH, WSECPF, WSWLHIT, WSDFLASH, and WSECDF
1)
These bits and bit fields can be changed at any time, also with code fetched from Program Flash. A modified
wait state parameter will be taken into account with the next corresponding access.
Page 8-5 to 8-7 and 8-13 to 8-14
The respective address ranges (in bold) for Segment 8 and 10 of Table 8-2 and Table 84 must be updated as the following :
Table 8-2
SPB Address Map of Segment 0 to 14
Seg- Address
ment Range
Size
8
48 Kbyte
Reserved
LMBBE &
SPBBE
LMBBE
8FE2 0000H 8FF1 FFFFH
1 Mbyte
Reserved
LMBBE &
SPBBE
LMBBE
8FF2 0000H 8FF5 FFFFH
256
Kbyte
Reserved for TC1766
emulation device memory
8FF6 0000H 8FFF BFFFH
624
Kbyte
Reserved
8FE1 4000H 8FE1 FFFFH
Description
Access Type
Read
8FFF C000H - 16 Kbyte
8FFF FFFFH
Documentation Addendum
Boot ROM (BROM)
14
Write
access
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Table 8-2
SPB Address Map of Segment 0 to 14 (cont’d)
Seg- Address
ment Range
10
Size
Description
Access Type
Read
AFE1 4000H - 48 Kbyte
AFE1 FFFFH
Write
Reserved
LMBBE &
SPBBE
ignore
1 Mbyte
Reserved
LMBBE &
SPBBE
ignore
AFF2 0000H AFF5 FFFFH
256
Kbyte
Reserved for TC1766
emulation device memory
AFF6 0000H AFFF BFFFH
624
Kbyte
Reserved
AFE2 0000H AFF1 FFFFH
AFFF C000H - 16 Kbyte
AFFF FFFFH
Table 8-4
Boot ROM (BROM)
access
LMB Address Map
Seg- Address
ment Range
Size
Description
Action
81)
8FE1 4000H 8FE1 FFFFH
48 Kbyte
Reserved
LMBBET
LMBBET
8FE2 0000H 8FF1 FFFFH
1 Mbyte
Reserved
LMBBET
LMBBET
8FF2 0000H 8FF5 FFFFH
256 Kbyte Reserved for TC1766
emulation device memory
8FF6 0000H 8FFF BFFFH
624 Kbyte Reserved
Read
8FFF C000H - 16 Kbyte
8FFF FFFFH
Documentation Addendum
Boot ROM (BROM)
15
Write
access
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Table 8-4
LMB Address Map (cont’d)
Seg- Address
ment Range
102)
Size
Description
Action
Read
Write
AFE1 4000H - 48 Kbyte
AFE1 FFFFH
Reserved
LMBBET
LMBBET
AFE2 0000H - 1 Mbyte
AFF1 FFFFH
Reserved
LMBBET
LMBBET
AFF2 0000H AFF5 FFFFH
256 Kbyte Reserved for TC1766
emulation device memory
AFF6 0000H AFFF BFFFH
624 Kbyte Reserved
AFFF C000H - 16 Kbyte
AFFF FFFFH
Boot ROM (BROM)
access
1) Cached area
2) Non-cached area
Page 8-17
In Table 8-5, the four “–” of Double-word column and CRAM and PRAM rows must be
replaced by “✔”. “CRAM” must be replaced with “CMEM”. Footnote 1 must be added to
the PMI and DMI memory cells as "The module also supports LMB 2-Word and 4-Word
Block read and write accesses”.Footnote 2 must be added to the PCP memory cell as
"The module also supports FPI 4-Word and 8-Word Block read and write accesses”.
Page 9-15
The following sentence must be added at the end of paragraph “Port 0 is a generalpurpose 16-bit ... software later.”:
“Note that some of the P0.[7:0] lines are used for configuration purposes, too (see Page
9-25).”
Page 9-25
Section 9.3.3.3 must be changed as described below:
9.3.3.3
Reserved Port 0 Pins
Depending on the TC1766 device version used in an application, several Port 0 lines
(meaning several SWOPT bits) are reserved and cannot be used for user system
purposes during a HDRST reset operation. Table 9-8 defines the reserved Port 0 lines
(indicated by 0 or 1) as well as the Port 0 lines that can be used by a user program
Documentation Addendum
16
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
(indicated by “user”) for software configuration selection (or as GPIO pins) depending on
the specific TC1766 device version.
Table 9-8
Reserved Port 0 Lines of TC1766 Devices
TC1766 Device Versions
TC1766
SWOPTx Bits (x = 0-15)
P0.
[15:8]
P0.
[7:6]
P0.5
P0.4
P0.3
P0.
[2:0]
user
user
user
1
user
1)
XXB2)
0 or 13)
TC1766ED (Emulation device)
1) The P0.[2:0] bits are only used in alternate boot modes (see Table 4-7). If alternate boot modes are not
required or used in an application, P0.[2:0] can also be used for user program software configuration selection
purposes during a hardware reset operation or as GPIO pins.
2) 00B, 11B : The USB interface of the TC1766ED is not connected to device pins.
01B : The USB interface of the TC1766ED is connected to JTAG I/O lines.
10B : The USB interface of the TC1766ED is connected to P2.[5:0] lines.
3) 0: Emulation device functionality is not available.
1: Emulation device functionality is fully supported.
Page 9-32
The reset value for P1_IOCR12 should be corrected as 0020 2020H.
Page 9-41
P2_IOCR0 should not be linked to footnote 1.
Page 9-42
The reset value for P2_IOCR12 should be corrected as 0000 2020H.
Documentation Addendum
17
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 9-49 to 9-50
In Table 9-13, P3.12 and P3.14 Input rows should be updated as below:
Table 9-13
Port
Pin
I/O
P3.12 I
Port 3 Functions
Pin Functionality
Associated Reg./ Port I/O Control Select.
I/O Line
Reg./Bit Field Value
General-purpose input
P3_IN.P12
CAN node 0 receive input 0 RXDCAN0
CAN node 1 receive input 1
P3_IOCR12.
PC12
0XXXB
ASC0 input (Asynchronous RXD0B
Mode /Synchronous Mode)
O
P3.14 I
General-purpose output
P3_OUT.P12
ASC0 output (Synchronous RXD0B
Mode)1)
1X01B
ASC0 output (Synchronous RXD0B
Mode)
1X10B
Reserved1)
–
1X11B
General-purpose input
P3_IN.P14
CAN node 1 receive input 0 RXDCAN1
CAN node 0 receive input 1
O
1X00B
P3_IOCR12.
PC14
0XXXB
ASC1 output
(Asynchronous
Mode/Synchronous Mode)
RXD1B
General-purpose output
P3_OUT.P14
1X00B
ASC1 output
(Synchronous Mode)1)
RXD1B
RXD0B
ASC1 output
(Synchronous Mode)
RXD1B
RXD0B
Reserved1)
–
–
1) The ALT1 and ALT2 for this pin are connected together. There are no dependencies. Either one can be
chosen.
In Table 9-13, the text of the associated Reg. I/0 Line TCD0B of P3.13 with
P3_IOCR12.PC13 = 1X10B must be changed to TXD0B.
Documentation Addendum
18
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 9-55
In Table 9-15, the text of Pin Functionality SCU input of Pin 4.3 with P4_IOCR0.PC3 =
1X11B must be replaced with SCU output. In Table 9-16, P4_IOCR0 should not be
linked to footnote 1.
Page 9-57
Section 9.7.3.3 should be updated as below:
9.7.3.3
Port 4 Input/Output Control Register x (x=4, 8 and 12)
Port lines P4.[15:4] are not available. Therefore, PC bit fields; PC[15:4] in registers
P4_IOCR4, P4_IOCR8, P4_IOCR12 are not connected.
Page 10-58
Bit 5 in the register image of register PCP_ES must be changed into 0,r (instead of
ME,rh).
Page 10-59
The column “Description ” for bit 5 must be corrected into: “Reserved; read as 0.
Page 10-73
The second row (RC0) of Table 10-12 must be replaced by the following row:
Documentation Addendum
19
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 10-77
Figure 10-14 must be replaced by the following figure (block “DATA Transfer” has been
changed):
BCOPY
Instruction
DATA Transfer
(Block size
determined by
CNT0 field)
00
10
CNC = ?
01
CNT1 := CNT1 - 1
CNT1 := CNT1 - 1
CNT1 = 0 ?
no
yes
Next
Instruction
MCA06148
Figure 10-14 Counter Operation for BCOPY Instruction
Page 10-98
In the syntax description of the ST.PI instruction of the PCP, the register name "Ra"
should be replaced by "Rb".
Documentation Addendum
20
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 11-9
The wordings “SHADR0n with CHCR0n.SHCT = 01B“on the left of the first waveform
from the bottom of Figure 11-5 must be replaced with “SHADR0n with ADRCR0n.SHCT
= 01B“.
1)
CHSR0n.TCOUNT
tc1
CHCR0n.TREL
2)
1
tc1-1
sa1
sa1+
tc1-1
sa1+1
SHADR0n with
ADRCR0n.SHCT= 01B
sa2
tc1
tc2
sa1
sa2
tc2
tc2-1
tc2
tc1
SADR0n
0
3)
sa1+
tc1
tc2-2
tc3
sa2
sa2+1 sa2+2
0000 0000H
sa3
1) 3) = writing to CHCR0n and SADR0n
2)
= start of new DMA transaction with
shadow transfer of source address
= transfer count 1
= transfer count 2
= source address 1
= source address 2
MCT06153_c
Figure 11-5 Shadow Source Address and Transfer Count Update
Documentation Addendum
21
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 11-10
Figure 11-6 must be updated as per the corresponding changes on pages 11-35 and 1150.
CHCR0n
Suspend Request
CHMODE
TRSR
HTREQ
&
End of
Transaction
Reset TRSR
Reset
HTRE0n
Set
Reset
SUSEN0n
STREQ
SCH0n
CH0n_REQI0
CH0n_REQI1
CH0n_REQI2
CH0n_REQI4
SUSPMR
ECH0n
DCH0n
Pattern
Match
CH0n_REQI3
Suspend Control
≥1
&
M
U
X
CH0n_REQ
CH0n_REQI5
End of
Transfer
CH0n_REQI6
CH0n_REQI7
End of
Transaction
Reset
Set
Reset
TRSR
&
CH0n
&
0M
≥1
U
X
1
3
PRSEL
CHCR0n
Transfer
Request
To
Channel
Arbiter
RROAT
CH0n
CHCR0n
CHRSTR
Set
TRL0n
ERRSR
Transfer
Request
Lost
Interrupt
MCA06154c
Figure 11-6 Channel Request Control
The last sentence of the second last paragraph should be replaced with:
“A software request can be generated by setting bit STREQ.SCH0n.”
Page 11-16
The paragraphs below “When CHRST.CH0n is set to 1:” must be replaced by the
following paragraphs:
•
•
•
Bits TRSR.HTRE0n, TRSR.CH0n, ERRSR.TRL0n, INTSR.ICH0n, INTSR.IPM0n,
WRPSR.WRPD0n,
WRPSR.WRPS0n,
CHSR0n.LXO,
and
bit
field
CHSR0n.TCOUNT are reset.
Source and destination address register will be set to the wrap boundary. SHADR0n
will be cleared.
All automatic functions are stopped for channel 0n.
Documentation Addendum
22
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
A user program must execute the following steps for resetting a DMA channel:
1. If hardware requests are enabled for the DMA channel 0n, disable the DMA channel
0n hardware requests by setting HTREQ.ECH0n = 0.
2. Writing a 1 to CHRST.CH0n.
3. Waiting (polling) until CHRST.CH0n = 0.
A user program should execute the following steps for restarting a DMA channel after it
was reset:
1. Optionally (re-)configuring the address and other channel registers.
2. Restarting the DMA channel 0n by setting HTREQ.ECH0n = 1 for hardware requests
or STREQ.SCH0n = 1 for software requests.
The value of CHCR0n.TREL is copied to CHSR0n.TCOUNT when a new DMA
transaction is requested and shadow address register contents is not equal 00000000H.
Page 11-29
In Section 11.1.8.2, the register name EERSR must be replaced by ERRSR in the third
sentence of the first paragraph, first sentence of the second paragraph and within Figure
11-18. The corresponding text must be replaced by :
“If such a transaction request lost condition occurs, bit ERRSR.TRL0n is set.” and “A
transaction request lost condition of DMA channel 0n is indicated by status flag
ERRSR.TRL0n, which can be reset by setting bit CLRE.CTL0n or CHRSTR.CH0n.“
Figure 11-18 must be replaced by:
CLRE
C TL 0 0
R e se t
EER
ER R SR
TR L 0 0
Se t
ETR L 0 0
C H R STR
CH00
R e se t
EER
TR L IN P
4
Tra n sa ctio n
L o st
In te rru p t 0 0
≥1
n = 0 -7
CLRE
C TL 0 7
R e se t
ER R SR
Se t
EER
TR L 0 7
ETR L 0 7
C H R STR
CH07
R e se t
Tra n sa ctio n
L o st
In te rru p t 0 7
MCA06166_c
Figure 11-18 Transaction Lost Interrupt
Documentation Addendum
23
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 11-30
In Section 11.1.8.3, the register name EERSR must be replaced by ERRSR in the first
sentence of the third paragraph and within Figure 11-19. The corresponding text must
be replaced by :
“A source error of Move Engine 0 is indicated by the status flag ERRSR.ME0SER.“
Figure 11-19 must be replaced by:
CLRE
C ME0 SER
ER R SR
R e se t
ME0 SER
EER
EER
EME0 SER
ME0 IN P
Se t
4
Mo ve En g in e 0
So u rce Erro r
In te rru p t
CLRE
C ME0 D ER
ER R SR
R e se t
ME0 D ER
EER
≥1
EME0 D ER
Se t
Mo ve En g in e 0
D e stin a tio n Erro r
In te rru p t
MCA06167_c
Figure 11-19 Move Engine Interrupts
Documentation Addendum
24
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 11-35
The following paragraphs should be added after the last paragraph(“..for a specific value
of CHDW“) under Section 11.1.9 Pattern Detection:
Depending on CHCR0n.PATSEL and on the positive result of the comparison, two
actions follow (if CHCR0n.PATSEL=00, no action will be taken when a pattern match is
detected, so the wrap interrupt can be used):
•
•
The activation of the interrupt corresponding to the current active channel 0n using
the Interrupt Pointer defined in CHICR0n.WRPP.
Reset TRSR.HTRE0n and TRSR.CH0n in order to stop the current transaction
(Hardware and Software request enable). The value of CHSR0n.TCOUNT can be
read out by the interrupt SW.
The software will have to service the interrupt and to activate again the channel.
Page 11-50
The description of bit field CH0n must be extended by the following sentence:
“CH0n is reset when a pattern match is detected”.
The description of bit field HTRE0n must be extended by the following sentence:
“HTRE0n is reset when a pattern match is detected”.
Page 11-79
The second sentence of the last paragraph should be replaced with:
“If DMA channel 0n is active when writing to SADR0n, the source address will not be
written into SADR0n directly but will be buffered in the shadow register SHADR0n until
the start of the next DMA transaction.
Page 11-80
The second sentence of the last paragraph should be replaced with:
“If DMA channel 0n is active when writing to DADR0n, the source address will not be
written into DADR0n directly but will be buffered in the shadow register SHADR0n until
the start of the next DMA transaction.
Documentation Addendum
25
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 11-91
Figure 11-29 must be corrected as below:
Control Register
DMA Interrupt
Registers
MLI Interrupt
Registers
System Interrupt DMA Bus Time-Out
Registers
Register
DMA_CLC
DMA_SRC0
DMA_MLI0SRC0
DMA_SYSSRC0
DMA_SRC1
DMA_MLI0SRC1
DMA_SYSSRC1
DMA_SRC2
DMA_MLI0SRC2
DMA_SYSSRC2
DMA_SRC3
DMA_MLI0SRC3
DMA_SYSSRC3
DMA_MLI1SRC0
DMA_MLI1SRC1
DMA_SYSSRC4
DMA_TOCTR
MCA06177a
Figure 11-29 DMA Implementation-specific Registers
Documentation Addendum
26
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 12-26
Figure 12-5 must be updated with the following corrected drawing.
Entry in Trap
Handler Routine
V2.NMIEXT set?
V1 := SCU_PETSR
yes
Execute External
NMI Req. Handler
V2 := NMISR
no
no
V2.NMIPER = 1?
V2.NMIPLL set?
yes
no
yes
V1 = 0? 1)
Execute NMI PLL
Request Handler
no
yes
V1 := SCU_PETSR
V2.NMIWDT set?
no
yes
V2 := NMISR
Execute Watchdog
NMI Req. Handler
Execute Parity Error
NMI Req. Handler
Exit Trap Handler
Routine
1) This
test is for the case that a parity error
occurs after the first read of SCU_PETSR.
MCA06449a
Figure 12-5 NMI Trap Handler Routine for Parity Error Handling
Page 14-4
The below note must be added to the end of the last sentence of the page.
Note: The resetting of the ENDINIT bit takes some time. Accesses to Endinit-protected
registers after the resetting of the ENDINT bit must only be done when ENDINIT
is really reset. As a solution, WDT_CON0 (the register with the ENDINIT bit)
should be read back once before Endinit-protected registers are accessed the first
time after ENDINIT has been reset.
Documentation Addendum
27
V1.2, 2007-04
TC1766
User’s Manual - System Units Part (Volume 1)
Page 16-15
The read and write access modes for address location F000 0804H of Table 16-7
must be changed from “nBE” to “BE”.
Page 16-16
The “Reserved” column for address location F000 0850H to F000 08F4H of Table 16-7
must be separated to two different rows of access rights. The read and write access
rights for F000 0850H -F000 0854H are both “nBE” and F000 0858H -F000 08F4H are both
“BE”.
Page 16-20 to 16-25
The write accesses for all Px_OMR registers (x = 0-5) are corrected from "U,SV" into
"U,SV,32".
Page 16-69
The long name of register MMU_CON must be changed to “MMU Configuration
Register”.
Page 16-79
The contents for the short name, description and reset value columns for Table 16-26 at
address locations F800 05F0H, F800 05F8H, and F800 05FCH must be replaced as
shown in Table 16-26.
Table 16-26 Address Map of PMU
Short Name Description
Address
Access Mode Reset
1)
Read
Write Value
Program Memory Unit (PMU)
–
Reserved2)
F800 05F0H
U, SV
E, U,
SV
–
–
Reserved
F800 05F4H
BE
BE
–
–
Reserved2)
F800 05F8H
BE
E, U,
SV,
32
–
–
Reserved2)
F800 05FCH
U, SV
BE
–
1) Which Resets affect the register, see Table 4-2.
2) Do not read from or write to these address locations.
Documentation Addendum
28
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
3
User’s Manual - Peripheral Units Part (Volume 2)
This section describes corrections for the Peripheral Units part of the User‘s Manual.
Page 17-28
Figure 17-12 should be updated with the below figure:
Clock
Control
fASC
A2
P3.0 /
RXD0A
A2
P3.1 /
TXD0A
A2
P3.12 /
RXD0B
A2
P3.13 /
TXD0B
A2
P3.9 /
RXD1A
RXD_I0
Address
Decoder
Interrupt
Control
ASC0
Module
(Kernel)
EIR
TBIR
TIR
RIR
RXD_I1
RXD_O
TXD_O
ASC0_RDR
To
DMA
Port 3
Control
ASC0_TDR
RXD_I0
ASC1
Module
(Kernel)
Interrupt
Control
To
DMA
EIR
TBIR
TIR
RIR
RXD_I1
P3.8 /
A2 TXD1A
RXD_O
TXD_O
P3.14 /
A2 RXD1B
A2 P3.15 /
TXD1B
ASC1_RDR
ASC1_TDR
MCB06211c
Figure 17-12 ASC0/ASC1 Module Implementation and Interconnections
Page 18-15
In Figure 18-8, the description at the bottom of the figure, “CON.PH = CON.PO = 1” must
be replaced by “CON.PH = 0; CON.PO = 1”.
Documentation Addendum
29
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 18-16
After the first sentence on the top of this page, the following sentence must be added:
“With a TB write operation, all timing parameters stored in register SSOTC as well as the
SSOC register are latched and remain valid for the consecutive transmission.“
In the first line of the paragraph below “Slave Select Output Control”, the text
“SSOC.OENn = 0” must be replaced by “SSOC.OENn = 1”.
Page 18-17
In the first line below heading “Slave Select Register Update”, the text in brackets “with
the activation of SLSOn” must be replaced by the text “with the TB register write
operation“.
Documentation Addendum
30
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 18-18
Figure 18-11 should be updated with the below figure:
& Set
CON.TEN
Transmit Error
STAT.TE
Set
EFM.SETTE
Reset
EFM.CLRTE
& Set
CON.REN
Receive Error
Set
EFM.SETRE
CON.PEN
EFM.SETPE
EFM.CLRPE
EFM.SETBE
EFM.CLRBE
Error
Interrupt
EIR
&
Set
Set
STAT.PE
Reset
CON.BEN
Baud Rate Error
≥1
Reset
EFM.CLRRE
Phase Error
STAT.RE
&
Set
Set
STAT.BE
Reset
MCA05789_c
Figure 18-11 SSC Error Interrupt Control
Documentation Addendum
31
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 18-19
In the first note which is located at the upper part of the page, the text “CON.REN = 1”
must be replaced by “CON.AREN = 1”.
Page 18-19
The following note must be inserted after the first note of the page:
Note: This error can occur after any transfer if the communication is stopped. This is due
to the fact that SSC supports back-to-back transfers for multiple transfers. In order
to handle this, the baud rate detection logic expects a next clock cycle immediately
for a new transfer after a finished transfer.
Page 18-23
In the STIP bit description, the sentence “This bit determines...” must be replaced by the
following sentence:
“This bit determines the logic level of the Slave Mode transmit signal when the SSC slave
select input signals are inactive (PISEL.SLSIS ≠ 000B).”
Page 18-25
The bit description of bit EN must be extended by the following sentence: “Note that EN
should only be reset by software while no transfer is in progress (STAT.BSY = 0)”.
Page 18-29
The note paragraph at the bottom of the page must be replaced by the following note
paragraph:
Note: The SSOC register content is latched by each TB register write operation and
remains latched during the consecutive serial transmission.
Page 18-30
In the bit description of register SSOTC a footnote 1) must be added to the bit
combinations 00Β of bit fields LEAD, TRAIL, and INACT:
“1) For getting a best case timing with no timing delays (see Figure 18-8), this bit field
value should be set when the SLSOn outputs are disabled (SSOC.OENn bits set to 0).”
Page 18-30
The note paragraph after the SSOTC register description table must be replaced by the
following note paragraph:
Note: The SSOTC register timing parameters are latched by each TB register write
operation and remain latched during a consecutive serial transmission.
Documentation Addendum
32
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 19-20
The following sentence should be added at the end of the Section 19.1.2.6 “Note that in
this case no time frame finished interrupt is generated any more.“.
Page 19-42
Description of bit field NDBH: for bit combination NDBH = 00000B, the text “No SRH bit
shifted“ should be replaced by “No SRH bit shifted; no selection bit is generated, the SRH
active phase is completely skipped.“.
Page 20-49
The following paragraph should be added after the last paragraph:
"In order to avoid direct reception of a message by a slave message object, as if it was
an independent message object and not a part of a FIFO, the bit RXEN of each slave
object must be cleared. The setting of the bit RXEN is “don’t care” only if the slave object
is located in a list not assigned to a CAN node."
Page 20-50
The first paragraph should be extended by a second sentence:
"A transmit FIFO consists of one base message object and one or more slave message
objects."
Page 20-54
Table 20-4: The offset addresses of the four registers must be corrected as follows:
MSIMASK = 01C0H
PANCTR = 01C4H
MCR = 01C8H
MITR = 01CCH
Page 20-75
In Table 20-6, the two sentences in column “Signification” for LEC value 111B at the
bottom of the page must be replaced by the following two sentences:
"Whenever the CPU writes the value 111B to LEC, it takes the value 111B. Whenever
the CPU writes another value to LEC, the written LEC value is ignored."
Page 20-85
In the first row of Table 20-8, column “CAN Bus State”, the wording “reserved bits, “ must
be deleted. In the second row of Table 20-8, column “CAN Bus State”, the wording
“reserved bits, “ must be inserted at: “ .....RTR, reserved bits, IDE, ....”.
Documentation Addendum
33
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 20-109
The paragraph after Equation (20-2) must be replaced by the following:Equation (20-1)
applies to normal divider mode (CAN_FDR.DM = 01B) of the fractional divider.
Equation (20-2) applies to fractional divider mode (CAN_FDR.DM = 10B).
Page 20-116
The first sentence of the second paragraph must be replaced by: “Each of the 136
hardware initiated interrupt sources is controlled by a 4-bit interrupt pointer that directs
the interrupt source to one of the six interrupt outputs INT_Om (m = 0-5).“
Documentation Addendum
34
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 20-117
Figure 20-27 should be updated with the below figure:
Inte r r upt Pointe r C ontr ol
4 -b it
In te rru p t
Po in te r
Inte r r upt Output C ontr ol
4
0000
In te rru p t
So u rce
..
..
72
.
Inputs ...
.
..
..
.. 16
.. Outputs
.
≥1
1111
In te rru p t
R e q u e st
Ou tp u t
IN T_ Om
16
C AN
Node
0
73
16
≥1
IN T_ O0
16
16
73
≥1
IN T_ O1
16
C AN
Node
1
Me ssa g e
Ob je ct
0
..
..
..
Me ssa g e
Ob je ct
63
R e g iste r
MITR
16
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
16
16
16
In te rru p t
Wirin g
Ma trix
16
73
16
≥1
IN T_ O4
16
73
≥1
IN T_ O5
16
MCA06284_c
Figure 20-27 Interrupt Compressor
Documentation Addendum
35
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 20-118
The first sentence of the page must be replaced by: “Each of the six interrupt outputs
INT_Om of the MultiCAN module is controlled by its service request control registers.“
Page 21-2
The bullet paragraph “Programmable baud rate: .....” under “Features” must be changed
as follows:
•
Programmable baud rates
– MLI transmitter baud rate: max. fMLI/2 (= 40.0 Mbit/s @ 80 MHz module clock)
– MLI receiver baud rate: max. fMLI
Page 21-30
The following sentence must be added at the end of section “21.1.5 MLI Receiver
Operation”:
“The MLI receiver is able to operate with a maximum receive clock (RCLK) frequency up
to the frequency of the module clock fMLI.
Page 21-79
In the register table of register RPxBAR the row for bits [3:0] should be deleted. The
range for ADDR bit field must be extended to [31:0].
Page 21-108
The following paragraph with the formula must be added after the last paragraph:
The receiver baud rate is defined by the following formula.
Baud rateRCLKmax = fMLI
Documentation Addendum
(21.4)
36
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 21-116
In the register table, P5_IOCR8 and P5_IOCR12 should be updated as below:
Field
Bits
Type Description
rw
PC8,
PC9,
PC10,
PC11
[7:4],
[15:12],
[23:20],
[31:28]
1)
Port Input/Output Control for Port 5.[11:8]
Port input/output control for P5.8/RDATA0B/TDATA1
Port input/output control for P5.9/RVALID0B/TVALID1
Port input/output control for P5.10/RREADY0B/TREADY1
Port input/output control for P5.11/RCLK0B/TCLK1
1) For coding of bit field, see Table 21-9. Shaded bits and bit fields are “don’t care” for MLI I/O port control.
Field
Bits
Type Description
rw
PC12,
PC13,
PC14,
PC15
[7:4],
[15:12],
[23:20],
[31:28]
1)
Port Input/Output Control for Port 5.[15:12]
Port input/output control for P5.12/TDATA0B/RDATA1
Port input/output control for P5.13/TVALID0B/RVALID1
Port input/output control for P5.14/TREADY0B/RREADY1
Port input/output control for P5.15/TCLK0B/RCLK1
1) For coding of bit field, see Table 21-9. Shaded bits and bit fields are “don’t care” for MLI I/O port control.
Page 21-117
In the register table, P5_PDR should be updated as below:
Field
Bits
PDMLI0,
PDMLI1
[18:16],
[22:20]
Documentation Addendum
Type
rw
rw
Description
Pad Driver Mode for P5.15, P5.[13:12] and P5.10
Pad Driver Mode for P5.14, P5.11 and P 5.[9:8]
37
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-60
The first three sentences of the first paragraph on the top must be replaced by three
extended sentences:
Old:
“Normally, a GTC is enabled by writing GTCCTRk.EOA (Enable-Of-Action) with 0. Note
that bit EOA is hardware protected. Therefore, any bit operation on EOA will result in a
read-modify-write access.“
New:
“A GTC is enabled by writing (ST byte, word, half-word operation) GTCCTRk.EOA
(Enable-Of-Action) with 0. Because bit EOA is hardware protected, read-modify-write
operations (LDMST, ST.X, SWAP) only enable the GTC if bit EOA is modified from 1 to
0.“
Page 22-69
In the first sentence, the wording "adjacent GTCs" must be replaced by "adjacent LTCs".
Page 22-70
Fourth bullet paragraph in section "Free-Running Timer Mode": "GTCkOUT" must be
replaced by "LTCkOUT".
Page 22-71
Second bullet from the top: "GTCkOUT" must be replaced by "LTCkOUT".
Third bullet paragraph in section "Compare Mode": "GTCkOUT" must be replaced by
"LTCkOUT"
The last note paragraph must be deleted.
Page 22-74
Paragraph above the figure: "GTCs" must be replaced twice by "LTCs".
Paragraph below the figure title paragraph: "GTCCTRk.OCM0" must be replaced by
"LTCCTRk.OCM0".
Page 22-75
The header text “Local Capture or Compare Event” of the second column in Table 22-4
must be replaced by “Local Capture, Compare, or TImer Overflow Event”.
Documentation Addendum
38
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-76
The first three sentences of the first paragraph on the top must be replaced by three
extended sentences:
Old:
“Normally an LTC is enabled by writing LTCCTRk.EOA (Enable-Of-Action) with 0. Note
that bit EOA is hardware protected. Therefore, any bit operation on EOA will result in a
read-modify-write access.“
New:
“An LTC is enabled by writing (ST byte, word, halfword operation) LTCCTRk.EOA
(Enable-Of-Action) with 0 in Capture Mode or Compare Mode. Because bit EOA is
hardware prodected, read-modify-write operations (LDMST, ST.X) only enable the LTC
if bit EOA is modified from 1 to 0 in Capture Mode or Compare Mode. If switching to
Timer Mode, the LTC cell is enabled. If in Timer Mode every write operation into bit 0..7
will enable the LTC..“
Documentation Addendum
39
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-89
The last sentence of the first paragraph should be replaced by “The GPTA module
provides a total of 56 input lines and 112 output lines, assigned to seven I/O groups
IOG[6:0] and seven output groups OG[6:0].”
Figure 22-59 should be updated with the below figure:
56
GTC
Input
Multiplexer
32
GTC Groups
I/O Groups
GTCG0
IOG0
GTCG1
32
56
GTCG2
GTCG3
LTC
Input
Multiplexer
IOG2
OUT
[55:00]
IOG4
Output
Multiplexer
LTCG0
56
IN
[55:00]
56
LTC Groups
IOG1
IOG3
IOG5
IOG6
LTCG1
64
Output
Groups
LTCG2
LTCG3
OG0
64
56
LTCG4
OUT
[111:56]
LTCG5
8
8
OG2
LTCG6
OG3
LTCG7
OG4
OG5
PDL[3:0]
INT[3:0]
OG6
CLK[7:0]
24
8
OG1
FPC[5:0]
GPTA
Module
Kernel
INT[1:0]
INT[3:0]
4
MCA06382_c
Figure 22-59 Input/Output Line Sharing Unit Overview
Documentation Addendum
40
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-90
Figure 22-60 should be updated with the below figure with the example for OG2
corrected:
Example for an
LTC Group:
LTCG3
LTC24IN
LTC25IN
LTC26IN
LTC27IN
LTC28IN
LTC29IN
LTC30IN
LTC31IN
LTC24
LTC25
LTC26
LTC27
LTC28
LTC29
LTC30
LTC31
Example for an
GTC Group:
GTCG1
LTC24OUT
GTC08IN
LTC25OUT
LTC26OUT
LTC27OUT
LTC28OUT
LTC29OUT
LTC30OUT
LTC31OUT
GTC09IN
GTC10IN
GTC11IN
GTC12IN
GTC13IN
GTC14IN
GTC15IN
Example for an
I/O Group:
IOG5
IN40
IN41
IN42
IN43
IN44
IN45
IN46
IN47
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
IO40
IO41
IO42
IO43
IO44
IO45
IO46
IO47
OUT40
OUT41
OUT42
OUT43
OUT44
OUT45
OUT46
OUT47
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
FPC/INT
Group
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
GTC09OUT
GTC10OUT
GTC11OUT
GTC12OUT
GTC13OUT
GTC14OUT
GTC15OUT
Example for an
Output Group:
OG2
Clock Group
Clock Bus
of
Clock
Distribution
Logic
GTC08OUT
GTC08
GTC09
GTC10
GTC11
GTC12
GTC13
GTC14
GTC15
FPC0
FPC1
FPC2
FPC3
FPC4
FPC5
INT0
INT1
O72
O73
O74
O75
O76
O77
O78
O79
OUT72
OUT73
OUT74
OUT75
OUT76
OUT77
OUT78
OUT79
PDL/INT
Group
SOL0
SOL1
SOL2
SOL3
SOL4
SOL5
INT0
INT1
PDL Bus
of
PDL0/
PDL1
INT0
INT1
INT2
INT3
PDL0
PDL1
PDL2
PDL3
INT0
INT1
INT2
INT3
MCA06383_c
Figure 22-60 Group Definitions For I/O Line Sharing Unit
Documentation Addendum
41
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-91
The third and fourth paragraphs should be replaced by:
“An I/O group combines eight GPTA I/O lines connected to bi-directional device pins with
its input and output lines. This results in seven I/O groups, IOG0 to IOG6, supporting
56 I/O lines.”
“An output group combines eight GPTA output lines connected to device pins as an
output. This results in seven output groups, OG0 to OG6, supporting 56 output lines.”
In Table 22-8, the input and output lines assigned for I/O Groups and Output Groups
should be replaced by:
Table 22-8
Group to I/O lines/Cell Assignment
Group/Module
Cell/Line
Input
Output
IOG0
–
IN[07:00]
OUT[07:00]
IOG1
–
IN[15:08]
OUT[15:08]
IOG2
–
IN[23:16]
OUT[23:16]
IOG3
–
IN[31:24]
OUT[31:24]
IOG4
–
IN[39:32]
OUT[39:32]
IOG5
–
IN[47:40]
OUT[47:40]
IOG6
–
IN[55:48]
OUT[55:48]
OG0
–
–
OUT[63:56]
OG1
–
–
OUT[71:64]
OG2
–
–
OUT[79:72]
OG3
–
–
OUT[87:80]
OG4
–
–
OUT[95:88]
OG5
–
–
OUT[103:96]
OG6
–
–
OUT[111:104]
I/O Group
Output Group
Documentation Addendum
42
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-94
The first paragraph of Section 22.2.4.2 should be replaced by “The output multiplexer
shown in Figure 22-59 and Figure 22-61 below connects the 32 GTC output lines and
the 64 LTC output lines with the I/O groups (7 x 8 = 56 input/output lines) and the output
groups (7 x 8 = 56 output lines).
Figure 22-61 should be updated with the below figure:
LTC Groups
GTC Groups
I/O Groups
GTCG0
GTC[07:00]
8
GTCG1
GTC[15:08]
8
GTCG2
GTC[23:16]
8
GTCG3
GTC[31:24]
8
LTCG0
LTC[07:00]
8
LTCG1
LTC[15:08]
8
LTCG2
LTC[23:16]
8
LTCG3
LTC[31:24]
8
LTCG4
LTC[39:32]
8
LTCG5
LTC[47:40]
8
LTCG6
LTC[55:48]
8
LTCG7
LTC[63:56]
8
Output Groups
IOG0
IOG1
IOG2
IOG3
IOG4
IOG5
IOG6
OG0
OG1
OG2
OG3
OG4
OG5
OG6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
OMG
00
OMG
04
OMG
01
OMG
08
OMG
05
OMG
02
OMG
0C
OMG
09
OMG
06
OMG
03
OMG
10
OMG
0A
OMG
07
OMG
14
OMG
11
OMG
0B
OMG
18
OMG
15
OMG
12
OMG
1C
OMG
19
OMG
16
OMG
13
OMG
20
OMG
1D
OMG
1A
OMG
17
OMG
24
OMG
21
OMG
0D
OMG
1B
OMG
28
OMG
25
OMG
22
OMG
29
OMG
26
OMG
23
OMG
2C
OMG
2D
OMG
2A
OMG
27
OMG
2B
Output
Multiplexer
MCA06384_c
Figure 22-61 Output Multiplexer
The third sentence onwards for the paragraph below Figure 22-61 should be replaced
by “In the same way, I/O groups and output groups are grouped into 14 groups (seven
I/O groups and seven output groups) with 8 lines each. IOG0 and OG0 share the same
physical pins, similarly for IOG1 and OG1, IOG2 and OG2. IOG3 and IOG6 share the
same physical pins for inputs and outputs.
Documentation Addendum
43
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-96
The second sentence of the third bulleted point should be replaced by:
“I/O groups IOG0 to IOG6 are assigned to index variable (g = 0 to 6) and output groups
OG0 to OG6 are assigned to index variable (g = 7 to 13).”
Figure 22-63 should be updated with the below figure:
MRACTL
OMLn
OMCRLg
OMCRHg
(g = 0-13)
3
GTC Group 8
(OMG0g)
OMGn
M
U
X
LTC Group 8
(OMG1g)
M
U
X
LTC Group 8
(OMG2g)
M
U
X
MAEN
Not a reserved
OMGn bit combination
0
3
000
001
010
&
M
U
X
0
1
M
U
X
To input of
I/O Group g or
Output Group (g-7)
2. Level
Mux
1. Level
Mux
MCA06386_c
Figure 22-63 Output Multiplexer Group (Programmer’s View)
Documentation Addendum
44
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-97
In Table 22-10, the input and output lines assigned for I/O Groups IOG3 and Output
Groups OG0 to OG7 should be replaced by:
Table 22-8
Output Multiplexer Control Register Assignment
Input/Output Group
Controlled by Multiplexer
Control Register
Selectable
Groups via
OMGng
IOG3
IN[27:24]/OUT[27:24]
OMCRL3
IN[31:28]/OUT[31:28]
OMCRH3
GTGG3,LTCG3,
LTCG7
IN[51:48]/OUT[51:48]
OMCRL6
IN[55:52]/OUT[55:52]
OMCRH6
OUT[59:56]
OMCRL7
OUT[63:60]
OMCRH7
OUT[67:64]
OMCRL8
OUT[71:68]
OMCRH8
OUT[75:72]
OMCRL9
OUT[79:76]
OMCRH9
OUT[83:80]
OMCRL10
OUT[87:84]
OMCRH10
OUT[91:88]
OMCRL11
OUT[95:92]
OMCRH11
OUT[99:96]
OMCRL12
OUT[103:100]
OMCRH12
OUT[107:104]
OMCRL13
OUT[111:108]
OMCRH13
IOG6
OG0
OG1
OG2
OG3
OG4
OG5
OG6
Documentation Addendum
45
GTGG2,LTCG2,
LTCG6
GTGG3,LTCG3,
LTCG7
GTGG0,LTCG0,
LTCG4
GTGG1,LTCG1,
LTCG5
GTGG2,LTCG2,
LTCG6
GTGG3,LTCG3,
LTCG7
GTGG0,LTCG0,
LTCG4
GTGG1,LTCG1,
LTCG5
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-99
Figure 22-64 should be updated with the below figure:
GTC Groups
GTCG0
GTC[07:00]
8
IOG0
IOG1
I/O Groups
IOG2
IOG3
IOG4
IOG5
LTC Gr oups
IOG6
8
GTCG1
GTC[15:08]
8
GTCG2
GTC[23:16]
8
GIMG
01
8
GIMG
02
8
GIMG
03
GIMG
10
8
GIMG
11
8
LTCG0
LTC[07:00]
8
LTCG1
LTC[15:08]
8
LTCG2
LTC[23:16]
8
LTCG3
LTC[31:24]
8
LTCG4
LTC[39:32]
8
LTCG5
LTC[47:40]
8
LTCG6
LTC[55:48]
8
LTCG7
LTC[63:56]
8
FPC[5:0]
INT[1:0]
8
8
GIMG
00
8
8
GTCG3
GTC[31:24]
GIMG
12
GIMG
20
GIMG
21
GIMG
22
GIMG
23
GIMG
30
GIMG
31
LTC
Input
Multiplexer
GIMG
32
GIMG
33
GIMG
40
GIMG
41
GIMG
42
GIMG
43
MCA06387_c
Figure 22-64 GTC Input Multiplexer
Documentation Addendum
46
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-100
The second sentence of the first paragraph should be replaced by:
“GTC input Multiplexer Group are grouped into seven IOGs (IOG[6:0]) with seven blocks
of eight lines each and eight LTC groups (LTCG[7:0]) with 8 cells each.”
Page 22-101
The second bulleted point should be replaced by:
“Index n is a group number. I/O groups IOG[3:0] have group number 0, I/O groups
IOG[6:4] have group number 1, local timer cell groups LTCG[3:0] have group number 2,
Local Timer Cell Groups LTCG[7:4] have group number 3, and the FPC/INT group has
group number 4.”
The last sentence of the next paragraph should be replaced by:
“For example, based on Figure 22-64, each of the eight GTC input multiplexer output
lines to GTC group GTCG2 is connected via five GIMGn2 (n =0-4) with the eight outputs
of two I/O group (IOG2 and IOG6), two LTC groups (LTCG2 and LTCG6), and the
FPC/INT group.”
Page 22-103
In Table 22-11, the text IOG3 of GTCG2 row should be replaced by “IOG6”
Documentation Addendum
47
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-104
Figure 22-67 should be updated with the below figure:
LTC Groups
LTCG0
LTC[07:00]
8
IOG0
IOG1
I/O Groups
IOG2
IOG3
IOG4
IOG5
GTC Groups
IOG6
8
8
8
8
LTCG4
LTC[39:32]
8
LTCG5
LTC[47:40]
8
LTCG6
LTC[55:48]
LTCG7
LTC[63:56]
8
8
LIMG
04
LIMG
01
LIMG
05
LIMG
02
LIMG
06
LIMG
03
LIMG
10
8
LIMG
07
LIMG
14
LIMG
11
8
8
PDL[3:0]
INT[3:0]
LTCG3
LTC[31:24]
8
GTCG1
GTC[15:08]
CLK[7:0]
8
8
8
GTCG3
GTC[31:24]
LTCG2
LTC[23:16]
LIMG
00
8
GTCG0
GTC[07:00]
GTCG2
GTC[23:16]
LTCG1
LTC[15:08]
LIMG
15
LIMG
12
LIMG
16
LIMG
20
LTC
Input
Multiplexer
LIMG
24
LIMG
21
8
LIMG
25
LIMG
22
LIMG
26
8
LIMG
23
LIMG
27
8
LIMG
30
LIMG
31
LIMG
32
LIMG
33
LIMG
34
LIMG
35
LIMG
36
LIMG
37
8
LIMG
40
LIMG
41
LIMG
42
LIMG
43
LIMG
44
LIMG
45
LIMG
46
LIMG
47
MCA06390_c
Figure 22-67 LTC Input Multiplexer
Page 22-105
The second sentence of the first paragraph should be replaced by:
“IOGs and GTCs are grouped into seven IOGs (IOG[6:0]) with seven blocks of eight
lines each and four GTC groups (GTCG[3:0]) with 8 cells each.”
Documentation Addendum
48
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-106
The second bulleted point of the first paragraph should be replaced by:
“Index n is a group number. I/O groups IOG[3:0] have group number 0, I/O groups
IOG[6:4] have group number 1, Global Timer Cell Groups GTCG[3:0] have group
number 2, clock bus lines CLK[7:0] have group number 3, and the PDL/INT group has
group number 4.”
The last sentence of the next paragraph should be replaced by:
“For example, based on Figure 22-67, each of the eight LTC input multiplexer output
lines to LTC group LTCG2 is connected via five LIMGn2 (n = 0-4) with the eight outputs
of two I/O group (IOG2 and IOG6), one GTC group (GTCG2), the clock group, and the
PDL/INT group.”
Page 22-108
In Table 22-12, the text IOG3 of LTCG2 row should be replaced by “IOG6”
Page 22-125
The text "else DCMk.Timer ++" must be included between the last two "endif" lines on
the bottom.
Page 22-132
Below the second last line of the page : "GTCk.Cell_Enable = 1", the following line must
be added: "GTCk.Enable_Of_Action = 0"
Pages 22-173 and 22-174
The long name of register LTCCTRk must be corrected as “Local Timer Cell Control
Register k .....”.
Page 22-178
The long name of register LTCCTR63 must be corrected as “Local Timer Cell Control
Register 63”.
Page 22-184
The text for Section Output Multiplexer Control Registers should be replaced by:
“Two registers, OMCRL and OMCRH, are assigned to each I/O Group IOG[6:0] and
each Output Group OG[6:0]. OMCRL[6:0]/OMCRH[6:0] are assigned to IOG[6:0] and
OMCRL[13:7]/OMCRH[13:7] are assigned to OG[6:0].
OMCRL controls the connections of group pins 0 to 3. OMCRH controls the connections
of group pins 4 to 7.”
Documentation Addendum
49
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-200
The first sentence of the first paragraph of Section 22.4.3.1 should be replaced by:
“In the TC1766, the seven I/O groups and three output groups of GPTA0 with their input
lines IN[55:0] and output lines OUT[79:0] are assigned to five 8-bit port groups and two
4-bit port groups as shown in Figure 22-75.”
Figure 22-75 should be updated with the below figure:
Port Control
OUT[79:0] (from GPTA0)
[7:0]
[7:0]
IN[55:0]
IOG0
IOG0
[63:56]
OG0
[8:15]
IOG1
[8:15]
IOG1
[71:64]
OG1
[23:16]
IOG2
[23:16]
[79:72]
IOG2
OG2
[31:24]
IOG3
[31:24]
IOG3
[55:48]
[55:48]
IOG6
IOG6
[39:32]
IOG4
[39:32]
IOG4
[47:40]
IOG5
[47:40]
IOG5
P0.[7:0]
P0.[15:8]
P1.[7:0]
P1.[11:8]
P4.[3:0]
P2.[7:0]
P5.[7:0]
8
8
8
4
4
8
8
MCA06398_c
Figure 22-75 I/O Port Line Assignment
Documentation Addendum
50
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 22-205
The following sentence should be added above Table 22-22, “ Table 22-22 also shows
the assignment of the GPTA module’s four OGx output group lines OGx.y to the output
signals OUT[111:80].”
Table 22-22 GPTA0 to MSC Interconnection Assignment
MSC0
Input Line
Assigned
GPTA0 Output Line
MSC0
Input Line
Assigned
GPTA0 Output Line
ALTIN0.0
OUT80 / OG3.0
ALTIN1.0
OUT96 / OG5.0
ALTIN0.1
OUT81 / OG3.1
ALTIN1.1
OUT97 / OG5.1
ALTIN0.2
OUT82 / OG3.2
ALTIN1.2
OUT98 / OG5.2
ALTIN0.3
OUT83 / OG3.3
ALTIN1.3
OUT99 / OG5.3
ALTIN0.4
OUT84 / OG3.4
ALTIN1.4
OUT100 / OG5.4
ALTIN0.5
OUT85 / OG3.5
ALTIN1.5
OUT101 / OG5.5
ALTIN0.6
OUT86 / OG3.6
ALTIN1.6
OUT102 / OG5.6
ALTIN0.7
OUT87 / OG3.7
ALTIN1.7
OUT103 / OG5.7
ALTIN0.8
OUT88 / OG4.0
ALTIN1.8
OUT104 / OG6.0
ALTIN0.9
OUT89 / OG4.1
ALTIN1.9
OUT105 / OG6.1
ALTIN0.10
OUT90 / OG4.2
ALTIN1.10
OUT106 / OG6.2
ALTIN0.11
OUT91 / OG4.3
ALTIN1.11
OUT107 / OG6.3
ALTIN0.12
OUT92 / OG4.4
ALTIN1.12
OUT108 / OG6.4
ALTIN0.13
OUT93 / OG4.5
ALTIN1.13
OUT109 / OG6.5
ALTIN0.14
OUT94 / OG4.6
ALTIN1.14
OUT110 / OG6.6
ALTIN0.15
OUT95 / OG4.7
ALTIN1.15
OUT111 / OG6.7
Page 22-209
The following attention paragraph must be added at the bottom of the page:
Attention: If the frequency of the module timer clock fGPTA0 is configured to be
smaller than the control clock fCLC (as programmed in register
GPTA0_FDR) or even disabled (as programmed in register
GPTA0_EDCTR), an action initiated by a write access to a module
register could be significantly delayed, because the register write
access is clocked by fCLC and the register content is evaluated by
hardware using the slower or disabled module timer clock fGPTA0.
Documentation Addendum
51
V1.2, 2007-04
TC1766
User’s Manual - Peripheral Units Part (Volume 2)
Page 23-9
The formula on the bottom of the page must be corrected into:
20
t TPERIOD = TRLD × ----------f ADC
(23.1)
Page 23-96
Footnote 1 must be deleted from AN24 to AN31 cells.
Page 23-97
The below text must be inserted before Figure 23-30.
For safety reasons, the measurement of the ADC channels 0-15 (GRPS = 0) is always
related to the reference input pin (the programmed selection is not taken into account).
The measurement of the ADC channels 16-31 (GRPS = 1) is always related to the
programmed reference (the programmed selection is taken into account).
Page 24-6
The two heading paragraphs must be corrected in the following way:
Replace “Configuration 3” with “Configuration 2”
Replace “Configuration 4” with “Configuration 3”
Page 24-7
The text in the leftmost column of Table 24-1 must be corrected in the following way:
Replace “(Configuration 2)” with “(Configuration 1)”
Replace “(Configuration 3)” with “(Configuration 2)”
Replace “(Configuration 4)” with “(Configuration 3)”
The last row of Table 24-1 (FAINxN | FAINxP I XXB | 512) must be deleted.
Page 24-8
The second formula of equation (24.1) should be corrected into:
VFAREFM = VFAGND + (VFAREF -VFAGND)/2
Documentation Addendum
52
V1.2, 2007-04
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG