CD4048BMS CMOS Multifunction Expandable 8 Input Gate December 1992 Features Pinout • High-Voltage Type (20V Rating) CD4048BMS TOP VIEW • Three State Output • Many Logic Functions Available in One Package 16 VDD J (OUTPUT) 1 • Standardize, Symmetrical Output Characteristics 15 EXPAND Kd 2 • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC H 3 14 A G 4 13 B F 5 12 C E 6 11 D INPUTS • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V INPUTS Kb 7 10 Ka VSS 8 9 Kc • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Functional Diagram Applications BINARY CONTROL INPUTS • Selection of Up to 8 Logic Functions FUNCTION CONTROL • Digital Control of Logic Ka • General Purpose Gating Logic - Decoding - Encoding 10 A B C D 14 13 12 11 EXPAND 15 INPUTS Description CD4048BMS is an 8-input gate having four control inputs. Three binary control inputs - Ka, Kb, and Kc - provide the implementation of eight different logic functions. These functions are OR, NOR, AND, NAND, OR/AND, OR/NAND, AND/OR and AND/ NOR. INPUTS E F G H 6 5 4 3 3 STATE CONTROL Kb Kc Kd 7 9 2 I J OUTPUT VSS = 8 VDD = 16 A fourth control input, Kd, provides the user with a 3-state output. When control input Kd is high, the output is either a logic 1 or a logic 0 depending on the inner states. When control input Kd is low, the output is an open circuit. This feature enables the user to connect this device to a common bus line. In addition to the eight input lines, an EXPAND input is provided that permits the user to increase the number of inputs into a CD4048BMS (see Figure 2). For example, two CD4048BMS’s can be cascaded to provided a 16-input multifunction gate. When the EXPAND input is not used, it should be connected to VSS. The CD4048BMS is supplied in these 16 lead outline packages: Braze Seal DIP H4S Frit Seal DIP H1E Ceramic Flatpack H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-912 File Number 3314 Specifications CD4048BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 0.5 µA 2 +125 C - 50 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 0.5 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Functional F VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V 1 +25oC -0.4 - µA Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V 2 +125oC -12 - µA VDD = 18V 3 -55oC -0.4 - µA VDD = 20V 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-913 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4048BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Ka to Output Transition Time SYMBOL TPHL TPLH CONDITIONS (NOTE 1, 2) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 600 ns - 810 ns - 200 ns - 270 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND 1, 2 TEMPERATURE o o -55 C, +25 C VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 MAX UNITS - 0.25 µA +125 C - 7.5 µA -55oC, +25oC - 0.5 µA +125oC - 15 µA o VDD = 10V, VIN = VDD or GND MIN - 0.5 µA +125oC - 30 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL Input Voltage High VIH Propagation Delay Ka to Output TPHL1 TPLH1 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V 1, 2 o +125 C 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA +25oC, +125oC, - 3 V VDD = 10V, VOH > 9V, VOL < 1V 1, 2 VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V 1, 2, 3 +25oC - 300 ns 1, 2, 3 +25oC - 240 ns VDD = 10V VDD = 15V 7-914 -55oC Specifications CD4048BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay Inputs to Output Propagation Delay Kb to Output Propagation Delay Kc to Output Propagation Delay Expand Input to Output SYMBOL TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 TPLH4 TPHL5 TPLH5 CONDITIONS VDD = 5V Input Capacitance 3 State Output Capacitance CIN MAX UNITS 1, 2, 3 +25oC - 600 ns o 1, 2, 3 +25 C - 300 ns 1, 2, 3 +25oC - 240 ns 1, 2, 3 +25 oC - 450 ns VDD = 10V 1, 2, 3 +25oC - 170 ns VDD = 15V 1, 2, 3 +25oC - 110 ns 1, 2, 3 +25 oC - 280 ns VDD = 10V 1, 2, 3 +25o C - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns VDD = 5V 1, 2, 3 +25 oC - 380 ns VDD = 10V 1, 2, 3 +25oC - 180 ns 1, 2, 3 o +25 C - 130 ns 1, 2, 4 +25o C - 160 ns 1, 2, 4 +25oC - 70 ns 1, 2, 4 +25oC - 50 ns VDD = 10V 1, 2, 3 +25 oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns 1, 2 o +25 C - 7 pF 1, 2 oC - 10 pF VDD = 5V VDD = 5V TPHZ, LZ VDD = 5V TPZH, ZL VDD = 10V TTLH TTHL MIN VDD = 15V VDD = 15V Transition Time TEMPERATURE VDD = 10V VDD = 15V Propagation Delay 3 State Kd to Output NOTES Any Input CO +25 NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 20V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - 25 µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record 7-915 Specifications CD4048BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - SSI IDD ±0.1µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10 Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10 Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B IDD, IOL5, IOH5A, RONDEL10 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 1 2 - 15 16 Static Burn-In 2 Note 1 1 8 2 - 7, 9 - 16 Dynamic BurnIn Note 1 - 8, 15 2, 16 Irradiation Note 2 1 8 2 - 7, 9 - 16 9V ± -0.5V 50kHz 25kHz 1 9 - 14 3-7 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-916 CD4048BMS Logic Diagrams NOR OR NAND AND A B C D E F G H A B C D E F G H A B C D E F G H A B C D E F G H EXP EXP EXP EXP OR/AND OR/NAND AND/OR AND/NOR A B C D A B C D A B C D A B C D E F G H E F G H E F G H E F G H EXP EXP EXP EXP FIGURE 1. BASIC LOGIC CONFIGURATIONS Ka * * A 14 * * * Ka Kb Kc Kd 10 7 9 2 Kb * B 13 * C 12 * Kc D 11 Ka Ka Kb Kb Kc Kc VDD Kd * Kd Kd EXP 15 * E 6 1 J Kb * F 5 Kd * G VSS VDD 4 * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK * H 3 VSS FIGURE 2. LOGIC DIAGRAM 7-917 CD4048BMS Logic Diagrams (Continued) NOR 11 12 13 14 15 3 4 5 6 NAND Ka - Kb - Kc 0-0-0 1-0-1 AND OR AND/OR 1-1-1 0-0-1 1-0-0 AND/NOR OR/NAND 1-1-0 OR/AND 0-1-1 0-1-0 FIGURE 3. ACTUAL CIRCUIT LOGIC CONFIGURATIONS Applications of Expand Input OR FUNCTION VDD J (OUTPUT) 1 Kd VDD 2 16 14 A H 3 VDD G 4 13 B F 5 12 C E 6 Kb 7 11 D VSS X1 X2 X3 X4 15 8 1/2 CD4002A 10 Ka 9 Kc VDD OUTPUT VDD Kd 16 2 15 VSS VDD VDD Kd 1 16 2 15 H1 3 14 A1 H2 3 14 A2 13 B1 G2 4 13 B2 F1 5 12 C1 F2 5 12 C2 E1 6 Kb 7 11 D1 10 Ka VSS E2 6 Kb 7 11 D2 10 Ka VDD 8 9 8 Kc VSS 9 Kc VSS 16 - INPUT NOR GATE J = A1 +B1 +C1 +D1 +E1 +F1 +G1 +H1 +A2 +B2 +C2 +D2 +E2 +F2 +G2 +H2 FIGURE 4. 12 INPUT OR/AND GATE FIGURE 5. 16 INPUT NOR GATE IMPLEMETATION OF EXPAND INPUT FOR 9 OR MORE INPUTS OUTPUT FUNCTION EXP G1 4 VSS 12 - INPUT OR/AND GATE J = (A+B+C+D) . (E+F+G+H) . (X1+X2+X3+X4) 1 J(OUTPUT) FUNCTION NEEDED AT EXPAND INPUT OUTPUT BOOLEAN EXPRESSION NOR OR J=(A+B+C+D+E+F+G+H)+(EXP) OR OR J=(A+B+C+D+E+F+G+H)+(EXP) AND NAND J=(ABCDEFGH)•(EXP) NAND NAND J=(ABCDEFGH)•(EXP) OR/AND NOR J=(A+B+C+D)•(E+F+G+H)•(EXP) OR/NAND NOR J=(A+B+C+D)•(E+F+G+H)•(EXP) AND/NOR AND J=(ABCD)+(EFGH)+(EXP) AND/OR AND J=(ABCD)+(EFGH)+(EXP) NOTES: 1. (EXP) designates the EXPAND function (i.e., X1 + X2 + . . .XN). 2. Refer to FUNCTION TRUTH TABLE for connection of unused inputs. 7-918 VSS CD4048BMS FUNCTION TRUTH TABLE OUTPUT FUNCTION BOOLEAN EXPRESSION Ka Kb Kc UNUSED INPUT* NOR J=A+B+C+D+E+F+G+H 0 0 0 VSS OR J=A+B+C+D+E+F+G+H 0 0 1 VSS OR/AND J=(A+B+C+D)•(E+F+G+H) 0 1 0 VSS OR/NAND J=(A+B+C+D)•(E+F+G+H) 0 1 1 VSS AND J=ABCDEFGH 1 0 0 VDD NAND J=ABCDEFGH 1 0 1 VDD AND/NOR J=ABCD+EFGH 1 1 0 VDD AND/OR J=ABCD+EFGH 1 1 1 VDD Kd = 1 Normal Inverter Action Kd = 0 High Impedance Output EXPAND Input = 0 *See Figures 1, 2, 3, 4 and 5 AMBIENT TEMPERATURE (TA) = +25oC 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 FIGURE 6. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 7. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-919 CD4048BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -5 -10 -15 -10V -20 -25 -15V -30 -5 -10V TRANSITION TIME (fTHL, fTLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 200 10V 15V 40 60 80 100 FIGURE 10. TYPICAL PROPAGATION DELAY TIME (LOGIC INPUTS TO OUTPUT) AS A FUNCTION OF LOAD CAPACITANCE DYNAMIC POWER DISSIPATION (PD) (µW) 6 4 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 15V 50 0 0 LOAD CAPACITANCE (CL) (pF) 105 8 -15 FIGURE 9. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 300 20 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 11. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50pF 2 SUPPLY VOLTAGE (VDD) = 5V 4 10 8 6 4 10V 2 103 15V 8 6 4 2 102 8 6 4 2 10 2 1 -10 -15V AMBIENT TEMPERATURE (TA) = +25oC 0 4 6 8 2 4 6 8 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 8. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 100 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 (Continued) 2 4 6 8 2 4 6 8 103 10 102 INPUT FREQUENCY (fI) (kHz) 104 2 4 6 8 FIGURE 12. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY 7-920 105 CD4048BMS Test Circuits and Wave Forms VDD VDD H PULSE GENERATOR 500µF OUTPUT CL 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 16 1 2 15 3 14 4 13 5 12 6 11 7 10 CL = 15pF OR 50pF 0.1µF INPUT 9 8 VDD FIGURE 13. DYNAMIC POWER DISSIPATION TEST CIRCUIT VDD (tPLZ) (tPZL) VSS (tPHZ) (tPZH) 50pF PULSE GENERATOR FIGURE 14. TEST CIRCUIT FOR tPHL, tTHL, AND tTHL (AND) MEASUREMENTS 1 16 2 15 3 14 4 (AND) 13 5 12 6 11 7 10 8 9 Kd Kd 50% tPZL OUTPUT tPLZ 90% 10% tPZH 90% 10% OUTPUT VDD tPHL VSS FIGURE 15. TEST CIRCUIT FOR tPZL, tPZH, tPLZ, AND tPHZ (AND) FIGURE 16. WAVEFORMS FOR tPZL, tPZH, tPLZ AND tPHZ (AND) 50% 50% INPUT INPUT 90% 10% 50% OUTPUT OUTPUT tPHL tTHL FIGURE 17. WAVEFORMS FOR tPHL AND tPHL (AND) tTLH FIGURE 18. WAVEFORMS FOR tTHL AND tTLH (AND) 7-921 CD4048BMS Chip Dimensions and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. 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