AK4118AEQ

[AKD4118A-A]
AKD4118A-A
AK4118A Evaluation Board Rev.0
GENERAL DESCRIPTION
AKD4118A-A is the evaluation board for AK4118A, 192kHz digital audio transceiver. This board has
optical and BNC connector to interface with other digital audio equipment.
„ Ordering guide
AKD4118A-A
--- Evaluation board for AK4118A
(A cable for connecting with printer port of IBM-AT compatible PC
and a control software are packed with this. The control software
does not operate on Windows NT.)
FUNCTION
† Digital interface
-S/PDIF :
8 channel input (optical or BNC)
2 channel output (optical or BNC )
- Serial audio data I/F :
1 input/output (for DIR deta output/DIT data input. 10-pin port)
-B,C,U,V bit :
1 input/output port (10-pin port)
-Serial control data I/F
1 input/output port (10-pin port)
5V
REG
GND
Control
3.3V
Opt
RX0
RX1
RX7
TX0
AK4118A
Opt
TX1
B,C,U,V
Serial Data out
(For DIR)
Figure 1. AKD4118A-A Block Diagram
*Circuit diagram and PCB layout are attached at the end of this manual.
[KM100300]
-1-
2009/08
[AKD4118A-A]
Evaluation Board Manual
„ Operating sequence
(1) Set up the power supply lines.
[+ 5V]
(Red) = 5V
[GND]
(Black) = 0V
Each supply line should be distributed from the power supply unit.
(2) Set up the evaluation mode and jumper pins. (Refer to the following item.)
(3) Connect cables. (Refer to the following item.)
(4) Power on.
The AK4118A should be reset once bringing PDN(SW2) “L” upon power-up.
„ Evaluation modes
(1) Evaluation for DIR (Default)
S/PDIF in (optical or BNC) – AK4118A – Serial Data out (10pin port)
S/PD IF
Optical, XLR or
BNC connector
AK4118A
(DIR)
MCLK
BICK
LR CK
SDTO
PORT2
(10pin Header)
MCLK
BICK
LRCK
SDTO
DAC
AKD4118A-A
The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical
connector(PORT1: TORX176) or BNC connector. The AKD4118A-A can be connected with the AKM’s
DAC evaluation board via 10-line cable.
a.
Set-up of Bi-phase Input
RX0 and RX1-7 should not select BNC at the same time.
a-1. RX0
Connector
Optical (PORT1)
BNC (J2)
JP2(RXP0)
JP3(RXN0)
OPT
BNC
BNC
BNC
Table 1. Set-up of RX0
a-2. RX1, 2, 3, 4, 5, 6, and 7 can be inputted from a BNC (J2) connector only.
Only RX1, RX2 and RX 3 can be used in parallel mode. The jumper which selects the Rx channel should be
Short.
Input
JP
[KM100300]
RX1
JP4
Short
RX2
JP5
Short
RX3
JP6
Short
Table 2. Set-up of
RX4
RX5
RX6
JP7
JP8
JP9
RX4
RX5
RX6
RX1, 2, 3, 4, 5, 6 and 7
-2-
RX7
JP10
RX7
2009/08
[AKD4118A-A]
a-3. Set-up of AK4118A input path
It sets up by SW 1_1 and SW 1_5 in parallel mode. Please set up IPS2-0 bits in serial mode.
IPS1 pin
IPS0 pin
(SW1_5)
(SW1_1)
INPUT Data
IPS2 bit
IPS1 bit
IPS0 bit
0
0
0
RX0
0
0
1
RX1
0
1
0
RX2
0
1
1
RX3
1
0
0
RX4
1
0
1
RX5
1
1
0
RX6
1
1
1
RX7
(In parallel mode, IPS2 is fixed to “0”)
Table 3. Recovery Data Select
-
b.
Default
Set-up of clock input and output
SDTO
DAUX
GND
GND
BICK
LRCK
GND
10
GND
1
GND
PORT2
DIR
MCLK
The signal level outputted/inputted from PORT2 is 3.3V.
5
6
Figure 2. PORT2 pin layout
b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of
MCKO1/MCKO2 is selected by OCKS 1-0.
Output
JP12
signal
Default
MCKO1
MCKO1
MCKO2
MCKO2
Table 4. Set-up of MCKO1/MCKO2
OCKS1 pin
(SW3_2)
OCKS1 bit
0
0
1
1
[KM100300]
OCKS0 pin
(SW3_3)
OCKS0 bit
(X’tal)
MCKO1
0
256fs
256fs
1
256fs
256fs
0
512fs
512fs
1
128fs
128fs
Table 5. Master Clock Frequency Select
-3-
MCKO2
fs (max)
256fs
128fs
256fs
64fs
96 kHz
96 kHz
48 kHz
192 kHz
Default
2009/08
[AKD4118A-A]
b-2. Set-up of input/output of BICK and LRCK
Please select SW 3_7 (DIR_I/O) according to the setup of audio format of AK4118A (Refer to Table 7).
Audio format
SW3_7 (DIR_I/O)
Slave mode
0
Master mode
1
Table 6. Set-up of DIR_I/O
c.
Default
Set-up of Audio format
It sets up by SW 1_2, SW 1_3 and SW1_4 in parallel mode. Please set up DIF2-0 bit in serial mode.
DIF2 pin
(SW1_4)
DIF2 bit
DIF1 pin
(SW1_3)
DIF1 bit
0
0
0
1
0
0
2
0
1
3
0
1
4
1
0
5
1
0
6
1
1
7
1
1
Mode
d.
DIF0 pin
(SW1_2)
DIF0 bit
DAUX
LRCK
SDTO
BICK
I/O
24bit, Left
justified
24bit, Left
1
justified
24bit, Left
0
justified
24bit, Left
1
justified
24bit, Left
0
justified
1
24bit, I2S
24bit, Left
0
justified
1
24bit, I2S
Table 7. Audio format
0
16bit, Right
justified
18bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
24bit, Left
justified
24bit, I2S
I/O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
L/H
O
64fs
O
H/L
I
64-128fs
I
L/H
I
64-128fs
I
Default
Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_1 and
JP18. In serial mode, it can be selected by CM1-0 bits.
CM1 pin
(SW3_1)
CM1 bit
CM0 pin (JP18)
(UNLOCK)
PLL
X'tal
Clock
source
SDTO
source
0
1
ON
OFF
ON
ON
ON(Note)
ON
ON
ON
PLL(RX)
X'tal
PLL(RX)
X'tal
RX
DAUX
RX
DAUX
CM0 bit
0
0
0 (CM0)
1 (CDTO/CM0=H)
1
0 (CM0)
Default
1
1 (CDTO/CM0=H)
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 8. Clock Operation Mode Select
[KM100300]
-4-
2009/08
[AKD4118A-A]
(2) Evaluation for DIT
Serial Data in(10pin port) – AK4118A – S/PDIF out(optical or BNC)
MCLK
BIC K
LRCK
ADC
DAUX *
MC LK
BICK
LRCK
DAUX
PORT2
(10pin Header)
Optical, XLR or
BNC connector
AK4118A
(DIT)
S/PDIF
* Input to the fifth pin.
AKD4118A-A
MCLK, BICK, LRCK and DAUX are input the via 10pin header (PORT2: DIR).
a. Set-up of a Bi-phase output signal
TX0 and TX1 should not select an optical connector or a BNC connector at the same time.
a-1. The data outputted from TX1 can be selected by OPS12-10 bit.
Connector
JP19 (TX1)
Optical (PORT4)
OPT
BNC (J4)
BNC
Table 9. Set-up of TX1
JP14 (TX1)
BNC
BNC
a-2. As for TX0, only the loop back mode of RX corresponds. This mode is fixed to RX0 in parallel mode. In
serial mode, it can be selected by OPS02-00 bits.
Connector
Optical (PORT4)
BNC (J4)
JP13 (TX0)
JP19 (TXP1)
OPT
Open
BNC
Open
Table 10. Set-up of TX0
JP14 (TXN1)
BNC
BNC
b.Set-up of clock input and output
SDTO
DAUX
GND
GND
BICK
LRCK
GND
10
GND
1
GND
PORT2
DIR
MCLK
The used signals are MCLK, LRCK, BICK, and DAUX.
The signal level outputted and inputted from PORT2 is 3.3V.
5
6
Figure 3. PORT2 pin layout
Clock
MCLK
BICK
LRCK
DAUX
[KM100300]
PORT
I/O
PORT2
OUT
PORT2
IN / OUT
PORT2
IN / OUT
PORT2
IN
Table 11. Clock input/output
-5-
2009/08
[AKD4118A-A]
b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of
MCKO1/MCKO2 sets up by OCKS 1-0.
Output
signal
MCKO1
MCKO2
JP12
Default
MCKO1
MCKO2
Table 12. Selection of MCKO1/MCKO2
OCKS1 pin
(SW3_2)
OCKS1 bit
OCKS0 pin
(SW3_3)
OCKS0 bit
0
0
1
1
(X’tal)
MCKO1
MCKO2
0
256fs
256fs
1
256fs
256fs
0
512fs
512fs
1
128fs
128fs
Table 13. Master Clock Frequency Select
256fs
128fs
256fs
64fs
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Default
b-2. Set-up of input/output of BICK and LRCK
Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4118A (Refer to Table 20).
JP16 and 17 should be fixed to the “DC” side.
Audio format
SW3_8 (DIT_I/O)
Slave mode
0
Master mode
1
Table 14. Set-up of DIT_I/O
c.
Default
Set-up of audio data format
Please refer to Table 7.
d.
Set-up of CM1 and CM0
CM1 pin
(SW3_1)
CM1 bit
CM0 pin
(JP18)
CM0 bit
0
0
0
1
1
0
1
1
(UNLOCK)
PLL
X'tal
Clock source
SDTO
source
0
1
ON
OFF
ON
ON
ON(Note)
ON
ON
ON
PLL(RX)
X'tal
PLL(RX)
X'tal
RX
DAUX
RX
DAUX
Default
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 15. Clock Operation Mode Select
[KM100300]
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2009/08
[AKD4118A-A]
„ B, C, U, V Inputs and output
VOUT
VIN
GND
GND
U
GND
GND
1
B
10
GND
PORT3
BCUV
C
B(block start), C(channel status), U(user data) and V(validity) are inputted/outputted via 10pin header (PORT3:
BCUV). Pin arrangement of PORT3 has become like Figure 3.
6
5
Figure 4. PORT3 pin layout
„ Serial control
The AK4118A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT6
(uP-I/F) with PC by 10-line flat cable packed with the AKD4118A-A. Take care of the direction of connector. There
is a mark at pin#1. The pin layout of PORT6 is as Figure 5.
GND
GND
CCLK
CSN
GND
CDTI
1
GND
2
CDTO
PORT6
uP I/F
GND
SW1_6
JP18
CDTO/CM0=“H”
L
SDA and CM0=“L”(Note)
H
Note: In IIC mode, the chip address is fixed to “01”.
Table 16. Set-up of Parallel mode and Serial mode
NC
Mode
4 wire Serial
IIC
10
9
Figure 5. PORT6 pin layout
This evaluation board encloses control software. A software operation procedure is included in an evaluation board
manual.
[KM100300]
-7-
2009/08
[AKD4118A-A]
„ Toggle switch set-up
SW2
PDN
„ LED indication
LE1
INT0
LE2
INT1
Reset switch for AK4118A. Set to “H” during normal operation. Bring to “L” once after
the power is supplied.
Bright when INT0 pin goes to “H”.
Bright when INT1 pin goes to “H”.
„ DIP switch (SW1) set-up: -off- means “L”
No.
Switch Name
Function
1
IPS0
Set-up of IPS0 pin. (in parallel mode)
2
DIF0
Set-up of DIF0 pin. (in parallel mode)
3
DIF1
Set-up of DIF1 pin. (in parallel mode)
4
DIF2
Set-up of DIF2 pin. (in parallel mode)
Set-up of IPS1 pin. (in parallel mode)
5
IPS1/IIC
Set-up of IIC pin. (in serial mode) “L”: 4 wire Serial, “H”: IIC
Set-up of P/SN pin. “L”: Serial mode, “H”: Parallel mode
6
P/SN
7
TEST
Don’t care
8
ACKS
Don’t care
„ DIP switch (SW3) set-up: -off- means “L”
No.
Switch Name
Function
1
CM1
Set-up of CM1 pin. (in parallel mode)
2
OCKS1
Set-up of OCKS1 pin. (in parallel mode)
3
OCKS0
Set-up of OCKS0 pin. (in parallel mode)
4
PSEL
Don’t care
5
XTL0
See Table 17
6
XTL1
Set-up of the transmission direction of 74AC245
DIR_I/O
7
“L”: When inputting from PORT2, “H”: When outputting from
PORT2
8
DIT_I/O
Don’t care
„ Set-up of XTL1 and XTL0
SW3_6
SW3_5
X’tal Frequency
XTL1
XTL0
X’tal
0
0
11.2896MHz
0
1
12.288MHz
1
0
24.576MHz
1
1
(Use channel status)
Table 17. Set-up of XTL1 and XTL0
[KM100300]
Default
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Default
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
Default
-8-
2009/08
[AKD4118A-A]
„ Jumper set up.
No.
Jumper Name
1
D3V/VD
2
RXP0
4,5,6
RX1-3
7,8,9,10
RX4-7
11,12
DIR MCLK ,
DIT MCLK
13
TX0
18
SDA/CDTO
19
TXP1
[KM100300]
Function
Set-up of Power supply source for 74AC245.
D3V : D3V (default)
VD : VD
Set-up of RXP0 input circuit.
OPT : Optical (default)
BNC : BNC
Set-up of RX1-3 input circuit.
RX4-7 set-up depending serial/parallel mode
RX4-7 : Serial mode (default)
DIF2-0,IPS0 : Parallel mode
MCKO set-up for PORT5(DIT) and PORT2(DIR)
MCKO1 : MCKO1 of AK4118A (default)
MCKO2 : MCKO2 of AK4118A
Set-up of TX0 output circuit.
OPT : Optical
BNC : BNC (default)
Set-up of SDA/CDTO pin.
4 wire Serial : CDTO/CM0=“H”. (default)
IIC : SDA
Set-up of TXP1 input circuit.
OPT : Optical (default)
BNC : BNC
-9-
2009/08
[AKD4118A-A]
Control Software Manual
„ Set-up of evaluation board and control software
1. Set up the AKD4118A-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4118A-A by 10-line type flat cable (packed with AKD4118A-A). Take
care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AKD4118A-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4118a-a.exe” to set up the control program.
5. Then please evaluate according to the follows.
„ Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Write default” button.
3. Then set up the dialog and input data.
„ Explanation of each buttons
1. [Port Setup] :
2. [Write default] :
3. [All Write] :
4. [Read All] :
5. [Function1] :
6. [F3] :
7. [SAVE] :
8. [OPEN] :
9. [Write] :
10. [Read] :
[KM100300]
Set up the printer port.
Initialize the register of AK4118A.
Write all registers that is currently displayed.
All the registers of AK4118A are read.
Dialog to write data by keyboard operation.
Dialog of sequential writing.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
The data corresponding to each register is read.
- 10 -
2009/08
[AKD4118A-A]
„ Explanation of each dialog
1. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box:
Data Box:
Input register address in 2 figures of hexadecimal.
Input register data in 2 figures of hexadecimal.
If you want to write the input data to AK4118A, click “OK” button. If not, click “Cancel” button.
2. [Write Dialog] : Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the “Write” button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to AK4118A, click “OK” button. If not, click “Cancel” button.
„ Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
„ Attention on the operation
If you set up Function1 dialog, input data to all boxes. Attention dialog is indicated if you input data or address that is not
specified in the datasheet or you click “OK” button before you input data. In that case set up the dialog and input data once
more again. These operations does not need if you click “Cancel” button or check the check box.
[KM100300]
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2009/08
[AKD4118A-A]
REVISION HISTORY
Date
(yy/mm/dd)
09/08/05
Manual
Revision
KM100300
Board
Revision
0
Reason
Page
First edition
-
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use
of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
[KM100300]
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2009/08
5
4
3
2
1
D
49
50
51
52
P/SN
AVDD
53
54
55
56
RX0
57
58
RX1
59
60
61
62
RX2
IPS0/RX4
RX3
63
64
CN4
D
P/SN
+
1
10u
C20
0.1u
2
CN1
2
C19
R61
10k
C21
0.47u
1
+
5
PDN
PDN
DIF2/RX7
6
7
8
VIN
DAUX
DAUX
9
10
MCKO1
MCKO1
1
IPS0/RX4
2
3
37
INT1
AVDD
R
38
39
40
VCOM
VSS3
41
42
RX0
43
NC
45
44
RX1
RX2
TEST1
46
47
36
NC
OCKS0/CSN/CAD0
35
DIF0/RX5
OCKS1/CCLK/SCL
34
CM1/CDTI/SDA
33
43
CM0/CDTO/CAD1
32
42
PDN
31
XTI
30
4
TEST2
5
DIF1/RX6
6
VSS1
7
DIF2/RX7
8
IPS1/IIC
U1
AK4118A
XTL0
IPS1/IIC
XTO
MCKO2
MCKO2
12
IPS1/IIC
PDN
29
44
C
41
OCKS0/CSN/CAD
C22
X1
IPS1/IIC
46
45
40
5p
OCKS1/CCLK/SCL
C23
11.2896MHz
11
XTL0
47
INT0
2
C
DIF1/RX6
XTL1
XTL1
1
4
VSS4
RX3
2
3
CN3
48
48
1
DIF0/RX5
P/SN
9
P/SN
DAUX
28
DAUX
XTL0
10
XTL0
MCKO2
27
MCKO2
XTL1
11
XTL1
BICK
26
BICK
12
VIN/GP0
SDTO
25
SDTO
39
5p
CM1/CDTI/SDA
CM0/CDTO/CAD1
38
37
+
LRCK
33
MCKO1
C27
2 10u
32
31
30
28
27
26
25
24
OVDD
A
Title
CN2
Size
A3
Date:
5
4
35
24
MCKO1
INT0
36
LRCK
TX1
23
VOUT
TX0
1
INT1
34
C25
0.1u
C26
2 10u
20
UOUT
19
18
17
BOUT
A
COUT
1
23
22
VSS2
DVDD
21
20
VOUT/GP7
UOUT/GP6
19
COUT/GP5
18
BOUT/GP4
17
16
C24
0.1u
29
LRCK
22
LRCK
+
16
15
SDTO
21
SDTO
NC/GP1
BICK
13
15
BICK
TVDD
14
14
13
TX1/GP3
B
TX0/GP2
B
3
2
AKD4118A-A-48LQFP
AK4118A
Document Number
Tuesday, August 04, 2009
Sheet
1
1
of
Rev
0
3
5
4
3
2
1
CN1
JP1
For U6
For U1, U2, U5
VD
PORT1
D3V
D3V
For U3, U4
6
D3V
6
D3V/VD
VD
VD
5
5
L1
4
3
2
1
GND
VCC
GND
OUT
VD
C7
TORX176
C1
C2 C3 C4
C5
0.1u
0.1u0.1u0.1u
0.1u 0.1u
49
10u
C6
50
C8
+
0.1u
R1
10u
51
JP2
OPT
XLR
BNC
470
D
1
3
5
2
4
6
AVDD
P/SN/ANS
T2
LP2950A
ACKS
+5V
L2
1
short
+
OUT
C11
47u
IN
RXP0
R4
RX1
R5
0.1u
GND
AVDD
AVDD
+
C14
47u
RX2
C15
47u
IPS0
DIF0
DIF1
DIF2/XSEL
IPS1/IIC
P/SN/ANS
TEST
ACKS
R8
short
16
15
14
13
12
11
10
9
JP7
D3V
RX4
RX3
IPS0
AVDD
AVDD
IPS0/RX4
JP8
RX6
TEST
TEST
DIF1/RX6
DIF1
PDN
DIF2/XSEL
R9
1A
1B
2A
2B
3A
3B
4A
4B
15
1
G
A/B
U2A
4
2Y
7
3Y
9
100
R11
4Y
12
100
R12
H
U2B
2
3
DAUX2
4
L
74HC14
EMCK2
VIN
R10
1
1Y
DAUX2
PDN
R22
DIR
100k
100k
R23
100k
B0
B1
B2
B3
B4
B5
B6
B7
DIR
OE
1
19
5
6
7
8
9
MCKO1
MCKO2
MCKO2
DIT_MCLK
100
MCKO2
A0
A1
A2
A3
A4
A5
A6
A7
DAUX
MCKO1
JP12
MCKO1
U3
4
JP11
0.1u
DIR_MCLK
2
3
4
5
6
7
8
9
VIN
C16
SW2
3
100
74HC14
74LVC157
18
17
16
15
14
13
12
11
DVDD
2
B
D1
1S1588
U1
2
3
5
6
11
10
14
13
DVDD
10k
D3V
B
1
JP9
DIF2/XSEL/RX7
A
64
CN2
DIF0/RX5
JP10
RX7
R15
R16
R18
R20
C
63
DIF0
IPS1/IIC
P/SN/ANS
TEST
ACKS
47k
100
100
100
100
62
RX5
1
2
3
4
5
6
7
8
9
MCLK
BICK
LRCK
SDTO
DAUX
60
61
SW1
1
2
3
4
5
6
7
8
RP1
1
2
3
4
5
59
JP6
D3V
PORT2
10
9
8
7
6
58
JP5
short
GND
GND
GND
GND
GND
56
JP4
IN
OVDD
C
55
C13
RX0
75
OUT
+
54
57
J2
R6
R7
D
53
VD
short
short
ACKS
52
TVDD/VDD
T3
TA48M33F
DVDD
P/SN/ANS
RXN0
10u
3
2
AVDD
GND
R3
AVDD
R13
DVDD
OVDD
100
R14
100
100
R17
R19
BICK
100
R21
SDTO
10
11
12
13
LRCK
14
15
A
16
DIR_I/O
74AC245
Title
Size
A3
Date:
5
4
3
2
AKD4118A-A
Document Number
Rev
MAIN1
Tuesday, August 04, 2009
0
Sheet
1
1
of
2
5
4
3
2
1
CN3
PORT3
JP19
OPT
XLR
BNC
1
3
5
1
2
3
4
5
TXP1
2
4
6
10
9
8
7
6
R24
R25
R26
R27
R28
B
C
U
VOUT
VIN
B
100
100
100
100
100
C
VIN
U
BCUV
R29
R30
R31
R32
D
JP13
PORT4
5
6
5
6
47k
47k
47k
47k
VOUT
TX0
IN
VCC
IF
GND
TX0
VD
TXP1
C17
R33
1k
0.1u
TXN1
J4
TX0
18
19
20
D
21
OPT
4
3
2
1
TOTX176
TVDD
TVDD/VDD
17
T5
22
23
24
R36
DA02-F
25
R37
240
26
150
1:1
27
28
29
OVDD
OVDD
C
30
C
31
EBICK
32
CN4
U2C
LE1
6
INT0
EMCK
EMCK2
R45
5
ELRCK
1k
U2D
8
INT1
9
1k
74HC14
U5
R48
10k
R49
470
R51
10k
R52
470
R54
10k
R55
470
VD
B
PORT6
10
8
6
4
2
9
7
5
3
1
CSN
R56
SCL/CCLK
SDA/CDTI
51
SDA(ACK)/CDTO
P/SN/ANS
15
1
G
A/B
1Y
4
2Y
7
3Y
9
4Y
12
37
R50
CM1/CDTI/SDA
100
R53
1
38
B
100
U6A
OCKS1/CCLK/SCL
2
OCKS0/CSN/CAD0
D3V
R57
DVDD
DVDD
10k
R59
R60
39
40
41
42
100
43
SDA/CDTO
100
D3V
IPS1/IIC
IPS1/IIC
PSEL
D3V/VD
XTL0
XTL1
RP2
1
2
3
4
5
6
7
8
9
36
74LS07
SDA
CDTO/CM0=H
CM0=L
SW3
16
15
14
13
12
11
10
9
1A
1B
2A
2B
3A
3B
4A
4B
JP18
10k
1
2
3
4
5
6
7
8
2
3
5
6
11
10
14
13
R58
D3V
CM1/FS1
OCKS1/FS2
OCKS0/FS0
PSEL
XTL0/CKS1
XTL1/TRANS
DIR_I/O
DIT_I/O
CM0/CDTO/CAD1
74LVC157
uP-I/F
A
35
R47
D3V
INT1
34
74HC14
INT0
LE2
33
44
45
46
47
A
48
DIR_I/O
DIT_I/O
47k
Title
Size
A3
Date:
5
4
3
2
AKD4118A-A
Document Number
Rev
MAIN2
Tuesday, August 04, 2009
0
Sheet
1
2
of
2
AKD4115-A L1
AKD4115-A L1_SILK
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