AK4371VN

[AKD4371-B]
AKD4371-B
AK4371 Evaluation Board Rev.1
GENERAL DESCRIPTION
The AKD4371 is an evaluation board for 24bit DAC with Headphone Amplifier, AK4371. The AKD4371
has the interface with AKM’s ADC evaluation boards. Therefore, it’s easy to evaluate the AK4371. The
ADK4370 also has the digital audio interface and can achieve the interface with digital audio systems via
opt-connector.
Ordering guide
AKD4371-B ---
Evaluation board for AK4371
(Cable for connecting with printer port of IBM-AT compatible PC and control software
are packed with this. This control software does not operate on Windows NT.)
FUNCTION
• Compatible with 2 types of interface
- Direct interface with AKM’s A/D converter evaluation boards
- On-board AK4116 as DIR which accepts optical input
• 10pin header for serial control interface
• Mini-jack for external Stereo Speaker
• On-board Class-D Speaker Amplifier (AK7832)
Vcc (5.0V)
GND
Regulator
(3.3V)
Opt In
(PORT1)
MOUT
HPL
AK4116
(DIR)
DSP
10pin Header
(PORT2)
HPR
AK4371
SPPL
AK7832
(SPK-Amp)
Control Data
10pin Header
(PORT3)
LIN1
RIN1
LIN2
RIN2
LIN3
RIN3
HP
SPPR
LOUT
ROUT
L/ROUT
Figure 1. AKD4371 Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM086201>
2007/07
-1-
[AKD4371-B]
Evaluation Board Manual
Operation sequence
1) Set up the power supply lines.
[VCC] (red) = 5.0V
: for Regulator
[AGND] (black) = 0V
: for analog ground
[DGND] (black) = 0V
: for logic ground
Each supply line should be distributed from the power supply unit.
3.3V is supplied to AK4371 via the regulator.
2) Set up the evaluation mode, jumper pins. (See the followings.)
3) Power on.
The AK4371 and AK4116 should be resets once bringing SW1(DAC/DIR_PDN) “L” upon power-up.
And the AK7832 should be resets once bringing SW2(SPK_PDN) “L” upon power-up.
Evaluation mode
When evaluating the AK4371 using the PORT1(AK4116), it is possible to use the initial setting of the audio
interface format (24bit MSB justified). The AK4116 operates at fs of 32kHz or more. If the fs is slower than
32kHz, any other evaluation mode should be used.
When inputting the data from the PORT2, the AK4371’s audio interface format should be set to correspond
the input data’s audio interface format. Refer to the AK4371’s datasheet.
Applicable Evaluation Mode
(1) PLL Master Mode
(2) PLL Slave Mode
(2-1) PLL Reference Clock : MCKI pin
(2-2) PLL Reference Clock : BICK or LRCK pin
(3) External Slave Mode
(3-1) Evaluation using DIR (Optical Link) of AK4116 <default>
(3-2) Evaluation connecting AKD4371 with external DSP
(4) External Master Mode
<KM086201>
2007/07
-2-
[AKD4371-B]
(1) PLL Master Mode
PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR). BICK and LRCK are supplied from
PORT2.It is possible to evaluate at various sampling frequencies using built-in the AK4371’s PLL.
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
AK4371
DSP or μP
MCKI
MCKO
BICK
256fs/128fs/64fs/32fs
32fs, 64fs
BCLK
1fs
LRCK
MCLK
LRCK
SDTO
SDATA
Figure 2. PLL Master Mode
The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of
DSP. The JP3(LRCK2) and JP4(BICK2)’s right side should be connected to LRCK and BICK of DSP.
In case of supplying MCKO to DSP, the test pin(MCKO) should be connected to MCLK of DSP.
Set up the jumper pins.
JP3
LRCK2
JP4
BICK2
JP5
MCLK
JP6
BICK
<KM086201>
JP7
LRCK
JP8
SDTO
2007/07
-3-
[AKD4371-B]
(2) PLL Slave Mode
(2-1) PLL Reference Clock : MCKI pin
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs ~ 64fs
MCLK
BCLK
1fs
LRCK
SDTO
SDATA
Figure 3. PLL Master Mode (PLL Reference Clock : MCKI pin)
PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR).
MCKO is needed for a synchronous signal of BICK and LRCK.
MCLK,BICK,LRCK and SDATA are supplied from PORT2. The test pin(MCKO) should be connected to
MCLK of DSP.
Set up the jumper pins.
JP3
LRCK2
JP4
BICK2
JP6
BICK
JP5
MCLK
<KM086201>
JP7
LRCK
JP8
SDTO
2007/07
-4-
[AKD4371-B]
(2-2) PLL Reference Clock : BICK or LRCK pin
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
32fs or 64fs
BCLK
1fs
LRCK
SDTO
SDATA
Figure 4. PLL Master Mode (PLL Reference Clock : BICK or LRCK pin)
PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR).
BICK,LRCK and SDATA are supplied from PORT2.
Set up the jumper pins.
JP3
LRCK2
JP4
BICK2
JP6
BICK
JP5
MCLK
<KM086201>
JP7
LRCK
JP8
SDTO
2007/07
-5-
[AKD4371-B]
(3) External Slave Mode
The AK4371’s register should be set to EXT Slave Mode. MCKI frequency should be set to the same as the
specification of DSP or DIR. About the AK4371’s register definitions, refer to datasheet of the AK4371.
AK4371
DSP or μP
MCKO
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
32fs ~ 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 5. External Slave Mode
(3-1) Evaluation using DIR (Optical Link) of AK4116 <default>
PORT1 (DIR) is used. Nothing should be connected to PORT2(DSP).
Set up the jumper pins.
JP3
LRCK2
JP4
BICK2
JP5
MCLK
JP6
BICK
JP7
LRCK
JP8
SDTO
(3-2) Evaluation connecting AKD4371 with external DSP
PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR).
Set up the jumper pins.
JP3
LRCK2
JP4
BICK2
JP5
MCLK
JP6
BICK
<KM086201>
JP7
LRCK
JP8
SDTO
2007/07
-6-
[AKD4371-B]
(4) External Master Mode
The AK4371’s register should be set to EXT Master Mode. MCKI frequency should be set to the same as DSP’s
specification. About the AK4371’s register definitions, refer to datasheet of the AK4371.
AK4371
DSP or μP
MCKO
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 6. EXT Master Mode
PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR).
The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of
DSP. The JP4(LRCK2) and JP3(BICK2)’s right side should be connected to LRCK and BICK of DSP.
Set up the jumper pins.
JP3
LRCK2
JP4
BICK2
JP6
BICK
JP5
MCLK
<KM086201>
JP7
LRCK
JP8
SDTO
2007/07
-7-
[AKD4371-B]
Other jumper pins set up
JP1 (GND) : Analog ground and Digital ground.
OPEN : Separated.
SHORT : Common. <default>
JP11 (INLN) : Setting of AK7832 Input pin “INLN”.
OPEN : When SW2 (SPK_PDN) is “L”.
SHORT : When SW2 (SPK_PDN) is “H”. <default>
JP12 (INRN) : Setting of AK7832 Input pin “INRN”.
OPEN : When SW2 (SPK_PDN) is “L”.
SHORT : When SW2 (SPK_PDN) is “H”. <default>
JP13 (DVDD_REG) : Setting of Power Supply “DVDD”.
OPEN : It supplies “DVDD” from the outside.
SHORT : It supplies “DVDD” from the Regulator (3.3V). <default>
The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (DAC/DIR_PDN): Power down of AK4371 and AK4116. Keep “H” during normal operation.
[SW2] (SPK_PDN): Power down of AK7832. Keep “H” during normal operation.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4116. LED turns on when some error has occurred to AK4116.
<KM086201>
2007/07
-8-
[AKD4371-B]
Serial Control
The AK4371 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(uP -IF) with PC by 10 wire flat cable packed with the AKD4371.
CSN
Connect
CCLK
CDTI
PC
AKD4371
10 Wire Flat Cable
10pin Connector
10pin Header
Figure 7. Connect of 10 wire flat cable
(1) 3-wire Serial Control Mode <Default>
The jumper pins should be set to the followings.
JP10
CAD0
JP9
SDA
JP2
I2C_SEL
I2C
3-wire
(2) I2C-bus Control Mode
The jumper pins should be set to the followings.
(2-1) In case of using CAD0=0 (device address bits).
JP10
CAD0
JP9
SDA
JP2
I2C_SEL
I2C
3-wire
(2-2) In case of using CAD0=1 (device address bits).
JP10
CAD0
JP9
SDA
JP2
I2C_SEL
I2C
<KM086201>
3-wire
2007/07
-9-
[AKD4371-B]
Input / Output circuit
(1) Input Circuit
LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 Input circuits
C19
1u
RIN1
6
LIN1
+
C21
1u
RIN2
6
+
C27
1u
4
3
LIN2
C29
1u
+
J5
LIN3/RIN3
+
C20
1u
4
3
J3
LIN2/RIN2
+
J2
LIN1/RIN1
RIN3
6
+
C31
1u
4
3
LIN3
Figure 8. LIN1/RIN1,LIN2/RIN2,LIN3/RIN3 Input circuits
(2)
Output Circuit
R9 (short)
+
1) HPL/HPR Output Circuit
C25
100u
HPR
R10(short)
+
6
J4
4
3
C28
100u
HPL
HP
Figure 9. HPL/HPR Output Circuit
+
2) MOUT Output Circuit
6
C18
1u
J1
4
3
MOUT
MOUT
Figure 10. MOUT Output Circuit
<KM086201>
2007/07
- 10 -
[AKD4371-B]
+
3) LOUT/ROUT Output Circuit
C30
1u
R11
220
ROUT
R12
47k
+
6
C32
1u
R13
220
J6
4
3
LOUT
L/R OUT
R14
47k
Figure 11. LOUT/ROUT Output Circuit
4) Speaker Output Circuit
Evaluation using AK7832’s Speaker , the jumper pins should be set to the followings.
JP11
INLN
JP12
INRN
TP2
VCLN
6
1
VCLN
4
3
1
TP3
VCLP
VCLP
SPP_L
TP4
VCRN
6
1
VCRN
J8
4
3
1
TP5
VCRP
VCRP
J7
SPP_R
Figure 12. SPK-Amp Output Circuit
∗ AKM assumes no responsibility for the trouble when using the above circuit examples.
<KM086201>
2007/07
- 11 -
[AKD4371-B]
Control Software Manual
Set-up of evaluation board and control software
1. Set up the AKD4371 according to previous term.
2. Connect IBM-AT compatible PC with AKD4371 by 10-line type flat cable (packed with AKD4371). Take care of
the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AK4371 Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “AKD4371.exe” to set up the control program.
5. Then please evaluate according to the follows.
Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
Explanation of each buttons
1.
2.
3.
4.
5.
6.
7.
8.
[Port Reset] :
[Write default] :
[All Write] :
[Function1] :
[Function2] :
[Function3] :
[Function4] :
[Function5] :
9. [SAVE] :
10. [OPEN] :
11. [Write] :
Set up the USB interface board (AKDUSBIF-A) when using the board.
Initialize the register of AK4371.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is
the part that is not defined in the datasheet.
<KM086201>
2007/07
- 12 -
[AKD4371-B]
Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes
“H” or “1”. If not, “L” or “0”.
If you want to write the input data to AK4371, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box:
Data Box:
Input registers address in 2 figures of hexadecimal.
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4371, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
There are dialogs corresponding to register of 05h , 06h , 09h , 0Eh and 13h.
Address Box:
Input registers address in 2 figures of hexadecimal.
Start Data Box:
Input starts data in 2 figures of hexadecimal.
End Data Box:
Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to AK4371 by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK4371, click [OK] button. If not, click [Cancel] button.
<KM086201>
2007/07
- 13 -
[AKD4371-B]
4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
“akr”.
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is “akr”.
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK4371. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
<KM086201>
2007/07
- 14 -
[AKD4371-B]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button. The default setting sequence DAC->HP(3D=OFF) is displayed. Jump to (3) below if the
default setting sequence is used. Go to (2) if the other setting sequence is required.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused
step.
This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of
file name is “aks”.
Figure 13. Window of [F3]
<KM086201>
2007/07
- 15 -
[AKD4371-B]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 9 opens.
Figure 14. [F4] window
<KM086201>
2007/07
- 16 -
[AKD4371-B]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 10. ( In case that the selected sequence file name is
“DAC_Stereo_ON.aks”)
Figure 15. [F4] window (2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name
is “*.ak4”.
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect
the change.
<KM086201>
2007/07
- 17 -
[AKD4371-B]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed. When [F5] button is clicked, the window as shown in Figure 11 opens.
Figure 16. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 12. (In case that the selected file name is
“DAC_Output.akr”)
(2) Click [WRITE] button, then the register setting is executed.
<KM086201>
2007/07
- 18 -
[AKD4371-B]
Figure 17. [F5] window (2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file
name is “*.ak5”.
[OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr)
should be loaded again in order to reflect the change.
<KM086201>
2007/07
- 19 -
[AKD4371-B]
MEASUREMENT RESULTS
[Measurement condition]
• Measurement unit
• MCLK
• BICK
• fs
• Bit
• Measurement Mode
• Power Supply
• Measurement Filter
• Temperature
: Audio Precession System Two Cascade
: 11.2896MHz
: 64fs
: 44.1kHz
: 24bit
: EXT Slave Mode
: AVDD = HVDD = DVDD = PVDD = 3.3V
:22Hz ∼ 20kHz
: Room
Parameter DAC Analog Output Characteristics
DAC -> HP AMP (RL=16Ω)
THD+N
(0dBFS Output)
D-Range
(-60dB Output, A-weighted)
S/N
(A-weighted)
DAC -> LOUT (RL=47kΩ)
THD+N
(0dBFS Output)
D-Range
(-60dB Output, A-weighted)
S/N
(A-weighted)
<KM086201>
Result (Lch / Rch)
Unit
54.1 / 54.1
92.7 / 92.7
93.0 / 93.0
dB
dB
dB
59.8 / 60.0
90.2 / 90.3
90.2 / 90.3
dB
dB
dB
2007/07
- 20 -
[AKD4371-B]
[Plot of Headphone Amp]
AKM
HP-AMP THD + N vs Input Level
fs=44.1kHz , fin=1kHz
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 18. THD+N vs. Input Level
AKM
HP-AMP THD + N vs Input Frequency
fs=44.1kHz , 0dB Input
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 19. THD+N vs. Input Frequency
<KM086201>
2007/07
- 21 -
[AKD4371-B]
AKM
HP-AMP Linearity
fs=44.1kHz , fin=1kHz
+0
-10
-20
-30
-40
d
B
r
A
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 20. Linearity
AKM
HP-AMP Frequency Response
fs=44.1kHz , 0dB Input
+2
-0
-2
-4
-6
-8
d
B
r
-10
-12
A
-14
-16
-18
-20
-22
-24
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 21. Frequency Response
(including external HPF)
<KM086201>
2007/07
- 22 -
[AKD4371-B]
AKM
HP-AMP FFT
fs=44.1kHz , 0dB Input
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
2k
5k
10k
20k
Hz
Figure 22. FFT Plot(1kHz,0dB)
AKM
HP-AMP FFT
fs=44.1kHz , -60dB Input
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
Hz
Figure 23. FFT Plot(1kHz,-60dB)
<KM086201>
2007/07
- 23 -
[AKD4371-B]
AKM
HP-AMP FFT
fs=44.1kHz , No Signal
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 24. FFT Plot(Noise Floor)
AKM
HP-AMP FFT
fs=44.1kHz , Outband Noise
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 25. Out-band Noise
<KM086201>
2007/07
- 24 -
[AKD4371-B]
AKM
HP-AMP Crosstalk
fs=44.1kHz , 0dB Input
+0
-10
-20
-30
-40
-50
d
B
-60
-70
-80
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 26. Crosstalk
<KM086201>
2007/07
- 25 -
[AKD4371-B]
REVISION HISTORY
Date
(yy/mm/dd)
Manual
Revision
Board
Revision
Reason
Page
06/12/12
KM086200
0
07/07/24
KM086201
1
First Edition
Change
Change
27
Contents
C12 4.7nF 47nF
Device revision was changed. Rev. A
Rev. B
IMPORTANT NOTICE
These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
<KM086201>
2007/07
- 26 -
D
E
RIN2
RIN3
LIN2
C
LIN3
RIN1
B
LIN1
A
DGND
JP1
GND
AGND
E
E
HPL
HPR
HPL
25
26
27
RIN2
28
LIN2
29
RIN3
30
31
1
SDATA
VSS1
24
2
BICK
HVDD
23
C1
0.1u
BICK
D
DVDD
22
VCOM
21
5
DVDD
VREF
20
6
PVDD
ROUT
19
7
VCOC
LOUT
18
AK4371VN
AVDD_REG
2.2u
C6
C7
0.22u
ROUT
C11
0.1u
LOUT
17
C
A1
A2
A3
B1
A5
NC
INRN
B4
INLN
INLP
C15
0.1u
NC
E5
VSS3
VCLP
E4
VCLP
B5
VC
VSS1
E3
VCLN
C1
DVDDI
VCRP
E2
1
B3
SCL
1u
C14
R7
51
TP1
MCKO
B2
C13
0.1u
U2
NC
MUTET
+
JP12
INRN
MOUT
16
I2C
PDN
15
9
R6
10k
MOUT
14
VSS2
13
8
CSN/CAD0
JP11
INLN
CCLK/SCL
C12
47n
C
MCKI
C9
0.1u
10u
C8
AVDD_REG
+10u
C10
4
D
C4
10u
C5
0.1u
MCKI
+
AVDD
12
10
LRCK
CDTI/SDA
R5
3
11
51
LRCK
MCKO
R4
HVDD_REG
C3
0.1u
10
51
VSS3
R3
C2
10u
INRP
51
+
R2
+
51
+
R1
SDATA
LIN3
LIN1
U1
RIN1
32
HPR
C16
PDN
VDD1
D5
D4
D3
D2
D1
C4
R8
47k
VCLN
C3
I2C_SEL
VSS2
E1
VCRN
NC
VDD2
SDA
I2CEN
SPK_PDN
B
C2
VDD3
PDN
CSN
CCLK
CDTI
B
JP2
AK7832
0.01u
C5
C17
0.1u
VCRP
VCRN
D_REG
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4371-B
Document Number
Rev
AK4371 , AK7832
Friday, August 10, 2007
Sheet
E
1
of
1
3
A
B
C
D
E
E
E
4
3
MOUT
MOUT
LIN1
DIR_REG
2
GND
JP13
C21
1u
J3
LIN2/RIN2
RIN2
6
DVDD
C27
1u
4
3
DVDD_REG
R9 (short)
C25
100u
HPR
J4
6
+
+ C26
47u
AVDD_REG
+
C24
0.1u
2
+
HVDD_REG
L4 (short)
1
LIN2
D
R10(short)
+
1
OUT
C23
0.1u
6
L3 (short)
T1
TA48M33F
+ C22
47u
2
C20
1u
4
3
J1
C18
1u
+
D_REG
L2 (short)
IN
RIN1
6
2
1
+
L1 10u
1
C19
1u
J2
LIN1/RIN1
+
VCC +5V
C28
100u
4
3
D
HPL
HP
+
C29
1u
J5
LIN3/RIN3
RIN3
+
C31
1u
4
3
+
6
C30
1u
R11
220
ROUT
LIN3
R12
47k
J6
+
6
C32
1u
R13
220
4
3
LOUT
L/R OUT
R14
47k
C
C
TP2
VCLN
J7
6
1
VCLN
TP3
VCLP
1
VCLP
4
3
SPP_L
TP4
VCRN
B
J8
6
1
VCRN
B
TP5
VCRP
1
VCRP
4
3
SPP_R
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4371-B
Document Number
Rev
Input/Output
Friday, August 10, 2007
Sheet
E
1
2
of
3
A
B
C
D
E
E
E
D_REG
D_REG
1
C33
0.1u
R15
1k
2
K
PORT1
ERF
PDN
TORX141
C35
0.1u
C36
10u
D
14
Vcc
7
8
9
10
11
12
13
SPK_PDN
GND
U3 74HC14
D1
HSU119
L
1
H
3
L
R19
12k
1
RX0
2
DVDD
3
DVSS
4
XTI
C39
0.1u
INT0
16
17
PDN
18
AVSS
R
D
R17
10k
H
C38 SW2
0.1u SPK_PDN
2
SW1
DAC/DIR_PDN
19
20
AVDD
U4
D2
HSU119
A
C37
0.1u
R18
470
R16
10k
A
+
DIR_REG
3
GND
OUT
C34
0.1u
4Y
4A
5Y
5A
6Y
6A
2
3
2
1
1A
1Y
2A
2Y
3A
3Y
K
VCC
1
2
3
4
5
6
K
LED1
A
1
L5
47u
INT1
15
R20
5.1
CSN
14
CSN
CCLK
13
CCLK
CDTI
12
CDTI
U5
CDTO
11
3
A1
B1
21
4
A2
B2
20
5
A3
B3
19
6
A4
B4
18
7
A5
B5
17
MCKI
8
A6
B6
16
CSN
CCLK
PDN
CDTO
SDATA
JP3
LRCK2
10
6
C
MCKO
XTO
LRCK
5
DAUX
X1
11.2896MHz
SDTO
C43
10p
AK4116
9
TP6
XTI
1 1
C42
10p
8
C41
0.1u
2
C
10u
C40
BICK
+
7
DIR_REG
LRCK
JP4
BICK2
BICK
JP5
MCLK
JP6
BICK
9
A7
B7
15
10
A8
B8
14
JP7
LRCK
B
B
JP8
SDTO
D_REG
C44
0.1u
1
VCCA
VCCB
24
2
DIR
VCCB
23
11
GND
OE
22
12
GND
GND
13
PORT2
MCLK
BICK
LRCK
SDTI
1
2
3
4
5
10
9
8
7
6
GND
GND
D_REG
R21
10k
R22
470
R23
10k
R24
470
R25
10k
R26
470
DVDD
C45
0.1u
DSP
74AVC8T245
D_REG
R27
10k
PORT3
1
2
3
4
5
A
10
9
8
7
6
uP-I/F
CSN
SCL/CCLK
SDA/CDTI
CDTO
CDTI
CDTO
JP9
SDA
A
JP10
CAD0
Title
Size
A2
Date:
A
B
C
D
AKD4371-B
Document Number
Rev
CLOCK
Friday, August 10, 2007
E
Sheet
1
3
of
3
Similar pages