[AKD4373-B] AKD4373-B AK4373 Evaluation Board Rev.2 GENERAL DESCRIPTION The AKD4373 is an evaluation board for 24bit DAC with Headphone Amplifier and a monaural speaker driver. The ADK4373 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4373-B --- Evaluation board for AK4373 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not operate on Windows NT.) FUNCTION • Compatible with 2 types of interface - Audio serial I/F input (port2) - On-board AK4116 as DIR which accepts optical input(Port1) • 10pin header for serial control interface • Mini-jack for external Stereo HP and a monaural speaker Vcc (5.0V) GND Regulator (3.3V) Opt In (PORT1) AK4116 (DIR) DSP 10pin Header (PORT2) AK4373 MIN+/LOUT L/ROUT ROUT Control Data 10pin Header (PORT3) SPK /HPR HP /HPL Figure 1. AKD4373 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM091603> 2008/12 -1- [AKD4373-B] Board Outline Chart Outline Chart GND +5V AKD4373-B Rev.2 Evaluation Board AKM U2 PORT1 MIN+/- TORX141 AK4116 SW1 X1 10 U3 74AVC8T245 U5 5 6 U4 1 74HC14 J3 L/R OUT J4 AK4373 HP J1 6 5 J2 PORT3 10 1 SPK/HPR PORT2 Figure 2. AKD4373-B Outline Chart Comment (1) J1, J2, J3, J4 (MINI-JACK) J1 (SPK/HPR-JACK): An analog signal output Jack. The signal is output to SPK or HPR pin. J2 (HP-JACK): An analog signal output Jack. The signal is output to HP or HPL pin. J3 (MIN-JACK): An analog signal input Jack. The signal is input to MIN+/- pin. J4 (L/ROUT-JACK): An analog signal output Jack. The signal is output to L/ROUT pin. (2) +5V, GND +5V-JACK: The power supply connector. GND-JACK: The ground connector. (3) PORT1 (Optical Connecter) PORT1 (Input): Optical digital signal (SPDIF, Fs: 32~48kHz) is input to the AK4116. (4) PORT2, PORT3 (10 pin header) PORT2 (10 pin header): The clock and data can be input and output with this connector. PORT3 (10 pin header): Control port. Connect the bundled cable into this port. <KM091603> 2008/12 -2- [AKD4373-B] Operation sequence 1) Set up the power supply lines. Name +5V GND Color Red Black Voltage +5V 0V Comments Input to regulator For ground Attention This jack is always needed. Power line This jack is always needed. Table 1. Set up power supply lines * Setting of Power Supply “DVDD”: JP10 (DVDD-REG) Open: It supplies “DVDD” from the outside to right pin. Short: It supplies “DVDD” from the Regulator (3.3V) <default>. Each supply line should be distributed from the power supply unit. 3.3V is supplied to AK4373 via the regulator. 2) Set up the evaluation mode, jumper pins. (See the followings.) 3) Power on. The AK4373 and AK4116 should be resets once bringing SW1 (DAC/DIR-PDN) “L” upon power-up. Evaluation mode When evaluating the AK4373 using the PORT1 (AK4116), it is possible to use the initial setting of the audio interface format (24bit MSB justified). The AK4116 operates at fs of 32kHz or more. If the fs is slower than 32kHz, any other evaluation mode should be used. When inputting the data from the PORT2, the AK4373’s audio interface format should be set to correspond the input data’s audio interface format. Refer to the AK4373’s datasheet. Applicable Evaluation Mode (1) PLL Master Mode (2) PLL Slave Mode (2-1) PLL Reference Clock: MCKI pin (2-2) PLL Reference Clock: BICK or LRCK pin (3) External Slave Mode (3-1) Evaluation using DIR (Optical Link) of AK4116 <default> (3-2) Evaluation connecting AKD4373 with external DSP (4) External Master Mode <KM091603> 2008/12 -3- [AKD4373-B] (1) PLL Master Mode PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR). BICK and LRCK are supplied from PORT2. It is possible to evaluate at various sampling frequencies using built-in the AK4373’s PLL. 11.2896MHz,12MHz,12.288MHz 13.5MHz,24MHz,25MHz,27MHz AK4373 DSP or μP MCKI MCKO 256fs/128fs/64fs/32fs 32fs, 64fs BICK BCLK 1fs LRCK MCLK LRCK SDTO SDATA Figure 3. PLL Master Mode The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of DSP. The JP16 (LRCK2) and JP17 (BICK2)’s right side should be connected to LRCK and BICK of DSP. In case of supplying MCKO to DSP, the test pin (MCKO) should be connected to MCLK of DSP. Set up the jumper pins. JP16 LRCK2 JP17 BICK2 JP12 JP11 MCLK BICK <KM091603> JP13 LRCK JP14 SDTO 2008/12 -4- [AKD4373-B] (2) PLL Slave Mode (2-1) PLL Reference Clock: MCKI pin 11.2896MHz,12MHz,12.288MHz 13.5MHz,24MHz,25MHz,27MHz AK4373 DSP or μP MCKI MCKO BICK 256fs/128fs/64fs/32fs ≥32fs BCLK 1fs LRCK MCLK LRCK SDTO SDATA Figure 4. PLL Slave Mode (PLL Reference Clock: MCKI pin) PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR). MCKO is needed for a synchronous signal of BICK and LRCK. MCLK, BICK, LRCK and SDATA are supplied from PORT2. The test pin (MCKO) should be connected to MCLK of DSP. Set up the jumper pins. JP16 LRCK2 JP17 BICK2 JP12 JP11 BICK MCLK <KM091603> JP13 LRCK JP14 SDTO 2008/12 -5- [AKD4373-B] (2-2) PLL Reference Clock: BICK or LRCK pin AK4373 DSP or μP MCKI MCKO BICK 32fs or 64fs BCLK 1fs LRCK LRCK SDTO SDATA Figure 5. PLL Master Mode (PLL Reference Clock : BICK or LRCK pin) PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR). BICK, LRCK and SDATA are supplied from PORT2. Set up the jumper pins. JP16 LRCK2 JP17 BICK2 JP12 JP11 BICK MCLK <KM091603> JP13 LRCK JP14 SDTO 2008/12 -6- [AKD4373-B] (3) External Slave Mode The AK4373’s register should be set to EXT Slave Mode. MCKI frequency should be set to the same as the specification of DSP or DIR. About the AK4373’s register definitions, refer to datasheet of the AK4373. AK4373 DSP or μP MCKO 256fs, 512fs or 1024fs MCKI MCLK ≥32fs BICK 1fs LRCK BCLK LRCK SDTO SDATA Figure 6. External Slave Mode (3-1) Evaluation using DIR (Optical Link) of AK4116 <default> PORT1 (DIR) is used. Nothing should be connected to PORT2 (DSP). Set up the jumper pins. JP16 LRCK2 JP17 BICK2 JP11 MCLK JP12 BICK JP13 LRCK JP14 SDTO (3-2) Evaluation connecting AKD4373 with external DSP PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR). Set up the jumper pins. JP16 LRCK2 JP17 BICK2 JP11 MCLK JP12 BICK <KM091603> JP13 LRCK JP14 SDTO 2008/12 -7- [AKD4373-B] (4) External Master Mode The AK4373’s register should be set to EXT Master Mode. MCKI frequency should be set to the same as DSP’s specification. About the AK4373’s register definitions, refer to datasheet of the AK4373. AK4373 DSP or μP MCKO 256fs, 512fs or 1024fs MCKI MCLK 32fs or 64fs BICK 1fs LRCK BCLK LRCK SDTO SDATA Figure 7. EXT Master Mode PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR). The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of DSP. The JP16 (LRCK2) and JP17 (BICK2)’s right side should be connected to LRCK and BICK of DSP. Set up the jumper pins. JP16 LRCK2 JP17 BICK2 JP12 JP11 BICK MCLK <KM091603> JP13 LRCK JP14 SDTO 2008/12 -8- [AKD4373-B] The function of the toggle SW Upper-side is “H” and lower-side is “L”. [SW1] (DAC/DIR_PDN): Power down of AK4373 and AK4116. Keep “H” during normal operation. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4116. LED turns on when some error has occurred to AK4116. <KM091603> 2008/12 -9- [AKD4373-B] Serial Control The AK4373 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (uP -IF) with PC by 10 wire flat cable packed with the AKD4373. 1 10 CSN Connect CCLK PC CDTI 10 Wire Flat Cable 5 AKD4373 6 PORT3 10pin Connector 10pin Header Figure 8. Connect of 10 wire flat cable (1) 3-wire Serial Control Mode <Default> The jumper pins should be set to the followings. JP15 CAD0 JP18 SDA JP1 I2C_SEL 3-wire I2C (2) I2C-bus Control Mode The jumper pins should be set to the followings. (2-1) In case of using CAD0=0 (device address bit). JP15 CAD0 JP18 SDA JP1 I2C_SEL 3-wire I2C (2-2) In case of using CAD0=1 (device address bit). JP15 CAD0 JP18 SDA JP1 I2C_SEL 3-wire <KM091603> I2C 2008/12 - 10 - [AKD4373-B] Input / Output circuit (1) Input Circuit R10 C13 1u 6 + MIN+ + MIN+/- Circuits 4 3 20k MIN- R11 J3 C14 1u MIN+/- 20k Figure 9. MIN+/- Input Circuits (2) Output Circuit 1) LOUT/ROUT Output Circuit LOUT C15 + 1u R14 220 R12 47k 4 ROUT C16 + 1u R15 220 R13 47k J4 6 3 L/R OUT Figure 10. LOUT/ROUT Output Circuits <KM091603> 2008/12 - 11 - [AKD4373-B] 2) HP Output Circuits a. Single-ended mode <default> JP5 HPL Cap-less + R9 HPL C12 47u HPR + R8 C11 J2 4 0 6 3 47u HP 0 HVCM HVCM JP4 HP-SEL GND JP3 HPR Cap-less Figure 11. HP Output Circuit (Single-ended mode) Set up the jumper pins. JP3 HPR Cap-less JP5 HPL Cap-less JP4 HP-SEL HVCM GND b. Differential mode JP5 HPL Cap-less TP7 HPL+ 1 HPL+ + R9 C12 1 TP8 HPL- + R8 HPL- 47u C11 J2 4 0 6 3 47u HPL 0 HVCM TP9 JP4 HP-SEL GND JP3 HPR Cap-less 1HPR+ HPR+ 1 SPN JP2 HP/SPK-SEL TP10 HPR- J1 4 HP HPR- 6 3 HPR Figure 12. HP Output Circuit (Differential mode) Set up the jumper pins. JP3 HPR Cap-less JP5 HPL Cap-less JP4 HP-SEL HVCM <KM091603> GND JP2 HP/SPK-SEL HP SPN 2008/12 - 12 - [AKD4373-B] c. Pseudo cap-less mode JP5 HPL Cap-less + R9 HPL+ C12 47u HPL- + R8 C11 J2 4 0 6 3 47u HP JP3 HPR Cap-less HP HVCM HVCM GND 0 JP4 HP-SEL SPN JP2 HP/SPK-SEL Figure 13. HP Output Circuit (Pseudo cap-less mode) Set up the jumper pins. JP3 HPR Cap-less JP5 HPL Cap-less JP4 HP-SEL HVCM <KM091603> GND JP2 HP/SPK-SEL HP SPN 2008/12 - 13 - [AKD4373-B] 3) Speaker Output Circuit <default> SPP HP SPN SPN JP2 HP/SPK-SEL 4 J1 6 3 SPK Figure 14. Speaker Output Circuit Set up the jumper pins. JP2 HP/SPK-SEL HP SPN ∗ AKEMD assumes no responsibility for the trouble when using the above circuit examples. <KM091603> 2008/12 - 14 - [AKD4373-B] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4373 according to previous term. 2. Connect IBM-AT compatible PC with AKD4373 by 10-line type flat cable (packed with AKD4373). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK4373 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “AKD4373.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button. Explanation of each buttons 1. 2. 3. 4. 5. 6. 7. 8. [Port Reset]: [Write default]: [All Write]: [Function1]: [Function2]: [Function3]: [Function4]: [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK4373. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM091603> 2008/12 - 15 - [AKD4373-B] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4373 click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog]: Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4373 click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog]: Dialog to evaluate Digital Volume. There are dialogs corresponding to register of 09h, 0Ah, 0Ch and 0Dh. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4373 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4373 click [OK] button. If not, click [Cancel] button. <KM091603> 2008/12 - 16 - [AKD4373-B] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is “akr”. <Operation flow> (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is “akr”. 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4373. The file type is the same as [SAVE]. <Operation flow> (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button. <KM091603> 2008/12 - 17 - [AKD4373-B] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. The default setting sequence DAC->HP (3D=OFF) is displayed. Jump to (3) below if the default setting sequence is used. Go to (2) if the other setting sequence is required. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval = “-1”. Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is “aks”. Figure 15. Window of [F3] <KM091603> 2008/12 - 18 - [AKD4373-B] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 16 opens. Figure 16. [F4] window <KM091603> 2008/12 - 19 - [AKD4373-B] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 17. (In case that the selected sequence file name is “DAC_Stereo_ON.aks”) Figure 17. [F4] window (2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE]: The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is “*.ak4”. [OPEN]: The name assign of sequence file (*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. <KM091603> 2008/12 - 20 - [AKD4373-B] 7. [Function5 Dialog] The register setting file (*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 18 opens. Figure 18. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 19. (In case that the selected file name is “DAC_Output.akr”) (2) Click [WRITE] button, then the register setting is executed. <KM091603> 2008/12 - 21 - [AKD4373-B] Figure 19. [F5] window (2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE]: The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is “*.ak5”. [OPEN]: The name assign of register setting file (*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. <KM091603> 2008/12 - 22 - [AKD4373-B] 8. [Filter Dialog] This dialog can easily set the AK4373’s programmable filter. A calculation of a coefficient of Digital Programmable Filter such as HPF, EQ filter ,a write to a register and check frequency response. Window to show to Figure 20 opens when push a [Filter] button. Figure 20. [Filter] window <KM091603> 2008/12 - 23 - [AKD4373-B] 8-1. Setting of a parameter (1) Please set a parameter of each Filter. Item Sampling Rate FIL3 Cut Off Frequency Contents Sampling frequency (fs) Setting range 7350Hz ≤ fs ≤ 48000Hz Stereo separation emphasis filter cut off frequency Type of stereo separation emphasis filter Gain of stereo separation emphasis filter fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs) LPF or HPF –10dB ≤ Gain ≤ 0dB High pass filter cut off frequency fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs) LPF Cut Off Frequency Low pass filter cut off frequency fs/20 ≤ Cut Off Frequency ≤ (0.497 * fs) EQ for Gain Compensation (EQ) Pole Frequency Pole Frequency Zero-point Frequency Zero-point Frequency Gain 5 Band Equalizer EQ1-5 Center Frequency Gain fs/10000 ≤ Pole Frequency ≤ (0.497 * fs) fs/10000 ≤ Zero-point Frequency ≤ (0.497 * fs) 0dB ≤ Gain ≤ +12dB Filter type Gain HPF Cut Off Frequency EQ1-5 Center Frequency EQ1-5 Band Width EQ1-5 Band Width ( Note 1) EQ1-5 Gain EQ1-5 Gain ( Note 2) Note 1. Bandwidth where the gain gap is 3dB compared with center frequency. Note 2. When a gain is smaller than “0”, EQ1-5 becomes a notch filter. 0Hz ≤ Center Frequency < (0.497 * fs) 1Hz ≤ Band Width < (0.497 * fs) -1≤ Gain < 3 (2) Please set ON/OFF of Filter with check buttons of “FIL3”, “EQ”, “LPF”, “HPF”, “EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5”. When the button is checked, Filter becomes ON. When “Notch Filter Auto Correction” is checked, automatic compensation is executed for center frequency of notch filter. (“Cf. 8-4. automatic compensation for center frequency of a notch filter”) Figure 21. Filter ON/OFF setting button <KM091603> 2008/12 - 24 - [AKD4373-B] 8-2. A calculation of a register A register setting values are displayed when [Register Setting] button is clicked. When any value is set to out or range, error message is displayed, and a calculation of register setting is not executed. Figure 22. A register setting calculation result In the following cases, a register set values are updated. (1) When [Register Setting] button was pushed. (2) When [Frequency Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button “Notch Filter Auto Correction”. <KM091603> 2008/12 - 25 - [AKD4373-B] 8-3.Indication of a frequency characteristic A frequency characteristic is displayed when [Frequency Response] button is clicked. The register values are updated at the same time. If “Frequency Range” is changed, and [UpDate] button is clicked, indication of a frequency characteristic is updated. Figure 23. A frequency characteristic indication result In the following cases, a register set values are updated. (1) When [Register Setting] button was pushed. (2) When [Frequency Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button “Notch Filter Auto Correction”. 8-4. Automatic compensation for center frequency of a notch filter When a gain of 5 band Equalizer is set to “-1”, Equalizer becomes a notch filter. When center frequency of several notch filters are near frequency each other, center frequency error occurs (Figure 24). When “Notch Filter Auto Correction” button is checked, automatic compensation is executed for center frequency of a notch filter. Register setting and frequency characteristics are displayed after automatic compensation (Figure 25). This automatic compensation is available for Equalizer Band where a gain is set to “-1”. (Note) When distance among center frequencies is smaller than band width, there is a possibility that automatic compensation does not operate normally. Please confirm a compensation result by indication of a frequency characteristic. <KM091603> 2008/12 - 26 - [AKD4373-B] Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width: 200Hz (3 band common) Figure 24. When there is no compensation of center frequency Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width: 200Hz (3 band common) Figure 25. When there is compensation of center frequency <KM091603> 2008/12 - 27 - [AKD4373-B] REVISION HISTORY Date (yy/mm/dd) Manual Revision Board Revision Reason 08/01/18 KM091600 0 First Edition 08/06/20 KM091601 08/06/25 08/07/01 KM091602 08/12/09 KM091603 1 2 Page Parts Change 1 Error Correction 11 Error Correction 2 Parts Change 1 Error Correction 5 Error Correction 10 Contents Board Revision: Rev.0 → Rev.1 AK4373: Rev. A → Rev. B Figure 9 was changed. R10, R11: 0Ω → 20kΩ PORT2 and PORT3 were exchanged. Board Revision: Rev.1 → Rev.2 Figure 26. PLL Master Mode (PLL Reference Clock: MCKI pin) →Figure 27. PLL Slave Mode Change in 3-wire Serial Control Mode,I2C-bus Control Mode IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM091603> 2008/12 - 28 - A B C D E AVDD-REG R2 47k E JP1 I2C-SEL E PDN CSN C1 10u C9 2.2u + R1 10k + C3 4.7n C2 C8 0.1u 0.1u R4 SDTI R5 LRCK 51 51 1 2 3 VSS1 NC 4 AVDD VCOC 5 6 7 9 CCLK/SCL NC 32 10 CDTI/SDA NC 31 11 SDTI NC 30 12 NC MIN- 29 13 LRCK MIN+ 28 R10 J3 + ACK D C13 1u 6 + 100 VCOM R3 CDTI I2C D PDN CSN/CAD0 U5 8 CCLK 4 3 20k AK4373 R11 C14 1u MIN+/- ROUT MUTET C15 1u + 27 C16 1u 26 TP1 MCKO 220 J4 6 3 25 L/R OUT R13 47k C10 1u TP10 HPR- B C6 10u 1 1 B TP9 HPR+ 1 51 C7 0.1u 1 R7 R15 C + MCKI 220 4 + 1 R14 R12 47k 24 HPR/HPL23 VSS2 HVDD 22 18 17 21 VSS3 MCKI 16 HPL/HPL+ DVDD C5 0.1u 19 C4 + 10u LOUT SPP/HPR+/TEST 15 DVDD BICK 20 14 SPN/HPR-/HVCM 51 MCKO R6 BICK C + 20k TP8 HPL- TP7 HPL+ R8 0 HVDD-REG HP SPN JP2 HP/SPK-SEL JP3 C11 HPR Cap-less 47u R9 0 + +C12 47u JP5 HPL Cap-less A 4 GND JP4 HP-SEL 3 6 3 6 A 4 HVCM Title Size J1 SPK/HPR A B J2 HP C A3 Date: D AKD4373-B Document Number Rev AK4373 Tuesday, December 09, 2008 Sheet E 2 1 of 3 A B T21 TA48033F T45-RED GND IN + C17 47u C18 0.1u D E L20 1 OUT 2 D-REG D-REG 10u C19 0.1u E + C20 47u U3 0 R29 1 A HVDD-REG K R17 1k LED1 ERF T45-BLACK R30 0 AVDD-REG C29 0.1u R28 10 1A 1Y 2A 2Y 3A 3Y 14 Vcc 7 GND 4Y 4A 5Y 5A 6Y 6A 8 9 10 11 12 13 74HC14 DVDD D1 HSU119 R16 10k A JP10 DVDD-REG 1 2 3 4 5 6 K E 1 GND +5V C 1 H 3 L SW1 DAC/DIR_PDN C30 0.1u 2 D-REG D C28 0.1u L23 10u 2 C21 0.1u 1 D + C27 10u PORT1 16 INT0 17 PDN AVSS AVDD U2 R TORX141 18 R19 12k C22 0.1u 20 3 2 1 19 VCC GND OUT 1 RX0 INT1 15 2 DVDD CSN 14 3 DVSS CCLK 13 1 1 4 XTI CDTI 12 2 R18 470 5 XTO CDTO 11 R20 5.1 AK4116 U4 C MCKO 3 A1 B1 21 4 A2 B2 20 PDN SDTI JP16 LRCK2 5 A3 B3 19 6 A4 B4 18 7 A5 B5 17 MCKI 8 A6 B6 16 CSN 9 A7 B7 15 CCLK B8 14 10 DAUX 9 6 SDTO X1 11.2896MHz LRCK C26 10p TP6 XTI 8 C C24 0.1u BICK C25 10p C23 10u 7 + LRCK JP17 BICK2 JP11 MCLK JP12 BICK JP13 JP14 BICK LRCK SDTO 10 A8 B B D-REG PORT3 DSP 1 2 3 4 5 10 9 8 7 6 uP-I/F CSN SCL/CCLK SDA/CDTI CDTO 10k VCCA VCCB 24 2 DIR VCCB 23 11 GND OE 22 12 GND GND 13 DVDD C32 0.1u R25 GND GND 10k 10 9 8 7 6 R23 R27 10k 1 2 3 4 5 R21 MCLK BICK LRCK SDTI C31 0.1u 10k PORT2 1 R22 R24 R26 470 470 470 74AVC8T245 3-wire CDTI I2C JP15 CAD0 JP18 SDA ACK A Title Size A2 Date: A B C D A AKD4373-B Document Number Rev CLOCK Tuesday, December 09, 2008 E Sheet 2 3 of 3 - 31 - - 32 - - 33 - - 34 -