AK4440EF

[AKD4440-A]
AKD4440-A
AK4440 Evaluation Board Rev.3
GENERAL DESCRIPTION
The AKD4440-A is an evaluation board for the AK4440, 24bit DAC with 2Vrms line output for cost and
performance based audio systems. The AKD4440-A has the interface with AKM’s A/D converter
evaluation boards and the interface with digital audio systems via optical connector. Therefore, it is easy
to evaluate the AK4440.
„ Ordering guide
AKD4440-A ---
AK4440 Evaluation Board
FUNCTION
• Compatible with 2 types of input data interface
- Direct interface with AKM’s A/D converter evaluation boards via 10-pin header
- On-board AK4118 as DIR, which accepts optical or BNC Inputs
• Optical output for internal DIT
• BNC connector for an external clock input
• BNC connector for DAC output
DGND
VCC
VDD AVSS1
Digital In
Analog Out
LOUT1
AK4118
(DIR)
74LVC541
AK4440
BNC
ROUT1
LOUT2
ROUT2
10 pin
Header
LOUT3
DSP data
ROUT3
LOUT4
ROUT4
AVDD AVSS2
Figure 1. AKD4440-A Block Diagram
.
<KM097205>
2009/8
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[AKD4440-A]
„ Operation sequence
1) Set up the power supply lines.
[VDD]
(Red)
= 4.5 ∼ 5.5V (typ. 5.0V, for AK4440)
[VCC]
(Red)
= 2.7 ∼ 3.6V (typ. 3.3V, for AK4118, for 74LVC541 and for logic)
[AVDD] (Red)
= 4.5 ∼ 5.5V (typ. 5.0V, AK4440)
[AVSS1] (Black)
= 0V
[AVSS2] (Black)
= 0V
[DGND] (Black)
= 0V
Each supply line should be distributed from the power supply unit.
2) Set-up the evaluation modes, jumper pins and DIP switches (See the followings.)
3) Power on.
When AK4118 is used, The AK4118 should be reset once by bringing SW2 “L” upon power-up.
„ Evaluation mode
1) D/A part evaluation using optical or S/PDIF input <Default>
Use PORT1 (RX3: OPT) or J2 (RX3: BNC).
The AK4118 (DIR) generates MCLK, BICK, LRCK and SDTI from the received data through Optical connector
(TORX141) or BNC connector. This evaluation mode should be used for the evaluation using CD test disk.
Nothing should be connected to PORT3 (DSP). The selection of OPT and BNC should be done by JP8 (RX1)
JP4
MCLK
DIR
JP5
BICK
DIR
EXT
JP6
SDTI1
JP7
JP8
LRCK
RX1
DIR
EXT
OPT
EXT
BNC
2) D/A part evaluation using 10-pin connector on the AKM’s A/D evaluation board
Use PORT3 (DSP).
It is able to evaluate the AK4440, connecting the 10-pin connector on the AKM’s A/D evaluation board and
PORT3 (DSP) via 10-line flat cable. MCLK, BICK, LRCK and SDTI are sent from the A/D converter evaluation
board to the AKD4440 through PORT3 (DSP) via 10-line flat cable.
JP4
MCLK
DIR
EXT
JP5
BICK
DIR
JP6
SDTI1
JP7
LRCK
DIR
EXT
EXT
3) D/A part evaluation using PORT3 (DSP), and supplying all interface signals from external equipments
In case of using PORT3 (DSP), and supplying signals (MCLK, BICK, LRCK, SDTI) that is needed for
the AK4440 from external equipments, set up as following.
JP4
MCLK
DIR
EXT
JP5
BICK
DIR
JP6
SDTI1
EXT
<KM097205>
JP7
LRCK
DIR
EXT
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„ Other Jumper pins set up
(1) JP1 (SDTI1): Select the input of SDTI2 pin
OPEN:
Separated
SHORT: <Default>
(2) JP2 (SDTI1): Select the input of SDTI3 pin
OPEN:
Separated
SHORT: <Default>
(3) JP3 (SDTI1): Select the input of SDTI4 pin
OPEN:
Separated
SHORT: <Default>
(4) JP14 (VDD): VDD and VCC
OPEN:
Separated <Default>
SHORT: Prohibition
(5) JP15 (VDD): VDD and AVDD
OPEN:
Separated <Default>
SHORT: Prohibition
(6) JP16 (GND): Analog ground and Digital ground
OPEN:
Separated <Default>
SHORT: Prohibition
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[AKD4440-A]
„ DIP Switch set up
[S1]: AK4118 Setting
No.
Pin
1
2
3
4
DIF1
DIF0
OCKS1
OCKS0
L
H
Default
L
L
H
L
Setting of AK4118 Audio Interface Format
(Refer Table 2.)
Selection of AK4118 Master Clock Output frequency
(Refer Table 3.)
Table 1. Set up modes of AK4118
Mode
4
5
OCKS1
L
H
H
DIF1
DIF0
SDTO
L
L
24bit, Left justified
L
H
24bit, I2S
Table 2. Audio Data Format of AK4118
OCKS0
MCKO1
L
256fs
L
512fs
H
128fs
Table 3. MCLK Frequency of AK4118
[SW2]: AK4440 Setting
No Pin
OFF (L)
.
Soft Mute Pin in parallel mode
1
SMUTE
2
ACKS
3
DIF0
4
TDM0B
5
DEM0
6
DEM1/I2
S
P/S
7
(Default)
fs (max)
96kHz
48kHz
192kHz
(Default)
ON (H)
Default
Soft Mute Pin in parallel mode
: “Disable”
: “Enable”
Normal Speed Mode
Auto setting mode
(Parallel control mode)
(Parallel control mode)
24-bit MSB
24-bit I2S
(Parallel control mode)
(Parallel control mode)
TDM256 mode
Normal mode
(Parallel control mode)
(Parallel control mode)
De-emphasis Filter Enable Pin in parallel mode. This pin is valid
in parallel mode. (Refer Table 5.)
De-emphasis Filter Enable Pin in parallel mode. This pin is valid
in parallel mode. (Refer Table 5.)
Serial control mode
Parallel control mode
OFF
OFF
OFF
ON
ON
OFF
OFF
Table 4. SW2 set-up
DEM1
pin
DEM0
pin
Mode
0
0
44.1kHz
0
1
OFF
1
0
48kHz
(Default)
1
1
32kHz
Table 5. De-emphasis Filter Control (Normal Speed Mode)
„ Toggle switch
[SW2] AK4118-PDN:
Switch for power down reset of AK4118.Keep “H” during operation of AK4118.
Power down reset of AK4118 will be done by setting SW2 to “L” once, after power on.
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„ Register control
AKD4440 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(uP-I/F) to PC by 10-line flat cable packed with this. Take care of the direction of connector. There is a mark at
connector. Connect the mark of 10-pin connector to pin1 of PORT3. (Figure 2.)
PORT3
uP-I/F
10 wire
flat Cable
10
CSN
CCLK/SCL
AKD4440-A
CDTI/SDA
CDTO/SDA(ACK)
Connect
PC
Red
10pin Connector
9
2 ▲
10pin Header
Figure 2. PORT3 pin layout
„ Analog Output Circuit
The DAC of AK4440 outputs analog audio signals through J3 and J4.
R15
560
C18
R16
(short)
1
+
AK4440-ROUT1
J3
BNC-R-PC
(short)
R17
(open)
C19
3.3n
R18
560
C20
R19
(short)
1
(short)
R20
(open)
ROUT1
J4
BNC-R-PC
+
AK4440-LOUT1
2
3
4
5
2
3
4
5
LOUT1
C21
3.3n
Figure 3. LOUT/ROUT Output circuit
* AKM assumes no responsibility for the trouble when using the above circuit examples.
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[AKD4440-A]
Control Soft Manual
■ Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10wire flat cable. Be aware of the direction of
the 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD
must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing the
driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This control soft
does not support the Windows NT.
3. Proceed evaluation by following the process below.
■ Operation Screen
1. Start up the control program following the process above.
The operation screen is shown below.
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[AKD4440-A]
■ Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting.
1. [Port Reset]: For when connecting to USB I/F board (AKDUSBIF-A)
Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-A).
2. [Write Default]: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executing write commands for all registers displayed.
4. [Save]: Saving current register settings to a file.
5. [Load]: Executing data write from a saved file.
6. [All Req Write]: “All Req Write” dialog box is popped up.
7. [Data R/W]: “Data R/W” dialog box is popped up.
8. [Read]: Reading current register settings and display on to the Register area (on the right of the main window).
This is different from [All Read] button, it does not reflect to a register map, only displaying
hexadecimal.
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[AKD4440-A]
■ Tab Functions
1. [REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Grayout registers are Read Only registers. They can not be controlled.
The registers which is not defined in the datasheet are indicated as “---”.
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[AKD4440-A]
[Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
[Read]: Data Read
Click [Read] button located on the right of the each corresponded address to execute register reading.
After register reading, the display will be updated regarding to the register status.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Please be aware that button statuses will be changed by Read command.
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[AKD4440-A]
■ Dialog Boxes
1. [All Req Write]: All Req Write dialog box
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
[Open (left)]: Selecting a register setting file (*.akr).
[Write]: Executing register writing.
[Write All]: Executing all register writings.
Writings are executed in descending order.
[Help]: Help window is popped up.
[Save]: Saving the register setting file assignment. The file name is “*.mar”.
[Open (right)]: Opening a saved register setting file assignment “*. mar”.
[Close]: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register
settings.
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[AKD4440-A]
2. [Data R/W]: Data R/W Dialog Box
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Address Box: Input data address in hexadecimal numbers for data writing.
Data Box: Input data in hexadecimal numbers.
Mask Box: Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write]: Writing to the address specified by “Address” box.
[Read]: Reading from the address specified by “Address” box.
The result will be shown in the Read Data Box in hexadecimal numbers.
[Close]: Closing the dialog box and finish the process.
Data writing can be cancelled by this button instead of [Write] button.
*The register map will be updated after executing [Write] or [Read] commands.
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[AKD4440-A]
Measurement Results
[Measurement condition]
• Measurement unit
• MCLK
• BICK
• Fs
• Bit
• Power Supply
• Interface
• Temperature
: Audio Precision System two Cascade (AP2)
: 512fs ,256fs,128fs
: 64fs
: 44.1kHz,96kHz,192kHz
: 24bit
: VDD=AVDD=5V
: DIR
: Room
Table Data(DAC1 ON)
MCLK=512fs,fs=44.1kHz
Parameter
Input signal
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
MCLK=256fs,fs=96kHz
Parameter
Input signal
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
MCLK=128fs,fs=192kHz
Parameter
Input signal
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
Lch
Filter condition
20kHz LPF
20kHz SPCL,
A-weighted
20kHz SPCL,
A-weighted
Filter condition
20kHz LPF
40kHz SPCL
A-weighted
40kHz SPCL
A-weighted
Filter condition
20kLPF
40kHz SPCL
A-weighted
40kHz SPCL
A-weighted
<KM097205>
93.7
105.5
Rch
93.2
105.3
105.5
105.5
Lch
92.8
105.2
Rch
92.1
105.1
105.5
105.5
Lch
92.3
103.3
Rch
92.1
103.3
105.3
105.3
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[AKD4440-A]
Plot Data
fs=44.1kHz
FFT 0dB
fs=44.1kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
2k
5k
10k
20k
Hz
Figure 4. FFT (0dB)
FFT -60dB
fs=44.1kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
Hz
Figure 5. FFT (-60dB)
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[AKD4440-A]
FFT No Input
fs=44.1kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 6. FFT (No Signal)
FFT Out of Band Noise
fs=44.1kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 7. FFT (Out of Band Noise)
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[AKD4440-A]
THD+N vs Input Level
fs=44.1kHz,fin=1kHz
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 8. THD + N vs Input Level
THD+N vs Input Frequency
fs=44.1kHz,0dB
-60
TT
T
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 9. THD + N vs Input Frequency
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[AKD4440-A]
Frequency Response
fs=44.1kHz,0dB
+1
+0.8
+0.6
+0.4
d
B
r
A
+0.2
+0
-0.2
-0.4
-0.6
-0.8
-1
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
5k
10k
20k
Hz
Figure 10. Frequency Response
Crosstalk
fs=44.1kHz,0dB
-60
-65
-70
-75
-80
-85
d
B
-90
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
Hz
Figure 11. Crosstalk
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[AKD4440-A]
Linearity
fs=44.1kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 12. Linearity
fs=96kHz
FFT 0dB
fs=96kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 13.FFT(0dB)
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[AKD4440-A]
FFT -60dB
fs=96kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
Figure 14. FFT (-60dB)
FFT No Signal
fs=96kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
Hz
Figure 15.FFT(No Signal)
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[AKD4440-A]
THD+N vs Input Level
fs=96kHz,fin=1kHz
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 16.THD+N vs Input Level
THD+N vs Input Frequency
fs=96kHz,0dB
-60
TT
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 17. THD+N vs Input Frequency
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[AKD4440-A]
Crosstalk
fs=96kHz,0dB
-60
-65
-70
-75
-80
-85
d
B
-90
-95
-100
-105
-110
-115
-120
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 18. Crosstalk
Frequency Response
fs=96kHz,0dB
+1
+0.8
+0.6
+0.4
d
B
r
A
+0.2
+0
-0.2
-0.4
-0.6
-0.8
-1
5k
10k
15k
20k
25k
30k
35k
40k
Hz
Figure 19. Frequency Response
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[AKD4440-A]
Linearity
fs=96kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 20. Linearity
fs=192kHz
FFT 0dB
fs=192kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 21.FFT(0dB)
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[AKD4440-A]
FFT -60dB
fs=192kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
5k
10k
20k
50k
80k
Hz
Figure 22.FFT(-60dB)
FFT No Signal
fs=192kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
Hz
Figure 23.FFT(No Signal)
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[AKD4440-A]
THD+N vs Input Level
fs=192kHz,fin=1kHz
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 24.THD+N vs Input Level
THD+N vs Input Frequency
fs=192kHz,0dB
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 25. THD+N vs Input Frequency
<KM097205>
2009/8
- 23 -
[AKD4440-A]
Frequency Response
fs=192kHz,0dB
+1
+0.5
-0
-0.5
-1
d
B
r
-1.5
A
-2.5
-2
-3
-3.5
-4
-4.5
-5
10k
20k
30k
40k
50k
60k
70k
80k
Hz
Figure 26. Frequency Response
Crosstalk
fs=192kHz,0dB
-60
-65
-70
-75
-80
-85
d
B
-90
-95
-100
-105
-110
-115
-120
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 27. Crosstalk
<KM097205>
2009/8
- 24 -
[AKD4440-A]
Linearity
fs=192kHz,fin=1kHz
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 28. Linearity
<KM097205>
2009/8
- 25 -
[AKD4440-A]
Revision History
Date
(yy/mm/dd)
08/11/13
08/12/01
Manual
Revision
KM097200
KM097201
Board
Revision
0
0
Reason
Page
First Edition
Correction
5
Contents
AK4118 Setting Change:
Table 3. Audio Data Format of AK4118=> Table 2. Audio
Data Format of AK4118, (24bit, I2S=>24bit, Left justified)
08/12/03
09/01/13
09/04/07
KM097201
KM097202
KM097203
0
1
2
Correction
Correction
Correction
16
6
5
1
12~17
09/05/08
KM097204
3
Correction
6,8
09/08/26
KM097205
3
Modification
22
12~25
Selection of AK4114 Master Clock Output frequency
(Refer Table 4.) => Selection of AK4118 Master Clock
Output frequency (Refer Table 3.)
Addition of circuit chart around AK4440
Change in Control Soft Manual
Change in Analog output
Board Revision: Rev.1 → Rev.2
Device Revision Change: Rev.AÆRev.B
The addition of Table Data and plot data
Change in Control Soft Manual
Circuit Change:PORT3
Update of measurement results and Plots.
(fs=44.1kHz,fs=96kHz,fs=192kHz)
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices
Corporation (AKM) or authorized distributors as to current status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any
information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official approval under
the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard
related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express
written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether
directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore
meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for
applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably
be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product
with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said
product in the absence of such notification.
<KM097205>
2009/8
- 26 -
A
B
C
D
E
E
E
CN2
CN1
1
MCLK
VDD
30
2
BICK
VSS2
29
3
SDTI1
CP
28
4
LRCK
CN
27
5
TEST
VEE
26
LOUT1
25
ACKS/CCLK/SCL
ROUT1
24
DIF0/CDTI/SDA
LOUT2
23
SDTI2
ROUT2
22
SDTI3
LOUT3
21
7
ACKS/CCLK/SCL
8
9
AK4440-SDTI1
JP2
JP3
(2x1)
(2x1)
9
11
SDTI4
ROUT3
20
12
TDM0B
LOUT4
19
ROUT4
18
VSS1
17
AVDD
16
TP11
SDTI3
13
DEM0
14
I2C/DEM1
10
TP13
SDTI4
15
P/S
11
TP7
ROUT1
TP8
LOUT2
C5
0.1uF
TP12
LOUT3
C6
10uF
AK4440-I2C/DEM1
14
AK4440-P/S
B
15
LOUT4
LOUT4
TP16
ROUT4
DEM0
1
13
TDM0B
ROUT4
I2C
AK4440-LOUT1
24
AK4440-ROUT1
23
AK4440-LOUT2
22
AK4440-ROUT2
21
AK4440-LOUT3
20
AK4440-ROUT3
19
AK4440-LOUT4
18
AK4440-ROUT4
C
17
TP17
AVDD
P/S
1
AK4440-DEM0
ROUT3
25
TP15
1
12
ROUT2
LOUT3
TP14
ROUT3
AK4440
AK4440-TDM0B
ROUT1
LOUT2
TP10
ROUT2
1
AK4440-SDTI1
(2x1)
10
TP9
SDTI2
1
C
JP1
DIF0/CDTI/SDA
1
AK4440-SDTI1
8
1
AK4440-DIF0/CDTI/SDA
LOUT1
1
AK4440-ACKS/CCLK/SCL
SMUTE/CSN/CAD0
1
7
1
6
26
TP6
LOUT1
1
SMUTE/CNS/CAD0
D
2
6
27
+ C4
1uF
2
+ C3
1uF
2
5
+ C2
10uF
C1
0.1uF
1
D
AK4440-SMUTE/CNS/CAD0
28
1
1
1
LRCK
4
TP4
LRCK
1
AK4440-LRCK
U1
1 2
SDTI1
3
VDD
30
29
TP3
SDTI1
1
AK4440-SDTI1
1
BICK
2
VDD
TP5
BICK
1
AK4440-BICK
1
MCLK
1
TP2
VDD
+
AK4440-MCLK
TP1
MCLK
AVDD
AVDD
16
B
30pin_4
30pin_2
A
A
- 27 -
Title
Size
A3
Date:
A
B
C
D
AKD4440
AK4440
Friday, May 08, 2009
Document Number
Sheet
E
Rev
7
1
of
5
A
B
C
D
PORT1
A1-10PA-2.54DSA
1
10
MCLK
2
9
BICK
3
8
LRCK
4
7
SDTI1
5
6
SDTI2
VCC
VCC1
R2
(open)
R3
(open)
+
4118-VCC
+
R1
E
51
4118-VCC
DSP
E
E
C7
10u
11
LRCK
24
23
MCKO1
VSS2
DVDD
U3
22
21
20
VOUT/GP7
18
19
UOUT/GP6
BOUT/GP4
VIN/GP0
COUT/GP5
17
16
TX1/GP3
15
TX0/GP2
NC/GP1
TVDD
12
VCC
C10
0.1u
14
13
C9
0.1u
C8
10u
10
26
BICK
XTL0
EXT
EXT-MCLK
27
MCKO2
8
P/SN
EXT
EXT-BICK
U2
GND
10
2
A1
Y1
18
JP6(2x1)
SDTI1
29
XTO
DIF2/RX7
G2
JP5(3x1)
BICK
EXT
EXT-LRCK
JP7 (3x1)
LRCK
DIR
7
19
DIF1
5
VSS1
Y2
17
4
A3
Y3
16
5
A4
Y4
15
6
A5
Y5
14
7
A6
Y6
13
8
A7
Y7
12
9
A8
Y8
11
51
R5
51
AK4440-MCLK
D
AK4440-BICK
R6
51
R7
51
AK4440-SDTI1
AK4440-LRCK
31
PDN
DIF1/RX6
A2
R4
30
XTI
AK4118
6
3
28
DAUX
IPS1/IIC
20
JP4(3x1)
MCLK
DIR
9
VCC
C11
0.1u
DIR
D
G1
25
SDTO
XTL1
1
32
CM0/CDTO/CAD1
C
C
4
DIF0
TEST2
33
CM1/CDTI/SDA
3
DIF0/RX5
OCKS1/CCLK/SCL
34
OCKS1
2
NC
OCKS0/CSN/CAD0
35
OCKS0
74LVC541A
U4E
VCC
11
10
74HC14
36
A
INT1
AK4118-RX3
1
2
3
4
A
H
8
7
6
5
SW DIP-4
L
B
C13
0.1u
L1
47u
PORT2
TORX141
VCC
3
GND
OUT
2
1
C16
0.1u
R12
470
OPT
DIF0
DIF1
OCKS0
OCKS1
DIF0
DIF1
OCKS0
OCKS1
J1
RX3(BNC) BNC-R-PC
RP1
4
3
2
1
2
3
4
5
C17
1
R13
75
BNC
JP8 (3x1)
AK4118-RX3
RX1
A
Title
-0.1u
28 -
Size
A3
Date:
47k
A
74HC14
74HC14
VCC
C14
10u
RX3(OPT)
VCC
8
12
2
C15
10u
4118-VCC
S1
74HC14
H
3
C12
0.1u
U4D
9
VCC
U4F
1
L
6
13
1
+
R11
(open)
R10
10k
U4C
5
SW1
ATE1D-2M3
AK4118-PDN
+
R9
(open)
R8
10k
2
37
AVDD
38
R
39
VCOM
40
VSS3
41
RX0
42
NC
43
44
RX1
TEST1
45
RX2
46
VSS4
47
RX3
48
TEST1
AK4118-INT0
TEST2
AK4118-INT1
B
D1
HSU119
14
INT0
7
IPS0/RX4
K
1
B
C
D
AKD4440
DIR&CLOCK
Document Number
Friday, May 08, 2009
Sheet
E
2
Rev
7
of
5
A
B
C
D
E
EXT-MCLK
VCC
CLK
R14
51
DIV
Q
6
2
4
6
16
CLK
VCC
PR
3
x1 1
x2 3
x3 5
10
CLK
11
RST
CLK
8
Q
7
10
2
9
1
14
13
12
11
15
U7
74HC4040
14
1
3
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
9
7
6
5
3
2
4
13
12
14
15
1
x1
x2
x4
x8
1
2
3
4
5
6
7
8
EXT-BICK
BCFS
JP13
(3x2)
x3 1
x1 3
x2 5
D
2
4
6
EXT-LRCK
LRFS
2
U9A
74HC14
4
U9B
74HC14
C
5
8
ENP
ENT
CLK
LOAD
CLR
QA
QB
QC
QD
RCO
7
16
VCC
A
B
C
D
GND
3
4
5
6
VCC
GND
JP12
(2x1)
VCC
U8
74AC163
C
2
4
6
5
JP10
(4x2)
8
D
EXT
x1 1
x2 3
x3 5
Q
VCC
11
1
9
Q
D
GND
CL
D
GND
CL
2
3
4
5
12
2
VCC
JP9
(3x2)
7
1
J2
BNC-R-PC
JP11
(3x2)
U5A
74AC74
7
13
EXT
U5B
74AC74
14
10
VCC
14
4
E
VCC
PR
E
6
U9C
74HC14
9
8
U9D
74HC14
11
10
U9E
74HC14
B
B
13
12
U9F
74HC14
OPEN
A
A
Title
AKD4440
- 29 Size
A4
Date:
A
B
C
D
Document Number
Rev
External Master Clock Divider
Friday, May 08, 2009
Sheet
E
3
of
7
5
A
B
E
SW2
1
2
3
4
5
6
7
8
D
R15
560
C18
16
15
14
13
12
11
10
9
VCC
1
AK4440-ROUT1
(short)
R17
(open)
1
2
3
4
5
6
7
8
9
AK4440-SMUTE
AK4440-ACKS
AK4440-DIF0
AK4440-TDM0B
AK4440-DEM0
AK4440-I2C/DEM1
AK4440-P/S
E
J4
BNC-R-PC
R19
(short)
1
+
AK4440-LOUT1
(short)
R20
(open)
1
+
R26
10k
R30
10k
R24
470
AK4440-SMUTE
R27
470
AK4440-ACKS
R31
470
AK4440-DIF0
PORT3
CSN
CCLK/SCI
CDTI/SDA
AK4440-P/S
(short)
U10
2
3
5
6
11
10
14
13
1A
1B
2A
2B
3A
3B
4A
4B
1
15
A/B
G
1Y
4
R28
100 CSN
2Y
7
R29
3Y
9
R32
100 CCLK AK4440-ACKS/CCLK/SCL
100 CDTI AK4440-DIF0/CDTI/SDA
4Y
12
R25
(open)
AK4440-SMUTE/CNS/CAD0
R33
560
C24
1
(short)
uP-I/F
D
ROUT2
J6
BNC-R-PC
R34
(short)
AK4440-LOUT2
74HCT157
2
3
4
5
C23
3.3n
+
10k
LOUT1
J5
BNC-R-PC
R22
(short)
AK4440-ROUT2
R23
2
3
4
5
C21
3.3n
R21
560
C22
D
9
7
5
3
1
ROUT1
C19
3.3n
R18
560
C20
10k
10
8
6
4
2
2
3
4
5
MODE2
RP2
VCC
E
J3
BNC-R-PC
R16
(short)
+
SMUTE
ACKS
DIF0
TDM0B
DEM0
DEM1/I2C
P/S
C
R35
(open)
2
3
4
5
LOUT2
C25
3.3n
C
C
R36
560
C26
J7
BNC-R-PC
R37
(short)
1
+
AK4440-ROUT3
(short)
R38
(open)
J8
BNC-R-PC
R40
(short)
1
+
AK4440-LOUT3
(short)
R41
(open)
B
J9
BNC-R-PC
R43
(short)
1
+
(short)
R44
(open)
R45
560
ROUT4
J10
BNC-R-PC
R46
(short)
1
+
(short)
R47
(open)
2
3
4
5
C31
3..3n
AK4440-LOUT4
A
LOUT3
B
AK4440-ROUT4
C32
2
3
4
5
C29
3.3n
R42
560
C30
ROUT3
C27
3.3n
R39
560
C28
2
3
4
5
2
3
4
5
LOUT4
C33
3.3n
A
- 30 -
Title
Size
A3
Date:
A
B
C
D
AKD4440
Document Number
Analog Output
Friday, May 08, 2009
Rev
7
Sheet
E
4
of
5
1
VDD
T_45(RED)
1
AVDD
T_45(RED)
AVDD
VDDi
VCCi
E
AVSS1
AVSS2
DGND
T_45(BLACK) T_45(BLACK)T_45(BLACK)
AVSS1
AVSS2
DGND
1
VCCi
1
VDDi
1
AVDD
VCC
T_45(RED)
E
1
E
D
1
C
1
B
1
A
D
D
L3
(short)
JP14
(2x1)
2
2
L2
(short)
2
L4
(short)
For 74HC14 x 1, 74HCT04 x 1, 74AC74 x 1, 74HC4040 x 1,
74AC163 x 1, 74HC14 x 1
R48
VCC
C43
47u +
C34
47u +
AVSS2
AVSS1
VDD
+
C35
47u
(short)
C36
0.1u
C37
0.1u
C38
0.1u
C39
0.1u
C40
0.1u
C41
0.1u
C42
0.1u
C
C
VCC1
R49
VDD
(short)
JP15
(2x1)
R50
JP16
AGND (2x1) DGND
GND
AVDD
(short)
B
B
AVDD1
A
A
Title
- 31 Size
A4
Date:
A
B
C
D
Document Number
AKD4440
Power Supply
Friday, May 08, 2009
Sheet
E
5
Rev
7
of
5
- 32 -
- 33 -
- 34 -
- 35 -
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