AK4497EQ

[AK4497]
= Preliminary =
AK4497
Quality Oriented 32-Bit 2ch DAC
1. General Description
The AK4497 is a new generation Premium 32-bit 2ch DAC with VELVET SOUNDTM technology,
achieving industry’s leading level low distortion characteristics and wide dynamic range. The AK4497
integrates a newly developed switched capacitor filter “OSR Doubler”, making it capable of supporting
wide range signals and achieving low out-of-band noise while realizing low power consumption.
Moreover, the AK4497 has six types of 32-bit digital filters, realizing simple and flexible sound tuning in
wide range of applications. The AK4497 accepts up to 768kHz PCM data and 22.4MHz DSD data, ideal
for a high-resolution audio source playback that are becoming widespread in network audios,
USB-DACs and Car Audio Systems.
Application: AV Receivers, CD/SACD player, Network Audios, USB DACs, USB Headphones, Sound
Plates/Bars, Measurement Equipment, Control Systems, Public Audios (PA), IC-Recorders,
Bluetooth Headphones, HD Audio/Voice Conference Systems
2. Features
 THD+N: -115dB
 DR, S/N: 127dB (Mono Mode, 130dB)
 256 Times Over Sampling
 Sampling Rate: 8kHz  768kHz
 32-bit 8x Digital Filter
- Short Delay Sharp Roll-off, GD=6.0/fs,
Ripple: 0.005dB, Attenuation: 100dB
- Short Delay Slow Roll-off, GD=5.0/fs
- Sharp Roll-off
- Slow Roll-off
- Low-dispersion Short Delay Filter
- Super Slow Roll-off
 2.8MHz, 5.6MHz, 11.2MHz, 22.4MHz DSD Input Support
- Filter1 (fc=39kHz, 2.8MHz mode), Filter2 (fc=76kHz, 2.8MHz mode)
 Digital De-emphasis for 32, 44.1, 48kHz sampling
 Soft Mute
 Digital Attenuator (255 levels and 0.5dB step)
 Mono Mode
 External Digital Filter Interface
 Audio I/F Format: 24/32 bit MSB justified, 16/20/24/32 bit LSB justified, I2S, DSD
 Master Clock
8kHz ~ 32kHz: 1152fs
8kHz ~ 54kHz: 512fs or 768fs
8kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
~ 384kHz: 64fs or 128fs
~ 768kHz: 64fs
 Power Supply:
TVDD=AVDD= 3.3  3.6V (by Internal LDO),
TVDD=AVDD= 1.7  3.6V, DVDD=1.7  1.98V (by external supply),
VDDL/R= 4.75  5.25V
 Digital Input Level: CMOS
 Package: 64-pin TQFP
Rev. 0.1
2015/11
-1-
[AK4497]
3. Table of Contents
General Description ........................................................................................................................ 1
Features .......................................................................................................................................... 1
Table of Contents............................................................................................................................ 2
Block Diagram ................................................................................................................................. 4
Pin Configurations and Functions ................................................................................................... 5
■ Pin Configurations .............................................................................................................................. 5
■ Pin Functions ..................................................................................................................................... 6
■ Handling of Unused Pin ..................................................................................................................... 8
6.
Absolute Maximum Ratings ............................................................................................................ 9
7.
Recommended Operating Conditions ............................................................................................ 9
8.
Electrical Characteristics .............................................................................................................. 10
■ Analog Characteristics ..................................................................................................................... 10
■ DSD mode ........................................................................................................................................ 11
■ Sharp Roll-Off Filter Characteristics (fs = 44.1kHz) ........................................................................ 12
■ Short Delay Sharp Roll-Off Filter Characteristics (fs = 44.1kHz) .................................................... 14
■ Slow Roll-Off Filter Characteristics (fs = 44.1kHz) .......................................................................... 16
■ Short Delay Slow Roll-Off Filter Characteristics (fs = 44.1kHz) ...................................................... 18
■ Low-dispersion Short Delay Filter Characteristics (fs = 44.1kHz) ................................................... 20
■ DSD Filter Characteristics ................................................................................................................ 21
■ DC Characteristics ........................................................................................................................... 22
■ Switching Characteristics ................................................................................................................. 23
■ Timing Diagram ................................................................................................................................ 28
9.
Functional Descriptions................................................................................................................. 33
■ D/A Conversion Mode ...................................................................................................................... 35
■ D/A Conversion Mode Switching Timing ......................................................................................... 35
■ System Clock ................................................................................................................................... 37
■ Power ON/OFF Sequence in FS Auto Detect Mode (LDOE pin = “H”) ........................................... 42
■ Audio Interface Format .................................................................................................................... 45
■ Digital Filter ...................................................................................................................................... 57
■ De-emphasis Filter (PCM) ............................................................................................................... 58
■ Output Volume (PCM, DSD, EXDF) ................................................................................................ 58
■ Gain Adjustment Function (PCM, DSD, EXDF)............................................................................... 59
■ Zero Detection (PCM, DSD, EXDF)................................................................................................. 60
■ L/R Channel Output Signal Select, Phase Inversion Function (PCM, DSD, EXDF) ....................... 61
■ Sound Quality (PCM, DSD, EXDF).................................................................................................. 62
■ DSD Signal Full Scale (FS) Detection ............................................................................................. 63
■ Soft Mute Operation (PCM, DSD, EXDF) ........................................................................................ 64
■ LDO .................................................................................................................................................. 65
■ Shutdown Switch.............................................................................................................................. 65
■ Over Current Protection for Analog Output Pins ............................................................................. 65
■ Power Up/Down Function ................................................................................................................ 66
■ Synchronize Function (PCM, EXDF) ............................................................................................... 73
■ Register Control Interface ................................................................................................................ 75
■ Register Map .................................................................................................................................... 79
■ Register Definitions .......................................................................................................................... 81
10.
Recommended External Circuits .................................................................................................. 91
11.
Package ........................................................................................................................................ 95
■Outline Dimensions ........................................................................................................................... 95
■ Material & Lead Finish ..................................................................................................................... 96
■ Marking............................................................................................................................................. 96
12.
Ordering Guide ............................................................................................................................. 97
1.
2.
3.
4.
5.
Rev. 0.1
2015/11
-2-
[AK4497]
■ Ordering Guide................................................................................................................................. 97
IMPORTANT NOTICE............................................................................................................................. 98
Rev. 0.1
2015/11
-3-
[AK4497]
4. Block Diagram
TVDD DVDD DVSS
LDOE
PDN
BICK/BCK/DCLK
SDATA/DINL/DSDL
LRCK/DINR/DSDR
TDMO
AVDD
AVSS
LDO
VSSL
VDDL
PCM
Data
Interface
De-emphasis
&
Interpolator
External
DF
Interface
SCF
AOUTLP

Modulator
DATT
Soft Mute
Vref
Normal path
DSDD bit “0”
DSD
Data
Interface
VCML
VREFHL
VREFLL
VREFLR
VREFHR
VCMR
SSLOW/WCK
TDM0/DCLK
DEM0/DSDL
GAIN/DSDR
AOUTLN
DSD
Filter
SCF
AOUTRP
AOUTRN
Volume bypass
DSDD bit “1”
VDDR
VSSR
MCLK停止検出
SMUTE/CSN
SD/ CCLK/SCL
SLOW/CDTI/SDA
Control
Register
Clock
Divider
Oscillator
IREF
PSN DIF0/ DIF1/ DIF2/ TDM1 DCHAIN INVR ACKS/ TESTE HLOAD
/I2C
CAD1
DZFL DZFR CAD0
MCLK
EXTR
Block Diagram
Rev. 0.1
2015/11
-4-
[AK4497]
5. Pin Configurations and Functions
■ Pin Configurations
Rev. 0.1
2015/11
-5-
[AK4497]
■ Pin Functions
No. Pin Name
1 LDOE
2
PDN
I
3
BICK
BCK
DCLK
I
I
I
Function
Internal LDO Enable Pin. “L”: Disable, “H”: Enable
Power-Down Mode Pin
When at “L”, the AK4497 is in power-down mode and is held in reset. The
AK4497 must always be reset upon power-up.
Audio Serial Data Clock Pin in PCM Mode
Audio Serial Data Clock Pin
DSD Clock Pin in DSD Mode (DSDPATH bit = “1”)
SDATA
I
Audio Serial Data Input Pin in PCM Mode
DINL
DSDL
LRCK
DINR
DSDR
SSLOW
WCK
TDMO
I
I
I
I
I
I
I
O
SMUTE
I
CSN
SD
CCLK
SCL
SLOW
CDTI
SDA
DIF0
DZFL
DIF1
DZFR
DIF2
CAD0
I
I
I
I
I
I
I/O
I
O
I
O
I
I
Lch Audio Serial Data Input Pin
DSD Lch Data Input Pin in DSD Mode(DSDPATH bit = “1”)
L/R Clock Pin in PCM Mode
Rch Audio Serial Data Input Pin
DSD Rch Data Input Pin in DSD Mode(DSDPATH bit = “1”)
Digital Filter Select Pin in Parallel Control Mode
Word Clock input pin
Audio Serial Data Onput in Daisy Chain mode (Internal pull-down pin)
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
Chip Select Pin in Serial Control Mode
Digital Filter Select Pin in Parallel Control Mode
Control Data Clock Pin in Serial Control Mode
I2C=”H”: Control Data Clock Input Pin
Digital Filter Select Pin in Parallel Control Mode
Control Data Input Pin in Serial Control Mode
I2C=”H”: Control Data Input Pin
Digital Input Format 0 Pin in Parallel Control Mode
Lch Zero Input Detect Pin in Serial Control Mode (Internal pull-down pin)
Digital Input Format 1 Pin in Parallel Control Mode
Rch Zero Input Detect Pin in Serial Control Mode (Internal pull-down pin)
Digital Input Format 2 Pin in Parallel Control Mode
Chip Address 0 Pin in Serial Control Mode
Parallel or Serial Select Pin
(Internal pull-up pin)
“L”: Serial Control Mode, “H”: Parallel Control Mode
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
I/O
I
PSN
I
HLOAD
I
I2C
Heavy Load Mode Enable Pin in Parallel Control Mode.
Resister Control Interface Pin in Serial Control Mode.
DEM0
I
De-emphasis Enable 0 Pin in Parallel Control Mode
DSDL
I
DSD Lch Data Input Pin in DSD Mode (DSDPATH bit =”0”)
GAIN
I
Output Gain Control Pin in Parallel control mode (+2.5dB)
DSDR
I
ACKS
I
CAD1
I
DSD Rch Input Pin in DSD Mode (DSDPATH bit =”0”)
Auto Setting Mode Select Pin in Parallel control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
Chip Address 1 Pin in Serial Control Mode
Rev. 0.1
2015/11
-6-
[AK4497]
No.
20
21
22
23
Pin Name
TDM0
DCLK
TDM1
DCHAIN
INVR
TESTE
I/O
I
I
I
I
I
I
24-26
VREFHR
I
Rch High Level Voltage Reference Input Pin
27-29
VREFLR
I
VCMR
I
AOUTRN
AOUTRP
VDDR
VSSR
VSSL
VDDL
AOUTLP
AOUTLN
O
O
O
O
VCML
-
VREFLL
VREFHL
I
I
58
EXTR
I
59
AVDD
Rch Low Level Voltage Reference Input Pin
Right channel Common Voltage Pin,
Normally connected to VREFLR with a 10uF electrolytic cap.
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
Rch Analog Power Supply Pin
Analog Ground Pin
Analog Ground Pin
Lch Analog Power Supply Pin .
Lch Positive Analog Output Pin
Lch Negative Analog Output Pin
Left channel Common Voltage Pin
Normally connected to VREFLL with a 10uF electrolytic cap.
Lch Low Level Voltage Reference Input Pin
Lch High Level Voltage Reference Input Pin
External Resistor Connect Pin
Rext=33kΩ(±1%) toAVSS
(LDOE pin = “H”)
Analog Power Supply Pin, 3.0  3.6V
(LDOE pin = “L”)
Analog Power Supply Pin, 1.7  3.6V
Analog Ground Pin
Master Clock Input Pin
(LDOE pin = “H”)
LDO Output Pin,
This pin should be connected to DVSS with 1.0µF.
(LDOE pin = “L”)
Digital Power Supply Pin, 1.7  1.98V
19
30
31,32
33,34
35-37
38-40
41-43
44-46
47,48
49,50
51
52-54
55-57
60
61
AVSS
MCLK
62
DVDD
I
O
-
63
DVSS
-
Function
TDM Mode select pin in Parallel control mode.
DSD clock Pin in DSD Mode (DSDPATH bit = “0”)
TDM Mode select pin in Parallel control mode.
Daisy Chain Mode select pin in Parallel control mode.
Rch output data invert enable pin in Parallel control mode.
Testmode Enable pin. (Internal pull-down pin)
Digital Ground Pin
(LDOE pin = “H”)
Digital Power Supply Pin, 3.0  3.6V
TVDD
64
(LDOE pin = “L”)
Digital Power Supply Pin, 1.7  3.6V
Note 1. All input pins except internal pull-up/down pins must not be left floating.
Note 2. The AK4497 must be reset by PDN pin after changing Parallel/Serial mode by the PSN pin.
Note 3. PCM mode, DSD mode and EXDF mode are controlled by register settings.
-
Rev. 0.1
2015/11
-7-
[AK4497]
■ Handling of Unused Pin
Unused I/O pins must be connected appropriately.
(1) Parallel Mode (PCM mode only)
Classification Pin Name
AOUTLP, AOUTLN
Analog
AOUTRP, AOUTRN
Digital
I2C, TESTE
Setting
Open
Open
Connect to DVSS
(2) Serial Mode
1. PCM Mode
Classification
Analog
Digital
Pin Name
AOUTLP, AOUTLN
AOUTRP, AOUTRN
TESTE
Setting
Open
Open
Connect to DVSS
2. DSD Mode
Classification Pin Name
AOUTLP, AOUTLN
Analog
AOUTRP, AOUTRN
BICK, SDATA, LRCK, WCK, TDM1,
Digital
DCHAIN, INVR, TESTE
Pull-up and Pull-down pins List
Classification
pull-up pin (typ=100kΩ)
pull-down pin (typ=100kΩ)
Setting
Open
Open
Connect to DVSS
Pin Name
PSN
TDMO, DZFL, DZFR, TESTE
Rev. 0.1
Setting
Connect to TVDD
Connect to DVSS
2015/11
-8-
[AK4497]
6. Absolute Maximum Ratings
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 4)
Parameter
Symbol
Min.
Max.
0.3
4.0
Digital I/O
TVDD
0.3
2.5
Digital Core
DVDD
Power
Analog
AVDD
0.3
4.0
Supplies:
Analog
VDDL/R
0.3
6.0
|AVSS  DVSS| (Note 5)
GND
0.3
Input Current, Any Pin Except Supplies
IIN
10
Digital Input Voltage
VIND
0.3
TVDD+0.3
Ambient Temperature (Power applied)
Ta
40
85
Storage Temperature
Tstg
65
150
Note 4. All voltages with respect to ground.
Note 5. AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane.
Unit
V
V
V
V
V
mA
V
C
C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 4)
Parameter
Symbol
Min.
Typ.
Max.
■ LDOE pin= “L”
Digital I/O
TVDD
DVDD
1.8
3.6
Analog
AVDD
DVDD
1.8
3.6
Digital Core
DVDD
1.7
1.8
1.98
Power Supplies
Analog
VDDL/R
4.75
5.0
5.25
■ LDOE pin= “H”
Digital I/O
TVDD
3.0
3.3
3.6
Analog
AVDD
3.0
3.3
3.6
Analog
VDDL/R
4.75
5.0
5.25
Voltage Reference “H” voltage reference
VREFHL/R VDDL/R-0.5
VDDL/R
(Note 7)
“L” voltage reference
VREFLL/R
VSSL/R
Note 4. All voltages with respect to ground.
Note 6. The power-up sequence between AVDD, VDDL/R and DVDD is not critical.
Note 7. The analog output voltage scales with the voltage of (VREFH  VREFL).
AOUT (typ.@0dB) = (AOUT+)  (AOUT) = 2.8Vpp  (VREFHL/R  VREFLL/R)/5.
* TVDD must be powered up befor or at the same time of DVDD when the LDOE pin = “L”.
Unit
V
V
V
V
V
V
V
V
V
* The internal LDO outputs DVDD (1.8V) when the LDOE pin = “H”. The power-up sequence between
VDDL/R and TVDD or VDDL/R and AVDD is not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
Rev. 0.1
2015/11
-9-
[AK4497]
8. Electrical Characteristics
■ Analog Characteristics
(Ta=25C; LDOE=L, AVDD=TVDD=DVDD=3.3V; AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; RL  1k; BICK=64fs; Signal Frequency =
1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure
72; unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Resolution
32
Bits
Dynamic Characteristics
(Note 8)
0dBFS
fs=44.1kHz
-115
TBD
dB
THD+N
BW=20kHz
-64
TBD
dB
60dBFS
0dBFS
fs=96kHz
-113
TBD
dB
BW=40kHz
-61
TBD
dB
60dBFS
0dBFS
fs=192kHz
-110
TBD
dB
BW=40kHz
60dBFS
-61
TBD
dB
-58
TBD
dB
BW=80kHz
60dBFS
Dynamic Range (60dBFS with A-weighted)(Note 9, Note 11)
122
127
dB
S/N (A-weighted)
(Note 10, Note 11)
122
127
dB
S/N (Mono mode, A-weighted)
(Note 11)
125
130
dB
Interchannel Isolation (1kHz)
110
120
dB
DC Accuracy
Interchannel Gain Mismatch
0.15
0.3
dB
Gain Drift
(Note 12)
-
20
ppm/
C
Output Voltage
(Note 13)
2.65
2.8
2.95
Vpp
Output Voltage (GC[2:0]=000)
3.55
3.75
3.95
Load Resistance (HLOAD=L)
(Note 14)
k
Load Resistance (HLOAD=H)
120

Load Capacitance
(Note 14)
25
pF
Note 8. Measured by Audio Precision System Two. Averaging mode.
Note 9. Figure 72 External LPF Circuit Example. 101dB at 16bit data and 118dB at 20bit data.
Note 10. Figure 72 External LPF Circuit Example. S/N does not depend on the input data size.
Note 11. SC[1:0] bits = “00” or “01”
Note 12. The voltage on (VREFH  VREFL) is held +5V externally.
Note 13. Full scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R  VREFLL/R).
AOUT (typ.@0dB) = (AOUT+)  (AOUT) = 2.8Vpp  (VREFHL/R  VREFLL/R)/5.
Note 14. Regarding Load Resistance, AC load is 1k (min) with a DC cut capacitor. DC load is 1.5k ohm
(min) without a DC cut capacitor. The load resistance value is with respect to ground. Analog
characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the
capacitive load must be minimized.
Rev. 0.1
2015/11
- 10 -
[AK4497]
(Ta=25C; AVDD=TVDD=3.3V, DVDD=1.8V(@LDOE= “L”), AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; BICK=64fs; Signal Frequency = 1kHz;
Sampling Frequency = 44.1kHz; Internal OPAMP GBW=30MHz (SC[1:0] bit=”00”); 2Vrms output mode
(GC[2:0] bit= “000” or GAIN= “L”); Heavy load drive mode=off(HLOAD bit= “0” or HLOAD= “L”); unless
otherwise specified.)
Power Supplies
Min.
Typ.
Max.
Unit
Parameter
Power Supply Current
Normal operation (PDN pin = “H”)
VDDL/R(total)
64
mA
VREFHL/R
1
mA
AVDD
1
mA
TVDD
fs= 44.1kHz
8
mA
LDOE= “H”
fs= 96kHz
13
mA
fs = 192kHz
20
mA
LDOE= “L”
1
mA
DVDD
fs= 44.1kHz
8
mA
LDOE= “L”
fs= 96kHz
13
mA
fs = 192kHz
20
mA
Total Idd per channel (HLOAD= “H”)
45
mA/ch
・fs=44.1kHz
Power down (PDN pin = “L”)
(Note 15)
TVDD+AVDD+VDDL/R+DVDD
10
A
Note 15. In the power down mode. The PSN, DEM0 pin = DVDD, and all other digital input pins including
clock pins (MCLK, BICK and LRCK) are held to DVSS.
Note 16. The DVDD pin becomes an output pin when the LDOE pin = “H”.
■ DSD mode
(Ta=25C; LDOE=L, AVDD=TVDD=3.3V, DVDD=1.8V; AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Signal Frequency = 1kHz; Measurement bandwidth = 20Hz
~ 20kHz; External Circuit; unless otherwise specified.)
Min.
Typ.
Max.
Unit
Parameter
Resolution
32
Bits
Dynamic Characteristics
THD+N
DSD dataStream: 2.8224MHz
0dBFS
-115
dB
(Note 17)
DSD dataStream: 5.6448MHz
0dBFS
-115
dB
DSD dataStream: 11.2896MHz 0dBFS
-115
dB
S/N
DSD dataStream: 2.8224MHz
Digital“0”
127
dB
(A-weighted,
DSD dataStream: 5.6448MHz
Digital“0”
127
dB
Normal path)
Digital“0”
DSD dataStream: 11.2896MHz
127
dB
(Note 17)
DC Accuracy
Output Voltage (Normal path)
(Note 13)
2.65
2.8
2.95
Vpp
Output Voltage (Volume Bypass)
(Note 13)
2.6
2.5
2.63
Vpp
Note 17. Analog characteristics are not guaranteed when the DSD dataStream is 22.5782MHz.
Rev. 0.1
2015/11
- 11 -
[AK4497]
■ Sharp Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
PB
0
20.0
kHz
(Note 18)
6.0dB
22.05
kHz
Passband
(Note 19)
PB
0
20.0
kHz
Stopband
(Note 19)
SB
24.1
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
100
dB
Group Delay
GD
29.2
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  20.0kHz
+0.1/-0.2
dB
Sharp Roll-Off Filter Characteristics (fs=96kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
PB
0
43.5
kHz
(Note 18)
6.0dB
48.0
kHz
Passband
(Note 19)
PB
0
43.5
kHz
Stopband
(Note 19)
SB
52.5
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
100
dB
Group Delay
GD
29.2
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  40.0kHz
+0.1/-0.6
dB
Sharp Roll-Off Filter Characteristics (fs=192kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
0
87.0
kHz
(Note 18)
6.0dB
96.0
kHz
Passband
(Note 19)
PB
0
87.0
kHz
Stopband
(Note 19)
SB
105
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
100
dB
Group Delay
GD
29.2
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  80.0kHz
+0.1/-2.0
dB
Note 18. Frequency response refers to the output level (0dB) of a 1kHz, 0dB sine wave input.
Note 19. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@0.01dB),
SB=0.546×fs.
Note 20. The first step of the Interpolator. This is a passband gain amplitude of the 4 times oversampling
filter.
Note 21. The calculating delay time which occurred by digital filtering. This time is from setting the
16/20/24/32 bit data of both channels to the output of analog signal.
Rev. 0.1
2015/11
- 12 -
[AK4497]
Figure 1. Sharp Roll-off Filter Frequency Response
Figure 2. Sharp Roll-off Filter Passband Ripple
Rev. 0.1
2015/11
- 13 -
[AK4497]
■ Short Delay Sharp Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
0
20.0
kHz
(Note 18)
6.0dB
22.05
kHz
Passband
(Note 22)
PB
0
20.0
kHz
Stopband
(Note 22)
SB
24.1
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
100
dB
Group Delay
GD
6.25
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  20.0kHz
+0.1/ TBD
dB
Short Delay Sharp Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
0
43.5
kHz
(Note 18)
6.0dB
48.0
kHz
Passband
(Note 22)
PB
0
43.5
kHz
Stopband
(Note 22)
SB
52.5
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
100
dB
Group Delay
GD
6.25
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  40.0kHz
+0.1/ TBD
dB
Short Delay Sharp Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
0
87.0
kHz
(Note 18)
6.0dB
96.0
kHz
Passband
(Note 22)
PB
0
87.0
kHz
Stopband
(Note 22)
SB
105
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
100
dB
Group Delay
GD
6.25
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  80.0kHz
+0.1/ TBD
dB
Note 22. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@0.01dB),
SB=0.546×fs.
Rev. 0.1
2015/11
- 14 -
[AK4497]
Figure 3. Short delay Sharp Roll-off Filter Frequency Response
Figure 4. Short delay Sharp Roll-off Filter Passband Ripple
Rev. 0.1
2015/11
- 15 -
[AK4497]
■ Slow Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“0”, SLOW bit=“1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
PB
0
4.4
kHz
(Note 18)
6.0dB
18.2
kHz
Passband
(Note 23)
PB
0
4.4
kHz
Stopband
(Note 23)
SB
39.1
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
94
dB
Group Delay
GD
6.63
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  20.0kHz
+0.1/TBD
dB
Slow Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“0”, SLOW bit=“1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
PB
0
9.5
kHz
(Note 18)
6.0dB
39.6
kHz
Passband
(Note 23)
PB
0
9.5
kHz
Stopband
(Note 23)
SB
85.0
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
94
dB
Group Delay
GD
6.63
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  40.0kHz
+0.1/ TBD
dB
Slow Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0”, SLOW bit=“1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
0
19.1
kHz
(Note 18)
6.0dB
79.2
kHz
Passband
(Note 23)
PB
0
19.1
kHz
Stopband
(Note 23)
SB
171
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
94
dB
Group Delay
GD
6.63
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  80.0kHz
+0.1/ TBD
dB
Note 23. The passband and stopband frequencies scale with fs. For example, PB = 0.1836 × fs
(@0.01dB), SB = 0.8889 × fs.
Rev. 0.1
2015/11
- 16 -
[AK4497]
Figure 5. Slow Roll-off Filter Frequency Response
Figure 6. Slow Roll-off Filter Passband Ripple
Rev. 0.1
2015/11
- 17 -
[AK4497]
■ Short Delay Slow Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
0
20.0
kHz
(Note 18)
6.0dB
22.05
kHz
Passband
(Note 22)
PB
0
20.0
kHz
Stopband
(Note 22)
SB
24.1
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
100
dB
Group Delay
GD
6.25
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  20.0kHz
+0.1/ TBD
dB
Short Delay Slow Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
0
43.5
kHz
(Note 18)
6.0dB
48.0
kHz
Passband
(Note 22)
PB
0
43.5
kHz
Stopband
(Note 22)
SB
52.5
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
100
dB
Group Delay
GD
6.25
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  40.0kHz
+0.1/ TBD
dB
Short Delay Slow Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.75  5.25V, AVDD= TVDD=3.0 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.01dB
0
87.0
kHz
(Note 18)
6.0dB
96.0
kHz
Passband
(Note 22)
PB
0
87.0
kHz
Stopband
(Note 22)
SB
105
kHz
Passband Ripple
(Note 20)
PR
0.005
dB
Stopband Attenuation
(Note 19)
SA
100
dB
Group Delay
GD
6.25
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  80.0kHz
+0.1/ TBD
dB
Note 24. The passband and stopband frequencies scale with fs. For example, PB = 0.4535 × fs
(@0.01dB), SB = 0.546 × fs.
Rev. 0.1
2015/11
- 18 -
[AK4497]
Figure 7. Short Delay Slow Roll-off Filter Frequency Response
Figure 8. Short Delay Slow Roll-off Filter Passband Ripple
Rev. 0.1
2015/11
- 19 -
[AK4497]
■ Low-dispersion Short Delay Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=3.03.6V, DVDD=1.7~1.98V; Normal Speed Mode
DEM=OFF; SD bit pr SD pin =“1”, SLOW bit or SLOW pin=“0”, SSLOW bit or SSLOW pin =”0”)
Min.
Typ.
Max.
Unit
Parameter
Symbol
Digital Filter
Frequency Response
0.05dB
PB
0
18.4
kHz
(Note 18)
6.0dB
22.5
kHz
Passband
(Note 19)
PB
0
18.4
kHz
Stopband
(Note 19)
SB
25.7
kHz
Passband Ripple
(Note 20)
PR
0.05
dB
Stopband Attenuation
(Note 19)
SA
80
dB
Group Delay
GD
10.0
1/fs
Group Delay Distortion
ΔGD
±0.035
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  20.0kHz
+0.1/-0.2
dB
Low-dispersion Short Delay Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=3.03.6V, DVDD=1.7~1.98V; Double Speed Mode;
DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.05dB
PB
0
40.1
kHz
(Note 18)
6.0dB
49.0
kHz
Passband
(Note 19)
PB
0
40.1
kHz
Stopband
(Note 19)
SB
55.9
kHz
Passband Ripple
(Note 20)
PR
0.05
dB
Stopband Attenuation
(Note 19)
SA
80
dB
Group Delay
GD
10.0
1/fs
Group Delay Distortion
ΔGD
±0.035
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  40.0kHz
+0.1/ -0.6
dB
Low-dispersion Short Delay Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=3.03.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
0.05dB
0
80.2
kHz
(Note 18)
6.0dB
98.0
kHz
Passband
(Note 19)
PB
0
87.0
kHz
Stopband
(Note 19)
SB
112
kHz
Passband Ripple
(Note 20)
PR
0.05
dB
Stopband Attenuation
(Note 19)
SA
80
dB
Group Delay
GD
10.0
1/fs
Group Delay Distortion
ΔGD
±0.035
1/fs
Digital Filter + SCF
(Note 18)
Frequency Response: 0  80.0kHz
+0.1/ -2.0
dB
Rev. 0.1
2015/11
- 20 -
[AK4497]
■ DSD Filter Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=3.03.6V, DVDD=1.7~1.98V; fs=44.1kHz; D/P
bit=“1”, DSDF bit = “0”, DSDSEL[1:0] bits = “00” (Note 26))
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response
Frequency Response
20kHz
-0.77
dB
(Note 27)
50kHz
-5.25
dB
100kHz
-18.80
dB
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=3.03.6V, DVDD=1.7~1.98V; fs=44.1kHz; D/P
bit=“1”, DSDF bit=“1” DSDD bit=“1”, DSDSEL[1:0]= “00” (Note 26))
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response
Frequency Response
20kHz
-0.19
dB
(Note 27)
100kHz
-5.29
dB
150kHz
-18.91
dB
Note 25. The peak level of DSD signal should be in the range of 25% ~ 75% duty according to the SACD
format book (Scarlet Book).
Note 26. The frequency response refers to the output level of 0dB when a 1kHz 25%~75% duty sine wave
is input.
Note 27. The frequency (20k, 100k and 200kHz) will be doubled when the sampling speed is 128fs
(DSDSEL[1:0] bits = “01”) and it will be quadrupled when the sampling speed is 256fs
(DSDSEL[1:0] bits = “10”).
Rev. 0.1
2015/11
- 21 -
[AK4497]
■ DC Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=3.03.6V, DVDD=1.7~1.98V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
TVDD=1.7  3.0V
High-Level Input Voltage
VIH
80%TVDD
V
Low-Level Input Voltage
VIL
20%TVDD
V
TVDD=3.0V  3.6V
High-Level Input Voltage
VIH
70%TVDD
V
Low-Level Input Voltage
VIL
30%TVDD
V
High-Level Output Voltage
VOH
TVDD0.5
V
(TDMO, DZFL, DZFR pins: Iout=-100µA)
Low-Level Output Voltage
(except SDA pin: Iout= 100µA)
VOL
0.5
V
(SDA pin, 2.0V  TVDD  3.6V: Iout= 3mA)
VOL
0.4
V
(SDA pin, 1.7V  TVDD  2.0V: Iout= 3mA)
VOL
20%TVDD
V
Input Leakage Current
Iin
10
A
Note 28. The TESTE pin has internal pull-down and the PSN pin has internal pull-up devices. Therefore
the TESTE and PSN pins are not included in this specification.
Rev. 0.1
2015/11
- 22 -
[AK4497]
■ Switching Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, TVDD=AVDD=1.73.6V, DVDD=1.7~1.98V, CL=20pF)
Parameter
Symbol
Min.
Typ.
Max.
Master Clock Timing
Frequency
fCLK
2.048
49.152
Duty Cycle
dCLK
40
60
Minimum Pulse Width
tCLKH
9.155
tCLKL
9.155
Unit
MHz
%
nsec
nsec
LRCK Clock Timing (Note 29)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
fsn
8
54
kHz
Double Speed Mode
fsd
54
108
kHz
Quad Speed Mode
fsq
108
216
kHz
Oct speed mode
fso
384
kHz
Hex speed mode
fsh
768
kHz
Duty Cycle
Duty
45
55
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
fsn
8
54
kHz
Double Speed Mode
fsd
54
108
kHz
Quad Speed Mode
fsq
108
216
kHz
High time
tLRH
1/128fs
nsec
Low time
tLRL
1/128fs
nsec
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
fsn
8
54
kHz
Double Speed Mode
fsd
54
108
kHz
High time
tLRH
1/256fs
nsec
Low time
tLRL
1/256fs
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
fsn
8
54
kHz
High time
tLRH
1/512fs
nsec
Low time
tLRL
1/512fs
nsec
Note 29. The MCLK frequency must be changed while the AK4497 is in reset state by setting the PDN pin
= “L” or RSTN bit = “0”.
Rev. 0.1
2015/11
- 23 -
[AK4497]
(Ta=-40~85C; VDDL/R=4.755.25V, TVDD=AVDD=1.73.6V, DVDD=1.7~1.98V, CL=20pF, PSNpin=L,
AFSDbit= "1")
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing (FS Auto Detect Mode)
Frequency
fCLK
7.68
MHz
49.152
Duty Cycle
dCLK
40
%
60
Minimum Pulse Width
tCLKH
9.155
nsec
tCLKL
9.155
nsec
LRCK Clock Timing (FS Auto Detect Mode) (Note 30)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
fsn
30
54
kHz
Double Speed Mode
fsd
88.2
108
kHz
Quad Speed Mode
fsq
176.4
216
kHz
Oct speed mode
fso
384
kHz
Hex speed mode
fsh
768
kHz
Duty Cycle
Duty
45
55
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
fsn
30
54
kHz
Double Speed Mode
fsd
88.2
108
kHz
Quad Speed Mode
fsq
176.4
216
kHz
High time
tLRH
1/128fs
nsec
Low time
tLRL
1/128fs
ns
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
fsn
30
54
kHz
Double Speed Mode
fsd
108
kHz
High time
tLRH
1/256fs
nsec
Low time
tLRL
1/256fs
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
fsn
30
54
kHz
High time
tLRH
1/512fs
nsec
Low time
tLRL
1/512fs
nsec
Note 30. Normal operation is not guaranteed if a frequency not shown above is input to the LRCK when
the AK4497 is in Sampling Frequency Auto Detect Mode.
Rev. 0.1
2015/11
- 24 -
[AK4497]
Parameter
Symbol
Min.
Typ.
PCM Audio Interface Timing
Normal Mode (TDM[1:0] bits = “00”)
BICK Period
Normal Speed Mode
tBCK
1/256fsn
Double Speed Mode
tBCK
1/128fsd
Quad Speed Mode
tBCK
1/64fsq
Oct speed mode
tBCK
1/64fso
Hex speed mode
tBCK
1/64fsh
BICK Pulse Width Low
tBCKL
9
BICK Pulse Width High
tBCKH
9
BICK “” to LRCK Edge
(Note 31)
tBLR
5
tLRB
5
LRCK Edge to BICK “”
(Note 31)
tSDH
5
SDATA Hold Time
tSDS
5
SDATA Setup Time
TDM128 mode (TDM[1:0] bits = “01”)
BICK Period
Normal Speed Mode
tBCK
1/128fsn
Double Speed Mode
tBCK
1/128fsd
Quad Speed Mode
tBCK
1/128fsq
BICK Pulse Width Low
tBCKL
14
BICK Pulse Width High
tBCKH
14
tBLR
14
BICK “” to LRCK Edge
(Note 31)
tLRB
14
LRCK Edge to BICK “”
(Note 31)
tSDH
5
SDATA Hold Time
tSDS
5
SDATA Setup Time
TDM256 mode (TDM[1:0] bits = “10”)
BICK Period
Normal Speed Mode
tBCK
1/256fsn
Double Speed Mode
(Note 32)
tBCK
1/256fsd
BICK Pulse Width Low
tBCKL
14
BICK Pulse Width High
tBCKH
14
BICK “” to LRCK Edge
(Note 31)
tBLR
14
tLRB
14
LRCK Edge to BICK “”
(Note 31)
tBSS
5
TDMO Setup time BICK “”
tBSH
5
TDMO Hold time BICK “” (Note 34)
tSDH
5
SDATA Hold Time
tSDS
5
SDATA Setup Time
TDM512 mode (TDM[1:0] bits = “11”)
BICK Period
Normal Speed Mode
(Note 33)
tBCK
1/512fsn
BICK Pulse Width Low
tBCKL
14
BICK Pulse Width High
tBCKH
14
BICK “” to LRCK Edge
(Note 31)
tBLR
14
LRCK Edge to BICK “”
(Note 31)
tLRB
14
tBSS
5
TDMO Setup time BICK “”
tBSH
5
TDMO Hold time BICK “” (Note 34)
tSDH
5
SDATA Hold Time
tSDS
5
SDATA Setup Time
Note 31. BICK rising edge must not occur at the same time as LRCK edge.
Note 32. Daisy Chain Mode, fsd (max) = 96 kHz if “TVDD < 3.0V”.
Note 33. Daisy Chain Mode, fsn (max) = 48 kHz if “TVDD < 3.0V”.
Note 34. LDOE pin = “L”, tBSH (min) = 4 nsec if “TVDD > 2.6V”.
Rev. 0.1
Max.
Unit
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
2015/11
- 25 -
[AK4497]
Parameter
Symbol
Min.
Typ.
Max.
Unit
PCM Audio Interface Timing
External Digital Filter Mode
BCK Period
tB
27
nsec
BCK Pulse Width Low
tBL
10
nsec
BCK Pulse Width High
tBH
10
nsec
BCK “” to WCK Edge
tBW
5
nsec
WCK Period
tWCK
1.3
usec
tWB
5
nsec
WCK Edge to BCK “”
tWCKL
54
nsec
WCK Pulse Width Low
tWCKH
54
nsec
WCK Pulse Width High
tDH
5
nsec
DINL/R Hold Time
tDS
5
nsec
DINL/R Setup Time
DSD Audio Interface Timing
Sampling Frequency
fs
30
48
kHz
(64fs mode, DSDSEL [1:0] bits = “00”)
tDCK
1/64fs
nsec
DCLK Period
144
tDCKL
nsec
DCLK Pulse Width Low
144
tDCKH
nsec
DCLK Pulse Width High
tDDD
20
nsec
20
DCLK Edge to DSDL/R
(Note 35)
(128fs mode, DSDSEL [1:0] bits = “01”)
DCLK Period
tDCK
1/128fs
nsec
72
DCLK Pulse Width Low
tDCKL
nsec
72
DCLK Pulse Width High
tDCKH
nsec
DCLK Edge to DSDL/R
(Note 35)
tDDD
10
nsec
10
(256fs mode, DSDSEL [1:0] bits = “10”)
DCLK Period
tDCK
1/256fs
nsec
36
DCLK Pulse Width Low
tDCKL
nsec
36
DCLK Pulse Width High
tDCKH
nsec
DCLK Edge to DSDL/R
(Note 35)
tDDD
5
nsec
5
(512fs mode, DSDSEL [1:0] bit = “11”)
DCLK Period
tDCK
1/512fs
nsec
DCLK Pulse Width Low
tDCKL
18
nsec
DCLK Pulse Width High
tDCKH
18
nsec
DSDL/R Setup Time
tDDS
5
nsec
DSDL/R Hold Time
tDDH
5
nsec
Note 35. DSD data transmitting device must meet this time. “tDDD” is defined from DCLK “↓” until
DSDL/R edge when DCKB bit = “0” (default), “tDDD” is defined from DCLK “↑” until DSDL/R
edge when DCKB bit = “1”. If the audio data format is in phase modulation mode, “tDDD” is
defined from DCLK edge “↓” or “↑” until DSDL/R edge regardless of DCKB bit setting.
Note 36. The AK4497 does not support Phase Modulation Mode in DSD512fs Mode.
Rev. 0.1
2015/11
- 26 -
[AK4497]
Parameter
Symbol Min. Typ. Max.
Control Interface Timing (3-wire IF mode):
CCLK Period
200
tCCK
CCLK Pulse Width Low
80
tCCKL
Pulse Width High
80
tCCKH
CDTI Setup Time
40
tCDS
CDTI Hold Time
40
tCDH
CSN “H” Time
150
tCSW
50
tCSS
CSN “” to CCLK “”
50
tCSH
CCLK “” to CSN “”
2
Control Interface Timing (I C Bus mode):
SCL Clock Frequency
fSCL
400
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 37)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
1.0
Fall Time of Both SDA and SCL Lines
tF
0.3
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
50
Capacitive load on bus
Cb
400
Power-down & Reset Timing
(Note 38)
PDN Accept Pulse Width
tAPD
150
PDN Reject Pulse Width
tRPD
30
Note 37. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 38. The AK4497 can be reset by bringing the PDN pin “L” to “H” upon power-up.
Note 39. I2C -bus is a trademark of NXP B.V.
Rev. 0.1
Unit
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
kHz
usec
usec
usec
usec
usec
usec
usec
usec
usec
usec
nsec
pF
nsec
nsec
2015/11
- 27 -
[AK4497]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
VIL
LRCK
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
tWCK
VIH
WCK
VIL
tWCKH
tWCKL
tB
VIH
BCK
VIL
tBH
tBL
Figure 9. Clock Timing
Rev. 0.1
2015/11
- 28 -
[AK4497]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSH
tBSS
TDMO
50%TVDD
tSDS
tSDH
VIH
SDATA
VIL
Figure 10. Audio Interface Timing (PCM Mode)
VIH
WCK
VIL
tBW
tWB
VIH
BCK
VIL
tDS
tDH
VIH
DINL
DINR
VIL
Figure 11. Audio Interface Timing (External Digital Filter I/F Mode)
Rev. 0.1
2015/11
- 29 -
[AK4497]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
tDDD
VIH
DSDL
DSDR
VIL
DSD Audio Interface Timing (DSD64fs, 128fs, 256fs Mode)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDS
tDDH
VIH
DSDL
DSDR
VIL
DSD Audio Interface Timing (DSD512fs Mode)
Figure 12. Audio Interface Timing (DSD Normal Mode, DCKB bit = “0”)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Figure 13. Audio Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
Rev. 0.1
2015/11
- 30 -
[AK4497]
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
Figure 14. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 15. WRITE Data Input Timing
Rev. 0.1
2015/11
- 31 -
[AK4497]
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 16. I2C Bus Mode Timing
tAPD
tRPD
PDN
VIL
Figure 17. Power Down & Reset Timing
Rev. 0.1
2015/11
- 32 -
[AK4497]
9. Functional Descriptions
Each function of the AK4497 is controlled by Pins (pin control mode) and Registers (register control
mode) (Table 1). Select the control mode by setting the PSN pin. The AK4497 must be powered down
when changing the PSN pin setting. There is a possibility of malfunction if the device is not powered down
when changing the control mode since the previous setting is not initialized. Register settings are invalid
in pin control mode, and pin settings are invalid in register control mode.
Table 2 shows available functions of each control mode and Table 3 shows available functions in
PCM/DSD/EXDF mode.
Table 1. Pin/Register Control Mode Select
PSN pin
Control Mode
L
Register Control Mode
H
Pin Control Mode
Table 2. Function List @Pin/Register Control Mode
Register Control
Function
Pin Control Mode
Mode
DSD/EXDF Mode Select
Y
System Clock Setting Select
Y
Y
Audio Format Select
Y
Y
TDM Mode
Y
Y
Digital Filter Select
Y
Y
De-emphasis Filter Select
Y
Y
Digital Attenuator
Y
Zero Detection
Y
Mono Mode
Y
Output signal select
Y
(Monaural, Channel select)
Output signal polarity select
Y
Y
(Invert)
Sound Color Select
Y
DSD Full Scale Detect
Y
Soft Mute
Y
Y
Register Reset
Y
Clock Synchronization Function
Y
Resistor Control
Y
Gain Control
Y
Y
Heavy Load Mode
Y
Y
(Y: Available, -: Not available)
Rev. 0.1
2015/11
- 33 -
[AK4497]
Table 3. Function List of PCM/EXDF/DSD mode @Register Control Mode
Function
Default
Add
Bit
PCM EXDF
00H
EXDF
PCM/DSD/EXDF Mode Select
PCM mode
Y
Y
02H
DP
System clock setting @DSD mode
512fs
02H
DCKS
System clock setting @EXDF mode 16fs(fs=44.1kHz)
00H
ECS
Y
Digital Filter select @DSD mode
Digital Filter select @PCM mode
De-emphasis Response
Path select @ DSD mode
Audio Data Interface Format
@ PCM Mode
Audio Data Interface Format
@ EXDF Mode
TDM Interface Format
Daisy Chain
Attenuation Level
Data Zero Detect Enable
Inverting Enable of DZF
Mono/Stereo mode select
Data Invert mode select
The data selection of L channel and
R channel
Sound Color Select
DSD Mute Function @ Full scale
Detected
Soft Mute Enable
RSTN
Clock Synchronization Function
(Y: Available, N/A: Not available)
39kHz filter
Short delay
sharp roll off
filter
OFF
Normal Path
09H
DSDF
DSD
Y
Y
-
-
-
Y
Y
-
-
Y
-
-
Y
01H
06H
SD
SLOW
SSLOW
DEM[1:0]
DSDD
32bit MSB
00H
DIF[2:0]
Y
-
-
32bit LSB
00H
DIF[2:0]
-
Y
-
Normal Mode
Normal Mode
0dB
Disable
“H” active
Stereo
OFF
0AH
0BH
03-04H
01H
02H
02H
05H
TDM[1:0]
DCHAIN
ATT[7:0]
DZFE
DZFB
MONO
INVL/R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
R channel
02H
SELLR
Y
Y
Y
Off
08H
SC[2:0]
Y
Y
Y
Disable
06H
DDM
-
-
Y
01H
SMUTE
Y
Y
Y
00H
07H
RSTN
SYNCE
Y
Y
Y
Y
Y
-
Normal
Operation
RST
Enable
Rev. 0.1
01-02-05H
2015/11
- 34 -
[AK4497]
■ D/A Conversion Mode
The AK4497 can perform D/A conversion for either PCM data or DSD data. The DP bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from the #16, #17 and #19 pins if DSDPATH
bit = “0” and DSD data can be input from the #3, #4, and #5 pins if DSDPATH bit = “1”. The AK4497 must
be reset by setting RSTN bit = “0” when PSM/DSD mode is changed by DP bit or when DSD signal input
pins are changed by DSDPATH bit. It takes about 2 ~ 3/fs to change the mode. Wait 4/fs or more to
change DP or DSDPATH bit setting after setting RSTN bit = “0”.
When the AK4497 is in pin control mode, PCM mode is only available. External digital filter I/F can be
selected by setting DP bit = “0” and EXDF bit = “1”. When using an external digital filter (EXDF I/F mode),
data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXDF bit controls the modes. When
switching internal and external digital filters by EXDF bit, the AK4497 must be reset by RSTN bit. A Digital
filter switching takes 2~3k/fs. The AK4497 is in DSD mode when DP bit = “1” and EXDF bit “1”.
DP bit
EXDF bit
0
(default)
0
(default)
1
*
1
*
0
1
(*: Do not care)
Table 4. PCM/DSD/EXDF Mode Control
Pin Assignment
DSDPATH
D/A Conv.
bit
Mode
#3 pin
#4 pin
#5 pin
#16 pin
#17 pin
#19 pin
*
PCM
BICK
SDATA
LRCK
Not Use
Not Use
Not Use
DSD
Not Use
Not Use
Not Use
DCLK
DSDL
DSDR
DSD
EXDF
DCLK
BCK
DSDL
DINL
DSDR
DINR
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
0
(default)
1
*
■ D/A Conversion Mode Switching Timing
Figure 18 and Figure 19 show switching timing of PCM/EXDF and DSD modes. To prevent noise caused
by excessive input, DSD signal should be input 4/fs after setting RSTN bit = “0” until the device is
completely reset internally when the conversion mode is changed to DSD mode from PCM/ESDF mode.
DSD signal should be stopped 4/fs after setting RSTN bit = “0”until the device is completely reset
internally when the conversion mode is changed to PCM/EXDE from DSD mode.
RSTN bit
4/fs
D/A Mode
PCM or EXDF Mode
DSD Mode
0
D/A Data
PCM or EXDF Data
DSD Data
Figure 18. D/A Mode Switching Timing (PCM or EXDF to DSD)
Rev. 0.1
2015/11
- 35 -
[AK4497]
RSTN bit
0
D/A Mode
DSD Mode
PCM or EXDF Mode
4/fs
D/A Data
PCM Data
DSD Data
Figure 19. D/A Mode Switching Timing (DSD to PCM or EXDF)
Figure 20 shows switching timing of PCM and EXDF modes. Set EXDF bit 4/fs after setting RSTN bit =
“0” until the device is completely reset internally when changing the conversion mode.
RSTN bit
4/fs
D/A Mode
D/A Data
PCM or EXDF Mode
0
PCM or EXDF Mode
PCM or EXDF Data
PCM or EXDF Data
Figure 20. D/A Mode Switching Timing (PCM ⇔ EXDF)
Rev. 0.1
2015/11
- 36 -
[AK4497]
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4497, are MCLK, BICK and LRCK. MCLK
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital
interpolation filter, the delta-sigma modulator and SCF.
There are Manual Setting Mode, Auto Setting Mode and Fs Auto Detection mode for MCLK frequency
setting. In manual setting mode, MCLK frequency is set automatically but the sampling speed (LRCK
frequency) is set by DFS[2:0] bits (Table 6). Sampling frequency is fixed to normal speed mode in pin
control mode (PSN pin = “H”), and it is set by DFS[2:0] bits in register control mode (PSN pin = “L”). In
register control mode, the AK4497 is in manual setting mode when power-down is released (PDN pin =
“”).
In auto setting mode (ACKS pin = “H” or ACKS bit=“1”), sampling speed and MCLK frequency are
detected automatically (Table 7, Table 10) and then the initial master clock is set to the appropriate
frequency (Table 8, Table 14, Table 15).
In FS auto detect mode (AFSD bit= “1”), sampling speed is automatically detected (Table 7, Table 10)
and the initial master clock is set to the appropriate frequency. In this mode, ACKS bit and DFS[2:0] bits
settings are invalid. Fs auto detect mode is not supported by pin control mode.
The AK4497 is automatically placed in power-down state when MCLK is stopped for more than 1us
during a normal operation (PDN pin =“H”), and the analog output becomes Hi-z state. When MCLK is
input again, the AK4497 exits power-down state and starts operation. The AK4497 is in power-down
mode until MCLK BICK and LRCK are supplied and the analog output is floating state.
Table 5. System Clock Setting Mode @Register Control Mode
AFSD bit ACKS bit
Mode
0
0
Manual setting Mode
(default)
0
1
Auto setting Mode
1
FS Auto Detect Mode
Rev. 0.1
2015/11
- 37 -
[AK4497]
(1) Pin Control Mode (PSN pin = “H”)
1-1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided externally (Table 6).
DFS1-0 bit is fixed to “00”. In this mode, quad speed and double speed modes are not available.
Table 6. System Clock Example (Manual Setting Mode @Pin Control Mode)(N/A: Not available)
LRCK
MCLK (MHz)
BICK
fs
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
64fs
32.0kHz
N/A
N/A
8.1920
12.2880 16.3840 24.5760 36.8640 2.0480MHz
44.1kHz
N/A
N/A
11.2896 16.9344 22.5792 33.8688
N/A
2.8224MHz
48.0kHz
N/A
N/A
12.2880 18.4320 24.5760 36.8640
N/A
3.0720MHz
1-2. Auto Setting Mode (ACKS pin = “H”)
In auto setting mode, MCLK frequency and sampling frequency are detected automatically (Table 7).
MCLK of corresponded frequency to each sampling speed mode should be input externally (Table 8).
Table 7. Sampling Speed (Auto Setting Mode @Pin Control Mode)
MCLK
Sampling Speed
1152fs
Normal (fs32kHz)
512fs/256fs 768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
Table 8. System Clock Example (Auto Setting Mode @Pin Control Mode) (N/A: Not available)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
32fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
48fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
64fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
N/A
96fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
MCLK(MHz)
192fs
256fs
N/A
8.1920
N/A
11.2896
N/A
12.2880
N/A
22.5792
N/A
24.5760
33.8688
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
N/A
N/A
N/A
512fs
16.3840
22.5792
24.5760
N/A
N/A
N/A
N/A
N/A
N/A
768fs
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
1024fs
32.7680
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
Speed
Normal
Double
Quad
Quad
Oct
Hex
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 8kHz~96kHz (Table 9).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 9. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS pin
MCLK
DR,S/N
L
256fs/384fs/512fs/768fs
127dB
H
256fs/384fs
124dB
H
512fs/768fs
127dB
Rev. 0.1
2015/11
- 38 -
[AK4497]
(2) Register Control Mode (PSN pin = “L”)
1-1. Manual Setting Mode (AFSD bit=”0”, ACKS bit = “0”)
MCLK frequency is detected automatically and the sampling speed is set by DFS[2:0] bits (Table 10). The
MCLK frequency corresponding to each sampling speed that should be provided externally (Table 11).
The AK4497 is set to Manual Setting Mode at power-up (PDN pin = “L” →“H”). When DFS2-0 bits are
changed, the AK4497 should be reset by RSTN bit.
Table 10. Sampling Speed (Manual Setting Mode @Register Control Mode)
DFS2 DFS1 DFS0
Sampling Rate (fs)
0
0
0
Normal Speed Mode
(default)
8kHz  54kHz
0
0
1
Double Speed Mode
54kHz  108kHz
0
1
0
Quad Speed Mode
120kHz  216kHz
0
1
1
Quad Speed Mode
120kHz  216kHz
1
0
0
Oct Speed Mode
384kHz
1
0
1
Hex Speed Mode
768kHz
384kHz
1
1
0
Oct Speed Mode
768kHz
1
1
1
Hex Speed Mode
Table 11. System Clock Example (Manual Setting Mode @Register Control Mode)
Sampling
MCLK(MHz)
LRCK
Speed
Fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
16fs
32fs
48fs
64fs
96fs
128fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288
24.576
N/A
N/A
N/A
N/A
N/A
N/A
N/A
18.432
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
49.152
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
Normal
Double
Quad
Quad
Oct
Hex
Table 12. System Clock Example (Manual Setting Mode @Register Control Mode)
Sampling
LRCK
MCLK(MHz)
Speed
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
N/A
N/A
N/A
N/A
N/A
33.8688
36.8640
N/A
N/A
8.1920
11.2896
12.2880
22.5792
24.5760
45.1584
49.152
N/A
N/A
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
N/A
N/A
N/A
16.3840
22.5792
24.5760
45.1584
49.152
N/A
N/A
N/A
N/A
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
32.7680
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Rev. 0.1
Normal
Double
Quad
Quad
Oct
Hex
2015/11
- 39 -
[AK4497]
1-2. Auto Setting Mode (AFSD bit= “0”, ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 13) and DFS[2:0] bits are
ignored. The MCLK frequency corresponding to each sampling speed should be provided externally
(Table 14, Table 15).
Table 13. Sampling Speed (Auto Setting Mode)
MCLK
Sampling Speed
1152fs
Normal (fs32kHz)
512fs/256fs 768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
Table 14. System Clock Example (Auto Setting Mode)
Sampling
MCLK(MHz)
LRCK
Speed
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
32fs
48fs
64fs
96fs
128fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
Normal
Double
Quad
Quad
Oct
Hex
Table 15. System Clock Example (Auto Setting Mode)
MCLK(MHz)
192fs
256fs
384fs
512fs
768fs
1152fs
N/A
N/A
N/A
N/A
N/A
33.8688
36.8640
N/A
N/A
8.1920
11.2896
12.2880
22.5792
24.5760
N/A
N/A
N/A
N/A
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
N/A
N/A
N/A
16.3840
22.5792
24.5760
N/A
N/A
N/A
N/A
N/A
N/A
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
Speed
Normal
Double
Quad
Quad
Oct
Hex
When MCLK= 256fs/384fs, auto setting mode supports sampling rate from 8kHz to 96kHz (Table 13).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 16. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS bit
MCLK
DR,S/N
0
256fs/384fs/512fs/768fs
127dB
1
256fs/384fs
124dB
1
512fs/768fs
127dB
Rev. 0.1
2015/11
- 40 -
[AK4497]
1-3. Sampling Frequency (FS) Auto Detect Mode (AFSD bit=”1”)
MCLK frequency and the sampling rate is detected automatically (Table 13). In this mode, DFS[2:0] bits
and ACKS bit settings are invalid. The MCLK frequency corresponding to each sampling speed should
be provided externally (Table 17, Table 18). Internal operation sequence in FS auto detect mode is
shown in Figure 21.
LRCK
Fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
16fs
32fs
48fs
64fs
96fs
128fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288
24.576
N/A
N/A
N/A
N/A
N/A
N/A
N/A
18.432
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
49.152
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
Sampling
Speed
Normal
Double
Quad
Quad
Oct
Hex
Table 18. System Clock Example @PCM Mode
MCLK(MHz)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
Table 17. System Clock Example @PCM Mode
MCLK(MHz)
Sampling
Speed
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
N/A
N/A
N/A
N/A
N/A
33.8688
36.8640
N/A
N/A
8.1920
11.2896
12.2880
22.5792
24.5760
45.1584
49.152
N/A
N/A
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
N/A
N/A
N/A
16.3840
22.5792
24.5760
45.1584
49.152
N/A
N/A
N/A
N/A
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
32.768
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Rev. 0.1
Normal
Double
Quad
Quad
Oct
Hex
2015/11
- 41 -
[AK4497]
■ Power ON/OFF Sequence in FS Auto Detect Mode (LDOE pin = “H”)
Power
PDN pin
(1)
DVDD pin
(2)
Internal PDN
Internal
State
Normal Operation (Register Write and DAC Operation are Available)
AFSD bit
AFSD bit = “0”
AFSD bit = “1”
AFSD bit = “0”
(3)
Power up
Internal OSC
Clock In
Don’t care
LRCK
Internal FS Auto Detect Circuit
(4)
FS Auto Detect mode Enable
Note:
(1) Power-up AVDD and TVDD and the PDN pin should be “L” for more than 150ns.
(2) The internal LOD is powered up upon power-up of the AK4497 if the LDOE pin= “H”. The internal
circuit will be powered up in 2ms (max.) after the shutdown switch is ON following internal
oscillator count up. When LDOE pin = “L”, shutdown switch is ON after the AK4497 is powered
up. The internal circuit will be powered up in 1us (max.)
(3) The internal oscillator starts operation by setting AFSD bit= “1”. It takes 10us (max.) until the
internal oscillator is stabilized.
(4) FS auto detect mode starts in 8/fs ~ 9/fs after setting AFSD bit= “1”.
(5) FS auto detect mode ends by setting AFSD bit = “0” and the internal oscillator will stop operation.
Figure 21. Power-down/up Sequence in FS AutoDetect Mode
Rev. 0.1
2015/11
- 42 -
[AK4497]
[1] DSD Mode
The AK4497 has a DSD playback function. The external clocks that are required in DSD mode are MCLK
and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of
MCLK is set by DCKS bit (Table 19).
The AK4497 is automatically placed in power-down state when MCLK is stopped during a normal
operation (PDN pin =“H”), and the analog output becomes Hi-z state. When the reset is released (PDN
pin = “L” → “H”), the AK4497 is in power-down state until MCLK and DCLK are input.
Table 19. System Clock (DSD Mode, fs=32kHz, 44.1kHz, 48kHz)
DCKS bit MCLK Frequency DCLK Frequency
0
512fs
64fs/128fs/256fs (default)
1
768fs
64fs/128fs/256fs
The AK4497 supports DSD data stream of 2.8224MHz (64fs), 5.6448MHz (128fs) and 11.2896MHz
(256fs). The data sampling speed is selected by DSDSEL[1:0] bits (Table 20).
DSDSEL1
DSDSEL0
0
0
1
1
0
1
0
1
Table 20. DSD data stream select
DSD data stream
fs=32kHz
fs=44.1kHz
2.048MHz
2.8224MHz
4.096MHz
5.6448MHz
8.192MHz
11.2896MHz
16.284MHz
22.5792MHz
fs=48kHz
3.072MHz
6.144MHz
12.288MHz
24.576MHz
(default)
The AK4497 has a Volume bypass function for play backing DSD signal. Two modes are selectable by
DSDD bit (Table 21). When setting DSDD bit = “1”, the output volume control and zero detect functions
are not available.
Table 21. DSD Play Back Path Select
DSDD
Mode
0
Normal Path
(default)
1
Volume Bypass
Rev. 0.1
2015/11
- 43 -
[AK4497]
[2] External Digital Filter Mode (EXDF mode)
The external clocks that are required in EXDF mode are MCLK, BCK and WCK. The BCK and MCLK
clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each sampling
speed are shown in Table 22. ECS bit selects WCK frequency from 384kHz and 768kHz. DW indicates
the number of BCK in one WCK cycle.
All circuits except the internal LDO are automatically placed in power-down state when MCLK edge is not
detected for more than 1us during a normal operation (PDN pin =“H”), and the analog output becomes
Hi-Z state. The power-down state is released and the AK4497 starts operation by inputting MCLK again.
In this case, register settings are not initialized.
When the reset is released (PDN pin = “L” → “H”), the AK4497 is in power-down state until MCLK, BCK
and WCK are input.
Table 22. System Clock Example (EXDF mode)
Sampling
Speed[kHz]
44.1(30~48)
44.1(30~48)
96(54~96)
96(54~96)
192(108~192)
192(108~192)
MCLK&BCK [MHz]
128fs
N/A
N/A
N/A
12.28
8
32
192fs
N/A
N/A
N/A
18.432
256fs
N/A
384fs
N/A
512fs
768fs
22.5792
33.8688
48
11.2896
32
16.9344
32
N/A
33.8688
24.576
36.864
N/A
96
N/A
32
48
N/A
36.864
N/A
N/A
N/A
96
N/A
N/A
N/A
N/A
N/A
N/A
N/A
48
24.576
36.864
32
N/A
48
36.864
WCK
48
96
Rev. 0.1
16fs
DW
8fs
DW
8fs
DW
4fs
DW
4fs
DW
2fs
DW
ECS
0
(default)
1
0
1
0
1
2015/11
- 44 -
[AK4497]
■ Audio Interface Format
[1] PCM mode
(i) Input Data Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and
selected by the DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table
23. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of
BICK. Mode 2 can be used for 20-bit and 16-bit MSB justified formats by zeroing the unused LSBs.
Normal Mode (TDM[1:0] bits = “00” or TDM1-0 pins = “LL”)
2ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported
and selected by the DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in
Table 23. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge
of BICK. Mode 6 can be used for 24-bit, 20-bit and 16-bit MSB justified formats by zeroing the unused
LSBs.
TDM128 Mode (TDM[1:0] bits = “01” or TDM1-0 pins = “LH”)
4ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
SDS[2:0] bits (Table 24). BICK is fixed to 128fs. Six data formats are supported and selected by the
DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table 23. In all
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
TDM256 Mode (TDM[1:0] bits =“10” or TDM1-0 pins =“HL”)
8ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
SDS[2:0] bits (Table 24). BICK is fixed to 256fs. Six data formats are supported and selected by the
DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table 23. In all
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
TDM512 Mode (TDM[1:0] bits = “11” or TDM1-0 pins = “HH”)
16ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
SDS[2:0] bits (Table 24). BICK is fixed to 512fs. Six data formats are supported and selected by the
DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table 23. In all
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
Rev. 0.1
2015/11
- 45 -
[AK4497]
Table 23. Audio Interface Format
TDM1 TDM0 DIF2 DIF1 DIF0 SDATA Format
LRCK BICK
0
0
0
0
16-bit LSB justified
H/L
32fs
1
0
0
1
20-bit LSB justified
H/L
40fs
2
0
1
0
24-bit MSB justified
H/L
48fs
16-bit I2S Compatible
L/H
32fs
3
0
1
1
2
Normal
24-bit I S Compatible
L/H
0
0
48fs
(Note 45)
4
1
0
0
24-bit LSB justified
H/L
48fs
5
1
0
1
32-bit LSB justified
H/L
64fs
6
1
1
0
32-bit MSB justified
H/L
64fs
7
1
1
1
32-bit I2S Compatible
L/H
64fs
0
0
0
(16-bit LSB justified)
H/L
128fs
0
0
1
(20-bit LSB justified)
H/L
128fs
8
0
1
0
24-bit MSB justified
H/L
128fs
9
0
1
1
24-bit I2S Compatible
L/H
128fs
TDM128
0
1
10
1
0
0
24-bit LSB justified
H/L
128fs
11
1
0
1
32-bit LSB justified
H/L
128fs
12
1
1
0
32-bit MSB justified
H/L
128fs
13
1
1
1
32-bit I2S Compatible
L/H
128fs
0
0
0
(16-bit LSB justified)
H/L
256fs
0
0
1
(20-bit LSB justified)
H/L
256fs
14
0
1
0
24-bit MSB justified
H/L
256fs
15
0
1
1
24-bit I2S Compatible
L/H
256fs
TDM256
1
0
16
1
0
0
24-bit LSB justified
H/L
256fs
17
1
0
1
32-bit LSB justified
H/L
256fs
18
1
1
0
32-bit MSB justified
H/L
256fs
19
1
1
1
32-bit I2S Compatible
L/H
256fs
0
0
0
(16-bit LSB justified)
H/L
512fs
0
0
1
(20-bit LSB justified)
H/L
512fs
20
0
1
0
24-bit MSB justified
H/L
512fs
21
0
1
1
24-bit I2S Compatible
L/H
512fs
TDM512
1
1
22
1
0
0
24-bit LSB justified
H/L
512fs
23
1
0
1
32-bit LSB justified
H/L
512fs
24
1
1
0
32-bit MSB justified
H/L
512fs
2
25
1
1
1
32-bit I S Compatible
L/H
512fs
Note 40. BICK more than setting bit must be input to each channel. In the LRCK column, “H/L” indicates
that L channel data can be input when LRCK is “H” and R channel data can be input when
LRCK is “L”. “L/H” indicates L channel data can be input when LRCK is “L” and R channel data
can be input when LRCK is “H”.
Mode
Rev. 0.1
2015/11
- 46 -
[AK4497]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA
Mode 0
15
14
6
1
0
5
14
4
15
3
16
2
1
17
0
31
15
0
14
6
5
14
1
4
15
3
16
2
1
17
0
31
15
14
0
1
0
1
0
1
BICK
(64fs)
SDATA
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 22. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 23. Mode 1, 4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDATA
23
22
1
0
Don’t care
23
22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 24. Mode 2 Timing
Rev. 0.1
2015/11
- 47 -
[AK4497]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDATA
23
0
1
22
Don’t care
23
22
0
1
23
Don’t care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 25. Mode 3 Timing
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31
0
1
2
12
13
14
23
1
24
0
31
31
0
1
2
12
13
14
23
1
24
0
31
0
1
BICK(64fs)
SDATA
31 30
20 19 18
8
9
0
1
31 30
20
19 18
Lch Data
8
9
0
1
31
Rch Data
31: MSB, 0:LSB
Figure 26. Mode 5 Timing
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31 30
0
1
12 11 10
2
12
13
0
14
31 30
23
24
31
0
1
12
2
11 10
12
13
0
14
31
23
24
31
0
1
BICK(64fs)
SDATA
31 30
20 19 18
9
8
1
0
31 30
Lch Data
20
19 18
9
8
1
0
31
Rch Data
31: MSB, 0:LSB
Figure 27. Mode 6 Timing
Rev. 0.1
2015/11
- 48 -
[AK4497]
LRCK
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
24
25
31
0
1
BICK(128fs)
SDATA
31
0
1
13 12 11
2
12
13
0
14
31
24
25
31
0
1
13
2
12 11
12
0
13
14
0
1
BICK(64fs)
SDATA
0
31
21 20 19
9
8
1
2
0
31
21
20 19
Lch Data
9
8
2
1
0
Rch Data
31: MSB, 0:LSB
Figure 28. Mode 7 Timing
128 BICK
LRCK
BICK(128fs)
SDATA
Mode8
23 22
SDATA
Mode11,12
31 30
0
23 22
0
0 31 30
23 22
0
L1
R1
32 BICK
32 BICK
31 30
32 BICK
32 BICK
Figure 29. Mode 8/11/12 Timing
128 BICK
LRCK
BICK(128fs)
SDATA
Mode9
23 22
SDATA
Mode13
31 30
0
0
23 22
0 31 30
23
31 30
0
L1
R1
32 BICK
32 BICK
32 BICK
32 BICK
Figure 30. Mode 9/13 Timing
Rev. 0.1
2015/11
- 49 -
[AK4497]
128 BICK
LRCK
BICK(128fs)
SDATA
23 22
0
23 22
0
L1
R1
32 BICK
32 BICK
23
32 BICK
32 BICK
Figure 31. Mode 10 Timing
256 BICK
LRCK
BICK (256fs)
SDATA
Mode14
SDATA
Mode17,18
23 22
0
31 30
23 22
0
23 22
0 31 30
0
L1
R1
32 BICK
32 BICK
31 30
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 32. Mode 14/17/18 Timing
256 BICK
LRCK
BICK (256fs)
SDATA
Mode15
SDATA
Mode19
23
0
23
31 30
0
23
0 31 30
0
L1
R1
32 BICK
32 BICK
31
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 33. Mode 15/19 Timing
256 BICK
LRCK
BICK(256fs)
SDATA
23 22
0
23 22
L1
R1
32 BICK
32 BICK
0
23
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 34. Mode 16 Timing
Rev. 0.1
2015/11
- 50 -
[AK4497]
512BICK
LRCK
BICK(512fs)
SDATA
Mode8
SDATA
Mode11,12
23 22
0
23 22
23
0
2
31 22
0 31 22
31
0
R1
L1
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 35. Mode 20/23/24 Timing
512BICK
LRCK
BICK(512fs)
SDATA
Mode21
SDATA
Mode25
23 22
0
23 22
23
0
2
31 22
0 31 22
31
0
R1
L1
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 36. Mode 21/25 Timing
512BICK
LRCK
BICK(512fs)
SDATA
Mode22
23 22
L1
0
23 22
23
0
2
R1
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 37. Mode 22 Timing
Rev. 0.1
2015/11
- 51 -
[AK4497]
(ii) Data Slot Selection Function
Data slot of 1cycle LRCK for each audio data format is defined as Figure 38~ Figure 41. DAC output data
can be selected by SDS[2:0] bits as shown in Table 24.
LRCK
L1
SDATA
R1
Figure 38. Data Slot in Normal Mode
128 BICK
LRCK
L1
SDATA
R1
L2
R2
Figure 39. Data Slot in TDM128 Mode
256 BICK
LRCK
SDATA
L1
R1
L2
R2
L3
R3
L4
R4
Figure 40. Data Slot in TDM256 Mode
512 BICK
LRCK
SDATA
L1
R1
L2
R2
L3
R3
L4
R4
L5
R5
L6
R6
L7
R7
L8
R8
Figure 41. Data Slot in TDM512 Mode
Rev. 0.1
2015/11
- 52 -
[AK4497]
SDS2
Normal
*
Table 24. Data Select
DAC
SDS1
SDS0
Lch
Rch
*
*
L1
R1
*
*
0
L1
R1
*
*
1
L2
R2
*
*
*
*
0
0
1
1
0
1
0
1
L1
L2
L3
L4
R1
R2
R3
R4
0
0
0
0
0
1
L1
L2
R1
R2
0
0
1
1
1
1
0
0
0
1
0
1
L3
L4
L5
L6
R3
R4
R5
R6
1
1
(*: Do not care)
1
1
0
1
L7
L8
R7
R8
TDM128
TDM256
TDM512
Rev. 0.1
2015/11
- 53 -
[AK4497]
(iii) Daisy Chain
The AK4497 supports cascading of multiple devices by daisy chain connection in TDM512/256 mode
(TDM[1:0] bits = “10”, “11”). DCHAIN bit or DCHAIN pin controls Daisy Chain mode (Table 25). SDS[2:0]
bits setting will be invalid in Daisy Chain mode.
Table 25 Daisy Chain Control
DCHAIN bit
DCHAIN pin
0
1
Mode
TDMO
Normal
Daisy Chain
“L”
Data output
(default)
(1) TDM512 Mode
Figure 42 shows daisy chain connection in TDM512 mode (TDM[1:0] bits = “11”). 16ch data is input to the
SDATA pin of the second AK4497 and the TDMO pin of the second AK4497 is connected to the SDATA
pin of the first AK4497.
Figure 43 shows data input/output example of daisy chain in TDM512 mode. The second AK4497
receives L8 and R8 data as DAC inputs and outputs the data by shifting 2ch from the TDMO pin. The first
AK4497 receives L7 and R7 data as DAC input. Settings of DIF[2:0] bits of the first and second AK4497’s
must be the same.
TDMO
SDATA
TDMO
First
AK4497
SDATA
DSP
Second
AK4497
Figure 42. Daisy Chain (TDM512 Mode)
512 BICK
LRCK
SDATA
L1
R1
L2
R2
L3
R3
L4
R4
L5
R5
L6
R6
L7
R7
L8
R8
Second AK4497
TDMO
L8
R8
L1
R1
L2
R2
L3
R3
L4
R4
L5
R5
L6
R6
L7
R7
First AK4497
Figure 43. Daisy Chain (TDM512 Mode)
Rev. 0.1
2015/11
- 54 -
[AK4497]
(2) TDM256 Mode
Figure 42 shows daisy chain connection in TDM256 mode (TDM[1:0] bits = “10”). 8ch data is input to the
SDATA pin of the second AK4497 and the TDMO pin of the second AK4497 is connected to the SDATA
pin of the first AK4497.
Figure 44 shows data input/output example of daisy chain in TDM256 mode. The second AK4497
receives L4 and R4 data as DAC inputs and outputs the data from the TDMO pin by shifting 2ch. The first
AK4497 receives L3 and R3 data as DAC input. Settings of DIF[2:0] bits of the first and second AK4497’s
must be the same.
256 BICK
LRCK
SDATA
L1
R1
L2
R2
L3
R3
L4
R4
Second AK4497
TDMO
L4
R4
L1
R1
L2
L3
R2
R3
First AK4497
Figure 44. Daisy Chain (TDM256 Mode)
[2] DSD Mode
In DSD mode, L channel data and R channel data must be input to the DSDL pin and the DSDR pin,
respectively by synchronizing to DCLK. Input pins can be selected by DSDPATH bit. When DSDPATH bit
= “0”, the TDM0 pin, the DEM pin and the GAIN pin become DCLK, DSDL and DSDR input pins,
respectively. When DSDPATH bit = “1”, the BICK pin, the SDATA pin and the LRCK pin become DCLK,
DSDL and DSDR input pins, respectively.
In case of DSD mode, the settings of DIF2-0 pins and DIF[2:0] bits are ignored. The frequency of DCLK is
selected between 64fs, 128fs and 256fs by DSDSEL[1:0] bits. Phase modulation function is not available
in 512fs mode (DSDSEL[1:0] bits = “11”).
DCLK (64fs,128fs,256fs,512fs)
DCKB bit=”1”
DCLK (64fs,128fs,256fs,512fs)
DCKB bit=”0”
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D2
D3
Figure 45. DSD Mode Timing
Rev. 0.1
2015/11
- 55 -
[AK4497]
[3] External Digital Filter Mode (EXDF mode)
The audio data is input by BCK and WCK from the DINL and DINR pins. Three formats are available
(Table 26) by DIF2-0 bits setting. The data is latched on the rising edge of BCK. The BCK and MCLK
clocks must not burst.
Table 26. Audio Interface Format (EXDF mode) (N/A: Not available)
Mode DIF2
DIF1
DIF0
Input Format
0
0
0
0
16-bit LSB justified
1
0
0
1
N/A
2
0
1
0
16-bit LSB justified
3
0
1
1
N/A
4
1
0
0
24-bit LSB justified
5
1
0
1
32-bit LSB justified
6
1
1
0
24-bit LSB justified (default)
7
1
1
1
32-bit LSB justified
1/16fs or 1/8fs or 1/4fs or 1/2fs
WCK
0
1
8
9
10
11
16
17
26
27
28
29
30
31
0
1
BCK
DINL or
DINR
31
0
30
1
24 23
5
22
6
21
7
20
8
17
16
47
15
48
14
6
5
65
49
4
3
92
2
93
1
94
0
95
0
1
BCK
DINL or
DINR
Don’t care
0
1
Don’t care
13
14
15
Don’t care
16
23
24
31
25
2
3
44
45
1
46
0 Don’t care
47
0
1
BCK
DINL or
DINR
Don’t care
Don’t care
31
3
2
1
0
Don’t care
Figure 46. EXDF Mode Timing
Rev. 0.1
2015/11
- 56 -
[AK4497]
■ Digital Filter
Six types of digital filter in PCM mode and two types of digital filter in DSD mode are available in the
AK4497 for sound color selection of music playback.
In PCM mode, digital filter can be selected by the SD, SLOW and SSLOW pins if the AK4497 is in pin
control mode, and digital filter can be selected by SD, SLOW and SSLOW bits in register control mode
(Table 27).
In register control mode, programmable digital filter can be available by setting SSLOW bit = “1” and SD
bit = “1”. In this case, Low dispersion short delay filter is available if SLOW bit = “0” and the coefficient
can be changed if SLOW bit = “1”.
Table 27. Digital Filter Setting
SSLOW
SD
SLOW
Mode
0
0
0
Sharp roll-off filter
0
0
1
Slow roll-off filter
0
1
0
Short delay sharp roll off filter
(default)
0
1
1
Short delay slow roll off filter
1
0
0
Super Slow roll Off filter
1
0
1
Super Slow roll Off filter
Low dispersion Shot delay filter /
1
1
X
(Note 41)
Programmable FIR filter
Note 41. SSLOW=1, SD=1, SLOW=0: Low dispersion Short delay filter
SSLOW=1, SD=1, SLOW=1: Programmable FIR filter (only for register control mode)
In DSD mode, the cutoff frequency of digital filter can be switched by DSDF bit. Table 28 shows the cutoff
frequency of fs = 44.1kHz. The cutoff frequency tracks the sampling frequency (fs). Do not set GS[2:0]
bits to “100” when DSDD bit = “0” and DSDF bit = “1”. Otherwise a pop noise may occur.
DSDF bit
0
1
Table 28. DSD Filter Select
Cut Off Frequency @fs=44.1kHz
DSD64fs
39kHz
76kHz
DSD128fs DSD256fs DSD512fs
78kHz
156kHz
312kHz
(default)
152kHz
304kHz
608kHz
Rev. 0.1
2015/11
- 57 -
[AK4497]
■ De-emphasis Filter (PCM)
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is
enabled or disabled by DEM1-0 pins or DEM1-0 bits. When DSD mode or EXDF mode, DEM1-0 bits are
ignored. The setting value is held even if PCM, DSD and EXDF mode is switched.
Table 29. De-emphasis Control
DEM1
DEM0
Mode
0
0
44.1kHz
0
1
OFF
(default)
1
0
48kHz
1
1
32kHz
■ Output Volume (PCM, DSD, EXDF)
The AK4497 includes channel independent digital output volumes (ATTL/R) with 256 levels at 0.5dB step
including MUTE. When changing output levels, it is executed in soft transition thus no switching noise
occurs during these transitions. It can attenuate the input data from 0dB to -127dB and mute when
assuming the output signal level is 0dB when ATTL/R[7:0] bits = FFH.
Table 30. Attenuation level of Digital Attenuator
ATTL/R[7:0]bits
Attenuation Level
(register 03-04H)
FFH
+0dB
(default)
FEH
-0.5dB
FDH
-1.0dB
:
:
:
:
02H
-126.5dB
01H
-127.0dB
00H
MUTE (-∞)
The transition time of digital output volume is set by ATS[1:0] bits (Table 31). When changing output
levels between Mode0-3, it is executed in soft transition thus no switching noise occurs during these
transitions. Register setting values will be kept even switching the PCM and DSD modes.
Mode
0
1
2
3
Table 31. Transition Time between Set Values of ATT[7:0] bits
ATS1 ATS0
ATT speed
EXDF bit=”0”,
EXDF bit=”1”
DP bit=”1”
DP bit=”0”
DP bit=”0”
0
0
4080/fs
4080*WCK Cycle
4080/(2*fs)
0
1
2040/fs
2040*WCK Cycle
2040/(2*fs)
1
0
510/fs
510*WCK Cycle
510/(2*fs)
1
1
255/fs
255*WCK Cycle
255/(2*fs)
(default)
It takes 4080/fs ([email protected]=44.1kHz) from FFH (0dB) to 00H (MUTE) in Mode 0. The attenuation level is
initialized to FFH (0dB) by setting the PDN pin = “L”.
If the volume is changed during reset period, the output volume will become a setting value after releasing
the reset. It will change to a setting value immediately if the volume is changed within 5/fs after releasing
reset.
Rev. 0.1
2015/11
- 58 -
[AK4497]
■ Gain Adjustment Function (PCM, DSD, EXDF)
The AK4497 has the gain adjustment function. The analog output amplitude can be adjusted by GC[2:0]
bits or the GAIN pin.
GC[2]
0
0
0
0
1
1
1
1
Table 32. Output Level between Set Values of GC[2:0] bits
AOUTLP/LN/RP/RN Output Level
DSD:
GC[1]
GC[0]
DSD:
PCM
Volume
Normal Path
Bypass
0
0
2.8Vpp
2.8Vpp
2.5Vpp
0
1
2.8Vpp
2.5Vpp
2.5Vpp
1
0
2.5Vpp
2.5Vpp
2.5Vpp
1
1
2.5Vpp
2.5Vpp
2.5Vpp
0
0
3.75Vpp
3.75Vpp
2.5Vpp
0
1
3.75Vpp
2.5Vpp
2.5Vpp
1
0
2.5Vpp
2.5Vpp
2.5Vpp
1
1
2.5Vpp
2.5Vpp
2.5Vpp
(default)
Table 33. Output Level between Set Values of GAIN pin
AOUTLP/LN/RP/RN
GAIN
Output Level
0
2.8Vpp
1
3.75Vpp
Note 42. DSDF bit must be set to “0” if GC[2:0] bits are set to “100” when using DSD Normal Path. Click
noise may occur if DSDF bit is set to “0”.
Rev. 0.1
2015/11
- 59 -
[AK4497]
■ Zero Detection (PCM, DSD, EXDF)
The AK4497 has a channel-independent zeros detect function. When the input data at each channel is
continuously zeros for 8192 LRCK cycles, the DZF pin of each channel outputs zero detection flag
independently. The DZFL/R pin outputs zero detection flag if the input data is continuously zeros for
16384 LRCK cycles in DSD 512fs mode (DP bit = “1” and DSDSEL[1:0] bits = “11”). Polarity of the
detection flag of the DZFL/R pin can be selected by DZFB bit. The DZFL/R pin goes “H” for zero detection
when DZFB bit = “0”, the DZFL/R pin goes “L” when DZFB bit = “1”.
When DZFB bit = “0”, the DZFL/R pin immediately returns to “L” if the input data of each channel is not
zero after going to “H”. If the RSTN bit is “0”, the DZF pins of both L and R channels go to “H”. The DZFL/R
pin returns to “L” in 4 ~ 5/fs after the input data of each channel becomes “1” when RSTN bit is set to “1”.
If DZFM bit is set to “1” while DZFB bit = “0”, the DZF pins of both L and R channels go to “H” only when
the input data for both channels are continuously zeros for 8192 LRCK cycles (16384 LRCK cycles in
DSD 512fs mode). The zero detect function can be disabled by setting the DZFE bit. In this case, DZF
pins of both channels are always “L”. The zero detect function is also disabled when Volume Bypass is
selected in DSD mode (refer to p42).
DZFE
0
Table 34. Zero Detect Select.
DZFB
RSTN
Data
0
1
0
1
0
not zero
zero detect
not zero
zero detect
1
0
1
1
Rev. 0.1
DZF-pin
L
H
H
L
H
L
H
L
2015/11
- 60 -
[AK4497]
■ L/R Channel Output Signal Select, Phase Inversion Function (PCM, DSD, EXDF)
In register control mode, input and output combination of the AK4497 can be changed by MONO bit and
SELLR bit. In addition, the output signal phase can be inverted by INVL bit and INVR bit. These functions
are available on all audio formats. In pin control mode, the phase of R channel output can be inverted by
setting the INVR pin.
Table 35. Output Select (Register Control)
MONO bit SELLR bit INVL bit
0
0
1
1
INVR bit
Lch Out
Rch Out
0
0
0
1
1
0
1
0
1
Lch In
Lch In
Lch In Invert
Lch In Invert
Rch In
Rch In Invert
Rch In
Rch In Invert
1
0
0
1
1
0
1
0
1
Rch In
Rch In
Rch In Invert
Rch In Invert
Lch In
Lch In Invert
Lch In
Lch In Invert
0
0
0
1
1
0
1
0
1
Lch In
Lch In
Lch In Invert
Lch In Invert
Lch In
Lch In Invert
Lch In
Lch In Invert
1
0
0
1
1
0
1
0
1
Rch In
Rch In
Rch In Invert
Rch In Invert
Rch In
Rch In Invert
Rch In
Rch In Invert
Table 36. Output Select (Pin Control)
INVR pin
Lch Out
Rch Out
0
1
Lch In
Lch In
Rch In
Rch In Invert
Rev. 0.1
2015/11
- 61 -
[AK4497]
■ Sound Quality (PCM, DSD, EXDF)
Sound quality of the AK4497 can be selected by SC[2:0] bits.
Table 37. Sound Quality Select Mode
SC0
Sound
0
Sound Setting 1
1
Sound Setting 2
0
Sound Setting 3
1
Sound Setting 2
SC1
0
0
1
1
SC2
0
1
Table 38. Sound Quality Select Mode
Sound
Sound Setting 4
Sound Setting 5
Rev. 0.1
(default)
(default)
2015/11
- 62 -
[AK4497]
■ DSD Signal Full Scale (FS) Detection
The AK4497 has independent full scale detection function for each channel for DSD mode.
The AK4497 detects full scale signal when the DSDL/R input data is continuously “0” (-FS) or “1” (+FS) for
2048 cycles and the detection flag for corresponding channel (DML or DMR bit) becomes “1”. DML and
DMR bits can be read out at the register address 06H.
When the AK4497 detects full scale signal while DDM bit = “1”, the analog output is muted in ATT
transition period set by ATS[2:0] bits. This transition is executed by soft transition when DSDD bit = “0”.
The analog output is muted immediately when DSDD bit = “1”. These settings (ATS[2:0] bits and DSDD
bits) are also valid when the AK4497 returns to normal status from full scale detection status.
The recovery timing from full scale detection status is controlled by DMC bit when DDM bit = “1”. When
DMC bit = “0”, the AK4497 is automatically recovered and transitions to normal operation by a normal
signal input. When DMC bit = “1”, the AK4497 transitions to normal operation by setting DMRE bit = “1”
while normal signal is input. DMRE bit automatically returns to “0” when the transition is finished. When
DDM bit = “1”, full scale signal can be detected but the AK4497 does not change to mute status. RSTN bit
must be set to “0” when changing DDM bit setting.
Table 39. DSD Mode and Device Status after Full-Scale Detection (DDM bit= “1”)
DSDD
Mode
Full Scale Detection Status
Analog Output
0
Normal Path
DSD Mute
VCML/R
1
Volume Bypass
Digital Reset
VCM/L/R
DSD Data
DSD Data
DSD Error
(DML or DMRbit)
DSD Data (FS or -FS )
(default)
DSD Data
2048fs
ATT Transition Period
ATT Transition Period
AOUT
(DSDD bit= “0”)
AOUT
(DSDD bit= “1”)
Figure 47. Analog Output Waveform in DSD FS Detection (DMC bit= “0”)
DSD Data
DSD Error
(DML or DMRbit)
DSD Data
DSD Data (FS or -FS )
DSD Data
2048fs
DMRE bit
ATT Transition Period
ATT Transition Period
AOUT
(DSDD bit= “0”)
AOUT
(DSDD bit= “1”)
Figure 48. Analog Output Waveform in DSD FS Detection (DMC bit= “1”)
Rev. 0.1
2015/11
- 63 -
[AK4497]
■ Soft Mute Operation (PCM, DSD, EXDF)
The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE
bit set to “1”, the output signal is attenuated by  during ATT_DATA  ATT transition time from the
current ATT level. When the SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is
cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA  ATT
transition time. If the soft mute is cancelled before attenuating  after starting the operation, the
attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE pin or
SMUTE bit
(1)
(1)
ATT_Level
(3)
Attenuation
-
(2) GD
(2) GD
AOUTL/R
DZFL/R pin
(4)
8192/fs
Notes:
(1) ATT_DATA  ATT transition time. For example, this time is 4080LRCK cycles (1020/fs) at
ATT_DATA=255 in PCM Normal Speed Mode.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating  after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles (16384 LRCK
cycles in DSD 512fs mode), the DZF pin for each channel goes to “H”. The DZF pin immediately
returns to “L” if input data are not zero.
Figure 49. Soft Mute Function
Rev. 0.1
2015/11
- 64 -
[AK4497]
■ LDO
When TVDD = 3.0 ~3.6V, the power for digital core circuit (DVDD) is supplied by the internal LDO by
setting the LDOE pin to “H”. Table 40 shows the DVDD pin statuses with the PDN and LDOE pins setting.
The internal LDO is powered up by setting the PDN pin from “L” to “H” (power-down release) and it starts
supping 1.8V DVDD. It takes 0.1ms (max.) to power-up the internal LDO.
PDN
LDOE
L
L
TVDD
1.7~3.6V
L
H
H
H
L
H
3.0~3.6V
1.7~3.6V
3.0~3.6V
Table 40. LDO Select Mode
DVDD
Hi-z
500ohm Pull Down
LDO OFF: Supply 1.7 ~ 1.98V to the DVDD pin externally
LDO ON: LDO outputs 1.8V.
The AK4497 has error detect function as shown in Table 41 for LDO operation (LDOE pin = “H”). The
internal LDO will be powered down and stop supplying the power to the digital core when an error is
detected. In this case, the analog signal output becomes Hi-z state. The AK4497 must be reset by setting
the PDN pin = “L” → “H” to recover from the error detection status.
No
1
2
3
Table 41. Error Detection
Error
Error Detection Condition
Internal Reference Voltage Error
Internal reference voltage does not rise.
LDO Over Voltage Detection
LDO voltage exceeds 2.2V.
LDO Over Current Detection
LDO current is 40mA or less, or 110mA or more.
■ Shutdown Switch
A shutdown switch is placed between the DVSS pin and VSS for the digital core to prevent SIDD leak of
DVDD digital power supply. The on-resistance is maximum 1Ω and the DVDD leak current will be 2uA at
the maximum.
When using LDO (LDOE pin = “H”), the shutdown switch is ON after counting by internal oscillator
following a power-down release (PDN pin “L” → “H”). It takes 2ms (max.) for the shutdown switch
power-up.
When not using LDO (LDOE pin = “L”), the shutdown switch is ON immediately after a power-down
release (PDN pin “L” → “H”). It takes 1us (max.) for the shutdown switch power-up.
■ Over Current Protection for Analog Output Pins
The AK4497 has channel independent over current detection function for analog output pins
(AOUTLP/LN and AOUTRP/RN pins). This function limits the current not to exceed 120mA when an
excessive current over 120mA (min) is detected. It is valid when the AK4497 is in power-on state.
Rev. 0.1
2015/11
- 65 -
[AK4497]
■ Power Up/Down Function
The AK4497 is powered down by setting the PDN pin to “L”. In power-down state, all circuits stop
operation and initialized, and the analog output becomes floating (Hi-z) state. The PDN pin must held “L”
for more than 150ns for a certain reset. There is a possibility of malfunctions with the “L” pulse less than
150ns. Power-down is released by setting the PDN pin to “H” from “L”. In this time IREF and LDO (if
LDOE pin = “H”) are powered up and the analog output becomes floating (Hi-z) state.
(a) Pin Control Mode (PSN pin = “H”)
All circuits will be powered up by inputting MCLK, LRCK and BICK clocks after the PDN pin = “H”. The
analog circuit starts operation just after supplying all necessary clocks (MCLK, LRCK and BICK) and the
digital circuit starts operation about 4/fs after the clock supply. Figure 50 shows system timing example of
power down/up when using the internal LDO (LDOE pin “H”). When power up the AK4497 with the LDOE
pin = “H”, 3.3V power supplies (AVDD and TVDD) should be powered up before or at the same time of 5V
power supplies (VDDL/R and VREFHL/R).
Power
(TVDD,AVDD)
Power
(VDDL/R,VREFHL/R)
PDN pin
(1)
DVDD pin
(2)
Internal PDN
Internal
State
Normal Operation (DAC Input Available)
DAC In
(Digital)
“0”data
“0”data
GD
DAC Out
(Analog)
Clock In
(4)
(5)
(3)
GD
(5)
Don’t care
(4)
Don’t care
MCLK,LRCK,BICK
External
Mute
Reset
(6)
Mute ON
Mute ON
Figure 50. Power-down/up Sequence Example (Pin Control Mode, LDOE pin= “H”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal LDO is powered up after the PDN pin = “H” when the LDOE pin= “H”. The internal circuit
will starts operation after the shutdown switch is ON (max. 2ms) following the internal oscillator
count up.
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance. The
timing example when not using LDO (LODE pin = “L”) is shown in Figure 51. When the LDOE
pin= “L”, 1.8V (DVDD), 3.3V (AVDD, TVDD) and 5V (VDDL, VDDR, VREFHL, VREFHR) power
supplies should be powered up at the same time, otherwise power up the 3.3V power supplies
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[AK4497]
(AVDD, TVDD) first, 1.8V power supply (DVDD) next and 5V power supplies (VDDL/R,
VREFHL/R) last.
Power
(TVDD,AVDD)
Power
(DVDD)
Power
(VDDL/R,VREFHL/R)
(1)
PDN pin
(2)
Internal PDN
Internal
State
Normal Operation (DAC Input Available)
DAC In
(Digital)
“0”data
“0”data
GD
(4)
DAC Out
(Analog)
Clock In
(5)
(3)
GD
(5)
Don’t care
(4)
Don’t care
MCLK,LRCK,BICK
External
Mute
Reset
(6)
Mute ON
Mute ON
Figure 51. Power-down/up Sequence Example (Pin Control Mode, LDOE pin= “L”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after supplying AVDD, TVDD, DVDD and
VDDL/R.
(2) Internal shutdown switch is powered up after the PDN pin = “H” when the LDOE pin= “L”. The
internal circuit will start operation after the shutdown switch is ON (max. 1us).
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
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[AK4497]
(b) Register Control Mode (PSN pin= “L”)
A register access becomes available after the PDN pin = “H”. The analog circuit starts operation by
supplying necessary clocks (MCLK, LRCK and BICK for PCM mode, MCLK and DCLK for DSD mode,
MCLK, BCK and WCK for EXDF mode) and the clock divider is powered up about after 4/fs. The
analog output pins output analog common voltages (VCML, VCMR) in this time. Then the AK4497
transitions to normal operation by setting RSTN bit = “1”. When power up the AK4497 with the LDOE
pin = “H”, 3.3V power supplies (AVDD and TVDD) should be powered up before or at the same time of
5V power supplies (VDDL/R and VREFHL/R).
Power
(TVDD,AVDD)
Power
(VDDL/R,VREFHL/R)
PDN pin
(1)
DVDD pin
Internal PDN
(2)
RSTN bit
(8)
Internal State
(Resister
(Clock devider)
Normal Operation
Power Off
Power Off
(9)
Internal State
(Digital Core)
Power Off
DAC In
(Digital)
(9)
“0”data
“0”data
GD
DAC Out
(Analog)
Clock In
Power Off
Normal Operation
(4)
(5)
(3)
GD
(5)
Don’t care
(4)
Don’t care
MCLK,LRCK,BICK
(7)
DZFL/R
Figure 52. Power-down/up Sequence Example (Resister Control Mode, LDOE pin= “H”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal LDO is powered up after the PDN pin = “H” when the LDOE pin= “H”. The internal circuit
will starts operation after the shutdown switch is ON (max. 2ms) following the internal oscillator
count up.
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
(7) The DZFL/R pins are “L” in power-down mode (PDN pin = “L”).
(8) The clock divider is powered up in about 4/fs after the internal PDN is released.
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[AK4497]
(9) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes
2~3/fs when changing RSTN bit to “1”. The system timing example of power up/down when not
using LDO (LODE pin = “L”) is shown in Figure 53. When the LDOE pin= “L”, 1.8V (DVDD), 3.3V
(AVDD, TVDD) and 5V (VDDL, VDDR, VREFHL, VREFHR) power supplies should be powered up
at the same time, otherwise power up the 3.3V power supplies (AVDD, TVDD) first, 1.8V power
supply (DVDD) next and 5V power supplies (VDDL/R, VREFHL/R) last.
Power
(TVDD,AVDD)
Power
(DVDD)
Power
(VDDL/R,VREFHL/R)
PDN pin
(1)
Internal PDN
RSTN bit
(8)
Internal State
(Resister
(Clock devider)
Power Off
(9)
Internal State
(Digital Core)
Power Off
DAC In
(Digital)
(9)
“0”data
GD
DAC Out
(Analog)
Clock In
Power Off
Normal Operation
“0”data
(4)
Power Off
Normal Operation
(5)
GD
(5)
Don’t care
(4)
Don’t care
MCLK,LRCK,BICK
(7)
DZFL/R
Figure 53. Power-down/up Sequence Example (Resister Control Mode, LDOE pin= “H”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal shutdown switch is powered up after the PDN pin = “H” when the LDOE pin= “L”. The
internal circuit will start operation after the shutdown switch is ON (max. 1us).
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
(7) The DZFL/R pins are “L” in power-down mode (PDN pin = “L”).
(8) The clock divider is powered up in about 4/fs after the internal PDN is released.
(9) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes
2~3/fs when changing RSTN bit to “1”.
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[AK4497]
■ Power-OFF/Reset Function
Power-off and Reset function of the AK4497 are controlled by PW bit, RSTN bit and MCLK (Table 42).
Mode
PDN
Pin
Power Down
L
H
H
H
H
MCLK Stop
Power OFF
Reset
Normal Operation
Table 42. Power Off, Reset Function
MCLK PW RSTN DIGITAL ANALOG
LDO
Supply
bit
bit
Block
Block
Register
-
No
Yes
Yes
Yes
-
-
0
1
1
-
-
-
0
1
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
OFF
ON
ON
ON
ON
Analog Output
Hi-Z
Hi-Z
Hi-Z
VCML/R
Signal Output
(1) Power ON/OFF by MCLK Clock
The AK4497 detects a clock stop and all circuits including MCLK stop detection circuit, control register
and IREF (except LDO when the LDOE pin = “H”) stop operation if MCLK is not input for 1us (min.) during
operation (PDN pin = “H”). In this case, the analog output goes floating state (Hi-Z). The AK4497 returns
to normal operation if PW bit and RSTN bit are “1” after starting to supply MCLK again. The zero detect
function is disabled when MCLK is stopped.
(4)
PDN pin
Internal
State
Normal Operation
Normal Operation
Power-off
Clock In
MCLK Stop
MCLK,
D/A In
(Digital)
(3)
(1)
(1)
(2)
D/A Out
(Analog)
Hi-z
Notes:
(1) The AK4497 detects MCLK stop and becomes power off state when MCLK edge is not detected for
1us (min.) during operation.
(2) The analog output goes to floating state (Hi-Z).
(3) Click noise can be reduced by inputting “0” data when stopping and resuming MCLK supply.
(4) Resume MCLK input to release the power-off state by MCLK. In this case, power-up sequence by
the PDN pin or power-on sequence by PW bit are not necessary.
Figure 54. Power ON/OFF by MCLK Clock
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[AK4497]
(2) Power ON/OFF by PW bit
All circuits including control register and IREF (except LDO when the LDOE pin = “H”) stop operation by
setting PW bit to “0”. In this case, control register access is available. The analog output goes to floating
state (Hi-Z). Figure 55 shows power ON/OFF sequence by PW bit.
PW bit
RSTN bit
Internal
State
DAC In
(Digital)
Normal Operation
“0” data
(1)
GD
DZFL/DZFR
GD
(3) (2)
DAC Out
(Analog)
External
MUTE
Power-off
Normal Operation
Hi-z
(3)
(1)
(4)
(5)
Mute ON
Notes:
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is floating (Hi-Z) state when PW bit = “0”.
(3) Click noise occurs at the edge of PW bit. This noise is output even if “0” data is input.
(4) The zero detect function is enable when the AK4497 is power off (PW bit= “0”). This figure shows
the seuqnece when DZFE bit= “1”, DZFB bit = “0” and DZFM bit= “0”.
(5) Mute the analog output externally if click noise (3) or Hi-z output (2) adversely affect system
performance.
Figure 55. Power ON/OFF Timing Example
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[AK4497]
(3) Reset by RSTN bit
Digital circuits except control registers and clock divider are reset by setting RSTN bit to “0”. In this case,
control register settings are held and the analog output becomes VCML/R voltage. Figure 56 shows
power ON/OFF sequence by RSTN bit.
RSTN bit
3~4/fs (5)
2~3/fs (5)
Internal
RSTN signal
Internal
State
Normal Operation
Digital Block Power-off
DAC In
(Digital)
“0” data
(1)
DAC Out
(Analog)
Normal Operation
GD
GD
(3)
(2)
(3)
(1)
2/fs(4)
DZFL/R
(6)
Notes:
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is VCOM voltage when RSTN bit = “0”.
(3) Click noise occurs at the edge of PW bit. This noise is output even if “0” data is input.
(4) This figure shows the seuqnece when DZFE bit= “1”, DZFB bit = “0” and DZFM bit= “0”. The
DZFL/R pin goes “H” on a falling edge of RSTN bit and goes “L” 2/fs after a rising edge of internal
RSTN bit.
(5) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes
2~3/fs when changing RSTN bit to “1”.
(6) Mute the analog output externally if click noise (3) adversely affect system performance.
Figure 56. Reset Timing Example
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[AK4497]
■ Synchronize Function (PCM, EXDF)
The AK4497 has a function that resets the internal counter to keep the timing of falling edge of the internal
clock CLK1 and the external clock edge in a certain range. With this synchronize function, group delays
between each device can be kept within 4/256fs when using multiple AK4497’s.
Clock synchronize function becomes valid when input data of both L and R channels are “0” for 8192
times continuously in PCM mode or EXDF mode, when both L and R channels become “0” and kept for
8192 times continuously by attenuation or when RSTN bit = “0”. In PCM mode, the internal counter is
synchronized with a rising edged of LRCK (falling edge of LRCK in I2C mode), and it is synchronized with
a rising edge of WCK in EXDF mode. In this case, the analog output has the same voltage as VCML/R.
This function is disabled by setting SYNCE bit = “0” in register control mode. Figure 57 shows a
synchronizing sequence when the input data is “0” for 8192 times continuously. Figure 58 shows a
synchronizing sequence by RSTN bit.
D/A In
(Digital)
SMUTE
(1)
(1)
ATT_Level
Attenuation
-
GD
GD
(4)
AOUT
Both DZFL/R pin
(2)
8192/fs
(2)
8192/fs
SYNC
Operation (2)
Internal Counter
Reset
Internal
Data
GD
SYNC
Operation (2)
(5)
2~3/fs (3)
Notes:
(1) Regarding ATT Transition time, refer to “■ Output Volume (PCM, DSD, EXDF)”.
(2) When both L and R channels data are “0” for 8192 times continuously, the DZFL and DZFR pins
become “H” and the synchronize function is valid.
(3) Internal data is fixed to “0” forcibly for 2 to 3/fs when internal counter is reset.
(4) A click noise may occur when the internal counter is reset. This noise is output even if a “0” data is
input. Mute the analog output externally if this click noise affects the system performance.
(5) When the internal clock and external clock are in synchronization, the internal counter is not reset
even if the synchronize function is valid.
Figure 57. Synchronizing Sequenc by Continuous “0” Data Input for 8192 Times
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[AK4497]
If RSTN bit is set to “0”, the output signal of the DZFL/DZFR pin becomes “H”. Then, the DAC is reset 3 to
4/fs after the DZFL and the DZFR pins = “H” and the analog output becomes the same voltage as
VCML/R. The synchronize function becomes valid when both of the DZFL and the DZFR pins output “H”.
RSTN bit
3~4/fs (4)
2~3/fs (4)
Internal
RSTN bit
Internal
State
Normal Operation
D/A In
(Digital)
force”0” (2)
(3)
D/A Out
(Analog)
Normal Operation
Digital Block Power-down
GD
GD (3)
(5)
(5)
2/fs(4)
Both DZFL/R pin
SYNC Operation (1)
Internal Counter
Reset
Internal
Data
2~3/fs (2)
Note:
(1) The DZFL and the DZFR pins become “H” by a falling edge of RSTN bit, and becomes “L” 2/fs after a
rising edge of internal signal of RSTN bit. The synchronize function is valid During the DZFL/R pin =
“H”.
(2) Internal data is fixed to “0” forcibly for 2 to 3/fs when the internal counter is reset.
(3) Since the analog output corresponding to digital input has group delay (GD), it is recommended to
have a no-input period longer than the group delay before writing “0” to RSTN bit.
(4) It takes 3 to 4/fs when falling to change the internal RSTN signal of the LSI after writing to RSTN bit. It
also takes 2 to 3/fs when rising to change the internal RSTN signal of the LSI. The synchronize
function becomes valid immediately when “0” is written to RSTN bit. Therefore, there is a case that the
internal counter is reset before internal RSTN signal of the LSI is changed.
(5) A click noise occurs on the rising or falling edge of the internal RSTN signal and when the internal
counter is reset. This noise is output even if a “0” data is input. Mute the analog output externally if this
click noise affects the system performance.
Figure 58. Synchronizing Sequence by RSTN Bit
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[AK4497]
■ Register Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Pins (pin control mode) or registers (register control mode) can control the functions of the AK4497. In pin
control mode, the register setting is ignored, and in register control mode the pin settings are ignored.
When the state of the PSN pin is changed, the AK4497 should be powered down by the PDN pin.
Otherwise, malfunctions may occur since previous settings are not initialized. The register control
interface is enabled by the PSN pin = “L”. Internal registers may be written to through 3-wire µP interface
pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits, C1/0),
Read/Write (1-bit; fixed to “1”, write only), Register address (MSB first, 5-bits) and Control data (MSB first,
8-bits). The data is output on a falling edge of CCLK and the data is received on a rising edge of CCLK.
The writing of data is valid when CSN “”. The clock speed of CCLK is 5MHz (max).
Setting the PDN pin to “L” resets the registers to their default values. In register control mode, the digital
block except control registers and clock divider is reset by setting RSTN bit to “0”. In this case, the register
values are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 59. Control I/F Timing
* The AK4497 does not support read commands in 3-wire serial control mode.
* When the AK4497 is in power down mode (PDN pin = “L”), writing into control registers is prohibited.
* The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more
during CSN is “L”.
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[AK4497]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4497 supports the fast-mode I2C-bus (max: 400kHz, Ver 1.0).
(2)-1. WRITE Operations
Figure 60 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 66). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bits). This bit identifies
the specific device on the bus. The hard-wired input pin (CAD1pins, CAD0 pin) sets these device address
bits (Figure 61). If the slave address matches that of the AK4497, the AK4497 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and
release the SDA line (HIGH) during the acknowledge clock pulse (Figure 67). A R/W bit value of “1”
indicates that the read operation is to be executed, and “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4497 and the format is MSB first.
(Figure 62). The data after the second byte contains control data. The format is MSB first, 8bits (Figure
63). The AK4497 generates an acknowledge after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line
while SCL is HIGH defines a STOP condition (Figure 66).
The AK4497 can perform more than one byte write operation per sequence. After receipt of the third byte
the AK4497 generates an acknowledge and awaits the next data. The master can transmit more than one
byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data
packet the internal address counter is incremented by one, and the next data is automatically taken into
the next address. If the address exceeds “15H” prior to generating a stop condition, the address counter
will “roll over” to “00H” and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 68) except for the
START and STOP conditions.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 60. Data Transfer Sequence at I2C Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(CAD0 is set by the pin)
Figure 61. The First Byte
0
0
0
A4
A3
A2
A1
A0
D1
D0
Figure 62. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 63. The Third Byte and After The Third Byte
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[AK4497]
(2)-2. READ Operation
Set the R/W bit = “1” for the READ operation of the AK4497. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds “15H” prior to generating stop condition, the address counter will “roll over” to “00H” and the data
of “00H” will be read out.
The AK4497 supports two basic read operations: Current Address Read and Random Address Read.
(2)-2-1. Current Address Read
The AK4497 has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address
with R/W bit “1”, the AK4497 generates an acknowledge, transmits 1-byte of data to the address set by
the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK4497 ceases the transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 64. Current Address Read
(2)-2-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit “1”. The AK4497 then generates an acknowledge, 1 byte of data and increments
the internal address counter by 1. If the master does not generate an acknowledge but generates a stop
condition instead, the AK4497 ceases the transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 65. Random Address Read
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[AK4497]
SDA
SCL
S
P
start condition
stop condition
Figure 66. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 67. Acknowledge (I2C Bus)
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 68. Bit Transfer (I2C Bus)
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[AK4497]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
Control4
DSD1
Control5
Sound Control
DSD2
Control 7
Control 8
Control 9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DFS read
D7
ACKS
DZFE
DP
ATT7
ATT7
INVL
DDM
0
0
0
TDM1
ATS1
0
D6
EXDF
DZFM
0
ATT6
ATT6
INVR
DML
0
0
0
TDM0
ATS0
0
D5
ECS
SD
DCKS
ATT5
ATT5
0
DMR
0
0
0
SDS1
0
0
D4
AFSD
DFS1
DCKB
ATT4
ATT4
0
DMC
0
0
0
SDS2
SDS0
0
D3
DIF2
DFS0
MONO
ATT3
ATT3
0
DMRE
GC2
HLOAD
0
0
0
0
D2
DIF1
DEM1
DZFB
ATT2
ATT2
RSTPG
0
GC1
SC2
DSDPATH
PW
0
0
D1
DIF0
DEM0
SELLR
ATT1
ATT1
DFS2
DSDD
GC0
SC1
DSDF
0
DCHAIN
0
D0
RSTN
SMUTE
SLOW
ATT0
ATT0
SSLOW
DSDSEL0
SYNCE
SC0
DSDSEL1
0
TEST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADFS2
ADFS1
ADFS0
Notes:
• In 3-wire serial control mode, the AK4497 does not support read commands.
• The AK4497 supports read command in I2C-bus control mode.
• If the address exceeds “15H”, the address counter will “roll over” to “00H” and the next write/read
address will be “00H” by automatic increment function in I2C-Bus mode.
• Data must not be written into 0 bits, TEST bit in “0BH” and registers from “16H” to “1FH”. Malfunctions
may occur if data is written to these bits.
• When the PDN pin goes to “L”, the registers are initialized to their default values.
• When RSTN bit is set to “0”, the digital block except control registers and clock divider is reset, and the
registers are not initialized to their default values.
• When the state of the PSN pin is changed, the AK4497 should be reset by the PDN pin.
(Note) The AK4497 is register compatible with the AK4490 and the AK4495.
Rev. 0.1
2015/11
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[AK4497]
(Reference) AK4490 Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
Control4
DSD1
Control5
Sound Control
DSD2
D7
ACKS
DZFE
DP
ATT7
ATT7
INVL
DDM
0
0
0
D6
EXDF
DZFM
0
ATT6
ATT6
INVR
DML
0
0
0
D5
ECS
SD
DCKS
ATT5
ATT5
0
DMR
0
0
0
D4
0
DFS1
DCKB
ATT4
ATT4
0
DMC
0
0
0
D3
DIF2
DFS0
MONO
ATT3
ATT3
0
DMRE
0
0
0
D2
DIF1
DEM1
DZFB
ATT2
ATT2
0
0
0
0
0
D1
DIF0
DEM0
SELLR
ATT1
ATT1
DFS2
DSDD
0
SC1
DSDF
D6
EXDF
DZFM
0
ATT6
ATT6
INVR
DML
0
0
0
D5
ECS
SD
DCKS
ATT5
ATT5
0
DMR
0
0
0
D4
0
DFS1
DCKB
ATT4
ATT4
0
DMC
0
0
0
D3
DIF2
DFS0
MONO
ATT3
ATT3
0
DMRE
0
0
0
D2
DIF1
DEM1
DZFB
ATT2
ATT2
0
DSDD1
0
SC2
0
D1
DIF0
DEM0
SELLR
ATT1
ATT1
DFS2
DSDD0
0
SC1
0
D0
RSTN
SMUTE
SLOW
ATT0
ATT0
DFTHR
DSDSEL0
SYNCE
SC0
DSDSEL1
(Reference) AK4495 Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
Control4
Control5
Control6
Sound Control
Reserved
D7
ACKS
DZFE
DP
ATT7
ATT7
INVL
DDM
0
0
0
Rev. 0.1
D0
RSTN
SMUTE
SLOW
ATT0
ATT0
DFTHR
DSDSEL
SYNCE
SC0
0
2015/11
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[AK4497]
■ Register Definitions
Addr Register Name
00H Control 1
R/W
Default
D7
ACKS
R/W
0
D6
EXDF
R/W
0
D5
ECS
R/W
0
D4
AFSD
R/W
0
D3
DIF2
R/W
1
D2
DIF1
R/W
1
D1
DIF0
R/W
0
D0
RSTN
R/W
0
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized. (default)
1: Normal Operation
Writing “0” to this bit resets the internal timing circuit but register values are not initialized.
DIF[2:0]: Audio Data Interface Modes (Table 23)
Initial value is “110” (Mode 6: 32-bit MSB justified)
AFSD: Sampling Frequency Auto Detect Mode Enable (PCM & EXDF mode only). (Table 5)
0: Disable: Manual or Auto Setting Mode (default)
1: Enable: Auto Detect Mode
When AFSD bit = “1”, DFS[2:0] bits are ignored.
ECS: EXDF mode clock setting (Table 22)
0: WCK=768kHz mode (default)
1: WCK=384kHz mode
EXDF: External Digital Filter I/F Mode (Register Control mode only)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM & EXDF mode only). (Table 13, Table 5)
0: Disable: Manual Setting Mode (default)
1: Enable: Auto Setting Mode
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- 81 -
[AK4497]
Addr Register Name
01H Control 2
R/W
Default
D7
DZFE
R/W
0
D6
DZFM
R/W
0
D5
SD
R/W
1
D4
DFS1
R/W
0
D3
DFS0
R/W
0
D2
DEM1
R/W
0
D1
DEM0
R/W
1
D0
SMUTE
R/W
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM[1:0]: De-emphasis Filter Control (Table 29)
Initial value is “01” (OFF).
DFS[1:0]: Sampling Speed Control. (Table 7, Table 10)
Initial value is “000” (Normal Speed). Click noise occurs when DFS1-0 bits are changed.
SD:
Minimum delay Filter Enable. (Table 27)
0: Traditional filter
1: Short delay filter (default)
DZFM:
Data Zero Detect Mode
0: Channel Separated Mode (default)
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both L and R channels go to “H” only when the
input data at both channels are continuously zeros for 8192 LRCK cycles.
DZFE:
Data Zero Detect Enable
0: Disable (default)
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both
channels are always “L”.
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2015/11
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[AK4497]
Addr Register Name
02H Control 3
R/W
Default
SLOW:
D7
DP
R/W
0
D6
0
R/W
0
D5
DCKS
R/W
0
D4
DCKB
R/W
0
D3
MONO
R/W
0
D2
DZFB
R/W
0
D1
SELLR
R/W
0
D0
SLOW
R/W
0
Slow Roll-off Filter Enable. (Table 27)
0: Slow roll-off filter disable (default)
1: Slow roll-off filter
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output L channel data, when MONO mode. (default)
L channel output L channel data, Rchannel data output Rchannel data(default)
1: All channel output R channel data, when MONO mode.
L channel output R channel data, Rchannel data output Lchannel data
DZFB: Inverting Enable of DZF. (Table 34)
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP:
DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When DP bit is changed, the AK4497 should be reset by RSTN bit.
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2015/11
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[AK4497]
Addr Register Name
03H Lch ATT
04H Rch ATT
R/W
Default
D7
ATT7
ATT7
R/W
1
D6
ATT6
ATT6
R/W
1
D5
ATT5
ATT5
R/W
1
D4
ATT4
ATT4
R/W
1
D3
ATT3
ATT3
R/W
1
D2
ATT2
ATT2
R/W
1
D1
ATT1
ATT1
R/W
1
D0
ATT0
ATT0
R/W
1
D6
INVR
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
RSTPG
R/W
0
D1
DFS2
R/W
0
D0
SSLOW
R/W
0
ATT[7:0]: Attenuation Level
255 levels 0.5dB step + mute
Data
FFH
FEH
FDH
:
:
02H
01H
00H
Addr Register Name
05H Control 4
R/W
Default
Attenuation
0dB (default)
-0.5dB
-1.0dB
:
:
-126.5dB
-127.0dB
MUTE (-)
D7
INVL
R/W
0
SSLOW: Super Slow Roll Off (Digital Filter bypass mode) Enable. (Table 27)
0: Disable (default)
1: Enable
DFS2: Sampling Speed Control. (Table 10)
RSTPG: Programmable Filter Coefficient Reset
0: Disable (default)
1: Reset Coefficient
INVR:
AOUTR Output Phase Inverting
0: Disable (default)
1: Enable
INVL:
AOUTL Output Phase Inverting
0: Disable (default)
1: Enable
Rev. 0.1
2015/11
- 84 -
[AK4497]
Addr Register Name
06H Control 4
R/W
Default
D7
DDM
R/W
0
D6
DML
R
0
D5
DMR
R
0
D4
DMC
R/W
0
D3
DMRE
R/W
0
D2
0
R/W
0
D1
DSDD
R/W
0
D0
DSDSEL0
R/W
0
DSDSEL[1:0]: DSD sampling speed control
00: 2.8224MHz
01: 5.6448MHz
10: 11.2896MHz
11: 22.5792MHz
DSDD: DSD play back path control
0: Normal Path (default)
1: Volume Bypass
DMRE: DSD Mute Release
This register is only valid when DDM bit = “1” and DMC bit = “1”. When the AK4497 mutes
DSD data by DDM and DMC bits settings, the mute is released by setting DMRE bit to “1”.
0: Hold (default)
1: Mute Release
DMC: DSD Mute Control
This register is only valid when DDM bit = “1”. It selects the mute releasing mode of when the
DSD data level becomes under full-scale after the AK4497 mutes DSD data by DDM bit
setting.
0: Auto Return (default)
1: Mute Hold
DMR/DML
This register outputs detection flag when a full scale signal is detected at DSDR/L channel.
(only in I2C mode)
DDM: DSD Data Mute
The AK4497 has an internal mute function that mutes the output when DSD audio data
becomes all “1” or all “0” for 2048 Samples (1/fs). DDM bit controls this function.
0: Disable (default)
1: Enable
Rev. 0.1
2015/11
- 85 -
[AK4497]
Addr Register Name
07H Control 5
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
GC2
R/W
0
D2
GC1
R/W
0
D1
GC0
R/W
0
D0
SYNCE
R/W
1
SYNCE: SYNC Mode Enable
0: SYNC Mode Disable
1: SYNC Mode Enable (default)
GC[2:0]: PCM, DSD mode Gain Control
GC[2]
0
0
0
0
1
1
1
1
Addr Register Name
08H Sound Control
R/W
Default
Table 32. Output Level between Set Values of GC[2:0] bit
AOUTLP/LN/RP/RN Ouput Level
DSD:
GC[1]
GC[0]
DSD:
PCM
Volume
Normal Path
Bypass
0
0
2.8Vpp
2.8Vpp
2.5Vpp
0
1
2.8Vpp
2.5Vpp
2.5Vpp
1
0
2.5Vpp
2.5Vpp
2.5Vpp
1
1
2.5Vpp
2.5Vpp
2.5Vpp
0
0
3.75Vpp
3.75Vpp
2.5Vpp
0
1
3.75Vpp
2.5Vpp
2.5Vpp
1
0
2.5Vpp
2.5Vpp
2.5Vpp
1
1
2.5Vpp
2.5Vpp
2.5Vpp
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
HLOAD
R/W
0
D2
SC2
R/W
0
(default)
D1
SC1
R/W
0
D0
SC0
R/W
0
SC[2:0]: Sound Control. (Table 37, Table 38)
HLOAD: Heavy Load Mode Enable
0: Heavy Load Mode Disable (default)
1: Heavy Load Mode Enable
Rev. 0.1
2015/11
- 86 -
[AK4497]
Addr Register Name
09H DSD2
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
DSDPATH
R/W
0
D1
DSDF
R/W
0
D0
DSDSEL1
R/W
0
DSDSEL1: DSD Sampling Speed Control.
DSDF: Cut-off frequency of DSD Filter Control
DSDPATH: DSD Data Input Pin Select
0: #16, 17, 19 (default)
1: #3, 4, 5
Pin Assignment
DP bit
EXDF bit
DSDPATH
bit
D/A Conv.
Mode
#3 pin
#4 pin
#5 pin
#16 pin
#17 pin
#19 pin
0
(default)
0
(default)
*
PCM
BICK
SDATA
LRCK
Not Use
Not Use
Not Use
1
*
DSD
Not Use
Not Use
Not Use
DCLK
DSDL
DSDR
1
0
*
1
DSD
EXDF
DCLK
BCK
DSDL
DINL
DSDR
DINR
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
0
(default)
1
*
(*: Do not care)
Rev. 0.1
2015/11
- 87 -
[AK4497]
Addr Register Name
0AH Control 7
R/W
Default
D7
TDM1
R/W
0
D6
TDM0
R/W
0
D5
SDS1
R/W
0
D4
SDS2
R/W
0
D3
0
R/W
0
D2
PW
R/W
1
D1
0
R/W
0
D0
0
R/W
0
PW: Power ON/OFF Control
0: Power Off
1: Power On (default)
SDS[2:0]: Output Data Slot Selection of Each Channel
0: Normal Operation
1: Changing Data Slot (Table 24)
Default value is “000”
TDM[1:0]: TDM Mode Select
00: Normal (default)
01: TDM128
10: TDM256
11: TDM512
Rev. 0.1
2015/11
- 88 -
[AK4497]
Addr Register Name
0BH Control 8
R/W
Default
D7
ATS1
R/W
0
D6
ATS0
R/W
0
D5
0
R/W
0
D4
SDS0
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
DCHAIN
R/W
0
D0
TEST
R/W
0
D2
0
0
R/W
0
D1
0
0
R/W
0
D0
0
0
R/W
0
TEST: “0” data must be written to Test bit. Otherwise malfunctions may occur.
DCHAIN: Daisy Chain Mode Enable
0: Daisy Chain Mode Disable (default)
1: Daisy Chain Mode Enable
SDS[2:0]: Output Data Slot Selection of Each Channel
0: Normal Operation
1: Changing Data Slot (Table 24)
Default value is “000”.
ATS[1:0]: Transition Time between Set Values of ATT[7:0] bits (Table 31)
Default value is “00”.
Addr Register Name
0CH Reserved
0DH Reserved
R/W
Default
D7
0
0
R/W
0
D6
0
0
R/W
0
D5
0
0
R/W
0
D4
0
0
R/W
0
D3
0
0
R/W
0
0CH: Reserved
0DH: Reserved
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[AK4497]
Addr
0EH
0FH
10H
11H
Register Name
Reserved
Reserved
Reserved
Reserved
R/W
Default
D7
0
0
0
0
R/W
0
D6
0
0
0
0
R/W
0
D5
0
0
0
0
R/W
0
D4
0
0
0
0
R/W
0
D3
0
0
0
0
R/W
0
D2
0
0
0
0
R/W
0
D1
0
0
0
0
R/W
0
D0
0
0
0
0
R/W
0
D7
0
0
0
R
0
D6
0
0
0
R
0
D5
0
0
0
R
0
D4
0
0
0
R
0
D3
0
0
0
R
0
D2
0
0
0
R
0
D1
0
0
0
R
0
D0
0
0
0
R
0
0EH: Reserved
0FH: Reserved
10H: Reserved
11H: Reserved
Addr
12H
13H
14H
Register Name
Reserved
Reserved
Reserved
R/W
Default
12H: Reserved
13H: Reserved
14H: Reserved
Addr Register Name
15H
ADFS read
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
ADFS2
R
0
D1
ADFS1
R
0
D0
ADFS0
R
0
ADFS[2:0]: Mode Detection Result in FS Auto Detect Mode
ADFS2
0
0
0
0
1
1
1
1
ADFS1
0
0
1
1
0
0
1
1
ADFS0
0
1
0
1
0
1
0
1
Rev. 0.1
Mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Quad Speed Mode
Oct Speed Mode
Hex Speed Mode
Oct Speed Mode
Hex Speed Mode
2015/11
- 90 -
[AK4497]
10. Recommended External Circuits
Digital 3.3V Digital 1.8V
AVDD 3.3V
AOUTLN 49
VCML 51
VREFLL 53
VREFLL 54
EXTR 58
AVDD 59
AVSS 60
MCLK 61
DVDD 62
Lch
LPF
0.1u 10u AOUTLP 47
+
VDDL 46
4
SDATA/DINL
VDDL 45
5
LRCK/DINR
VDDL 44
6
SSLOW/WCK
7
TDMO
8
SMUTE/CSN
9
SD/CCLK/SCL
Lch
Mute
Lch Out
AOUTLP 48
AK4497
+
Electrolytic Capacitor
0.1u
VSSL 43
+
10u
Ceramic Capacitor
Resistor
VSSL 42
VSSL 41
VSSR 40
N
N
VSSR 39
11
DIF0/DZFL
12
DIF1/DZFR
13
DIF2/CAD0
14
PSN
15
HLOAD/I2C
AOUTRP 34
16
DEM0/DSDL
AOUTRP 33
VSSR 38
VDDR 37
0.1u
+
10u
VDDR 36
0.1u
+ 470u
32 AOUTRN
31 AOUTRN
30 VCMR
29 VREFLR
28 VREFLR
27 VREFLR
26 VREFHR
25 VREFHR
24 VREFHR
23 TESTE
22 INVR
21 DCHAIN
VDDR 35
GAIN
17 /DSDR
ACKS
18 /CAD1
19 TDM0/
DCLK
20 TDM1
Controller
AOUTLN 50
BICK/BCK
VREFHL 56
3
VREFHL 57
LDOE
PDN
DVSS 63
TVDD 64
1
2
10u
+
0.1u
10 SLOW/CDTI/SDA
Micro-
470u
+
0.1u
0.1u
DSP
33k
VREFLL 52
10u
+
+ 1u
VREFHL 55
10u +
Analog 5.0V
+
10u
Rch
LPF
Rch
Mute
Notes:
- Chip Address = “00”. BICK = 64fs, LRCK = fs
- Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately from the point
with low impedance of regulator etc.
- AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. (Analog
ground should has low impedance as a solid pattern. THD+N characteristics will degrade if there
are impedances between each VSS.)
- THD+N characteristics will degrade by high frequency noise of MCLK. Connect a 51 Ω damping
resistor to the MCLK pin.
- When AOUT drives a capacitive load, some resistance should be connected in series between
AOUT and the capacitive load.
- All input pins except pull-down/pull-up pins should not be allowed to float.
Figure 69. Typical Connection Diagram
(AVDD=TVDD=3.3V, VDDL/R=5.0V, LDOE= “L”, Register Control Mode)
Rev. 0.1
2015/11
- 91 -
Rch Out
[AK4497]
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, TVDD, DVDD,
VDDL and VDDR. AVDD and VDDL/R are supplied from analog supply in system, and TVDD and DVDD
are supplied from digital supply in system. Power lines of VDDL/R should be distributed separately from
the point with low impedance of regulator etc. When not using LDO (LDOE pin = “L”), AVDD and TVDD
should be powered up before or at the same time of DVDD. When using LDO (LDOE pin = “H”), power up
sequence between AVDD/TVDD and VDDL/R are not critical. AVSS, DVSS, VSSL and VSSR must be
connected to the same analog ground plane. Decoupling capacitors for high frequency should be
placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the full scale of the analog output range.
The VREFHL/R pin is normally connected to VDD, and the VREFLL/R pin is normally connected to VSS.
VREFHL/R and VREFLL/R should be connected with a 0.1µF ceramic capacitor and a 2200uF electrolytic
capacitor as near as possible to the pin to eliminate the effects of high frequency noise.
The VREFH and VREFL pins should be treated to not have noises from other supply pins. If the analog
characteristics cannot satisfy the specification by this noise, connect the VREFH to analog 5.0V via a 10 Ω
resistor and connect the VREFL pin to the analog ground via a 10 Ω resistor. (A low-pass filter of fc=500Hz
will be composed by a 2200uF capacitor and a 10Ω resistor. This low-pass filter removes signal frequency
noise from other power supply pins.)
VCML/R is a common voltage of this chip. No load current may be drawn from the VCML/R pin. All signals,
especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid
unwanted noise coupling into the AK4497.
3. Analog Outputs
The analog outputs are full differential outputs. The differential outputs are summed externally, VAOUT =
(AOUT+)  (AOUT) between AOUT+ and AOUT. If the summing gain is 1, the output range of the setting
the GAIN pin = “L” or GC[2] bit = “0” is 2.8Vpp (typ, VREFHL/R  VREFLL/R = 5V) centered around VCML
and VCMR voltages. In this case, the output range after summing will be 5.6V (typ.). The output range of
the setting the GAIN pin = “H” or GC[2] bit = “1” is 3.75Vpp (typ.) centered around VCML and VCMR
voltages. In this case, the output range after summing will be 7.5Vpp (typ.). The bias voltage of the external
summing circuit is supplied externally.
The input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFFFH
(@32bit) and a negative full scale for 80000000H (@32bit). The ideal VAOUT is 0V for 00000000H (@32bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond
the audio passband. Figure 70 and Figure 71 show examples of external LPF circuit summing the
differential outputs by a single op-amp. Figure 72 shows an example of differential output circuit and
external LPF circuit with two op-amps. Figure 73 shows an example of external LPF circuit with two
op-amps when MONO bit = “1”. A resistor that has 0.1% or less absolute error must be used for external
LPFs.
AK4497
AOUT-
300
300
30
43n
6.8n
+Vop
2
AOUT+
100
10
7
6
Analog
Out
3
4
130n
100
20n
-Vop
OPA1611
Figure 70. External LPF Circuit Example 1 (fc = 98kHz(typ), Q=0.667(typ))
Rev. 0.1
2015/11
- 92 -
[AK4497]
Table 43. Frequency Response of External LPF Circuit Example 1
Gain(1kHz,typ)
0 dB
20kHz
-0.07 dB
Frequency
Response
40kHz
-0.32 dB
(ref:1kHz,typ)
80kHz
-2.13 dB
AK4497
215
AOUT-
590
33
39.2n
3.09n
+Vop
7
2
33.2
AOUT+
5.1
6
Analog
Out
3
4
255n
90.9
20n
-Vop
OPA1611
Figure 71. External LPF Circuit Example 2 (fc = 104kHz(typ), Q=0.693(typ))
Table 44. Frequency Response of External LPF Circuit Example 2
Gain(1kHz,typ)
+8.78 dB
20kHz
-0.02 dB
Frequency
Response
40kHz
-0.15 dB
(ref:1kHz,typ)
80kHz
-1.46 dB
+15
27n
+
AK4497
22
8
3
2 +
* 4
+
22
56n
10k
AOUT-
100u
-15
10u
0.1u
1
OPA1612
+
10u
0.1u
Lch
200
400
27n
+
100u
8
5
+
6 4
+
22
56n
10k
AOUT+
22
10u
0.1u
7
OPA1612
LME49710
10u
200
400
+
0.1u
Figure 72. External LPF Circuit Example 3 (fc = 186kHz(typ), Q=0.67(typ))
Table 45. Frequency Response of External LPF Circuit Example 3
Gain(1kHz,typ)
+9.54 dB
20kHz
-0.01 dB
Frequency
Response
40kHz
-0.06 dB
(ref:1kHz,typ)
80kHz
-0.32 dB
Rev. 0.1
2015/11
- 93 -
[AK4497]
+15
27n
+
AK4497
100u
22
8
3
2 +
* 4
+
44
56n
10k
AOUTLP
0.1u
1
OPA1612
10k
44
27n
+
100u
22
8
5
+
6 4
+
44
56n
10k
AOUTRP
7
+
10u
0.1u
200
400
10u
0.1u
OPA1612
LME49710
100u
+
44
10k
AOUTRN
10u
200
+
AOUTLN
+
0.1u
400
100u
-15
10u
Figure 73. External LPF Circuit Example for mono mode (fc = 186kHz(typ), Q=0.67(typ))
Rev. 0.1
2015/11
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[AK4497]
11. Package
■Outline Dimensions
(HTQFP10×10-64)
C
12.0 ± 0.20
64
49
1
12.0 ± 0.20
A
16
10.0 ± 0.20
48
33
32
17
0.50
0.22 ± 0.05
0.10
M S A C
0.09 ~ 0.2
1.00 ± 0.05
0.10
S
0.60 ± 0.15
(5.95)
0.05 ~ 0.15
S
1.2 MAX
10.0 ± 0.20
(5.95)
Rev. 0.1
2015/11
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[AK4497]
■ Material & Lead Finish
Package molding compound: Epoxy, Halogen (bromine and chlorine) free
Lead frame material:
EFTEC64
Lead frame surface treatment: Solder (Pb free) plate
■ Marking
AK4497EQ
XXXXXXX
AKM
64
1
1) Pin #1 indication
2) AKM Logo
3) Date Code: XXXXXXX (7 digits)
4) Marking Code: AK4497EQ
5) Audio 4 pro Logo
Rev. 0.1
2015/11
- 96 -
[AK4497]
12. Ordering Guide
■ Ordering Guide
AK4497
AKD4497
40  +85C (Assuming the exposed pad is connected to the printing board)
64-pin TQFP (0.5mm pitch)
Evaluation Board for AK4497
Rev. 0.1
2015/11
- 97 -
[AK4497]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants
any license to any intellectual property rights or any other rights of AKM or any third party with
respect to the information in this document. You are fully responsible for use of such information
contained in this document in your product design or applications. AKM ASSUMES NO
LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE
USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace
industry, medical equipment, equipment used for automobiles, trains, ships and other
transportation, traffic signaling equipment, equipment used to control combustions or explosions,
safety devices, elevators and escalators, devices related to electric power, and equipment used
in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM
in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and
regulations. The Products and related technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable domestic
or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
and regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a
result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
Rev. 0.1
2015/11
- 98 -
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