AK4552VT

ASAHI KASEI
[AKD4552-A]
AKD4552-A
Evaluation board Rev.0 for AK4552
GENERAL DESCRIPTION
AKD4552-A is an evaluation board for the digital audio 24bit A/D and D/A converter, AK4552. The
AKD4552-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D
→ D/A). The A/D section can be evaluated by interfacing with AKM’s DAC evaluation boards directly. The
AKD4552-A has the interface with AKM’s ADC evaluation boards. Therefore, it’s easy to evaluate the D/A
section. The AKD4552-A also has the digital audio interface and can achieve the interface with digital
audio systems via opt-connector.
„ Ordering guide
AKD4552-A
---
Evaluation board for AK4552
FUNCTION
• DIT/DIR with optical input/output
• BNC connector for an external clock input
2.4 ~ 4.0V
GND
LIN
RIN
AK4112B
(DIR)
Opt In
AK4103A
(DIT)
Opt Out
AK4552
LOUT
ROUT
A/D, D/A Data
Clock
Generator
10pin Header
Figure 1. AKD4552-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM080600>
2005/10
-1-
ASAHI KASEI
[AKD4552-A]
„ Analog Input Circuit
External analog signal fed through the BNC connector is terminated by a resistor of 560 ohms. The resistor value should
be properly selected in order to meet the output impedance of the signal source.
J4(J2)
LIN(RIN)
C4(C2)
10u
+
LIN(RIN)pin
R6(R4)
560
Figure 2. Input buffer circuit on board
* AKM assumes no responsibility for the trouble when using the circuit examples.
„ Analog Output Circuit
The AK4552 includes a combination of switched-capacitor filter (SCF) and continuous-time filter (CTF), so any external
filters are not required.
„ Operation sequence
1) Set up the power supply lines.
[VA]
(orange)
= 2.4 ∼ 4.0V : for VA of AK4552 (typ. 3.0V)
[D2V]
(orange)
= 2.4 ∼ 4.0V : for D2V of 74LVC541 (typ. 3.0V)
[VCC]
(red)
= 3.6 ∼ 5.0V : for logic
[AGND] (black)
= 0V
: for analog ground (including VSS of AK4552)
[DGND] (black)
= 0V
: for logic ground
Each supply line should be distributed from the power supply unit.
D2V and VA must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4552 should be reset once bringing SW1 (PDN) “L” upon power-up.
„ Evaluation mode
Applicable Evaluation Mode
(1) Evaluation of A/D using DIT (Optical Link)
(2) Evaluation of D/A using DIR (Optical Link)
(3) Evaluation of loopback mode (default)
(4) Evaluation of D/A using A/D converted data
(5) Evaluation of A/D using D/A converted data
(6) All interface signals including master clock are fed externally.
<KM080600>
2005/10
-2-
ASAHI KASEI
[AKD4552-A]
(1) Evaluation of A/D using DIT (Optical Link)
PORT2 (DIT) and X2 (X’tal) is used. DIT generates audio bi-phase signal from received data and which is
output through optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation boards
on the digital-amplifier which equips DIR input. Nothing should be connected to PORT1 (DIR), PORT3
(ROM). In case of using external clock through a BNC connector (J5), select EXT on JP11 (CLK) and short JP8
(XTE) and open JP13 (EXT). AK4112B should be powered down.
JP3
JP4
JP6
JP8
LRCK
BCLK
SDTI
XTE
ADC
DIR
ADC
DIR
ADC
JP13
EXT
DIR
• Clock example
1-1) Normal speed of ADC (MCLK=256fs)
Master clock frequency example of X2 : X2 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2
JP7
JP9
JP10
JP11
JP12
MCKO
SPEED
MCLK
BCFS
CLK
LRFS
X4
M1
X2
M2
DIR
X1
X2
X1
X4
EXT
X1
X1
X4
XTL
1-2) Normal speed of ADC (MCLK=512fs)
Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
JP7
JP9
JP10
JP11
JP12
MCKO
SPEED
MCLK
BCFS
CLK
LRFS
X4
M1
X2
M2
DIR
X1
X2
X1
X4
EXT
X1
X1
X4
XTL
1-3) Double speed of ADC (MCLK=256fs)
Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
JP7
JP9
JP10
JP11
JP12
MCKO
SPEED
MCLK
BCFS
CLK
LRFS
X4
M1
M2
X2
DIR
X1
X2
X1
X1
X4
EXT
X1
X4
XTL
<KM080600>
2005/10
-3-
ASAHI KASEI
[AKD4552-A]
(2) Evaluation of D/A using DIR (Optical Link)
PORT1 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through
optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to
PORT3 (ROM). Set up “H” (AK4112B : PLL mode) for SW2-5 (CM0).
JP3
JP4
JP6
JP8
LRCK
BCLK
SDTI
XTE
ADC
DIR
ADC
DIR
ADC
JP13
EXT
DIR
• Clock example
2-1) Normal speed of DAC (MCLK=256fs)
Input fs example for PORT1 : fs = 32kHz, 44.1kHz, 48kHz
JP11
JP12
CLK
LRFS
X4
M1
X2
M2
SW2
MODE
DIR
X1
X2
X1
X4
EXT
X1
X1
X4
1 2
H
3
4
5
L
L
L
L
DEM0
XTL
CM0
JP10
BCFS
OCKS1
JP9
MCLK
OCKS0
JP7
SPEED
DEM1
JP2
MCKO
2-2) Normal speed of DAC (MCLK=512fs)
Input fs example for PORT1 : fs = 32kHz, 44.1kHz, 48kHz
JP11
JP12
CLK
LRFS
X4
M1
X2
M2
SW2
MODE
DIR
X1
X2
X1
X4
EXT
X1
X1
X4
1 2
H
3
L
L
DEM0
XTL
4
5
H
L
CM0
JP10
BCFS
OCKS1
JP9
MCLK
OCKS0
JP7
SPEED
DEM1
JP2
MCKO
2-3) Double speed of DAC (MCLK=256fs)
Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz
JP11
JP12
MCKO
SPEED
MCLK
BCFS
CLK
LRFS
X4
M1
M2
X2
SW2
MODE
DIR
X1
X2
X1
X4
X1
EXT
X1
X4
1 2
H
3
4
5
L
L
L
L
DEM0
XTL
<KM080600>
CM0
JP10
OCKS1
JP9
OCKS0
JP7
DEM1
JP2
2005/10
-4-
ASAHI KASEI
[AKD4552-A]
2-4) 1/2 decimation of DAC (MCLK=128fs)
Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz
JP9
JP10
JP11
JP12
MCKO
SPEED
MCLK
BCFS
CLK
LRFS
X2
M2
X1
X2
X1
X4
EXT
X1
X1
X4
1 2
H
3
L
DEM0
XTL
4
5
L
L
H
OCKS0
M1
DIR
DEM1
X4
SW2
MODE
CM0
JP7
OCKS1
JP2
(3) Evaluation of loopback mode (default)
Using U4 (AK4112B) and X1 (X’tal). Nothing should be connected to PORT1 (DIR), PORT3 (ROM). Set up
“H” (AK4112B : X’tal mode) for SW2-5 (CM0).
JP3
JP4
JP6
JP8
LRCK
BCLK
SDTI
XTE
ADC
DIR
ADC
DIR
ADC
JP13
EXT
DIR
• Clock example
3-1) Normal speed (MCLK=256fs)
Master clock frequency example of X1 : X1 = 8.192MHz, 11.2896MHz, 12.288MHz
JP11
JP12
CLK
LRFS
X4
M1
X2
M2
SW2
MODE
DIR
X1
X2
X1
X4
EXT
X1
X1
X4
1 2
H
3
L
L
DEM0
XTL
4
5
H
L
CM0
JP10
BCFS
OCKS1
JP9
MCLK
OCKS0
JP7
SPEED
DEM1
JP2
MCKO
3-2) Normal speed (MCLK=512fs)
Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
JP11
JP12
CLK
LRFS
X4
M1
M2
X2
SW2
MODE
DIR
X1
X2
X1
X4
X1
EXT
X1
X4
1 2
H
3
L
L
DEM0
XTL
<KM080600>
4
5
H H
CM0
JP10
BCFS
OCKS1
JP9
MCLK
OCKS0
JP7
SPEED
DEM1
JP2
MCKO
2005/10
-5-
ASAHI KASEI
[AKD4552-A]
3-3) Double speed (MCLK=256fs)
Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
JP11
JP12
MCKO
SPEED
MCLK
BCFS
CLK
LRFS
X4
M1
X2
M2
SW2
MODE
DIR
X1
X2
X1
X4
EXT
X1
X1
X4
1 2
H
3
L
L
DEM0
XTL
4
5
H
L
CM0
JP10
OCKS1
JP9
OCKS0
JP7
DEM1
JP2
(4) Evaluation of D/A using A/D converted data
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR). In case of
using external clock through a BNC connector (J5), select EXT on JP11 (CLK) and short JP8 (XTE) and open
JP13 (EXT). This mode corresponds to normal speed only.
JP3
JP4
JP6
JP8
LRCK
BCLK
SDTI
XTE
ADC
DIR
ADC
DIR
ADC
JP13
EXT
DIR
• Clock example
4-1) Normal speed of DAC (MCLK=256fs)
Master clock frequency example of X2 : X2 = 8.192MHz, 11.2896MHz, 12.288MHz
JP11
JP12
CLK
LRFS
X4
M1
X2
M2
SW2
MODE
DIR
X1
X2
X1
X4
EXT
X1
X1
X4
1 2
H
3
4
5
L
L
L
L
DEM0
XTL
CM0
JP10
BCFS
OCKS1
JP9
MCLK
OCKS0
JP7
SPEED
DEM1
JP2
MCKO
4-2) Normal speed of DAC (MCLK=512fs)
Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP11
JP12
CLK
LRFS
X4
M1
M2
X2
SW2
MODE
DIR
X1
X2
X1
X4
X1
EXT
X1
X4
1 2
H
3
4
5
L
L
L
L
DEM0
XTL
<KM080600>
CM0
JP10
BCFS
OCKS1
JP9
MCLK
OCKS0
JP7
SPEED
DEM1
JP2
MCKO
2005/10
-6-
ASAHI KASEI
[AKD4552-A]
(5) Evaluation of A/D using D/A converted data
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s D/A evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR).
JP3
JP4
JP6
JP8
LRCK
BCLK
SDTI
XTE
ADC
DIR
ADC
DIR
ADC
JP13
EXT
DIR
• Clock example
5-1) Normal speed of ADC (MCLK=256fs)
Do not use X2.
JP2
JP7
JP9
JP10
JP11
JP12
MCKO
SPEED
MCLK
BCFS
CLK
LRFS
X4
M1
X2
M2
DIR
X1
X2
X1
X4
EXT
X1
X1
X4
XTL
5-2) Normal speed of ADC (MCLK=512fs)
Do not use X2.
JP2
JP7
JP9
JP10
JP11
JP12
MCKO
SPEED
MCLK
BCFS
CLK
LRFS
X4
M1
M2
X2
DIR
X1
X2
X1
X1
X4
EXT
X1
X4
XTL
<KM080600>
2005/10
-7-
ASAHI KASEI
[AKD4552-A]
(6) All interface signals including master clock are fed externally.
Under the following set-up, all external signals needed for the AK4552 to operate could be fed through PORT3
(ROM). In case of interfacing external sources to D/A converter, JP6 (SDTI) should be open. And in case of
using A/D data to externally, JP6 (SDTI) is set ADC side. When JP6 (SDTI) is open, the A/D data can be output
from the SDTO pin of PORT3 (ROM) at the same time if JP5 (SDTO) is short.
JP3
JP4
JP6
JP8
LRCK
BCLK
SDTI
XTE
ADC
DIR
ADC
DIR
ADC
JP13
EXT
DIR
• Clock example
6-1) Normal speed, Double speed, 4 times speed of ADC and DAC
Do not use X2.
JP11
JP12
CLK
LRFS
X4
M1
X2
M2
SW2
MODE
DIR
X1
X2
X1
X4
X1
EXT
X1
X4
1 2
H
3
4
5
L
L
L
L
DEM0
XTL
CM0
JP10
BCFS
OCKS1
JP9
MCLK
OCKS0
JP7
SPEED
DEM1
JP2
MCKO
„ DIP switch set up
Upper-side is “H” and lower-side is “L”.
[SW2] (MODE) : Sets the de-emphasis filter of AK4552 and clock mode of U4 (AK4112B).
No.
1
2
3
4
5
Pin Name
Mode
DEM0
See Table 2.
DEM1
OCKS0
See Table 3.
OCKS1
CM0
L : X’tal mode, H : PLL mode
Table 1. Set up SW2
DEM1
DEM0
Mode
L
L
44.1kHz
default
L
H
OFF
H
L
48kHz
H
H
32kHz
Table 2. Set up of DEM0/1 of AK4552
No.
0
1
OCKS1
L
H
OCKS0
MCKO1
MCKO2
L
256fs
256fs
L
512fs
128fs
Table 3. Set up of OCKS0/1 for AK4112B
<KM080600>
fs (kHz)
32, 44.1, 48, 96
32, 44.1, 48
2005/10
-8-
ASAHI KASEI
[AKD4552-A]
„ Other jumper pins set up
[JP1] (GND): Analog ground and digital ground
open: separated
short: common (The connector “DGND” can be open.) <default>
[JP5] (SDTO): SDTO of AK4552
Always open. It is possible to short for evaluation mode 6.
„ The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Resets the AK4552. Keep “H” during normal operation.
[SW3] (DIR): Resets the AK4112B. Keep “H” during normal operation.
[SW4] (DIT): Resets the AK4103A. Keep “H” during normal operation.
„ Indication for LED
[LED1] (ERF): Monitor ERF pin of the AK4112B. LED turns on when some error has occurred to AK4112B.
<KM080600>
2005/10
-9-
ASAHI KASEI
[AKD4552-A]
MEASUREMENT RESULTS
[Measurement condition]
• Measurement unit
• MCLK
• BCLK
• fs
• Bit
• Band width
• Measurement Filter
• Power Supply
• Interface
• Temperature
: Audio Precision, System two Cascade
: 256fs
: 64fs
: 32kHz, 44.1kHz, 48kHz, 96kHz
: 24bit
: ADC : 10Hz ∼ 20kHz (Normal Speed), 10Hz ∼ 48kHz (Double Speed)
: DAC : 10Hz ∼ 20kHz (Normal Speed), 10Hz ∼ 40kHz (Double Speed)
: VA = VD = 3.0V
: DIT/DIR
: Room
Parameter
ADC Analog Input Characteristics
fs=32kHz
S/(N+D) (-0.5dB Input)
fs=44.1kHz
fs=48kHz
fs=96kHz
fs=32kHz, A-weighted
D-Range (-60dB Input)
fs=44.1kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
S/N
fs=32kHz, A-weighted
fs=44.1kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
Interchannel Isolation
DAC Analog Output Characteristics
fs=32kHz
S/(N+D) (0dB Output)
fs=44.1kHz
fs=48kHz
fs=96kHz
D-Range (-60dB Output)
fs=32kHz, A-weighted
fs=44.1kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
fs=32kHz, A-weighted
S/N
fs=44.1kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
Interchannel Isolation
<KM080600>
Result (Lch / Rch)
Unit
87.8 / 87.9
88.5 / 88.5
89.2 / 89.2
89.5 / 89.4
96.1 / 96.1
97.1 / 97.1
97.5 / 97.5
93.3 / 93.3
96.1 / 96.1
97.1 / 97.1
97.6 / 97.6
93.3 / 93.3
118.5 / 118.7
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
88.3 / 89.2
88.1 / 88.8
88.3 / 89.2
85.6 / 86.3
100.0 / 100.0
100.4 / 100.4
100.6 / 100.6
95.6 / 95.6
100.9 / 100.9
101.6 / 101.6
101.6 / 101.6
96.0 / 96.0
116.2 / 116.4
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
2005/10
- 10 -
ASAHI KASEI
[AKD4552-A]
1. ADC (Normal Speed)
AKM
AK4552 AD C THD+N vs. Input Level
VA=VD =3.0V, fs=44.1kHz, fin=1kHz
-80
-82
-84
-86
-88
d
B
F
S
-90
-92
-94
-96
-98
-100
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dB r
Figure 1. THD+N vs. Input Level
AKM
AK4552 AD C THD+N vs. Input Frequency
VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr
-80
-82
-84
-86
-88
d
B
F
S
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 2. THD+N vs. Input Frequency
<KM080600>
2005/10
- 11 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 ADC Linearity
VA=VD =3.0V, fs=44.1kHz, fin=1kHz
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB r
Figure 3. Linearity
AKM
AK4552 ADC Frequency Response
VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr
+0
-0.2
-0.4
-0.6
-0.8
d
B
F
S
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 4. Frequency Response
<KM080600>
2005/10
- 12 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 AD C C rosstalk
VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr
-80
-85
-90
-95
-100
-105
d
B
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 5. Crosstalk
AKM
AK4552 ADC FFT Plot
VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 6. FFT Plot
<KM080600>
2005/10
- 13 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 ADC FFT Plot
VA=VD=3.0V, fs=44.1kHz, Input=-60dBr, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 7. FFT Plot
AKM
AK4552 ADC FFT Plot
VA=VD=3.0V, fs=44.1kHz, fin=None
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 8. FFT Plot
<KM080600>
2005/10
- 14 -
ASAHI KASEI
[AKD4552-A]
2. DAC (Normal Speed)
AKM
AK4552 D AC THD+N vs. Input Level
VA=VD =3.0V, fs=44.1kHz, fin=1kHz
-60
-65
-70
-75
-80
d
B
r
A
-85
-90
-95
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB FS
Figure 1. THD+N vs. Input Level
AKM
AK4552 D AC THD+N vs. Input Frequency
VA=VD =3.0V, fs=44.1kHz, Input=0dBFS
-60
-65
-70
-75
-80
d
B
r
A
-85
-90
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 2. THD+N vs. Input Frequency
<KM080600>
2005/10
- 15 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 D AC Linearity
VA=VD=3.0V, fs=44.1kHz, fin=1kHz
+0
-10
-20
-30
-40
d
B
r
A
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB FS
Figure 3. Linearity
AKM
AK4552 DAC Frequency Response
VA=VD =3.0V, fs=44.1kHz, Input=0dBFS
+0.5
+0.4
+0.3
+0.2
+0.1
d
B
r
+0
A
-0.1
-0.2
-0.3
-0.4
-0.5
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 4. Frequency Response
<KM080600>
2005/10
- 16 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 D AC C rosstalk
VA=VD =3.0V, fs=44.1kHz, Input=0dBFS
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 5. Crosstalk
AKM
AK4552 DAC FFT Plot
VA=VD=3.0V, fs=44.1kHz, Input=0dBFS, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 6. FFT Plot
<KM080600>
2005/10
- 17 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 DAC FFT Plot
VA=VD=3.0V, fs=44.1kHz, Input=-60dBFS, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 7. FFT Plot
AKM
AK4552 DAC FFT Plot
VA=VD=3.0V, fs=44.1kHz, fin=None
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 8. FFT Plot
<KM080600>
2005/10
- 18 -
ASAHI KASEI
[AKD4552-A]
3. ADC (Double Speed)
AKM
AK4552 AD C THD+N vs. Input Level
VA=VD=3.0V, fs=96kHz, fin=1kHz
-80
-82
-84
-86
-88
d
B
F
S
-90
-92
-94
-96
-98
-100
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dB r
Figure 1. THD+N vs. Input Level
AKM
AK4552 AD C THD+N vs. Input Frequency
VA=VD =3.0V, fs=96kHz, Input=-0.5dBr
-80
-82
-84
-86
-88
d
B
F
S
-90
-92
-94
-96
-98
-100
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 2. THD+N vs. Input Frequency
<KM080600>
2005/10
- 19 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 ADC Linearity
VA=VD=3.0V, fs=96kHz, fin=1kHz
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB r
Figure 3. Linearity
AKM
AK4552 ADC Frequency Response
VA=VD =3.0V, fs=96kHz, Input=-0.5dBr
+0
-0.2
-0.4
-0.6
-0.8
d
B
F
S
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 4. Frequency Response
<KM080600>
2005/10
- 20 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 AD C C rosstalk
VA=VD =3.0V, fs=96kHz, Input=-0.5dBr
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
d
B
-110
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
20
50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 5. Crosstalk
AKM
AK4552 ADC FFT Plot
VA=VD =3.0V, fs=96kHz, Input=-0.5dBr, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 6. FFT Plot
<KM080600>
2005/10
- 21 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 ADC FFT Plot
VA=VD=3.0V, fs=96kHz, Input=-60dBr, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
Figure 7. FFT Plot
AKM
AK4552 ADC FFT Plot
VA=VD=3.0V, fs=96kHz, fin=None
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 8. FFT Plot
<KM080600>
2005/10
- 22 -
ASAHI KASEI
[AKD4552-A]
4. DAC (Double Speed)
AKM
AK4552 D AC THD+N vs. Input Level
VA=VD=3.0V, fs=96kHz, fin=1kHz
-60
-65
-70
-75
-80
d
B
r
A
-85
-90
-95
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB FS
Figure 1. THD+N vs. Input Level
AKM
AK4552 D AC THD+N vs. Input Frequency
VA=VD=3.0V, fs=96kHz, Input=0dBFS
-60
-65
-70
-75
-80
d
B
r
A
-85
-90
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 2. THD+N vs. Input Frequency
<KM080600>
2005/10
- 23 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 DAC Linearity
VA=VD=3.0V, fs=96kHz, fin=1kHz
+0
-10
-20
-30
-40
d
B
r
A
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dB FS
Figure 3. Linearity
AKM
AK4552 DAC Frequency Response
VA=VD=3.0V, fs=96kHz, Input=0dBFS
+0.5
+0.4
+0.3
+0.2
+0.1
d
B
r
+0
A
-0.1
-0.2
-0.3
-0.4
-0.5
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
20k
22.5k
25k
27.5k
30k
32.5k
35k
37.5k
40k
Hz
Figure 4. Frequency Response
<KM080600>
2005/10
- 24 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 D AC C rosstalk
VA=VD=3.0V, fs=96kHz, Input=0dBFS
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
20
50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 5. Crosstalk
AKM
AK4552 DAC FFT Plot
VA=VD =3.0V, fs=96kHz, Input=0dBFS, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 6. FFT Plot
<KM080600>
2005/10
- 25 -
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 DAC FFT Plot
VA=VD =3.0V, fs=96kHz, Input=-60dBFS, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
Figure 7. FFT Plot
AKM
AK4552 DAC FFT Plot
VA=VD=3.0V, fs=96kHz, fin=None
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 8. FFT Plot
<KM080600>
2005/10
- 26 -
ASAHI KASEI
[AKD4552-A]
Revision History
Date
05/10/18
Manual
Revision
KM080600
Board
Revision
0
Reason
Contents
First Edition
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
<KM080600>
2005/10
- 27 -
A
B
C
D
+
E
C1
22u
JP1
GND
DGND
C2
10u
R1
220
J1
ROUT
R3
220
J3
LOUT
E
R2
10k
AGND
+
J2
RIN
E
+
R4
560
D
C3
22u
J4
LIN
C4
10u
CN1
U1
D
R5
10k
CN2
U2
+
1
RIN
ROUT
16
2
2
LIN
LOUT
15
C5
0.1u
3
C7
10u
L1
1
C9
47u
+
2
C8
0.1u
+
VA
+
C
1
C11
0.1u
4
C10
10u
(short)
3
VSS
4
VA
5
5
VD
6
6
Y8
A8
9
PDN
15
12
Y7
A7
8
BCLK
C6
1u
C
14
14
13
Y6
A6
7
MCLK
PDN
13
13
14
Y5
A5
6
LRCK
12
15
Y4
A4
5
SDTI
BCLK
DEM0
11
VCOM
MCLK
R8
51
R9
51
12
R7
10
DM0
16
+
R6
560
11
11
DM1
16
Y3
A3
4
DEM1
10
DM0
17
Y2
A2
3
DEM0
18
Y1
A1
2
10
GND
G2
19
20
VCC
G1
1
R10 51
DM1
7
7
DEM1
LRCK
10
R11 51
SDTO
R12 51
8
8
SDTO
SDTI
9
9
B
B
AK4552
C12
47u
+
VCC
1
C13
0.1u
2
L2
10u
1
2
D2V
D1
1S1588
U3A
1
U3B
2
74HC14
3
4
PDN
74HC14
1
H
3
L
74LVC541
R13
10k
A
A
C14
0.1u
2
SW1
PDN
Title
Size
A3
Date:
A
B
C
D
AKD4552-A
Document Number
Rev
AK4552
Monday , September 26 , 2005 Sheet
E
0
1
of
3
A
B
C
D
E
E
E
1
2
3
4
5
10
9
8
7
6
L3
10u
1
C16
0.1u
C17
0.1u
C18
0.1u
C19
0.1u
VCC
T1
2
2
+ C15
47u
C20
0.1u
VIN
C21
0.1u
TO92
GND
for 74HCU04, 74HC14,
74HC4040, 74HCT04,
74AC74
SW2
VOUT
3
D3V
C22
0.1u
1
VCC
MODE
RP1
5
4
3
2
1
DEM0
DEM1
OCKS0
OCKS1
CM0
DEM0
DEM1
OCKS0
OCKS1
CM0
D
D
U4
47k
C23
10u
VCC
C25
10u
+
+
D3V
1
DVDD
CM0/CDTO
28
2
DVSS
CM1/CDTI
27
3
TVDD
OCKS1/CCLK
26
OCKS1
4
V/TX
OCKS0/CSN
25
OCKS0
5
XTI
MCKO1
24
6
XTO
MCKO2
23
7
PDN
DAUX
22
CM0
C24
0.1u
C26
0.1u
VCC
C27
5p
1
2
C
R14
10k
D2
1S1588
U3C
5
74HC14
DAUX
8
74HC14
SW3
DIR
C29
0.1u
2
C30
10u
VCC
8
R
DIR
DIR_BCLK
9
AVDD
SDTO
20
DIR_SDTI
10
AVSS
LRCK
19
1
SDTO
74HCT04
+
C31
0.1u
DIR_LRCK
U5C
RX1
ERF
18
5
R17
6
74HCT04
12
RX2/DIF0
FS96
17
13
RX3/DIF1
P/S
16
14
RX4/DIF2
AUTO
15
LED1
2
1k
VCC
1
B
ERF
2
PORT1
5
21
470
L4
47u
5
BICK
R16
1
B
GND
VCC
GND
OUT
2
74HCT04
11
6
U5A
3
18k
D3V
6
U5B
4
R15
1
H
3
L
9
C
DIR_MCLK
M2
C28
5p
U3D
6
JP2
MCKO
M1
X1
22.5792MHz
4
3
2
1
C32
0.1u
+ C33
10u
AK4112B
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4552-A
Document Number
Rev
DIR
Monday, September 26, 2005
0
Sheet
E
2
of
3
A
B
C
D
E
2
VCC
E
1
U6
R18
10k
D3
1S1588
E
U3F
13
12
11
74HC14
1
V1
U1
24
2
TRANS
DIF2
23
3
RESETN
DIF1
22
4
MCLK
DIF0
21
5
SDTI
TXP
20
6
BICK
TXN
19
10
74HC14
1
H
3
L
U3E
C34
0.1u
VCC
2
SW4
DIT
128FS
PORT2
X_LRCK
ADC
DIR_LRCK
DIR
X_BCLK
ADC
DIR_BCLK
DIR
LRCK
JP3
LRCK
C35
0.1u
7
LRCK
DVSS
18
8
FS0/CSN
DVDD
17
9
FS1/CDTI
CKS1
16
10
FS2/CCLK
CKS0
15
11
FS3/CDTO
BLS
14
12
C1
ANS
13
C36
0.1u
JP4
BCLK
BCLK
MCLK
BCLK
LRCK
SDTI
ROM
MCLK
SDTI
PORT3
1
2
3
4
5
10
9
8
7
6
JP5
SDTO
SDTO
+
D
4
3
2
1
C37
10u
R19
1k
IN
VCC
IF
GND
5
5
6
6
D
DIT
VCC
ROM
C
C
VCC
R20
JP6
SDTI
ADC
10k
DIR
AK4103A
DAUX
DIR_SDTI
128FS
X2
11.2896MHz
B
R21
U7B
C38
5p
U9A
74AC74
4
4
3
74HCU04
C39
5p
XTL
EXT
DIR
2
D
3
CLK
Q
5
Q
6
x2
1
DIR_MCLK
J5
EXT
U7C
74HCU04
5
x1
JP9
MCLK
B
U8
10
JP11
CLK
PR
2
74HCU04
CL
U7A
1
MCLK
VCC
1M
JP8
XTE
JP7
SPEED
x1
x2
x4
11
CLK
RST
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
9
7
6
5
3
2
4
13
12
14
15
1
JP10
BCFS
x4
X_BCLK
x1
x4
X_LRCK
x1
JP12
LRFS
74HC4040
6
A
A
JP13
EXT
Title
Size
A3
Date:
A
B
C
D
AKD4552-A
Document Number
Rev
DIT
Monday, September 26, 2005
0
Sheet
E
3
of
3
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