[AKD4558-A] AK4558 Evaluation Board Rev.2 GENERAL DESCRIPTION The AKD4558-A is an evaluation board for AK4558, which is 24/32bit, CODEC including 2ch ADC and 2ch DAC. The control settings of this board may be controlled via USB port, allowing for easy A/D and D/A evaluation. BNC connectors are used for the input and output of the analog signals. This board also has a digital interface which can be connected to the digital audio system via optical connector. Ordering guide AKD4558-A -- Evaluation board for AK4558 Control software included with package FUNCTION Clock generator circuit (AK4118A used) Compatible with 2types of digital audio interface - Optical input (x1) / Optical output (x1) - Pin header for external data source BNC connector for an external clock input ADC 2ch input, DAC 2ch output USB port and 10pin header for board control Figure 1. AKD4558-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM116602> 2015/04 -1- [AKD4558-A] Evaluation Board Diagram Board Diagram J700 J706 T1 J701 J702 J703 J705 J704 T3 T2 PORT600 SW500 U60 J200 J201 U1 PORT2 J202 U2 PORT1 J203 J400 SW501 SW401 SW400 SW300 Figure 2. AKD4558-A Board Diagram Description (1) U1 ( AK4558 ) 24/32bit,2ch A/D Converter, 2ch D/A Converter. (2) J200, J201, J202, J203 ( Analog data ) J200, J201 BNC connector : Analog Input for LIN, RIN. J202, J203 BNC connector : Analog Output for LOUT, ROUT. (3) PORT1, PORT2 ( Optical Connector ) PORT1 : Input optical signal to AK4118A. PORT2 : Output optical signal from AK4118A. (4) J700, J701, J702, J703, J704, J705, J706 ( Power supply ) J700 (+12V) : +12V Power Supply J701 (AVDD1), J704 (D3.3V) : 3.3V Power Supply J702 (TVDD) : 1.8V/3.3V Power Supply J703 (VDD18) : 1.8V Power Supply J705 (AVSS), J706 (DGND) : GND (5) U2 ( AK4118A ) AK4118A has DIR, DIT and X’tal oscillator. Transports input data to AK4558 when working in master mode, and output data from AK4558 when working in slave mode. (6) U60 ( PIC18F4550 ) USB control chip. Sets up AK4558 registers from PC via USB port (PORT600). (7) J400 (BNC Connector) Input external clock source. <KM116602> 2015/04 -2- [AKD4558-A] (8) SW300 ( Dip-switch ) DIP type switch. Sets clock and audio format of AK4118A. DIF[2:0] used to set audio interface format and OCKS[1:0] used to master clock frequency. (9) SW500, SW501 ( Dip-switch ) DIP type switch. Sets clock and audio format and filter of AK4558. (10) SW400 ( Toggle switch ) Toggle type-switch PDN for AK4558. “H” : PDN = High “L” : PDN = Low (11) SW401 ( Toggle switch ) Toggle type-switch PDN for AK4118A. “H” : PDN = High “L” : PDN = Low (12) T1, T2, T3 ( regulator ) Regulator for AK4558, AK4118A, Logic Circuit. T1 : Regulated AVDD1, TVDD (3.3V) from +12V. T2 : Regulated TVDD, VDD18 (1.8V) from +12V. T3 : Regulated D3.3V (3.3V) from +12V. <KM116602> 2015/04 -3- [AKD4558-A] Evaluation Board Manual Operation sequence [1] Power supply line settings [2] Jumped pins settings [3] DIP switches settings [4] Toggle switches settings [5] Data format settings [6] Register control (Serial control) [7] Evaluation modes <KM116602> 2015/04 -4- [AKD4558-A] [1] Power supply line settings (1-1) Power supply settings : Used the regulator (T1,T2,T3) <Default> Set up the power supplied lines. * Each supply line should be distributed from the power supply unit. Name Color Setting (Typ) Function Comments Default Settings J700 +12V Red +12V Regulator power supply Should always be connected +12V J701 AVDD1 Red +3.3V AK4558 AVDD 3.3V regulator is used REG : (JP700=1pin-2pin short) by (JP700=1pin-2pin default, when jack is used short) (JP700=2pin-3pin short) J702 TVDD Red +1.8 / +3.3V/ AK4558 TVDD, Logic 1.8V regulator is used REG (1.8V) : IC power supply (JP702=1pin-2pin short and (JP702=1pin-2pin JP701=REG1.8V) by default, short and when 3.3V regulator is used JP701=REG1.8V) (JP702=1pin-2pin short and JP701=REG3.3V), when jack is used (JP702=2pin-3pin short) J703 VDD18 Yellow +1.8V AK4558 VDD18 1.8V regulator is used REG : (JP703=1pin-2pin short and (JP703=1pin-2pin JP100=short) by default, short and when LDO of AK4558 is JP100=short) used (JP100=open), when jack is used (JP703=2pin-3pin short and JP100=short) J704 D3.3V Red +3.3V AK4118A 3.3V VDD, 3.3V regulator is used REG : Logic IC power supply (JP704=1pin-2pin short) by (JP704=1pin-2pin default, when jack is used short) (JP704=2pin-3pin short) J706 AVSS Black 0V Analog ground Should always be connected 0V J705 DGND Black 0V Digital ground Should always be connected 0V Table 1.Power supply line setting (default: used the regulator ) <KM116602> 2015/04 -5- [AKD4558-A] (1-2) About jumper for power supply The roles of the jumper for each power supply supplied from the regulator are as follows. Connection of the jumper for power supply : Name JP700 AVDD1 Function Comments Default Settings Select regulator power supply AVDD for AK4558: REG : or jack for AVDD1 JP700=1pin-2pin short : 3.3V regulator is used by default. JP700=1pin-2pin short JP700=2pin-3pin short : Jack is used. JP701 REG3.3V Select regulator power supply TVDD for AK4558 and Logic IC: REG1.8V : REG1.8V 3.3V or 1.8V for TVDD JP701=1pin-2pin short : 3.3V regulator is used. JP701=2pin-3pin short JP701=2pin-3pin short : 1.8V regulator is used by default. JP702 TVDD Select regulator power supply TVDD for AK4558 and Logic IC: REG : or jack for TVDD JP702=1pin-2pin short : Regulator is used by default. JP702=1pin-2pin short JP702=2pin-3pin short : Jack is used. JP703 VDD18 Select regulator power supply VDD18 for AK4558: REG : or jack for VDD18 JP703=1pin-2pin short : 1.8V regulator is used by default. JP703=1pin-2pin short JP703=2pin-3pin short : Jack is used. JP100 JP704 VDD18SEL D3.3V Select External power supply or VDD18 selector for AK4558: External : LDO power supply of AK4558 JP100=short : External Power supply is used by default. JP100=short for VDD18 JP100=open : LDO of AK4558 is used. Select regulator power supply D3.3V for AK4118A and Logic IC: REG : or jack for D3.3V JP704=1pin-2pin short : 3.3V regulator is used by default. JP704=1pin-2pin short JP704=2pin-3pin short : Jack is used. JP705 GND Select connection / separation between analog ground and digital ground. Analog ground / digital ground short or opem: JP705=open: Separate analog ground from digital ground JP705=short: Connect analog ground to digital ground by Short : JP705=short default. Table 2. Jumper for power supply <KM116602> 2015/04 -6- [AKD4558-A] [2] Jumped pins settings No 1 JP100 Names VDD18SEL Default Short 2 JP400 EXT Open 3 JP401 BICK-SEL DIR 4 JP402 LRCK-SEL DIR 5 JP403 MCKI-SEL DIR 6 JP404 BICK-PHASE THR (1pin-2pin short) 7 JP405 SDTI-SEL DIR 8 JP406 TDMI-SEL Open 9 JP407 DAUX_SEL Short 10 JP408 TDMI/O SEL Open 11 JP500 PMADL/SCLSEL SCL Functions Select Short / Open VDD18. Open: VDD18 pin of AK4558 open. Short: VDD18 pin of AK4558 input 1.8V. (default) Open: No input (default) Short: External MCLK(JACK:J400 EXT) input. Select input to AK4558 (U1) BICK Buffer Case of MCLK=256fs MCLK/2: 128fs divider MCLK/4: 64fs divider MCLK/8: 32fs divider MCLK/16: 16fs divider DIR: DIR-AK4118-BICK (default) PORT3: Pin Header PORT3-BICK Open: No signal Select input to AK4558 (U1) LRCK Buffer Case of MCLK=256fs MCLK/128: 2fs divider MCLK/256: 1fs divider MCLK/512: 0.5fs divider DIR: DIR-AK4118-LRCK (default) PORT3: Pin Header PORT3-LRCK Open: No signal PORT3: Pin Header PORT3-MCLK EXT: External MCLK (JACK:J400 EXT) input. GND: GND DIR: DIR-AK4118-MCKI (default) Select polarity (non-inverted output / inverted output) of BICK_SEL outputs. THR: Non-inverted output. (default) INV: Inverted output. Select input to AK4558 (U1) SDTI DIR: DIR-AK4118-SDTO (default) PORT4: Pin Header PORT4-SDTI GND: Digital ground Select connect to AK4558 (U1) TDMI/TDMO DIR: DIR-AK4118-SDTO (default) TDMI: Pin Header PORT4-TDMI/O TDMO: Pin Header PORT4-TDMI/O Select input to DIT:AK4118 (U2) DAUX short: AK4558-SDTO is used. (default) open: No signal Select input/output for AK4558 (U1) TDMI/O DIR: DIR-AK4118-SDTO TDMI: TDMI of AK4558 (PinHeader PORT4-TDMI/O) TDMO: TDMO of AK4558 (PinHeader PORT4-TDMI/O) open: No signal (default) Select input to AK4558 (U1) PMADL/SCL SCL: SCL signal input to AK4558. (default) PMADL: PMADL signal of SW500 input to AK4558. <KM116602> 2015/04 -7- [AKD4558-A] 12 JP501 PMADR/SDASEL SDA 13 JP502 PMDAL/CAD0SEL CAD0 14 JP503 PMDAR/CAD1SEL CAD1 15 JP504 TDMI/CKS0SEL CKS00 16 JP505 TDMI I/O SEL TDMO0 17 JP700 AVDD1-SEL REG (1pin-2pin short) 18 JP701 TVDDVOL-SEL 19 JP702 TVDD-SEL REG1.8V (2pin-3pin short) TVDD (1pin-2pin short) 20 JP703 VDD18-SEL VDD18 (1pin-2pin short) 21 JP704 D3.3V-SEL REG (1pin-2pin short) 22 JP705 GND Short Select input to AK4558 (U1) PMADR/SDA SDA: SDA signal input to AK4558. (default) PMADR: PMADR signal of SW500 input to AK4558. Select input to AK4558 (U1) PMDAL/CAD0 CAD0: CAD0 signal input to AK4558. (default) PMDAL: PMDAL signal of SW500 input to AK4558. Select input to AK4558 (U1) PMDAR/CAD1 CAD1: CAD1 signal input to AK4558. (default) PMDAR: PMDAR signal of SW500 input to AK4558. Select connect to AK4558 (U1) TDMI/CKS0 CKS00: CKS00 signal of SW501 input to AK4558. (default) TDMI: TDMI/O signal connect to AK4558. Select connect to AK4558 (U1) TDMI/TDMO TDMO: TDMO signal connect to AK4558. (default) TDMI: TDMI/O signal connect to AK4558. Select power supply to AVDD REG(1pin-2pin short): Regulator T1 (default) (When regulator “T1” is selected, power supply jack “AVDD1” should be open.) Jack(2pin-3pin short): Power supply jack J701 “AVDD1” Select power supply voltage of TVDD REG3.3V(1pin-2pin short): Regulator T1 (default) REG1.8V(2pin-3pin short): Regulator T2 (default) Select power supply to TVDD REG(1pin-2pin short): Regulator T1/T2 (default) (When regulator “T1/T2” is selected, power supply jack “TVDD” should be open.) Jack(2pin-3pin short): Power supply jack J702 “TVDD” Select power supply to VDD18 REG(1pin-2pin short): Regulator T2 (default) (When regulator “T2” is selected, power supply jack “VDD18” should be open.) Jack(2pin-3pin short): Power supply jack J703 “VDD18” Select power supply to D3.3V REG(1pin-2pin short): Regulator T3 (default) (When regulator “T3” is selected, power supply jack “D3.3V” should be open.) Jack(2pin-3pin short): Power supply jack J704 “D3.3V” Select connection / separation between analog ground and digital ground. Open: Separate analog ground from digital ground Short: Connect analog ground to digital ground (default) Table 3. Main board Jumper pin setting <KM116602> 2015/04 -8- [AKD4558-A] [3] DIP switches settings (3-1). Setting for SW300 (Sets AK4118 (U2) audio format and master clock setting) No. Switch Name Function 1 DIF0 Set-up of DIF0 pin. (in parallel mode) 2 DIF1 Set-up of DIF1 pin. (in parallel mode) 3 DIF2 Set-up of DIF2 pin. (in parallel mode) 4 OCKS1 Set-up of OCKS1 pin. (in parallel mode) 5 OCKS0 Set-up of OCKS0 pin. (in parallel mode) default H L H L L Table 4. SW1 Setting Mode DIF2 pin DIF1 pin DIF0 pin SW300_1 SW300_2 SW300_3 DIF2 bit DIF1 bit DIF0 bit 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 DAUX SDTO 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S LRCK BICK I/O I/O H/L O 64fs O H/L O 64fs O H/L O 64fs O H/L O 64fs O H/L O 64fs O L/H O 64fs O H/L I 64-128fs I L/H I 64-128fs I default Table 5. Audio format OCKS1 pin OCKS0 pin SW300_4 SW300_5 OCKS1 bit OCKS0 bit 0 0 (X’tal) MCKO1 MCKO2 fs (max) 0 256fs 256fs 256fs 96 kHz 1 256fs 256fs 128fs 96 kHz 1 0 512fs 512fs 256fs 48 kHz 1 1 128fs 128fs 64fs 192 kHz default Table 6. Master Clock Frequency Select <KM116602> 2015/04 -9- [AKD4558-A] (3-2). Setting for SW500 (Sets AK4558 (U1) ) No. Switch Name Function ADC Lch Power Management Pin in parallel control mode. (PS pin =”H”) 1 PMADL L: ADC Lch Power Down H: Normal Mode ADC Rch Power Management Pin in parallel control mode. (PS pin =”H”) 2 PMADR L: ADC Rch Power Down H: Normal Mode DAC Lch Power Management Pin in parallel control mode. (PS pin =”H”) 3 PMDAL L: DAC Lch Power Down H: Normal Mode DAC Rch Power Management Pin in parallel control mode. (PS pin =”H”) 4 PMDAR L: DAC Rch Power Down H: Normal Mode 5 CAD1 Chip Address1 Pin in serial control mode. (PS pin =”L”) 6 CAD0 Chip Address0 Pin in serial control mode. (PS pin =”L”) DAC Lch/Rch Output (LOUT/ROUT) Power Save Mode Pin in parallel control mode. (PS pin =”H”) 7 LOPS L: Normal Mode H: DAC LOUT/ROUT Power Save Mode LDO Enable Pin 8 LDOE L: LDO disable H: LDO enable default H H H H L L L L Table 7. SW500 Setting (3-3). Setting for SW501 (Sets AK4558 (U1) ) No. Switch Name Function Control mode select pin. 1 PS L: I2C Bus control mode. H: Parallel control mode. 2 CKS3 Mode Setting Pin #3 3 CKS2 Mode Setting Pin #2 4 CKS1 Mode Setting Pin #1 5 CKS0 Mode Setting Pin #0 6 Not used 7 Not used 8 Not used default L L H H H - Table 8. SW501 Setting <KM116602> 2015/04 - 10 - [AKD4558-A] [4] Toggle switches settings Up=”H”, Down=”L” [SW401] ( Power Down (PDN) for AK4558): Power Down (PDN) Switch for AK4558 Reset AK4558 (U1) once by brining SW401 to “L” once upon power-up. Keep “H” when AK4558 is in use; keep “L” when AK4558 is not in use. [SW400] ( Power Down (PDN) for AK4118A): Power Down (PDN) Switch for AK4118A Reset AK4118A (U2) once by brining SW400 to “L” once upon power-up. Keep “H” when AK4118A is in use; keep “L” when AK4118A is not in use. <KM116602> 2015/04 - 11 - [AKD4558-A] [5] Data format settings (5-1) Settings of Data Format (SDTI/SDTO) Audio Interface Format settings of SDTI/SDTO can be set change by switching CKS3-0. (5-1-1): Case1 : PS pin = “L” CKS3 pin CKS2 pin Mode L L Slave Mode L H Slave Mode default H L Slave Mode H H Master Mode Table 9. Audio Interface Format setting for AK4558 (PS pin = “L”) (5-1-2): Case2 : PS pin = “H” Mode CKS3 CKS2 CKS1 CKS0 HPF M/S 0 L L L L ON Slave 1 L L L H ON Slave 2 L L H L OFF Slave 3 L L H H OFF Slave 4 L H L L ON Slave 5 L H L H ON Slave 6 L H H L OFF Slave 7 L H H H OFF Slave 8 H L L L ON Slave 9 H L L H ON Slave 10 H L H L OFF Slave 11 H L H H OFF Slave 12 13 14 15 H H H H H H H H L L H H L H L H ON ON ON ON Master Master Master Master MCKI 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 256fs (Double Speed) 512fs (Normal Speed) 128fs (Quad Speed) 256fs (Normal Speed) Audio Interface Format 32bit LJ/RJ (Mode 5) 32bit I2S (Mode 7) 32bit LJ (Mode 6) 32bit I2S (Mode 15) Table 10.Audio Interface Format setting for AK4558 (PS pin = “H”) <KM116602> 2015/04 - 12 - [AKD4558-A] [6] Register control (Serial control) AKD4558-A can be controlled via USB (serial port). Connect board to PC using the USB cable (PORT600 serial) included with the AKD4558-A. The control software is packed with the evaluation board. The software operation sequence is included in the evaluation board manual. <KM116602> 2015/04 - 13 - [AKD4558-A] [7] Evaluation modes (7-1) ADC (Analog Digital) Toggle switch setting: SW400 SW401 L→H AK4118(U2) : Used L→H AK4558(U1) : Used Table 11. Toggle switch setting Start up Control Register Setting 1: Port Reset & Write Default. 2: Set Addr: 00h = “1D” to power on ADC. Other control register settings are default. RSTN bit: Internal timing reset 0: Reset. 1: Normal operation (default) PMADL/R bit: ADC L/Rch Power management 0: ADC power-down 1: Normal operation (default) Addr 00H Register Name D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 PMADR PMADL PMDAR PMDAL RSTN R/W RD RD RD R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 Power Management Table 12. Addr 00H control register setting (7-2) DAC (Digital Analog) Toggle switch setting: SW400 L→H AK4118(U2) : Used SW401 L→H AK4558(U1) : Used Table 13. Toggle switch setting Start up Control Register Setting 1: Port Reset & Write Default. 2: Set Addr: 00h = “07” to power on DAC. Other control register settings are default. RSTN bit: Internal timing reset 0: Reset. 1: Normal operation (default) PMDAL/R bit: DAC L/Rch Power management 0: DAC power-down 1: Normal operation (default) Addr 00H Register Name D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 PMADR PMADL PMDAR PMDAL RSTN R/W RD RD RD R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 Power Management Table 14. Addr 00H control register setting <KM116602> 2015/04 - 14 - [AKD4558-A] Control Software Manual ■ Evaluation Board and Control Soft Settings 1. Set an evaluation board properly. 2. Connect a PC (IBM-AT compatible) and an evaluation board via a USB cable. The evaluation board recognized as HID (Human Interface Device) on the PC. It is not necessary to install a new driver. 3. Start up the control program. When the screen does not display “AKUSBIF-B” at bottom left, reconnect the PC and the USB control box, and push the [Port Reset] button. 4. Proceed evaluation by following the process below. [Support OS] Windows XP / Vista / 7 (32bit) (XP compatible mode is recommended for Vista / 7) 64bit OS’s are not supported. Figure 3. Control software window <KM116602> 2015/04 - 15 - [AKD4558-A] ■ Operation Overview Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs. Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting. 1. [Port Reset]: For when connecting to PC Click this button after the control soft starts up when connecting to PC 2. [Write Default]: Initializes Registers When the device is reset by a hardware reset, use this button to initialize the registers. 3. [All Write]: Executes write commands for all registers displayed. 4. [All Read]: Executes read commands for all registers displayed. 5. [Save]: Saves current register settings to a file. 6. [Load]: Executes data write from a saved file. 7. [All Req Write]: Opens “All Req Write” dialog box. 8. [Data R/W]: Opens “Data R/W” dialog box 9. [Sequence]: Opens “Sequence” dialog box. 10. [Sequence(File)]: Opens “Sequence(File)” dialog box. 11. [Read]: Reads current register settings and displays on to the register area (on the right of the main window). This is different from [All Read] button, it does not reflect to a register map, only displaying register settings in hexadecimal. <KM116602> 2015/04 - 16 - [AKD4558-A] 1. [REG]: Register Map This tab is for a register writing and reading. Each bit on the register map is a push-button switch. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Grayout registers are Read Only registers. They can not be controlled. The registers which is not defined in the datasheet are indicated as “---”. Figure 4. Window of [REG] <KM116602> 2015/04 - 17 - [AKD4558-A] 1-1. [Write]: Data Writing Dialog It is for when changing two or more bits on the same address at the same time. Click [Write] button located on the right of the each corresponded address for a pop-up dialog box. When the checkbox is checked, the data will be “H” or “1”. When the checkbox is not checked, the data will be “L” or “0”. Click [OK] to write setting values to the registers, or click [Cancel] to cancel this setting. Figure 5. Window of [Register Set] 1-2. [Read]: Data Read Click [Read] button located on the right of the each corresponded address to execute a register read. After register reading, the display will be updated regarding to the register status. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Please be aware that button statuses will be changed by a Read command. <KM116602> 2015/04 - 18 - [AKD4558-A] 2. [Tool]: Testing Tools This tab screen is for the evaluation testing tool. Click button for each testing tool. Figure 6. Window of [Tool] <KM116602> 2015/04 - 19 - [AKD4558-A] 2-1. [Repeat Test]: Repeat Test Dialog Click [Repeat Test] button in the Test tab to open a repeat test dialog shown below. Repeat writing test can be executed by this dialog. Figure 7. Window of [ Repeat Test ] [Start] Button : Starts the repeat test. A dialog for saving a file of the test result will open when clicking this button. Name the file. Test will start after specifying a saving file. [Close] Button : Closes this dialog and finishes the process. [Address] Box : Data writing address in hexadecimal numbers. [Start Data] Box : Start data in hexadecimal numbers. [End Data] Box : End data in hexadecimal numbers. [Step] Box : Data write step interval. [Repeat Count] Box : Repeat count of the test writing. [Up and Down] Box : Data write flow is changed as below. • Checked: Writes in step interval from the start data to the end data and turn back from the end data to the start data. [Example] Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count. Data flow: [00→01→02→03→04→05→05→04→03→02→01→00] x Repeat Count Number • Not checked: Writes in step interval from the start data to the end data and finishes writing. [Example] Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count. Data flow: [00→01→02→03→04→05] x Repeat Count Number [Sampling Frequency] Box: Selects sampling frequency 44.1kHz/48kHz [Count] Box : Indicates the count number during a repeat test. [Lch Level] Box : Indicates the Lch Level during a repeat test. <KM116602> 2015/04 - 20 - [AKD4558-A] 2-2. [Loop Setting]: Loop Dialog Click [Loop Setting] button in the Tool tab to open loop setting dialog as shown below. Writing test can be executed. Figure 8. Window of [ Loop ] [ OK ] Button [ Cancel ] Button [ Address ] Box [ Start Data ] Box [ End Data ] Box [ Interval ] Box [ Step ] Box [ Mode Select ] Box : Starts the test. : Closes the dialog and finishes the process. : Data writing address in hexadecimal numbers. : Start data in hexadecimal numbers. : End data in hexadecimal numbers. : Data write interval time. : Data write step interval. : Mode select check box. • Checked: Writes in step interval from the start data to the end data and turn back from the end data to the start data. [Example] Start Data = 00, End Data = 05, Step = 1 Data flow: 00→01→02→03→04→05→05→04→03→02→01→00 • Not Checked: Writes in step interval from the start data to the end data and finishes writing. [Example] Start Data = 00, End Data = 05, Step = 1 Data flow: 00→01→02→03→04→05 <KM116602> 2015/04 - 21 - [AKD4558-A] ■ Dialog Boxes 1. [All Req Write]: All Reg Write dialog box Click [All Reg Write] button in the main window to open register setting files. Register setting files saved by [SAVE] button can be applied. Figure 9. Window of [ All Reg Write ] [Open (left)]: Selects a register setting file (*.akr). [Write]: Executes register writing by the setting of selected file. [Write All]: Executes all register writings. Selected files are executed in descending order. [Help]: Opens a help window. [Save]: Saves a register setting file assignment. The file name is “*.mar”. [Open (right)]: Opens a saved register setting file assignment “*. mar”. [Close]: Closes the dialog box and finish the process. ~ Operating Suggestions ~ 1. 2. Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be stored in the same folder. When register settings are changed by [Save] button in the main window, re-read the file to reflect new register settings. <KM116602> 2015/04 - 22 - [AKD4558-A] 2. [Data R/W]: Data R/W Dialog Box Click the [Data R/W] button in the main window for data read/write dialog box. Data write is available to specified address. Figure 10. Window of [ Data R/W ] [Address] Box: Input data address in hexadecimal numbers for data writing. [Data] Box : Input data in hexadecimal numbers. [Mask] Box : Input mask data in hexadecimal numbers. This is “AND” processed input data. [Write]: Writs the data generated from Data and Mask values to the address specified by “Address” box. [Read]: Reads data from the address specified by “Address” box. The result will be shown in the Read Data Box in hexadecimal numbers. [Close]: Closes the dialog box and finishes the process. Data writing can be cancelled by this button instead of executing a write command. *The register map will be updated after executing [Write] or [Read] commands. <KM116602> 2015/04 - 23 - [AKD4558-A] 3. [Sequence]: Sequence Dialog Box Click [Sequence] button to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure 11. Window of [Sequence ] ~ Sequence Setting ~ Set register sequence by following process bellow. 1. Select a command Use [Select] pull-down box to choose commands. Corresponding boxes will be valid. < Select Pull-down menu > · No_use: Not using this address · Register: Register writing · Reg(Mask): Register writing (Masked) · Interval: Taking an interval · Stop: Pausing the sequence · End: Finishing the sequence <KM116602> 2015/04 - 24 - [AKD4558-A] 2. Input sequence [Address]: Data address [Data]: Writing data [Mask]: Mask [Data] box data is ANDed with [Mask] box data. This is the actual writing data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written. When Mask =0x0F, lower 4bit data which is set in the [Data] box is written. Upper 4bit is hold to current setting. [ Interval ]: Interval time Valid boxes for each process command are shown bellow. · No_use : None · Register : [Address], [Data], [Interval] · Reg(Mask) : [Address], [Data], [Mask], [Interval] · Interval : [Interval] · Stop : None · End : None ~ Control Buttons~ The function of Control Button is shown bellow. [Start]: Executes the sequence [Help]: Opens a help window [Save]: Saves sequence settings as a file. The file name is “*.aks”. [Open]: Opens a sequence setting file “*.aks”. [Close]: Closes the dialog box and finishes the process. ~ Stop of the sequence~ When “Stop” is selected in the sequence, the process is paused and it starts again when [Start] button is clicked Restarting step number is shown in the “Start Step” box. When finishing the process at the end of sequence, “Start Step” will return to “1”. The sequence can be started from any step by writing the step number to the “Start Step” box. Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning. <KM116602> 2015/04 - 25 - [AKD4558-A] 4. [Sequence(File)]: Sequence Setting File Dialog Box Click [Sequence(File)] button to open sequence setting file dialog box. Those files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 12. Window of [ Sequence(File) ] [Open (left)]: Opens a sequence setting file (*.aks). [Start]: Executes the sequence by the setting of selected file. [Start All]: Executing all sequence settings. Selected files are executed in descending order. [Help]: Opens a help window. [Save]: Saves a sequence setting file assignment. The file name is “*.mas”. [Open(right)]: Opens a saved sequence setting file assignment “*. mas”. [Close]: Closes the dialog box and finishes the process. ~ Operating Suggestions ~ 1. 2. Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be stored in the same folder. When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click “OK” to continue the process. Figure 13. Window of [ Sequence Pause ] <KM116602> 2015/04 - 26 - [AKD4558-A] Measurement Results [Measurement condition] ・Measurement unit : Audio Precision, SYS-2722 (No.00122) : PSIA-2722 (No00096) ・MCKI : 256fs/128fs (12.288MHz/24.576MHz) ・BICK : 64fs ・fs : 48kHz/96kHz/192kHz ・Bit : 24bit ・Measurement Mode : Slave Mode ・Power Supply : VOP+(12V)=12V, GND AVDD=3.3V (Regulator), TVDD=VDD18=1.8V (Regulator) ・Input Frequency : 1kHz ・Measurement Frequency : 20 ~ 20kHz @48kHz, 20 ~ 40kHz @96kHz, 20 ~ 40kHz @192kHz ・Temperature : Room [Measurement Results] 1. ADC Result Unit Lch Rch fs = 48kHz (-1dBFS) 94.7 94.5 dB fs = 96kHz (-1dBFS) 95.0 94.8 dB fs = 192kHz (-1dBFS) 94.3 94.0 dB fs = 48kHz (-60dBFS, A-Weighted) 108.5 108.4 dB fs = 96kHz (-60dBFS, A-Weighted) 108.2 108.2 dB fs = 192kHz (-60dBFS, A-Weighted) 108.1 108.1 dB fs = 48kHz (A-weighted) 108.5 108.5 dB fs = 96kHz (A-weighted) 108.2 108.2 dB fs = 192kHz (A-weighted) 108.1 108.1 dB ADC : LIN/RIN => ADC => SDTO S/(N+D) DR S/N 2. DAC Result Unit Lch Rch fs = 48kHz (0dBFS) 100.5 100.6 dB fs = 96kHz (0dBFS) 98.7 98.7 dB fs = 192kHz (0dBFS) 98.6 98.6 dB fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL) 107.8 107.8 dB fs = 96kHz (-60dBFS, A-Weighted, 40kHz SPCL) 107.6 107.7 dB fs = 192kHz (-60dBFS, A-Weighted, 40kHz SPCL) 107.6 107.6 dB fs = 48kHz (A-weighted, 20kHz SPCL) 107.8 107.8 dB fs = 96kHz (A-weighted, 40kHz SPCL) 107.6 107.7 dB fs = 192kHz (A-weighted, 40kHz SPCL) 107.6 107.6 dB DAC : SDTI => DAC1 => LOUT/ROUT S/(N+D) DR S/N <KM116602> 2015/04 - 27 - [AKD4558-A] [Plot Data] 1. ADC (LIN/RIN => ADC) ADC (fs = 48kHz); LIN/RIN => ADC => SDTO AK4558 FFT ADC (LIN/RIN:L/R) [fs=48kHz, fin=1kHz, -1dBFS] +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 14. ADC – FFT (-1dBFS) [fs = 48kHz] AK4558 FFT ADC (LIN/RIN:L/R) [fs=48kHz, fin=1kHz, -60dBFS] +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 15. ADC – FFT (-60dBFS) [fs = 48kHz] <KM116602> 2015/04 - 28 - [AKD4558-A] AK4558 FFT ADC (LIN/RIN:L/R) [fs=48kHz, fin=1kHz, no signal] +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 16. ADC – FFT (No Signal) [fs = 48kHz] AK4558 THD+N vs Amplitude ADC (LIN/RIN:L/R) [fs=48kHz, fin=1kHz] -70 -75 -80 -85 -90 d B F S -95 -100 -105 -110 -115 -120 -140 -120 -100 -80 -60 -40 -20 +0 dBr Figure 17. ADC – THD+N vs. Amplitude (Input Level) [fs = 48kHz] <KM116602> 2015/04 - 29 - [AKD4558-A] AK4558 THD+N vs Input Frequency ADC (LIN/RIN:L/R) [fs=48kHz, -1dBFS] -70 RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR -75 -80 -85 -90 d B F S -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 18. ADC – THD+N vs. Input Frequency [fs = 48kHz] AK4558 Linearity ADC (LIN/RIN:L/R) +0 T [fs=48kHz, fin=1kHz] T T -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -140 -120 -100 -80 -60 -40 -20 +0 dBr Figure 19. ADC – Linearity [fs = 48kHz] <KM116602> 2015/04 - 30 - [AKD4558-A] AK4558 Frequency Response ADC (LIN/RIN:L/R) [fs=48kHz, -1dBFS] +0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 d B F S -0.9 -1 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 20. ADC – Frequency Response [fs = 48kHz] AK4558 Crosstalk ADC (LIN/RIN:L/R) [fs=48kHz, -1dBFS] -80 -85 -90 -95 -100 -105 -110 -115 d B -120 -125 -130 -135 -140 -145 -150 -155 -160 20 50 100 200 500 1k 2k Hz Figure 21. ADC – Crosstalk [fs = 48kHz] <KM116602> 2015/04 - 31 - [AKD4558-A] 2. DAC (SDTI => DAC) DAC (fs = 48kHz); SDTI => DAC => LOUT/ROUT AK4558 FFT DAC (LOUT/ROUT) [fs=48kHz, fin=1kHz, 0dBFS] +0 -10 -20 -30 -40 -50 -60 -70 d B r -80 A -100 -90 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 22. DAC – FFT (0BFS) [fs = 48kHz] AK4558 FFT DAC (LOUT/ROUT) [fs=48kHz, fin=1kHz, -60dBFS] +0 -10 -20 -30 -40 -50 -60 -70 d B r -80 A -100 -90 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 23. DAC – FFT (-60dBFS) [fs = 48kHz] <KM116602> 2015/04 - 32 - [AKD4558-A] AK4558 FFT DAC (LOUT/ROUT) [fs=48kHz, fin=1kHz, no signal] +0 -10 -20 -30 -40 -50 -60 -70 d B r -80 A -100 -90 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 24. DAC – FFT (No Signal) [fs = 48kHz] AK4558 THD+N vs Amplitude DAC (LOUT/ROUT) [fs=48kHz, fin=1kHz] -70 -75 -80 -85 -90 d B r -95 A -100 -105 -110 -115 -120 -140 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 25.DAC – THD+N vs. Amplitude (Input Level) [fs = 48kHz] <KM116602> 2015/04 - 33 - [AKD4558-A] AK4558 THD+N vs Input Frequency DAC (LOUT/ROUT) [fs=48kHz, 0dBFS] -70 -75 -80 -85 -90 d B r -95 A -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 26. DAC1 – THD+N vs. Input Frequency [fs = 48kHz] AK4558 Linearity DAC (LOUT/ROUT) [fs=48kHz,fin=1kHz] +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 27. DAC – Linearity [fs = 48kHz] <KM116602> 2015/04 - 34 - [AKD4558-A] AK4558 Frequency Response DAC (LOUT/ROUT) [fs=48kHz, 0dBFS] +1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d B r A +0.1 +0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 28. DAC – Frequency Response [fs = 48kHz] AK4558 Crosstalk DAC (LOUT/ROUT) [fs=48kHz, 0dBFS] -80 -85 -90 -95 -100 -105 -110 -115 d B -120 -125 -130 -135 -140 -145 -150 -155 -160 20 50 100 200 500 1k 2k 5k Hz Figure 29.DAC – Crosstalk [fs = 48kHz] <KM116602> 2015/04 - 35 - [AKD4558-A] REVISION HISTORY Date (YY/MM/DD) 14/04/09 Manual Revision KM116600 Board Revision 0 Reason Page Contents First edition - 14/10/07 KM116601 1 Modification P27-P35 Update of measurement results. 15/04/02 KM116602 2 Modification P27-P35 Update of measurement results. IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. <KM116602> 2015/04 - 36 - 5 4 3 2 1 PMDAR/CAD1 PMDAL/CAD0 PMADR/SDA LOPS PMADL/SCL LDOE PDN1 E E 15 16 R129 R128 R111 51 51 51 PDN PMADL/SCL 17 PMDAL/CAD0 PMADR/SDA 18 19 PMDAR/CAD1 20 LOPS LDOE 21 CN3 7pin_3 C109 Cap Dip open + 1pin Socket (C109) open AVSS LDOE=L : VDD18=1.8V(input), TVDD=1.8V(Input) -> VDD18SEL=Short, TVDDSEL=TVDD18V LDOE=H : VDD18=1.8V(Output), TVDD=3.3V(Input) -> VDD18SEL=Open, TVDDSEL=TVDD33V 15 PDN 16 PMADL/SCL 17 PMADR/SDA 18 PMDAL/CAD0 19 1 13 12 VSS2 C111 0.1u C113 10u VDD18 14 R113 1M R120 0 AVSS 13 12 TVDD MCKI 11 MCLK TVDD 11 R114 51 10 R115 51 SDTI 10 SDTI 9 R116 51 BICK 9 BICK 8 R117 51 SDTO 8 LRCK SDTO1 R118 51 B LRCK C108 10n AVSS VDD18 R112 1M 7 C120 open 0 CN2 7pin_2 7 TDMI/CKS0 PS 2 1 SDTO VCOC Cap(C120) Dip open B PMDAR/CAD1 ROUT 6 28 BICK TDMI/CKS0 ROUT LOUT 6 28 27 CKS1 ROUT1 VCOM SDTI 5 LOUT C112 1u D C VCOM CKS1 27 26 VCOC LOUT1 R106 1M 5 TP100 MCKI AK4558 CKS2 26 U1 VSS1 4 C C105 1u TVDD CKS2 25 VSS1 AVDD 4 C106 0.1u CKS3 24 C104 + 10u 3 R105 1M CKS3 25 0 R119 14 + VSS2 3 AVSS R104 24 VDD18 RIN PS AVDD AVDD1 23 RIN LIN 2 23 22 LIN LOPS 21 LDOE RIN1 22 + LIN1 JP100 VDD18SEL + CN4 7pin_4 20 D CN1 7pin_1 LRCK AVSS PS CKS3 A A CKS2 CKS1 TDMI/CKS0 Title <AKD4558-A> - 37 - Size A3 Date: 5 4 3 2 Document Number Rev <2> <AK4558> Tuesday, April 07, 2015 Sheet 1 1 of 7 5 4 3 2 1 E E D J200 LIN C200 10u 1 LIN1 + 2 3 4 5 D Cap(C200,C201) -> +,-Check AVSS J201 RIN C201 10u 1 RIN1 + 2 3 4 5 AVSS C J202 LOUT R202 220 1 LOUT1 C204 open C202 22u R200 5k AVSS Cap(C202,C203) -> +,-Check AVSS J203 ROUT AVSS 1 R203 220 + 2 3 4 5 C + 2 3 4 5 ROUT1 C205 open R201 5k C203 22u AVSS AVSS AVSS + 1pin Socket (C204,C205,R200,R201) B B A A Title <AKD4558-A> - 38 - Size A3 Date: 5 4 3 2 Document Number Rev <2> <Analog IN/OUT> Tuesday, April 07, 2015 Sheet 1 2 of 7 5 4 3 2 1 L300 47uH 1 C300 0.1u + D33V D33V TP300 RX C305 2 10 9 8 7 6 D33V 3 10k 37 41 VSS3 42 RX0 43 NC 44 RX1 45 TEST1 46 RX2 47 R306 C307 0.47u VSS4 48 RX3 1 IPS0/RX4 INT0 NC OCKS0/CSN/CAD0 DIF0/RX5 OCKS1/CCLK/SCL 36 INT0 35 OCKS0 34 OCKS1 SW300 4 L TEST2 CM1/CDTI/SDA 33 D33V C 6 OCKS0 OCKS1 8 47k 47k 47k Res 47kohm Chip R301 - R305 47k 47k 7 DIF1/RX6 CM0/CDTO/CAD1 U2 VSS1 32 DGND PDN DIF2/RX7 XTI IPS1/IIC XTO 31 PDN2 30 1 5 29 2 DIF2 DIF1 DIF0 OCKS1 OCKS0 1 2 3 4 5 C 0.1u C306 DGND H D 10u INT1 51 38 R300 + DGND AVDD PLRx D 39 2 1 C301 10u R GND OUT 2 3 40 VCC VCOM PORT1 C310 X300 12.288MHz 5p C311 5p X300 Frequency Check -> 12.288MHz (256fs) R305 R304 R303 R302 R301 DGND 9 10 P/SN DAUX XTL0 MCKO2 XTL1 BICK 28 DAUX 27 DGND 11 26 DIR-BICK 25 LRCK DIR-SDTO 24 MCKO1 23 22 VSS2 DVDD SDTO 21 VOUT/GP7 20 UOUT/GP6 19 18 17 TX1/GP3 16 TX0/GP2 15 14 13 TVDD NC/GP1 VIN/GP0 COUT/GP5 B 12 BOUT/GP4 B C308 0.1u + + DIR-LRCK C303 0.1u C304 10u C309 10u DIR-MCKI D33V A PORT2 IN VCC GND DGND TP301 TX 3 2 C302 0.1u 1 A D33V Title PLTx <AKD4558-A> - 39 - DGND Size A3 Date: 5 4 3 2 Document Number Rev <2> <DIR/DIT> Tuesday, April 07, 2015 Sheet 1 3 of 7 5 4 3 2 U400 MCLK-256fs 10 D 11 D33V 16 8 C400 0.1u CLK Q1 Q2 RST Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 VD Q11 DGND Q12 9 7 6 5 3 2 4 13 12 14 15 1 DIR-BICK JP401 MCLK/2 MCLK/4 MCLK/8 MCLK/16 DIR PORT3 THR D BICK0 INV BICK-PHASE DIR-LRCK TP401 LRCK JP402 MCLK/128 MCLK/256 MCLK/512 DIR PORT3 LRCK0 LRCK-SEL DGND D33V DIR PORT4 GND DIR-SDTO D33V K U401 3 R400 10k 1 A D400 HSU119 L SW400 PDN2 H 2 C401 0.1u 1 2 3 4 5 6 7 1A 1Y 2A 2Y 3A 3Y GND VCC 6A 6Y 5A 5Y 4A 4Y 14 13 12 11 10 9 8 PORT4 PORT3 C403 0.1u INT0 R402 LE400 1 1k 2 74HC14 LRCK BICK MCLK DIR-SDTO DIR TDMI TDMO SDTI/TDMI/SDTO TP404 SDTI SDTI0 TP406 TDMO JP406 TP403 TDMI C TDMI0 TDMO0 TDMI-SEL JP408 TDMI/O SEL DGND CLK INT0 SDTI TDMI/O SDTO JP405 SDTI-SEL DGND TP402 SDTO SDTO DGND JP407 DAUX_SEL DGND DGND DAUX PDN2 K D33V 1 A D401 HSU119 3 L SW401 PDN1 2 B TP400 BICK JP404 BICK-SEL 74HC4040 C 1 PDN10 R401 10k 2 3 4 5 H C402 0.1u J400 EXT 1 R403 51 DIR-MCKI PORT3 EXT GND DIR TP405 MCLK JP403 MCLK0 MCKI-SEL B JP400 EXT DGND DGND A A Title <AKD4558-A> - 40 5 4 3 Size 2 Document Number A3 <LOGIC> Date: Sheet Tuesday, April 07, 2015 1 Rev <2> 4 of 7 5 4 D33V -> TVDD (PDN1,MCLK,SDTI,TDMI) PDN10 MCLK0 SDTI0 TDMI0 R500 51 R501 51 R502 51 R503 51 R504 R505 R506 R507 2 3 4 5 6 7 8 9 0 0 0 0 1 19 DGND Res 0ohm Chip R504 - R507 D 3 U500 A1 A2 A3 A4 A5 A6 A7 A8 18 17 16 15 14 13 12 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 G1 G2 74VCX541 DGND 2 PDN1 MCLK SDTI TDMI/I U500 (Buffer) 10pin=DGND 20pin=TVDD R522 SDTO CKS31 CKS21 TVDD C500 0.1u LRCK0 R508 51 R509 51 C501 0.1u DGND R510 R511 R512 R513 R514 R515 for U503 74LCX541 2 3 4 5 6 7 8 9 0 0 0 0 0 0 1 19 U501 A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 G1 G2 74VCX541 Res 0ohm Chip R510 - R521 18 17 16 15 14 13 12 11 C U502 (Buffer) 10pin=DGND 20pin=D33V 0 0 0 0 0 0 R530 R531 R532 R533 R534 R535 Res 0ohm Chip R530 - R539 1 2 4 5 9 10 12 13 1A 1B 2A 2B 3A 3B 4A 4B 1Y 2Y 3Y 4Y 74VCX00 D33V DGND U504 C504 0.1u 3 6 0 0 0 0 R536 R537 R538 R539 8 11 U504 (NAND) 7pin=DGND 14pin=D33V DGND 1 3 5 9 11 13 U505 1A 2A 3A 4A 5A 6A 1Y 2Y 3Y 4Y 5Y 6Y 74VCX14 D33V C505 0.1u H SCL SDA SW501 SW DIP-8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 PMADL PMADR PMDAL PMDAR CAD1 CAD0 LOPS LDOE PS CKS3 CKS2 CKS1 CKS0 1 19 R556 51 R516 R517 R518 R519 R520 R521 DGND 0 0 0 0 0 0 DGND R557 51 PMDAR LOPS0 LDOE0 PS0 47k 47k 47k 47k 47k 47k 47k R555 R554 R553 R552 R551 R550 R549 C D33V TVDD -> D33V (BICK,LRCK) C503 0.1u DGND DGND for U502 74LCX541 JP500 PMADL/SCLSEL R559 0 JP501 PMADR/SDASEL R560 0 JP502 PMDAL/CAD0SEL R561 0 JP503 PMDAR/CAD1SEL R562 0 R563 0 R564 0 R565 0 R566 0 R567 0 R568 0 R569 0 CAD0 CKS00 CKS10 CKS20 CKS30 PS0 47k DGND D33V -> TVDD (BICK,LRCK) for U501 74LCX541 CAD1 R548 47k 47k 47k 47k 47k 47k 47k R547 R546 R545 R544 R543 R542 R541 47k R540 Res 47kohm Chip R540 - R547 D DGND DGND CKS20 Res 47kohm Chip R548 - R555 CKS10 CKS00 - 41 - TDMI/I TDMO0 PMADL/SCL B CKS30 A R558 51 JP504 TDMI/CKS0SEL PMADR/SDA Res 0ohm Chip R556 - R569 PMDAL/CAD0 PMDAR/CAD1 LOPS LDOE PS CKS3 A CKS2 CKS1 TDMI/CKS0 Title <AKD4558-A> Size JP505 TDMI I/O SEL A3 Date: 5 4 Res 0ohm Chip R523 - R529 1 19 74VCX541 BICK LRCK R525 R526 R527 R528 R529 SDTO1 TVDD -> D33V (SDTO) CKS30 CKS20 0 0 0 0 0 74VCX541 PMDAL L LDOE0 LOPS0 CAD0 CAD1 PMDAR PMDAL PMADR PMADL G1 G2 2 3 4 5 6 7 8 9 PMADR 16 15 14 13 12 11 10 9 SW500 SW DIP-8 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 2 3 4 5 6 7 8 9 TVDD C502 0.1u U501 (Buffer) 10pin=DGND 20pin=TVDD PMADL TVDD 16 15 14 13 12 11 10 9 TVDD Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 U505 (INV) 7pin=DGND 14pin=D33V for U505 74LCX14 for U504 74LCX00 U502 18 17 16 15 14 13 12 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 2 4 6 8 10 12 DGND DGND B U503 U502 (Buffer) 10pin=DGND 20pin=D33V DGND DGND CKS31 CKS21 18 17 16 15 14 13 12 11 0 0 D33V for U500 74LCX541 BICK0 51 R523 R524 1 3 2 Document Number Rev <2> <LOGIC> Tuesday, April 07, 2015 Sheet 1 5 of 7 5 4 3 2 1 R608 TVDD 100k 0.1u 4.7k C610 R602 D 10k 10k C6002.2u D R606 R607 5V => 3.3V 1 2 3 4 C PIC TP600 RD7 TP601 RD6 TP602 RD5 TP603 RD4 TP604 RD3 TP605 RD2 TP606 RD1 TP607 RD0 DGND 17 16 15 14 11 10 9 8 38 39 40 41 2 3 4 5 PORT600 USB(B type) B VUSB DD+ GND 1 2 3 4 R600 R601 0 0 42 43 44 1 5 SCL2 SCL1 SDA2 SDA1 10k C611 0.1u 10k TP608 SDA TP609 SCL SCL 3 SCL 4 SDA SDA 7 VSS0 6 28 MCLR_N/Vpp/RE3 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0/CSSPP RB3/AN9/CPP2/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA NC/ICCK/ICPGC NC/ICDT/ICPGD NC/ICRST_N/ICVpp NC/ICPORTS PIC18F4550 TQFP 44-PIN RD0/SPP0 RD1/SPP1 RD2/SPP2 RD3/SPP3 RD4/SPP4 RD5/SPP5/P1B RD6/SPP6/P1C RD7/SPP7/P1D U60 OSC1/CLKI OSC2/CLKO/RA6 RE0/AN5/CK1SPP RE1/AN6/CK2SPP RE2/AN7/OESPP VUSB 32 35 36 SDA VREF1 2 C605 0.1u VDD1 29 VSS1 1 2 3 4 5 6 VREF2 GND R610 C604 10u C603 0.1u JP600 SILK-SCREEN 1:VDD 2:MCLR 3:PGD 4:PGC 5:GND SCL EN R609 DGND VDD0 NC NC Vin Vout Vcont PCL NC GND T60 TK73633AME 8 7 6 5 C602 10u DGND C601 1u 7 1 PCA9306DP1 + + DGND DGND U61 8 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2/UOE_N RC2/CCP1/P1A RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT/SDO 18 USB-RST C C606 0.1u 12 13 33 34 30 31 XTI XTO C607 22p X600 20MHz 25 26 27 37 R603 100k C608 22p C609 0.47u DGND RA0/AN0 RA1/AN1 RA2/AN2/Vref-/CVref RA3/AN3/Vref+ RA4/T0CKI/C1OUT/RCV RA5/AN4/SS_N/HLVDIN/C2OUT 19 20 21 22 23 24 R604 R605 51 51 SCL SDA B DGND PIC18F4550 PORT601 open 10 8 6 4 2 9 7 5 3 1 SCL SDA R611 open R612 open 10pin-CTRL DGND A A Title <AKD4558-A> - 42 - Size Date: 5 4 3 Document Number A3 2 Rev <2> <PC-IF> Tuesday, April 07, 2015 Sheet 1 6 of 7 5 4 3 2 1 1 J700 +12V D D +12V-->+3.3V T1 LT1963AEST-3.3 1 IN TP700 AVDD1 JP700 REG 3 C703 0.1u +C704 47u J701 AVDD1 R700 0 AVDD1 AVDD1 AVDD1-SEL 1 AVSS OUT 2 C701 + C702 0.1u 47u GND C700 + 47u AVSS AVSS AVSS AVSS AVSS C713+ 47u JP701 TVDDVOL-SEL REG3.3V AVSS REG1.8V J702 TVDD TP701 TVDD TVDD JP702 R701 TVDD TVDD-SEL C 1 C 0 1 IN C705 C714+ 47u 3 C707 0.1u C708 + 47u TP702 VDD18 AVSS VDD18 JP703 R702 AVSS AVSS AVSS J703 VDD18 AVSS 0 VDD18 VDD18-SEL 1 AVSS OUT 2 + C706 0.1u 47u GND +12V-->+1.8V T2 LT1963AEST-1.8 C715+ 47u AVSS B 1 C709 OUT B TP703 D3.3V 3 REG C711 0.1u C712 + 47u J704 D3.3V JP704 R703 0 D33V D3.3V D3.3V-SEL 1 2 + C710 0.1u 47u IN GND +12V-->+3.3V T3 LT1963AEST-3.3 DGND DGND DGND DGND DGND C716+ 47u DGND J705 DGND J706 AVSS 1 A 1 A JP705 GND Title - 43 - DGND <AKD4558-A> Size A3 AVSS Date: 5 4 3 2 Document Number Rev <2> <POWER> Tuesday, April 07, 2015 Sheet 1 7 of 7 - 44 - - 45 - - 46 - - 47 -