AK4618VQ

[AKD4618-A]
AKD4618-A
AK4618 Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD4618-A is an evaluation board for AK4618, which is a 24bit CODEC including 6ch ADC and 12ch
DAC. The control settings of this board may be controlled via USB port, allowing for easy A/D and D/A
evaluation. RCA connectors are used for the input and output of the analog signals. This board also has a
digital interface which can be connected to the digital audio system via optical connector.
 Ordering guide
AKD4618-A
--- Evaluation board for AK4618
Control software included with package
FUNCTION
 Clock generator circuits (AK4118A used)
 Compatible with 2 types of digital audio interface
- Optical input (x1) / Optical output (x1)
- 10pin header for external data source
 RCA connector for external clock input
 ADC 6ch input, DAC 12ch output
 USB port for board control
DGND
D3.3V
TVDD
AVDD2 AVDD1
Reg
+12V
AGND
Reg
3.3V
3.3V
Opt In
AK4118A
Am
Opt Out
AK4618
Header
p
AIN
6ch
Buffer
AOUT
12ch
USB
PIC18F
4550
Reg
3.3V
Figure 1. AKD4618-A Block Diagram
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Evaluation Board Diagram
 Board Diagram
PORT7
USB
AVDD1
TVDD
AVDD2 AGND
+12V
DGND
LOUT1
PIC18F
4550
D3.3V
ROUT1
PORT5
LOUT2
ROUT2
PORT3
LOUT3
ROUT3
AK4618
PORT4
LOUT4
ROUT4
LOUT5
TORX
ROUT5
LOUT6
SW1
AK4118A
ROUT6
TOTX
IN6
IN5
IN4
IN3
EXT
IN2
SW3
IN1
SW2
Figure 2. AKD4618-A Board Diagram
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 Description
(1) IN1-IN6; L/ROUT1- L/ROUT6 (RCA Jack)
IN1-6;: Analog input jacks for IN1-6..
L/ROUT1-6: Analog output jacks for L/ROUT1-6.
White jacks are used for left channel and red ones are used for right channel.
(2) AK4118A
AK4118A has DIR, DIT and X’tal oscillator. Transports input data to AK4618 when working in master mode, and
output data from AK4618 when working in slave mode.
(3) TORX/TOTX (Optical Connector)
TORX PORT1: Input optical signal to AK4118A
TOTX PORT2: Output optical signal from AK4118A.
(4) +12V/AVDD1/AVDD2/TVDD/D3.3V/AVSS/DGND (Power supply)
+12V: +12V Power Supply
AVDD1-2,TVDD: +3.3V Power Supply
D3.3V: +3V Power Supply
Connect to +12V and GND according to the following operation sequence.
(5) PIC18F4550
USB control chip. Sets up AK4618 registers from PC via USB port.
(6) SW1
DIP type switch. Sets clock and audio format of AK4118A. DIF[2:0] used to set audio interface format and
OCKS[1:0] used to master clock frequency. Please refer to Table 3. SW1 Setting, Table 4. Audio format, Table 5.
Master Clock Frequency Select for details.
(7) SW2
Toggle type switch. Power-down switch for AK4118A.
(8) SW3
Toggle type switch. Power-down switch for AK4618. Reset board by bringing down SW2 once upon power-up.
(9) PORT3 (6-pin header)
DSP port. Input/output MCLK, BICK, LRCK
(10) PORT4 (12-pin header)
DSP port. Input SDTI1, SDTI2, SDTI3, SDTI4, SDTI5, SDTI6.
(11) PORT5 (6-pin header)
DSP port. Output SDTO1, SDTO2, SDTO3
(12) EXT (RCA jack)
Input external clock source.
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Evaluation Board Manual
 Operation sequence
[1] Power supply line settings
[2] Jumper pins settings
[3] DIP switches settings
[4] Toggle switches settings
[5] LED indication
[6] Register control (Serial control)
[7] Evaluation modes
Refer to the following pages for details.
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[1] Power Supply Line Settings
Red
Voltage
Range
+9+12V
Typ
Voltages
+12V
AVDD1
Yellow
+3.0+3.6V
+3.3V
AVDD2
Yellow
+3.0+3.6V
TVDD
Yellow
+3.0+3.6V
D3.3V
Yellow
+3.0+3.6V
AVSS
DGND
Black
Black
0V
0V
Name
Color
+12V
Function
Comments
Regulator power
supply
OPAmp +terminal
power supply
AK4618 AVDD1
Should always be connected
3.3V regulator is used (JP30
= REG) by default, when
jack is used
(JP30=AVDD1).
+3.3V
AK4618 AVDD2
3.3V regulator is used (JP31
= REG) by default, when
jack is used
(JP31=AVDD2).
+3.3V
AK4618 TVDD
3.3V regulator is used (JP32
= REG) by default, when
jack is used (JP32=TVDD).
+3.3V
AK4118A 3.3V,
3.3V regulator is used (JP33
Logic IC power
= REG) by default, when
supply
jack is used (JP33=D3V).
0V
Analog ground
Should always be connected
0V
Digital ground
Should always be connected
Table 1. Power supply line setting
Default
Settings
+12V
REG
REG
REG
REG
0V
0V
Note 1. Each power supply should be powered up while PDN pin = “L”. The PDN pin may be brought to “H” after all
power supplies are powered up. Do not turn off AK4618 while surrounding devices are still powered on and I2C bus is in
use.
<Operation procedure>
1) Connect power supply as above.
2) Set up jumper pin and evaluation mode (See below for details)
3) Power-up
Reset AK4618 once by bringing SW3 “L” upon power up.
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[2] Jumper Pin Settings
1
IN1N
JP
No.
JP1
2
IN1/IN1P
JP3
Single
Select Single-ended/Differential input.
Lch Analog Positive input to AK4618 (U1)
Single: Single-ended input (default)
Diff: Differential Input
3
IN2N
JP2
Open
Select Single-ended/Differential input.
Rch Analog Negative input to AK4618 (U1)
Open: Single-ended input (default)
Short: Differential Input
4
IN2/IN2P
JP4
Single
Select Single-ended/Differential input.
Rch Analog Positive input to AK4618 (U1)
Single: Single-ended input (default)
Diff: Differential Input
5
IN3N
JP5
Open
Select Single-ended/Differential input.
Lch Analog Negative input to AK4618 (U1)
Open: Single-ended input (default)
Short: Differential Input
6
IN3/IN3P
JP7
Single
Select Single-ended/Differential input.
Lch Analog Positive input to AK4618 (U1)
Single: Single-ended input (default)
Diff: Differential Input
7
IN4N
JP6
Open
Select Single-ended/Differential input.
Rch Analog Negative input to AK4618 (U1)
Open: Single-ended input (default)
Short: Differential Input
8
IN4/IN4P
JP8
Single
Select Single-ended/Differential input.
Rch Analog Positive input to AK4618 (U1)
Single: Single-ended input (default)
Diff: Differential Input
9
IN5N
JP9
Open
Select Single-ended/Differential input.
Lch Analog Negative input to AK4618 (U1)
Open: Single-ended input (default)
Short: Differential Input
10
IN5/IN5P
JP11
Single
Select Single-ended/Differential input.
Lch Analog Positive input to AK4618 (U1)
Single: Single-ended input (default)
Diff: Differential Input
11
IN6N
JP10
Open
12
IN6/IN6P
JP12
Single
Select Single-ended/Differential input.
Rch Analog Negative input to AK4618 (U1)
Open: Single-ended input (default)
Short: Differential Input
Select Single-ended/Differential input.
Rch Analog Positive input to AK4618 (U1)
Single: Single-ended input (default)
Diff: Differential Input
No
Names
Default
Functions
Open
Select Single-ended/Differential input.
Lch Analog Negative input to AK4618 (U1)
Open: Single-ended input (default)
Short: Differential Input
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13
BICK-SEL
JP13
DIR
Select input to AK4618 (U1) BICK Buffer
64fs: 64fs divider
32fs: 32fs divider
DIR: DIR-AK4118A-BICK (default)
PORT3: PORT3-BICK
Open: No signal
14
BICK-PHAS
E
JP14
THR
Select polarity (non-inverted output / inverted output) of BICK_SEL outputs.
THR: Non-inverted output. (default)
INV: Inverted output.
15
LRCK-SEL
JP15
DIR
16
MCKI-SEL
JP25
DIR
17
SDTI6-SEL
JP16
DIR
Select input to AK4618 (U1) LRCK Buffer
1fs: 1fs divider
DIR: DIR-AK4118A-BICK (default)
PORT3: PORT3-BICK
Open: No signal
PORT3: PORT3-MCKI
EXT: External MCLK (JACK: J19) input
GND: GND
DIR: DIR-AK4118A-MCKI (default)
Select input to AK4618 (U1) SDTI6
DIR: DIR-AK4118A-SDTO (default)
PORT4: PORT4-SDTI6
GND: Digital ground
18
SDTI5-SEL
JP18
DIR
Select input to AK4618 (U1) SDTI5
DIR: DIR-AK4118A-SDTO (default)
PORT4: PORT4-SDTI5
GND: Digital ground
19
SDTI4-SEL
JP21
DIR
Select input to AK4618 (U1) SDTI4
DIR: DIR-AK4118A-SDTO (default)
PORT4: PORT4-SDTI4
GND: Digital ground
20
SDTI3-SEL
JP22
DIR
21
SDTI2-SEL
JP23
DIR
Select input to AK4618 (U1) SDTI3
DIR: DIR-AK4118A-SDTO (default)
PORT4: PORT4-SDTI3
GND: Digital ground
Select input to AK4618 (U1) SDTI3
DIR: DIR-AK4118A-SDTO (default)
PORT4: PORT4-SDTI2
GND: Digital ground
22
SDTI1-SEL
JP24
DIR
Select input to AK4618 (U1) SDTI3
DIR: DIR-AK4118A-SDTO (default)
PORT4: PORT4-SDTI1
GND: Digital ground
23
EXT
JP27
Open
Open: No input (default)
Short: External MCLK(JACK: J19) input
24
DAUX-SEL
JP28
25
PIC
JP29
SDTO1 Select input to DIT:AK4118A (U8) DAUX
SDTO1: AK4618A-SDTO1 (default)
SDTO2: AK4618A-SDTO2
SDTO3: AK4618A-SDTO2
Open
Connect PIC microchip connector
VDD(pin.1),MCLR(pin.2),PGD(pin.3),PGC(pin.4),GND(pin.5)
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26
AVDD-SEL
JP30
REG
Select power supply to AVDD1
REG: Regulator T2 (default)
(When regulator “T2” is selected, power supply jack “AVDD1” should be
open.)
JACK: Power supply jack J21 “AVDD1”
27
AVDD2-SEL
JP22
REG
Select power supply to AVDD2
REG: Regulator T2 (default)
(When regulator “T2” is selected, power supply jack “AVDD2” should be
open.)
JACK: Power supply jack J22 “AVDD2”
28
TVDD-SEL
JP23
REG
Select power supply to TVDD
REG: Regulator T2 (default)
(When regulator “T2” is selected, power supply jack “TVDD” should be
open.)
JACK: Power supply jack J23 “TVDD”
29
D3.3V-SEL
JP24
REG
Select power supply to D3.3V
REG: Regulator T3 (default)
(When regulator “T3” is selected, power supply jack “D3.3V” should be
open.)
JACK: Power supply jack J24 “D3.3V”
30
GND
JP34
Short
Select connection / separation between analog ground and digital ground.
Open: Separate analog ground from digital ground
Short: Connect analog ground to digital ground (default)
Table 2. Main board Jumper pin setting
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[3] DIP switch setting
(1). Setting for SW1 (Sets AK4118A (U8) audio format and master clock setting)
No. Switch Name
Function
1
DIF0
Set-up of DIF0 pin. (in parallel mode)
2
DIF1
Set-up of DIF1 pin. (in parallel mode)
3
DIF2
Set-up of DIF2 pin. (in parallel mode)
4
OCKS1
Set-up of OCKS1 pin. (in parallel mode)
5
OCKS0
Set-up of OCKS0 pin. (in parallel mode)
Table 3. SW1 Setting
Mode
DIF2 pin
(SW1_1)
DIF2 bit
DIF1 pin
(SW1_2)
DIF1 bit
DIF0 pin
(SW1_3)
DIF0 bit
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
OCKS1 pin
(SW1_4)
OCKS1 bit
OCKS0 pin
(SW1_5)
OCKS0 bit
0
0
1
1
0
1
0
1
DAUX
SDTO
LRCK
default
H
L
H
L
L
BICK
I/O
24bit, Left
16bit, Right
justified
justified
24bit, Left
18bit, Right
justified
justified
24bit, Left
20bit, Right
justified
justified
24bit, Left
24bit, Right
justified
justified
24bit, Left
24bit, Left
justified
justified
24bit, I2S
24bit, I2S
24bit, Left
24bit, Left
justified
justified
24bit, I2S
24bit, I2S
Table 4. Audio format
(X’tal)
MCKO1
MCKO2
256fs
256fs
256fs
256fs
256fs
128fs
512fs
512fs
256fs
128fs
128fs
64fs
Table 5. Master Clock Frequency Select
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I/O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
L/H
O
64fs
O
H/L
I
64-128fs
I
L/H
I
64-128fs
I
default
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
default
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[4] Toggle switch settings
SW2, SW3 Settings
SW2
4118-PDN
SW3
4618-PDN
Power down switch for DIR/T: AK4118A (U8).
Reset AK4118A (U8) once by brining SW2 to “L” once upon power-up.
Keep “H” when AK4118A is in use; keep “L” when AK4118A is not in use.
Power down switch for AK4618 (U1).
Reset AK4618 (U1) once by brining SW3 to “L” once upon power-up.
Keep “H” during normal operation.
Table 6. Toggle switch settings
[5] LED
LE1 Indication
LE1
INT0
DIR: AK4118A (U8) INT0 pin output. Turns on when DIR: AK4118A (U8) is unlocked
Table 7. LED Indication
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[6] Evaluation modes
(1) ADC (Analog  Digital): Stereo ADC
(2) DAC (Digital  Analog)
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(1) ADC (Analog  Digital)
 Toggle switch setting:
SW2
SW3
H
L→H
AK4118A(U8) : Used
AK4618(U1) : Used
Table 8. Toggle switch setting
 Power management of ADC
Set Addr: 00H = “7F” to release Internal timing reset and power on ADC. Other control register settings are
default.
RSTN bit: Internal timing reset
0: Reset.
1: Normal operation (default)
PMADC bit: Power management of mono-stereo
0: All ADC’s power-down
1: Normal operation (default)
PMADC12/PMADC34/PMADC56 bit: Power management of ADC1-6 (0: Power-down, 1: Normal operation)
PMADC12 bit: Power management control of ADC1 and ADC2
PMADC34 bit: Power management control of ADC3 and ADC4
PMADC56 bit: Power management control of ADC5 and ADC6
Addr
00H
Register Name
Power Management
R/W
Default Setting
D7
MS
D6
PMMB
D5
PMADC
D4
PMDAC
D3
PMADC56
D2
PMADC34
D1
PMADC12
D0
RSTN
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Table 9. Addr 00H control register setting
 Analog Input Mode Selector for ADC
DIE6-1 bit: ADC Input Mode Table
DIEx bit
Input Mode Selector
INx Single-ended Input.(default)
0
Single-ended input to the INx pin.
INx Differential Input.
1
Differential input to the INxP and INxN
pins.
Table 10.Input Mode Selector for ADC
Addr
13H
Register Name
Input Selector
D7
0
D6
0
D5
DIE6
D4
DIE5
D3
DIE4
D2
DIE3
D1
DIE2
D0
DIE1
R/W
RD
RD
R/W
R/W
R/W
R/W
R/W
R/W
Default Setting
0
0
0
0
0
0
0
0
Table 11. Addr 13H control register setting
 For Differential Input Select for Amp. (DIE6-1 = “1”):
Change to following jumper setting:
JP1 (IN1N)
= Short ,
JP3 (IN1/IN1P) = Diff
JP2 (IN2N)
= Short ,
JP4 (IN2/IN2P) = Diff
JP5 (IN3N)
= Short ,
JP7 (IN3/IN3P) = Diff
JP6 (IN4N)
= Short ,
JP8 (IN4/IN4P) = Diff
JP9 (IN5N)
= Short ,
JP11(IN5/IN5P) = Diff
JP10 (IN6N)
= Short ,
JP12 (IN6/IN6P) = Diff
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(2) DAC (Digital  Analog)
 Toggle switch setting:
SW2
SW3
H
L→H
AK4118A(U8) : Used
AK4618(U1) : Used
Table 12. Toggle switch setting
 Power management of DAC
Set Addr: 00H = “7F” to release Internal timing reset and power on DAC. Other control register settings are default.
RSTN bit: Internal timing reset
0: Reset.
1: Normal operation (default)
PMDAC bit: Power management of DAC1-6
0: All DAC’s power-down. PMDA1-6 bits are invalid.
1: Normal operation (default). PMDA1-6 bits are valid.
Addr
00H
Register Name
Power Management
R/W
Default Setting
D7
D6
D5
D4
D3
D2
D1
D0
MS
PMMB
PMADC
PMDAC
PMADC56
PMADC34
PMADC12
RSTN
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Table 13. Addr 00H control register setting
PMDA6-1 bit: Power management of DAC 1-6 (0: Power-down, 1: Normal operation)
PMDA1 bit: Power management control of DAC1
PMDA2 bit: Power management control of DAC2
PMDA3 bit: Power management control of DAC3
PMDA4 bit: Power management control of DAC4
PMDA5 bit: Power management control of DAC5
PMDA6 bit: Power management control of DAC6
Addr
01H
Register Name
Power Management 2
R/W
Default Setting
D7
D6
D5
D4
D3
D2
D1
D0
0
0
PMDA3
PMDA2
PMDA1
RD
0
PMDA5
R/W
PMDA4
RD
0
PMDA6
R/W
1
1
R/W
1
R/W
1
R/W
1
R/W
1
Table 14. Addr 01H control register setting
*Only the DAC bit being used should be powered on for best results.
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Control Software Manual
 Set-up evaluation board and control software
1. Set up AKD4618-A evaluation board according to above instructions.
2. Connect PC with AKD4618-A evaluation board by USB cable (included in package).
The board is recognized as HID (Human Interface Device) on the PC.
When it can not be recognized correctly please reconnect Evaluation board to PC with USB cable.
[Support OS]
Windows XP / Vista / 7 (32bit) (XP compatible mode is recommended for Vista / 7)
64bit OS’s are not supported.
3. Insert the CD-ROM labeled “AKD4618-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive, double-click on “akd4618-a.exe” and set up the control program.
5. Evaluate according to the following.
 Operation flow
1.
Set up control program as above and open control program.
The following operation screen will be shown. (Default setting)
Figure 3. Control software window
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2.
Click the “Write” button on right side of Addr 00H register.
Figure 4. Register set window
3.
Input dummy command settings and click “OK” to write dummy command to AK4618.
The following No Ack error message will pop up. Click “OK”.
Figure 5. No ack message window
4.
Input registers accordingly into dialog box to evaluate AK4618.
 Button Functions
1. [Port Reset]
2. [Write Default]
3. [All Write]
4. [All Read]
5. [Save]
6. [Load]
7. [All Reg Write]
8. [Data R/W]
9. [Read]
10. [Close]
:
:
:
:
:
:
:
Set up USB interface board (AKDUSBIF-B).
Initialize all register setting.
Write all registers currently displayed.
Read all register setting.
Save the current register setting to .akr file.
Load register setting from saved .akr file.
Opens “All Register Write” dialog box. (see Dialog boxes below)
: Opens “Data Read/Write” dialog box . (see Dialog boxes below)
: Read and display current register setting in register window (on right side of main window).
Different from [All Read] as it does not reflect to the register map.
: Close Control Software window.
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 Dialog boxes
1. [All Register Write]: Dialog box to write register setting files
Clicking the [All Reg Write] button in the main window opens the dialog box below.
Multiple register setting files created by the [SAVE] button can be set and applied.
Figure 6. Window of [All Reg Write]
<Operation flow>
(1) Click [Open(left) Button.
(2) Select file (*.akr) and Click [Open] Button. Up to 10 files can be selected.
(3) Click [Write] to write each file. [Write ALL] writes all files selected.
Button Functions:
1. [Open (left)] :
2. [Write]
:
3. [Write ALL] :
4. [Help]
:
5. [Save]
:
6. [Open (right)] :
7. [Close]
:
Select register setting file (*.akr).
Write register setting file in textbox.
Write all register setting files selected. Write is executed in descending order.
“Help” window pops up.
Save the current register map setting (*.mar).
Load register map setting file (*.mar ).
Close dialog box.
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2. [Data Read/Write]: Dialog box to manually enter register setting
Click the [Data R/W] button in the main window to open the data read/write dialog box.
Data manually entered into Data box is written to the specified address.
Figure 7. Window of [Data R/W]
Textbox Functions:
[Address] : Input register address in 2 hexadecimal digits.
[Data]
: Input register data in 2 hexadecimal digits.
[Mask]
: Input mask data in 2 hexadecimal digits. This value is AND-ed with input data.
Button Functions:
[Write]
: Writes data generated from [Data] and [Mask] to register specified in [Address]
[Read]
: Displays register data specified in [Address] in [Read Data] box in hexadedimal.
[Close]
: Closes dialog box. To cancel a process close the dialog box without writing
※ Register map updated after [Write] and [Read] operation.
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Tab Functions
1. [REG]: Register Map
Register data is indicated on the register map. Each bit on the register map is a push-button switch.
Button DOWN and red lettering indicates “1” and button UP with blue lettering indicates “0”.
Buttons with “---“are undefined in the datasheet.
Figure 8. [REG] window (REG 0H-FH)
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Figure 9. [REG] window (REG 10H-1FH)
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2. [Tool]: Testing Tools
This tab screen is for the evaluation testing tool.
Click button for each testing tool.
Figure 10. [Tool] window
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Measurement Results
[Measurement condition]
・ Measurement unit
・ MCKI
・ BICK
・ fs
・ Bit
・ Measurement Mode
・ Power Supply
: Audio Precision, SYS-2722 (No.00069)
: 256fs (12.288MHz)
: 64fs
: 48kHz
: 24bit
: ADC @ Slave Mode / DAC @ Slave Mode
: +12V=12V, GND
AVDD1=AVDD2=3.3V (Regulator), TVDD=3.3V (Regulator)
・ Input Frequency
: 1kHz
・ Measurement Frequency : 20 ~ 20kHz @48kHz
・ Temperature
: Room
[Measurement Results]
1. ADC（Single-ended Inputs）
Result
Unit
Lch
Rch
S/(N+D) fs = 48kHz (-1dBFS)
DR
fs = 48kHz (-60dBFS, A-Weighted)
S/N
fs = 48kHz (A-weighted)
Stereo ADC : AIN2L/R => ADC => SDTO2
89.0
98.1
98.2
89.0
98.0
98.0
dB
dB
dB
S/(N+D) fs = 48kHz (-1dBFS)
DR
fs = 48kHz (-60dBFS, A-Weighted)
S/N
fs = 48kHz (A-weighted)
Stereo ADC : AIN3L/R => ADC => SDTO3
89.3
98.0
98.1
89.1
98.0
98.1
dB
dB
dB
S/(N+D)
DR
S/N
88.9
98.0
98.1
88.9
98.0
98.1
Stereo ADC : AIN1L/R => ADC => SDTO1
fs = 48kHz (-1dBFS)
fs = 48kHz (-60dBFS, A-Weighted)
fs = 48kHz (A-weighted)
dB
dB
dB
2. ADC（Differential Inputs）
Result
Unit
Lch
Rch
S/(N+D) fs = 48kHz (-1dBFS)
DR
fs = 48kHz (-60dBFS, A-Weighted)
S/N
fs = 48kHz (A-weighted)
Stereo ADC : AIN2L/R => ADC => SDTO2
89.1
97.7
97.7
89.0
98.6
98.6
dB
dB
dB
S/(N+D) fs = 48kHz (-1dBFS)
DR
fs = 48kHz (-60dBFS, A-Weighted)
S/N
fs = 48kHz (A-weighted)
Stereo ADC : AIN3L/R => ADC => SDTO3
89.4
98.8
99.1
89.1
98.6
98.7
dB
dB
dB
S/(N+D)
DR
S/N
89.1
98.7
99.1
88.8
98.1
98.8
dB
dB
dB
Stereo ADC : AIN1L/R => ADC => SDTO1
fs = 48kHz (-1dBFS)
fs = 48kHz (-60dBFS, A-Weighted)
fs = 48kHz (A-weighted)
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3. DAC
Result
Lch
Rch
Unit
DAC1 : SDTI1 => DAC1 => L/ROUT1
S/(N+D)
fs = 48kHz (0dBFS)
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
DAC2 : SDTI2 => DAC2 => L/ROUT2
S/(N+D)
fs = 48kHz (0dBFS)
97.5
99.0
dB
106.9
107.0
106.9
107.0
dB
dB
98.2
97.5
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
DAC3 : SDTI3 => DAC3 => L/ROUT3
106.9
107.0
106.9
107.0
dB
dB
S/(N+D)
98.2
97.5
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
DAC4 : SDTI4 => DAC4 => L/ROUT4
106.9
107.0
106.9
107.0
dB
dB
S/(N+D)
98.8
98.4
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
DAC5 : SDTI5 => DAC5 => L/ROUT5
106.9
107.0
106.9
107.0
dB
dB
S/(N+D)
97.5
97.6
dB
DR
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
S/N
fs = 48kHz (A-weighted, 20kHz SPCL)
DAC6 : SDTI6 => DAC6 => L/ROUT6
106.9
107.0
106.9
107.0
dB
dB
S/(N+D)
fs = 48kHz (0dBFS)
98.3
98.6
dB
DR
S/N
fs = 48kHz (-60dBFS, A-Weighted, 20kHz SPCL)
fs = 48kHz (A-weighted, 20kHz SPCL)
106.9
107.0
106.9
107.0
dB
dB
fs = 48kHz (0dBFS)
fs = 48kHz (0dBFS)
fs = 48kHz (0dBFS)
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[Plot Data]
1. ADC (Single-ended Inputs)
ADC (fs = 48kHz); IN1/IN2(Single-ended) => ADC => SDTO
AK4618 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 11. ADC (Single-ended) – FFT (-1dBFS) [fs = 48kHz]
AK4618 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 12. ADC (Single-ended) – FFT (-60dBFS) [fs = 48kHz]
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AK4618 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, no signal]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 11. ADC (Single-ended) – FFT (No Signal) [fs = 48kHz]
AK4618 THD+N vs Amplitude Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz]
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
F
S
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 12. ADC (Single-ended) – THD+N vs. Amplitude (Input Level) [fs = 48kHz]
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AK4618 THD+N vs Input Frequency Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
F
S
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 13. ADC (Single-ended) – THD+N vs. Input Frequency [fs = 48kHz]
AK4618 Linearity Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz]
+0
T TT
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 14. ADC (Single-ended) – Linearity [fs = 48kHz]
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AK4618 Frequency Response Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
-0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 15. ADC (Single-ended) – Frequency Response [fs = 48kHz]
AK4618 Crosstalk Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
-80
T TT
T
-85
-90
-95
-100
-105
-110
d
B
-115
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
5k
Hz
Figure 16. ADC (Single-ended) – Crosstalk [fs = 48kHz]
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2.
ADC (Differential Inputs)
ADC (fs = 48kHz); IN1P/IN2P,IN1N/IN2N(Differential) => ADC => SDTO
AK4618 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure Figure 17. ADC (Differential) – FFT (-1dBFS) [fs = 48kHz]
AK4618 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 18. ADC (Differential) – FFT (-60dBFS) [fs = 48kHz]
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AK4618 FFT Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz, no signal]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 19. ADC (Differential) – FFT (No Signal) [fs = 48kHz]
AK4618 THD+N vs Amplitude Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz]
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
F
S
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 20. ADC (Differential) – THD+N vs. Amplitude (Input Level) [fs = 48kHz]
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AK4618 THD+N vs Input Frequency Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
F
S
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 21. ADC (Differential) – THD+N vs. Input Frequency [fs = 48kHz]
AK4618 Linearity Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, fin=1kHz]
+0
TT
T
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 22. ADC (Differential) – Linearity [fs = 48kHz]
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AK4618 Frequency Response Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
-0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
d
B
F
S
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 23. ADC (Differential) – Frequency Response [fs = 48kHz]
-70
AK4618 Crosstalk Stereo ADC (IN1/IN2:L/R)
[fs=48kHz, -1dBFS]
T
-75
-80
-85
-90
-95
-100
-105
d
B
-110
-115
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 24. ADC (Differential) – Crosstalk [fs = 48kHz]
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3.
DAC (SDTI1 => L/ROUT1)
DAC1 (fs = 48kHz); SDTI1 => DAC1 => L/ROUT1
AK4618 FFT Single-end DAC (L/ROUT1)
[fs=48kHz, fin=1kHz, 0dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 25. DAC1 – FFT (0BFS) [fs = 48kHz]
AK4618 FFT Single-end DAC (L/ROUT1)
[fs=48kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 26. DAC1 – FFT (-60dBFS) [fs = 48kHz]
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AK4618 FFT Single-end DAC (L/ROUT1)
[fs=48kHz, fin=1kHz, no signal]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 27. DAC1 – FFT (No Signal) [fs = 48kHz]
AK4618 THD+N vs Amplitude Single-end DAC (L/ROUT1)
[fs=48kHz, fin=1kHz] 20kHz SPCL
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
r
A
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 28.DAC1 – THD+N vs. Amplitude (Input Level) [fs = 48kHz]
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AK4618 THD+N vs Input Frequency Single-end DAC (L/ROUT1)
[fs=48kHz, 0dBFS] 20kHz SPCL
-70
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
d
B
r
A
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 29. DAC1 – THD+N vs. Input Frequency [fs = 48kHz]
AK4618 Linearity Single-end DAC (L/ROUT1)
[fs=48kHz,fin=1kHz]
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 30. DAC1 – Linearity [fs = 48kHz]
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[AKD4618-A]
AK4618 Frequency Response Single-end DAC (L/ROUT1)
[fs=48kHz, 0dBFS]
+1
+0.9
+0.8
+0.7
+0.6
+0.5
+0.4
+0.3
+0.2
d
B
r
A
+0.1
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 31. DAC1 – Frequency Response [fs = 48kHz]
AK4618 Crosstalk Single-end DAC (L/ROUT1)
[fs=48kHz, 0dBFS]
-80
-85
-90
-95
-100
-105
-110
d
B
-115
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
Hz
Figure 32. DAC1 – Crosstalk [fs = 48kHz]
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[AKD4618-A]
REVISION HISTORY
Date
(yy/mm/dd)
13/09/04
Manual
Revision
KM113500
Board
Revision
0
Reason
Page
Contents
First edition
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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R1
R2
R3
R4
R5
R6
R7
51
51
51
51
51
51
51
1
AVDD2
TVDD
SDTO1
2
SDTO2
SDA
SCL
SDTO3
3
MCLK
4
BICK
5
AVSS
AVSS
D
D
51
SDTI6/TDMI
2
R10
51
SDTI5
VSS2
37
AVDD2
38
39
37
38
C5
0.1u
39
SDTO1
42
C4
0.1u
40
SDTO2
43
REGO
SDTO3
44
+
SDA
45
41
SCL
46
MCLK
47
48
3
LRCK
1
SDTI6/TDMI
2
SDTI5
3
SDTI4
4
SDTI3
5
SDTI2
6
AVDD2
VSS2
TVDD
VSS3
REGO
SDTO1
SDTO2
SDTO3
SDA
SCL
MCLK
BICK
51
1
R9
C2
1.0u
+
R8
C3
1.0u
CN1
48pin_3
CN2
LRCK
C1
1.0u
+
BICK
TP1
TVDD
40
41
VSS3
42
43
44
45
46
47
48
48pin_4
LRCK
LOUT1
SDTI6/TDMI
ROUT1
SDTI5
LOUT2
36
LOUT1
35
ROUT1
34
LOUT2
33
ROUT2
32
LOUT3
31
ROUT3
30
LOUT4
29
ROUT4
28
LOUT5
27
ROUT5
26
LOUT6
25
ROUT6
36
LOUT1
35
ROUT1
34
LOUT2
C
C
R11
51
SDTI4
4
R12
51
SDTI3
5
R13
51
SDTI2
6
R14
51
7
PDN
8
IN1N
9
IN1/IN1P
10
SDTI1
7
PDN
8
IN1N-MICBIAS
C6
short
9
+
IN1N
IN1/IN1P
+
SDTI1
C7
short
10
short
11
SDTI4
ROUT2
SDTI3
LOUT3
SDTI2
ROUT3
U1
AK4618VQ
SDTI1
LOUT4
PDN
ROUT4
IN1N
LOUT5
IN1/IN1P
ROUT5
IN2N
LOUT6
IN2/IN2P
ROUT6
33
ROUT2
32
LOUT3
31
ROUT3
30
LOUT4
29
ROUT4
28
LOUT5
27
ROUT5
26
LOUT6
25
ROUT6
IN1P-MICBIAS
IN6/IN6P
IN6N
IN5/IN5P
IN3/IN3P
IN3N
IN5N
12
VSS1
short
AVDD1
C9
IN4/IN4P
IN2/IN2P
IN2P-MICBIAS
IN4N
12
+
IN2/IN2P
C8
IN2N
+
11
VCOM
B
IN2N-MICBIAS
IN2N
MICBIAS
B
23
24
short
22
C15 +
short
21
C11 +
short
20
C14 +
short
19
16
C10 +
18
15
17
14
CN3
13
48pin_1
C17 +
C12 +
C13 +
C18 +
short
short
short
short
IN6/IN6P
IN6P-MICBIAS
24
IN6N-MICBIAS
IN6N
23
IN5/IN5P
IN5P-MICBIAS
22
IN5N
21
IN5N-MICBIAS
A
Title
48pin_2
4
3
Size
A3
IN6/IN6P
AVSS
IN6N
- 36-
IN5N
<AKD4618-A>
IN5/IN5P
AVSS
5
20
open
TP2
VSS1
open
R26
C21
1.0u
19
R25
IN6N-MICBIAS
+
IN5N-MICBIAS
CN4
AVDD1
open
18
open
R24
AVDD1
R23
IN4N-MICBIAS
17
IN3N-MICBIAS
IN4/IN4P
open
IN4P-MICBIAS
R22
16
IN2N-MICBIAS
IN4/IN4P
open
IN4N
R21
IN4N-MICBIAS
IN1N-MICBIAS
15
A
C19
1.0u
1.0u
IN4N
open
IN6P-MICBIAS
IN3/IN3P
R20
IN5P-MICBIAS
C16
0.1u
C20
+
IN3P-MICBIAS
open
14
open
R19
IN3N
R18
IN4P-MICBIAS
IN3/IN3P
open
IN3N
open
R17
IN3P-MICBIAS
IN3N-MICBIAS
open
R16
13
R15
IN2P-MICBIAS
+
IN1P-MICBIAS
VCOM
MICBIAS
Date:
2
Document Number
<AK4618>
Wednesday, February 20, 2013
Rev
<0>
Sheet
1
1
of
7
5
4
3
LOUT1
2
1
ROUT1
J1
LOUT1
1
LOUT1
R27
open
D
C24
open
R28
100k
1.0u
J2
ROUT1
C23
2
3
4
5
+
+
C22
1
ROUT1
LOUT1
R29
open
C25
open
2
3
4
5
R30
100k
1.0u
ROUT1
D
AVSS
AVSS
AVSS
+
C26
1
LOUT2
R31
open
C27
open
R32
100k
1.0u
AVSS
AVSS
AVSS
2
3
4
5
LOUT2
R33
open
C29
open
LOUT3
AVSS
R36
100k
AVSS
J6
ROUT3
C31
2
3
4
5
1
ROUT3
LOUT3
R37
open
AVSS
C33
open
AVSS
+
1
LOUT4
C36
open
R39
100k
1.0u
+
2
3
4
5
R40
open
C37
open
AVSS
+
1
LOUT5
C40
open
R44
100k
1.0u
AVSS
AVSS
AVSS
ROUT5
J10
ROUT5
C39
2
3
4
5
+
J9
LOUT5
C38
R43
open
AVSS
ROUT4
AVSS
LOUT5
B
2
3
4
5
R42
100k
1.0u
AVSS
AVSS
1
ROUT4
LOUT4
C
J8
ROUT4
C35
J7
LOUT4
ROUT3
AVSS
ROUT4
C34
2
3
4
5
R38
100k
1.0u
AVSS
LOUT4
R41
open
ROUT2
AVSS
+
+
1
AVSS
ROUT3
J5
LOUT3
1.0u
2
3
4
5
R34
100k
1.0u
AVSS
C30
C32
open
1
ROUT2
LOUT3
R35
open
J4
ROUT2
C28
AVSS
C
AVSS
ROUT2
J3
LOUT2
+
AVSS
LOUT2
1
ROUT5
LOUT5
R45
open
AVSS
C41
open
AVSS
LOUT6
R46
100k
1.0u
B
2
3
4
5
AVSS
ROUT5
AVSS
ROUT6
J11
LOUT6
1
LOUT6
R47
open
C44
open
AVSS
R48
100k
1.0u
AVSS
J12
ROUT6
C43
2
3
4
5
+
+
C42
LOUT6
1
ROUT6
R49
open
AVSS
C45
open
R50
100k
1.0u
AVSS
AVSS
2
3
4
5
ROUT6
AVSS
A
A
Title
<AKD4618-A>
Size
A3
- 37-
Date:
5
4
3
2
Document Number
<Analog OUT>
Rev
<0>
Wednesday, February 20, 2013
Sheet
1
2
of
7
5
4
3
2
1
AREA: SHORTEST WIRING
JP1
1.0u
2
3
4
5
C51
open
1
Diff
2
+12V
R60
+
JP3
8
C57
open
R64
1k
Single
R66
1k
4
AVSS
6
R62
5
2k
U3B
LME49720MA
D
IN2/IN2P
C55
Diff
7
JP4
IN2/IN2P
1.0u
Single
C59
open
C63
0.1u
AVSS
TP4
C65
10u
+
R61
4.7k
1
+12V
+
C62
10u
TP3
AVSS
C64
0.1u
U3A
LME49720MA
AVSS
open
C61
0.1u
3
2k
IN1/IN1P
1.0u
C58
4
IN1/IN1P
C54
7
+12V
+
C60
10u
C52
open
AVSS
8
5
2k
8
R59
U2B
LME49720MA
IN2N
1.0u
8
4
6
AVSS
R65
1k
C53 68p
22u
AVSS
R58
4.7k
1
+
C56
open
R63
1k
-
2k
U2A
LME49720MA
+
R57
3
-
2
+12V
R55 4.7k
+
AVSS
Diff
R56
4.7k
Single
AVSS
D
R54
4.7k
C49
-
Single
IN2N
+
J14
IN2
+
C50 68p
22u
IN2
IN1N
4
R52 4.7k
JP2
C47
IN1N
+
R53
4.7k
+
Diff
1
+
2
3
4
5
R51
4.7k
C48
+
J13
IN1
-
C46
IN1
C66
0.1u
AVSS
+
AVSS
C67
10u
AVSS
AVSS
C68
AVSS
AVSS
AVSS
C69
AVSS
AVSS
+
+
1.0u
1.0u
IN3N
2
3
4
5
C76
open
8
+
4
IN3/IN3P
C78
Diff
7
R77
C81
open
R80
1k
Single
R82
1k
AVSS
R74
4.7k
1
6
5
2k
U5B
LME49720MA
IN4/IN4P
C79
Diff
7
C83
open
JP8
IN4/IN4P
1.0u
C87
0.1u
Single
AVSS
TP6
C89
10u
+
C
+12V
+
C86
10u
TP5
AVSS
C88
0.1u
U5A
LME49720MA
AVSS
open
C85
0.1u
3
2k
R78
+12V
+
C84
10u
2
+12V
JP7
IN3/IN3P
1.0u
C82
AVSS
R81
1k
C77
open
8
+
C80
open
5
2k
U4B
LME49720MA
+
-
R76
R79
1k
4
6
IN4N
IN4N
1.0u
AVSS
AVSS
R73
4.7k
1
8
4
U4A
LME49720MA
+
3
2k
-
R75
C75 68p
22u
+
2
+12V
R72
4.7k
R71 4.7k
Single
AVSS
AVSS
Diff
-
Single
R70
4.7k
C73
1
+
J16
IN4
4
C74 68p
22u
1.0u
IN4
8
+
R69
4.7k
R68 4.7k
JP6
C71
IN3N
+
C
R67
4.7k
C72
Diff
1
+
2
3
4
5
JP5
+
J15
IN3
-
C70
IN3
C90
0.1u
AVSS
+
AVSS
C91
10u
AVSS
AVSS
C92
AVSS
AVSS
AVSS
C93
AVSS
AVSS
+
+
1.0u
1.0u
JP9
2
3
4
5
C100
open
1
C99 68p
22u
4
2
+12V
R92
JP11
IN5/IN5P
1.0u
U7A
LME49720MA
R90
4.7k
1
6
R93
open
R98
1k
TP7
AVSS
+
C110
10u
5
2k
U7B
LME49720MA
IN6/IN6P
C103
Diff
7
JP12
IN6/IN6P
1.0u
Single
C107
open
AVSS
AVSS
+
3
2k
C105
open
R96
1k
Single
+12V
C109
0.1u
C112
0.1u
C101
open
AVSS
8
Diff
7
IN6N
1.0u
8
4
+
C108
10u
4
C106
AVSS
R97
1k
5
2k
IN5/IN5P
C102
+
R94
U6B
LME49720MA
8
6
8
R95
1k
R87 4.7k
AVSS
R89
4.7k
1
+
C104
open
-
3
2k
U6A
LME49720MA
+
R91
Diff
R88
4.7k
Single
-
2
+12V
IN6N
+
C97
AVSS
AVSS
R86
4.7k
+
Single
B
J18
IN6
+
C98 68p
22u
1.0u
IN6
IN5N
4
R84 4.7k
JP10
C95
IN5N
+
R85
4.7k
-
Diff
1
+
2
3
4
5
C96
R83
4.7k
+
J17
IN5
+
IN5
-
C94
B
+12V
C111
0.1u
AVSS
TP8
C113
10u
C114
0.1u
AVSS
+
AVSS
C115
10u
AVSS
AVSS
C116
AVSS
AVSS
AVSS
AVSS
C117
AVSS
+
+
1.0u
1.0u
A
A
Title
<AKD4618-A>
5
4
3
- 38-
Size
A2
Date:
2
Document Number
<AnalogIN>
Rev
<0>
Wednesday, February 20, 2013
1
Sheet
3
of
7
5
4
L1
1
GND
OUT
2
1
47uH
2
D3.3V
PORT1
VCC
3
D3.3V
3
C118
0.1u
2
1
PLRx
+
C119
10u
TP9
R99
51
C121
RX
D
+
DGND
D
10u
C122
DGND
R100
C120
0.1u
10k
1
2
10
9
8
7
6
D3.3V
H
3
38
37
INT1
R
AVDD
39
40
VCOM
41
VSS3
42
RX0
43
NC
44
RX1
45
TEST1
46
RX2
47
IPS0/RX4
INT0
NC
OCKS0/CSN/CAD0
DIF0/RX5
OCKS1/CCLK/SCL
36
INT0
35
OCKS0
34
OCKS1
SW1
4
L
TEST2
CM1/CDTI/SDA
33
D3.3V
C
5
6
OCKS0
OCKS1
7
DIF1/RX6
CM0/CDTO/CAD1
U8
VSS1
DGND
PDN
AK4118A
DIF2/RX7
32
XTI
31
4118-PDN
30
1
DIF2
DIF1
DIF0
OCKS1
OCKS0
1
2
3
4
5
C
VSS4
RX3
48
0.47u
C123
5p
C124
5p
5
4
3
2
1
X1
12.288MHz
IPS1/IIC
XTO
29
2
8
DGND
DGND
9
P/SN
DAUX
XTL0
MCKO2
XTL1
BICK
28
DAUX
RP1
47k (R-PACK5R)
10
11
27
26
DIR-BICK
25
LRCK
DIR-SDTO
24
MCKO1
23
22
VSS2
DVDD
SDTO
21
VOUT/GP7
20
UOUT/GP6
19
18
17
TX1/GP3
16
TX0/GP2
15
14
13
TVDD
NC/GP1
VIN/GP0
COUT/GP5
B
12
BOUT/GP4
B
0.1u
0.1u
+
D3.3V
C126
+
DIR-LRCK
C125
C127
10u
C128
10u
DIR-MCKI
DGND
A
PORT2
IN
VCC
GND
A
TP10
3
2
TX
C129
D3.3V
0.1u
1
Title
PLTx
<AKD4618-A>
DGND
- 39-
Size
A3
Date:
5
4
3
2
Document Number
<DIR/DIT>
Wednesday, February 20, 2013
Rev
<0>
Sheet
1
4
of
7
5
4
3
2
1
U9
D3.3V
D
16
8
C130
0.1u
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
VD
Q11
DGND Q12
RST
9
7
6
5
3
2
4
13
12
14
15
1
JP13
DIR-BICK
TP20
THR
BICK
BICK
INV
JP15
BICK-PHASE
TP21
BICK-SEL
4040-1fs
DIR
PORT3
DIR-LRCK
JP14
4040-64fs
4040-32fs
DIR
PORT3
LRCK
LRCK
D
LRCK-SEL
SDTI1
SDTI2
SDTI3
SDTI4
SDTI5
TP26
TP25
TP24
TP23
DGND
TP27
74HC4040
SDTI6/TDMI
11
CLK
TP22
10
JP16
D3.3V
DIR
PORT4
GND
DIR-SDTO
D3.3V
K
U10
R101
10k
1
3
A
D1
HSU119
L
H
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
C132
0.1u
C
SDTI6/TDMI
SDTI6-SEL
14
13
12
11
10
9
8
DGND
PORT4
C131
0.1u
LRCK
BICK
MCLK
INT0
74HC14
1k 2
1
DGND
DIR
PORT4
GND
DIR-SDTO
SDTI1
JP21
C
DIR
PORT4
GND
DIR-SDTO
DGND
SDTI4-SEL
4118-PDN
D3.3V
SDTI2
DGND
SDTI
DGND
DGND
SDTI4
SDTI3
SDTI5-SEL
CLK
INT0
SDTI5
JP18
SDTI6
SDTI5
SDTI4
SDTI3
SDTI2
SDTI1
PORT3
LE1
R102
2
SW2
AK4118-PDN
1
2
3
4
5
6
7
DGND
K
JP22
A
D2
HSU119
DIR-SDTO
PDN
R103
10k
DIR
PORT4
GND
SDTI3-SEL
H
C133
0.1u
2
3
4
5
SDTO2
SDTO3
TP28
SDTI1-SEL
J19
EXT
TP29
DGND
B
SDTO1
JP24
DIR
PORT4
GND
DIR-SDTO
TP30
SDTI2-SEL
DGND
MCLK
2
SW3
AK4618-PDN
JP23
DIR
PORT4
GND
DIR-SDTO
TP31
1
L
3
DGND
B
JP25
PORT3
EXT
GND
DIR
1
R104
DIR-MCKI
DGND
PORT5
51
MCKI-SEL
SDTO3
SDTO2
SDTO1
JP27
EXT
SDTO3
SDTO2
SDTO1
JP28
SDTO-SEL
SDTO3
SDTO2
SDTO1
DAUX
DGND
DAUX-SEL
DGND
MCLK
A
A
Title
<AKD4618-A>
- 40-
Size
A3
Date:
5
4
3
2
Document Number
<LOGIC>
Wednesday, February 20, 2013
Rev
<0>
Sheet
1
5
of
7
5
4
3
2
1
R108
D3.3V
100k
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
VDD0
6
VSS0
VDD1
MCLR_N/Vpp/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
18
PIC18F4550
TQFP 44-PIN
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
U13
OSC1/CLKI
OSC2/CLKO/RA6
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VUSB
32
35
36
PORT6
VUSB
DD+
GND
1
2
3
4
R117
R118
USB(B type)
0
0
42
43
44
1
SDA
5
VREF2
SCL2
SDA2
VREF1
SCL1
SDA1
10k
C138
2
R113
10k
0.1u
SCL
3
SCL
SDA
4
SDA
USB-RST
12
13
33
34
C
C144
R114
0.1u
100k
C145
38
39
40
41
2
3
4
5
6
GND
R112
7
0.1u
28
C142
0.1u
29
PIC
17
16
15
14
11
10
9
8
SCL
EN
D
DGND
1
DGND
C141
VSS1
1
2
3
4
5
DGND
B
7
R110
R111
5V => 3.3V
NC
NC
Vin
Vout
Vcont PCL
NC
GND
8
7
6
5
T1
TK73633AME
1
2
3
4
+
C
DGND
1u
JP29
SILK-SCREEN
1:VDD
2:MCLR
3:PGD
4:PGC
5:GND
+
C143
C140
10u
U12
SDA
SCL
10k
10k
8
C139
10u
PCA9306DP1
4.7k
2.2u
DGND
0.1u
TP45
TP44
R109
C137
D
C136
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
30
31
XTI
XTO
X2
20MHz
25
26
27
37
22p
C146
C147
22p
0.47u
DGND
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
DGND
19
20
21
22
23
24
R115
R116
51
51
SCL
SDA
B
PIC18F4550
PORT7
10
8
6
4
2
open
9
7 SCL R119
5 SDA R120
3
1
open
open
10pin-CTRL
DGND
A
A
Title
<AKD4618-A>
Size
A3
- 41-
Date:
5
4
3
2
Document Number
<PC-IF>
Wednesday, February 20, 2013
Rev
<0>
Sheet
1
6
of
7
5
4
3
2
1
TP32
AVDD1
JP30
REG
J21
AVDD1
J20
AVDD1
AVDD1
+12V
1
1
AVDD-SEL
D
C148
47u
+12V-->+3.3V
D
+
TP33
C149
T2
LT1963AEST-3.3
+
AVSS
AVDD2
JP31
1
IN
C151
0.1u
REG
C152
+
0.1u
AVDD2
AVDD2
J22
AVDD2
C153
AVDD2-SEL
47u
1
47u
OUT
3
2
+
C150
AVSS
GND
47u
AVSS
AVSS
AVSS
AVSS
AVSS
C154
47u
+
AVSS
TP34
TVDD
JP32
REG
TVDD
TVDD
J23
TVDD
TVDD-SEL
C
1
C
C155
47u
+
+12V-->+3.3V
TP35
AVSS
T3
LT1963AEST-3.3
D3.3V
C157
OUT
2
+
C156
IN
DGND
REG
C158
+
0.1u
0.1u
47u
3
DGND
DGND
DGND
D3.3V
D3.3V
C159
J24
D3.3V
47u
D3.3V-SEL
1
1
GND
JP33
DGND
C160
47u
+
B
B
DGND
TP36
AVSS
AVSS
AVSS
AVSS
AVSS
TP38
TP39
TP40
1
TP37
DGND
TP19
DGND
TP41
J26
AVSS
1
DGND
J25
DGND
TP42
+12V
TP43
+12V
JP34
GND
DGND
AVSS
A
A
Title
<AKD4618-A>
- 42-
Size
A3
Date:
5
4
3
2
Document Number
<POWER>
Wednesday, February 20, 2013
Rev
<0>
Sheet
1
7
of
7
- 43-
- 44-
- 45-
- 46-