AK4627VQ

[AKD4627-A]
AKD4627-A
Evaluation board Rev.1 for AK4627
GENERAL DESCRIPTION
The AKD4627-A is an evaluation board for the AK4627, a single chip CODEC that includes four channels
of ADC and six channels of DAC. The AKD4627-A also has the digital audio interface and can achieve the
interface with digital audio systems via opt-connector or BNC connector.
„ Ordering guide
AKD4627-A
--- AK4627 Evaluation Board
(Cable for connecting with printer port of IBM-AT compatible PC
and control software are packed with this.) This control software can’t operate
on Windows NT.
FUNCTION
• On-board analog output buffer circuit
• Compatible with 2 types of interface
- AK4118 (DIT&DIR) with optical output/input and BNC output/input
- Direct interface with AC3 decoder by 10pin header
• 10pin header for serial control interface
-12V +12V
Regulator AVDD DVDD TVDD GND
Regulator
+5V
LOUT1
ROUT1
+3.3V
LOUT2
ROUT2
Output
Buffer
BNC In
AK4118
LOUT3
ROUT3
AK4627
Opt In
(DIT&DIR)
Opt Out
BNC Out
AC3
LIN1+/LIN1
10pin Header
LIN1-
Control Data
LIN2+/LIN2
10pin Header
LIN2-
Figure 1 AKD4627-A Block Diagram
*Circuit diagram and PCB layout are attached at the end of this manual.
<KM102001>
2012/04
[AKD4627-A]
Evaluation Board Manual
„ Operation sequence
1) Set up the power supply lines.
(1-1) In case of using separate power supply lines <Default>
Set up the jumper pins.
JP82
JP83
JP84
AVDD
DVDD
TVDD
REG JACK REG JACK REG JACK
Set up the power supply lines.
Name
+12V
-12V
AVDD
DVDD
TVDD
AGND
DGND
Color
Red
Red
Orange
Orange
Orange
Black
Black
Voltage
+12V
-12V
+5V
+5V
+5V
0V
0V
Comments
Regulator, Power Supply for Op-amp
Power Supply for Op-amp
Power supply for AVDD of the AK4627
Power supply for DVDD of the AK4627
Power supply for TVDD of the AK4627
Analog ground
Digital ground
Table 1 Set up of power supply lines
Attention
Should be connected.
Should be connected.
Should be connected.
Should be connected.
Should be connected.
Should be connected.
Should be connected.
(1-2) In case of using the regulator
Set up the jumper pins.
JP82
AVDD
JP83
DVDD
JP84
TVDD
REG JACK REG JACK REG JACK
Set up the power supply lines.
Name
+12V
-12V
AVDD
DVDD
TVDD
AGND
DGND
Color
Red
Red
Orange
Orange
Orange
Black
Black
Voltage
+12V
-12V
+5V
+5V
+5V
0V
0V
Comments
Regulator, Power Supply for Op-amp
Power Supply for Op-amp
Power supply for AVDD of the AK4627
Power supply for DVDD of the AK4627
Power supply for TVDD of the AK4627
Analog ground
Digital ground
Attention
Should be connected.
Should be connected.
Should be open.
Should be open.
Should be open.
Should be connected.
Should be connected.
Table 2 Set up of power supply lines
2) Set up the evaluation mode, jumper pins. (See the followings)
3) Power on.
The AK4627 and AK4118 should be reset once bringing SW1 “L” upon power-up.
<KM102001>
2012/04
[AKD4627-A]
„ Control mode
(1) Parallel control mode <Default>
(1-1) Set up Parallel/Serial select pin
Set up SW2-7 (PS) to “H”. (See Table 3)
(1-2) Set up the jumper pins
JP61
SEL1
CSN
JP63
SEL2
DIF0
SCL/CCLK DIF1
JP62
SEL3
SDA/CDTI TDM0
(2) Serial control mode
(1-1) Set up Parallel/Serial select pin
Set up SW2-7 (PS) to “L”. (See Table 3)
(1-2) Set up the jumper pins
JP61
SEL1
CSN
JP63
SEL2
DIF0
SCL/CCLK DIF1
JP62
SEL3
SDA/CDTI TDM0
„ Audio I/F evaluation mode
(1) Evaluation of ADC using DIT of AK4118
(1-1) Set up analog inputs
(1-1-1) Evaluation of ADC using DIT of AK4118 when single-ended inputs
PORT2 (DIT) or J2 (BNC_TX) is used. Nothing should be connected to PORT4 (AC3).
Set up SW2-2 (SGL) to H (See Table 3).
Set up the jumper pins.
<KM102001>
JP33
JP34
JP37
JP38
LIN1+
LIN1-
RIN1+
RIN1-
Canon RCA
Canon GND
CanonRCA
CanonGND
2012/04
[AKD4627-A]
JP31
JP32
JP35
JP36
LIN2+
LIN2-
RIN2+
RIN2-
Canon RCA
Canon GND
CanonRCA
CanonGND
(1-1-2) Evaluation of ADC using DIT of AK4118 when differential inputs <Default>
PORT2 (DIT) or J2 (BNC_TX) is used. Nothing should be connected to PORT4 (AC3).
Set up SW2-2 (SGL) to L (See Table 3).
Set up the jumper pins.
JP33
JP34
JP37
JP38
LIN1+
LIN1-
RIN1+
RIN1-
Canon RCA
Canon GND
CanonRCA
JP31
LIN2+
JP32
LIN2-
JP35
RIN2+
Canon RCA
Canon GND
CanonRCA
CanonGND
JP36
RIN2-
CanonGND
(1-2) Set up the digital output
(1-2-1) In case of selecting SDTO1 <Default>
Set up the jumper pin.
JP13
SDTO-SEL
SDTO1 SDTO2
(1-2-2) In case of selecting SDTO2
Set up the jumper pin.
JP13
SDTO-SEL
SDTO1 SDTO2
(1-3) Set up the audio interface.
Set up the jumper pins.
<KM102001>
JP14
JP16
JP17
SDTO-SEL
BICK-SEL
LRCK-SEL
2012/04
[AKD4627-A]
(2) Evaluation of DAC using DIR of AK4118 <Default>
J1 (BNC_RX) or PORT1 (DIR) is used. Nothing should be connected to PORT4 (AC3).
(2-1) Set up the digital inputs
Set up the jumper pins.
JP66
JP67
JP68
SDTI1
SDTI2
SDTI3
(2-2) Set up the audio interface
Set up the jumper pins.
JP16
JP17
BICK-SEL
LRCK-SEL
(2-3) Set up the SMUTE pin
Set up the jumper pin.
JP64
SMUTE
When JP64 (SMUTE) is open, soft mute cycle is initialized.
When JP64 (SMUTE) is short, the output mute releases.
<KM102001>
2012/04
[AKD4627-A]
„ DIP Switch set up
[SW2] (MODE1): Mode settings for AK4627.
About the TDM mode of AK4627, please refer to Page 18 of AK4627’s datasheet.
No.
1
Name
TDM0
2
SGL
3
4
I2C
DFS0
5
DZFE
6
7
8
PS
CAD1
CAD0
“H”
“L”
TDM Mode
Normal Mode
ADC Single-ended
ADC Differential
Input Mode
Input Mode
I2C Bus
3-wire Serial
Double Speed
Normal Speed
Zero Input Detect.
Refer to the datasheet P23 of the AK4627.
Parallel Control mode Serial Control mode
Chip Address Select.
Refer to Table 9
Default
L
L
L
L
L
H
L
L
Table 3 Mode Setting for AK4627
[SW3] (AK4118 Mode_setting): Mode setting for AK4118.
No.
1
2
3
4
5
6
7
Name
DIF2
DIF1
DIF0
OCKS1
OCKS0
CM1
CM0
“H”
“L”
AK4118’s Audio Data Format Settings, and
AK4627’s Audio Data Format Settings when
Parallel Control Mode. See Table 5 and Table 6
AK4118’s Master Clock Settings.
See Table 7
AK4118’s Clock Operation Mode Select.
See Table 8
Default
H
L
L
H
L
L
L
Table 4 Mode Setting for AK4118
AK4118’s audio data format and AK4627’s audio data format are set up at the same time by settings of SW3-1
(DIF2), SW3-2 (DIF1) and SW3-3 (DIF0) when AK4627 is on Parallel Control Mode.
SW3-1
DIF2
0
SW3-2
DIF1
1
SW3-3
DIF0
0
AK4627
DIF1
0
AK4627
DIF0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
AK4118
DAUX
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
AK4118
SDTO
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I2S
LRCK
BICK
H/L
O
64fs
O
H/L
O
64fs
O
H/L
O
64fs
O
L/H
O
64fs
O
Table 5 AK4118’s Audio Data Format (Parallel control mode <Default>)
It is necessary to set DIF1-0 bits of AK4627’s registers and SW3-1 (DIF2), SW3-2 (DIF1), SW3-3 (DIF0) to the
same audio data format when AK4627 is on Serial Control Mode.
Mode
DIF1
DIF0
SDTO1-2
SDTI1-3
0
1
2
3
0
0
1
1
0
1
0
1
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
(Default)
Table 6 AK4627’s Audio data formats (Serial control mode)
<KM102001>
2012/04
(Default)
[AKD4627-A]
AK4118 supplies AK4627’s Master Clock with MCKO1.
No.
0
1
2
3
OCKS1
0
0
1
1
OCKS0
0
1
0
1
MCKO1
256fs
256fs
512fs
128fs
MCKO2
256fs
128fs
256fs
64fs
X’tal
256fs
256fs
512fs
128fs
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
(default)
Table 7 AK4118’s Master Clock Frequency Select (Stereo mode)
Mode
0
1
2
3
CM1
0
0
CM0
0
1
PLL
X'tal
Clock source SDTO
ON
ON
PLL
RX
OFF
ON
X'tal
DAUX
ON
ON
PLL
RX
1
0
ON
ON
X'tal
DAUX
1
1
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
(default)
Table 8 AK4118’s Clock Operation Mode select
„ Other jumper pins set up
1. JP81 (GND) : Connection between AGND and DGND.
OPEN : AGND and DGND are separated on the board.
SHORT : AGND and DGND are connected on the board. <Default>
2. JP11 (RX3) : Digital input connector selection for AK4118.
OPT
: Optical connector (PORT1) is used, except when Quad Speed Mode for DAC evaluation.
BNC : BNC Jack (J1) is used. <Default>
3. JP12 (TX)
OPT
BNC
: Digital output connector selection for AK4118.
: Optical connector (PORT2) is used.
: BNC Jack (J2) is used. <Default>
4. JP15 (MCLK_SEL): This jumper pin is fixed to SHORT. <Default>
5. JP65 (SDTI4) : This jumper pin is not used. <Default>
„ The function of the toggle SW
[SW1] (PDN): Power down of AK4627. Keep “H” during normal operation.
„ The indication content for LED
[LE1] Monitor DZF1 pin of the AK4627.
[LE2] Monitor DZF2 pin of the AK4627.
About zero detection of AK4627, please refer to Page 23 of AK4627’s datasheet.
<KM102001>
2012/04
[AKD4627-A]
„ Serial Control
The AK4627 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(CTRL) with PC by 10 wire flat cable packed with the AKD4627-A.
PORT3
CTRL
10 wire
flat Cable
10
CSN
CCLK/SCL
AKD4627-A
CDTI/SDA
CDTO/SDA(ACK)
Connect
PC
Red
9
2 ▲
10pin Header
10pin Connector
Figure 2 Connect of 10 wire flat cable
The AK4627 supports 3-wire serial control mode and I2C-bus control mode (fast-mode, max : 400kHz).
Please set the jump pins: JP61 (SEL1), JP63 (SEL2) and JP62 (SEL3), referred to (2) Serial Control Mode.
Mode
3-wire
I2C
Chip Address
00
01
10
11
00
01
10
11
SW2-7
(CAD1)
0
0
1
1
0
0
1
1
SW2-8
(CAD0)
0
1
0
1
0
1
0
1
R/W
Write only
Write only
Write only
Write only
R/W
R/W
R/W
R/W
(default)
Table 9 Select Interface and Chip Address
<KM102001>
2012/04
[AKD4627-A]
„ Analog Input/Output Circuits
1. Analog Input Circuits
J5
LINA1
LIN1+
2
2
3
3
RCA
1
LIN1+/LIN1
1
JP33 canon
JP34 canon
LIN1-
LIN1-
2
3
1
GND
J9 LINB1
MR-552LS
J6
RINA1
2
RIN1+
2
3
3
1
JP37 canon
RCA
1
RIN1+/RIN1
JP38 canon
RIN1-
RIN1-
2
3
1
GND
J10 RINB1
MR-552LS
J3
LINA2
LIN2+
2
2
3
3
1
JP31 canon
RCA
1
LIN2+/LIN2
JP32 canon
LIN2-
LIN2-
GND
2
3
1
J7 LINB2
MR-552LS
J4
RINA2
2
3
3
RCA
1
RIN2+
2
1
JP35 canon
RIN2+/RIN2
JP36 canon
RIN2-
RIN2-
GND
2
3
1
J8 RINB2
MR-552LS
Figure 3 AKD4627-A Analog Input Circuits
<KM102001>
2012/04
[AKD4627-A]
2. Analog Output Circuits
ROUT1
U4B
R44
OP275GPZ 220
7
5 +
6 -
J11
ROUT1
8
+
ROUT2
5 +
6 -
R45
10k
R115
(open)
-12V
4
R41
10k
C101
(short)
-12V
LOUT2
8
3 +
2 -
R93
10k
-12V
J15
LOUT2
R119
(open)
330p C50
C48
330p
R90
4.7K
U5A
R96 C105
OP275GPZ 220 (short)
1
4
J14
LOUT1
R118
(open)
-12V
4
R89
10k
+12V
+
8
U4A
R92 C104
OP275GPZ 220 (short)
1
3 +
2 -
R116
(open)
R47
4.7k
C49
22u
+12V
+
LOUT1
R46
4.7K
R43
4.7k
C47
22u
J12
ROUT2
330p C44
330p C42
R42
4.7K
U5B
R48 C102
OP275GPZ 220 (short)
7
4
+
8
C41
22u
+12V
C43
22u
+12V
R94
4.7K
R91
4.7k
R95
4.7k
+12V
+
8
C45
22u
5 +
6 -
ROUT3
J13
ROUT3
R117
(open)
4
R49
10k
U6B
R88 C103
OP275GPZ 220 (short)
7
-12V
330p C46
R50
4.7K
+12V
+
8
C51
22u
LOUT3
R87
4.7k
3 +
2 4
R97
10k
U6A
R113 C106
OP275GPZ 220
(short)
1
-12V
J16
LOUT3
R120
(open)
330p C52
R98
4.7K
R99
4.7k
Figure 4 AKD4627-A Analog Output Circuits
<KM102001>
2012/04
[AKD4627-A]
Control Soft Manual
■ Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10 wire flat cable. Be aware of the direction of
the 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD
must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing the
driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This control soft
does not support the Windows NT.
3. Continue the evaluation by following the process below.
■ Operation Screen
1. Start up the control program following the process above.
The operation screen is shown below.
<KM102001>
2012/04
[AKD4627-A]
■ Operation Overview
Register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “Dialog Boxes” for details of each dialog box setting.
1. [Port Reset]: For when connecting to USB I/F board (AKDUSBIF-A)
Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-A).
2. [Write Default]: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executing write commands for all registers displayed.
4. [All Read]: Executing read commands for all registers displayed.
5. [Save]: Saving current register settings to a file.
6. [Load]: Executing data write from a saved file.
7. [All Reg Write]: “All Reg Write” dialog box is popped up.
8. [Data R/W]: “Data R/W” dialog box is popped up.
9. [Sequence]: “Sequence” dialog box is popped up.
10.
[Sequence(File)]: “Sequence(File)” dialog box is popped up.
11.
[Read]: Reading current register settings and display on to the Register area (on the right of the main window).
This is different from [All Read] button, it does not reflect to a register map, only displaying
hexadecimal.
<KM102001>
2012/04
[AKD4627-A]
1. [REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
The registers which is not defined in the datasheet are indicated as “---”.
<KM102001>
2012/04
[AKD4627-A]
[Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
[Read]: Data Read
Click [Read] button located on the right of the each corresponded address to execute register reading.
After register reading, the display will be updated regarding to the register status.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Please be aware that button statuses will be changed by Read command.
<KM102001>
2012/04
[AKD4627-A]
2. [Tool]: Testing Tools
This tab screen is for evaluation testing tool.
Click buttons for each testing tool.
<KM102001>
2012/04
[AKD4627-A]
„ Dialog Boxes
1. [All Reg Write]: All Register Write dialog box
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
[Open (left)]: Selecting a register setting file (*.akr).
[Write]: Executing register writing.
[Write All]: Executing all register writings.
Writings are executed in descending order.
[Help]: Help window is popped up.
[Save]: Saving the register setting file assignment. The file name is “*.mar”.
[Open (right)]: Opening a saved register setting file assignment “*. mar”.
[Close]: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register
settings.
<KM102001>
2012/04
[AKD4627-A]
2. [Data R/W]: Data R/W Dialog Box
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Address Box: Input data address in hexadecimal numbers for data writing.
Data Box: Input data in hexadecimal numbers.
Mask Box: Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write]: Writing to the address specified by “Address” box.
[Read]: Reading from the address specified by “Address” box.
The result will be shown in the Read Data Box in hexadecimal numbers.
[Close]: Closing the dialog box and finish the process.
Data writing can be cancelled by this button instead of [Write] button.
*The register map will be updated after executing [Write] or [Read] commands.
<KM102001>
2012/04
[AKD4627-A]
3. [Sequence]: Sequence Dialog Box
Click [Sequence] button to open register sequence setting dialog box.
Register sequence can be set in this dialog box.
Sequence Setting
Set register sequence by following process bellow.
(1)Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use: Not using this address
· Register: Register writing
· Reg(Mask): Register writing (Masked)
· Interval: Taking an interval
· Stop: Pausing the sequence
· End: Finishing the sequence
(1) Input sequence
[Address]: Data address
[Data]: Writing data
[Mask]: Mask
[Data] box data is ANDed with [Mask] box data. This is the actual writing data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
<KM102001>
2012/04
[AKD4627-A]
[ Interval ]: Interval time
Valid boxes for each process command are shown bellow.
· No_use: None
· Register: [Address], [Data], [Interval]
· Reg(Mask): [Address], [Data], [Mask], [Interval]
· Interval: [Interval]
· Stop: None
· End: None
Control Buttons
The function of Control Button is shown bellow.
[Start]: Executing the sequence
[Help]: Opening a help window
[Save]: Saving sequence settings as a file. The file name is “*.aks”.
[Open]: Opening a sequence setting file “*.aks”.
[Close]: Closing the dialog box and finish the process.
Stop of the sequence
When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked.
Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence, “Start
Step” will return to “1”.
The sequence can be started from any step by writing the step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
<KM102001>
2012/04
[AKD4627-A]
4. [Sequence(File)]: Sequence Setting File Dialog Box
Click [Sequence(File)] button to open sequence setting file dialog box.
Those files saved in the “Sequence setting dialog” can be applied in this dialog.
[Open (left)]: Opening a sequence setting file (*.aks).
[Start]: Executing the sequence setting.
[Start All]: Executing all sequence settings.
Sequences are executed in descending order.
[Help]: Pop up the help window.
[Save]: Saving sequence setting file assignment. The file name is “*.mas”.
[Open(right)]: Opening a saved sequence setting file assignment “*. mas”.
[Close]: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be
stored in the same folder.
(2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click “OK”
to continue the process.
<KM102001>
2012/04
[AKD4627-A]
MEASUREMENT RESULTS
1) ADC part
[Measurement condition]
• Measurement unit : Audio Precision, System two, Cascade
• MCLK
: 512fs at 48kHz, 256fs at 96kHz
• BICK
: 64fs
• fs
: 48kHz, 96kHz
• BW
: 20Hz∼20kHz at fs=48kHz, 20Hz∼40kHz at 96kHz
• Bit
: 24bit
• Power Supply
: AVDD=DVDD= TVDD=5V
• Interface
: DIT (AK4118)
• Temperature
: Room
a)
Single-ended Inputs
fs=48kHz
Parameter
S/(N+D)
DR
S/N
fs=96kHz
Parameter
S/(N+D)
DR
S/N
Input signal
1kHz,
-0.5dBFS
1kHz,
-60dBFS
No signal
Measurement filter
20kHz LPF
LIN1
RIN1
Units
96.9
96.5
dB
20kHz LPF
20kHz LPF+A-weighted
20kHz LPF
20kHz LPF+A-weighted
99.8
102.7
99.9
102.8
99.9
102.7
100.1
103.1
dB
dB
dB
dB
Input signal
1kHz,
-0.5dBFS
1kHz,
-60dBFS
No signal
Measurement filter
40kHz LPF
LIN1
RIN1
Units
93.1
93.0
dB
40kHz LPF
40kHz LPF+A-weighted
40kHz LPF
40kHz LPF+A-weighted
98.0
104.7
98.1
105.2
98.1
104.8
98.1
105.2
dB
dB
dB
dB
LIN1±
RIN1±
Units
98.3
97.4
dB
100.2
102.9
100.4
103.3
100.3
103.0
100.4
103.3
dB
dB
dB
dB
LIN1±
RIN1±
Units
95.9
95.5
dB
98.4
105.2
98.4
105.6
98.5
105.4
98.5
105.5
dB
dB
dB
dB
b) Differential Inputs
fs=48kHz
Parameter
S/(N+D)
DR
S/N
fs=96kHz
Parameter
S/(N+D)
DR
S/N
<KM102001>
Input signal
1kHz,
-0.5dBFS
1kHz,
-60dBFS
No signal
Measurement filter
20kHz LPF
Input signal
1kHz,
-0.5dBFS
1kHz,
-60dBFS
No signal
Measurement filter
40kHz LPF
20kHz LPF
20kHz LPF+A-weighted
20kHz LPF
20kHz LPF+A-weighted
40kHz LPF
40kHz LPF+A-weighted
40kHz LPF
40kHz LPF+A-weighted
2012/04
[AKD4627-A]
2) DAC part
[Measurement condition]
• Measurement unit : Audio Precision, System two, Cascade
• MCLK
: 512fs at 48kHz, 256fs at 96kHz, 128fs at 192kHz
• BICK
: 64fs
• fs
: 48kHz, 96kHz, 192kHz
• BW
: 20Hz∼20kHz at fs=48kHz, 20Hz∼40kHz at 96kHz, 20Hz~40kHz at 192kHz
• Bit
: 24bit
• Power Supply
: AVDD=DVDD= TVDD=5V
• Interface
: DIR (AK4118)
• Temperature
: Room
fs=48kHz
Parameter
S/(N+D)
DR
S/N
Input signal
1kHz,
0dBFS
1kHz,
-60dBFS
No signal
Measurement filter
20kHz Brick-wall LPF
LOUT1
ROUT1
101.5
100.4
20kHz Brick-wall LPF
103.3
103.2
105.7
105.7
103.3
103.1
105.8
105.7
Measurement filter
40kHz Brick-wall LPF
LOUT1
ROUT1
99.3
98.1
40kHz Brick-wall LPF
100.6
100.5
105.6
105.5
100.6
100.5
105.6
105.5
Measurement filter
40kHz Brick-wall LPF
LOUT1
ROUT1
98.3
97.6
40kHz Brick-wall LPF
100.5
100.6
105.6
105.5
100.7
100.5
105.6
105.5
20kHz Brick-wall LPF
A-weighted
20kHz Brick-wall LPF
20kHz Brick-wall LPF
A-weighted
fs=96kHz
Parameter
S/(N+D)
DR
S/N
Input signal
1kHz,
0dBFS
1kHz,
-60dBFS
No signal
40kHz Brick-wall LPF
A-weighted
40kHz Brick-wall LPF
40kHz Brick-wall LPF
A-weighted
fs=192kHz
Parameter
S/(N+D)
DR
S/N
Input signal
1kHz,
0dBFS
1kHz,
-60dBFS
No signal
40kHz Brick-wall LPF
A-weighted
40kHz Brick-wall LPF
40kHz Brick-wall LPF
A-weighted
<KM102001>
Units
dB
dB
dB
dB
dB
Units
dB
dB
dB
dB
dB
Units
dB
dB
dB
dB
dB
2012/04
[AKD4627-A]
1.1.1 ADC (fs=48kHz, Single-ended Inputs)
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
2k
5k
10k
20k
Hz
FFT (Input=-0.5dBr, fin=1kHz)
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
Hz
FFT (Input=-60dBr, fin=1kHz)
<KM102001>
2012/04
[AKD4627-A]
FFT (noise floor)
<KM102001>
2012/04
[AKD4627-A]
-60
-65
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-105
-110
-115
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
THD + N vs. Input Level (fin=1kHz)
-60
-65
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
THD + N vs. Input Frequency (Input=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
+0
TTT
T
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Linearity (fin=1kHz)
+1
+0.7
+0.4
+0.1
d
B
F
S
-0.2
-0.5
-0.8
-1.1
-1.4
-1.7
-2
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
v
Frequency Response (Input Level=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
-60
-68
-76
-84
-92
d
B
-100
-108
-116
-124
-132
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Crosstalk (Input Level=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
1.1.2 ADC (fs=96kHz, Single-ended Inputs)
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
FFT (Input=-0.5dBr, fin=1kHz)
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
FFT (Input=-60dBr, fin=1kHz)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
FFT (Noise floor)
<KM102001>
2012/04
[AKD4627-A]
-60
-65
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-105
-110
-115
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
THD + N vs. Input Level (fin=1kHz)
-60
-65
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
THD + N vs. Input Frequency (Input Level=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
+0
T TTT
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Linearity (fin=1kHz)
+1
+0.7
+0.4
+0.1
d
B
F
S
-0.2
-0.5
-0.8
-1.1
-1.4
-1.7
-2
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Frequency Response (Input Level=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
-60
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Crosstalk
<KM102001>
2012/04
[AKD4627-A]
1.2.1 ADC (fs=48kHz, Differential Inputs)
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FFT (Input=-0.5dBr, fin=1kHz)
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FFT
(Input=-60dBr, fin=1kHz)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FFT (noise floor)
<KM102001>
2012/04
[AKD4627-A]
-60
-65
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-105
-110
-115
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
THD + N vs. Input Level (fin=1kHz)
-60
-65
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
THD + N vs. Input Frequency (Input=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
+0
T
T T
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Linearity (fin=1kHz)
+1
+0.8
+0.6
+0.4
+0.2
+0
d
B
F
S
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Frequency Response (Input Level=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
-60
-70
-80
-90
-100
d
B
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Crosstalk (Input Level=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
1.2.2 ADC (fs=96kHz, Differential Inputs)
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
FFT (Input=-0.5dBr, fin=1kHz)
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
FFT (Input=-60dBr, fin=1kHz)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
FFT (Noise floor)
<KM102001>
2012/04
[AKD4627-A]
-60
-65
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-105
-110
-115
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
THD + N vs. Input Level (fin=1kHz)
-60
-65
-70
-75
-80
d
B
F
S
-85
-90
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
THD + N vs. Input Frequency (Input Level=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
+0
T
T
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Linearity (fin=1kHz)
+1
+0.7
+0.4
+0.1
d
B
F
S
-0.2
-0.5
-0.8
-1.1
-1.4
-1.7
-2
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Frequency Response (Input Level=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
-60
-70
-80
-90
-100
d
B
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Crosstalk (Input Level=-0.5dBr)
<KM102001>
2012/04
[AKD4627-A]
2.1 DAC (fs=48kHz)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
2k
5k
10k
20k
Hz
FFT (Input=0dBFS, fin=1kHz)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
Hz
FFT (Input=-60dBFS, fin=1kHz)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FFT (Noise floor)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
FFT (Out-of-band noise)
<KM102001>
2012/04
[AKD4627-A]
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
THD + N vs. Input Level (fin=1kHz)
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
THD + N vs. Input Frequency (Input=0dBFS)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
r
-60
-70
-80
A
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Linearity (fin=1kHz)
+1
+0.8
+0.6
+0.4
d
B
r
+0.2
A
-0.2
+0
-0.4
-0.6
-0.8
-1
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Frequency Response (Including external RC filter)
<KM102001>
2012/04
[AKD4627-A]
-60
T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Crosstalk
<KM102001>
2012/04
[AKD4627-A]
2.2 DAC (fs=96kHz)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
FFT (Input=0dBFS, fin=1kHz)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
Hz
FFT (Input=0dBFS, fin=1kHz, Notch on)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
FFT (Input=-60dBFS,fin=1kHz)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
FFT (Noise floor)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
FFT (Out-of-band noise)
<KM102001>
2012/04
[AKD4627-A]
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
THD + N vs. Input Level (fin=1kHz)
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
THD + N vs. Input Frequency (Input=0dBFS)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
r
-60
-70
-80
A
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Linearity (fin=1kHz)
d
B
r
A
+2
+1.8
+1.6
+1.4
+1.2
+1
+0.8
+0.6
+0.4
+0.2
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Frequency Response (Including external RC filter)
<KM102001>
2012/04
[AKD4627-A]
-60
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Crosstalk (Input=0dBFS)
<KM102001>
2012/04
[AKD4627-A]
2.3 DAC (fs=192kHz)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
80k
5k
10k
20k
80k
Hz
FFT (Input=0dBFS, fin=1kHz)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
FFT (Input=0dBFS, fin=1kHz, Notch on)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
80k
5k
10k
20k
80k
Hz
FFT (Input=-60dBFS,fin=1kHz)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
FFT (Noise floor)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
FFT (Out-of-band noise)
<KM102001>
2012/04
[AKD4627-A]
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
10k
20k
-10
+0
dBFS
THD + N vs. Input Level (fin=1kHz)
-60
-65
-70
-75
-80
d
B
r
-85
A
-95
-90
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
80k
Hz
THD + N vs. Input Frequency (Input=0dBFS)
<KM102001>
2012/04
[AKD4627-A]
+0
-10
-20
-30
-40
-50
d
B
r
-60
-70
-80
A
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Linearity (fin=1kHz)
+3
+2.5
+2
+1.5
+1
d
B
r
+0.5
A
-0.5
+0
-1
-1.5
-2
-2.5
-3
20
50
100
200
500
1k
2k
5k
10k
20k
80k
Hz
Frequency Response (Including external RC filter)
<KM102001>
2012/04
[AKD4627-A]
-60
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
80k
Hz
Crosstalk (Input=0dBFS)
<KM102001>
2012/04
[AKD4627-A]
Revision History
Date
Manual
Board
(YY/MM/DD) Revision Revision
2010/08/09
KM102000
0
2012/04/19
KM102001
1
Reason
Contents
First Edition
Change
Circuit pattern were changed.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
<KM102001>
2012/04
5
4
3
SMUTE DZFE
LIN1+/LIN1
SGL
2
RIN1+/RIN1
LIN1-
LIN2+/LIN2
RIN1-
RIN2+/RIN2
LIN2-
RIN2-
48pin_4
37
38
39
40
41
42
43
44
45
46
47
CN4
48
1
D
D
TP7
LIN1-
TP6
TP8
TP5
RIN1+
TP9
TP4
RIN1-
LIN1+
TP3
LIN2+
TP10
TP2
SGL
LIN2-
TP1
TP11
DZFE
38
37
RIN2-
LIN2-
RIN2+/RIN2
40
39
41
RIN1-
LIN2+/LIN2
LIN1-
RIN1+/RIN1
42
43
44
TST1
LIN1+/LIN1
46
45
SGL
DZFE
31
TVDD
AK4627
DZF2
36
DZF1
35
7
DVDD
ROUT1
30
8
DVSS
LOUT1
29
9
TDM0/SDA/CDTI
ROUT2
28
27
10
DIF1/SCL/CCLK
LOUT2
11
DIF0/CSN
ROUT3
26
LOUT3
25
12
100
PDN
C6
32
C7
C8
0.1u
2.2u
TP40
R9
11
R10
DIF0/CSN
TP23
100
12
LOUT1
LOUT1
29
TP38
ROUT2
28
ROUT2
100
TST5
LOUT2
TP36
R6
100
TP27
26
ROUT3
TP35
R11
100
ROUT3
25
LOUT3
LOUT3
TP29
SDTI3
SDTI1
TP26
LRCK
TP28
TP31
SDTI2
DFS0
TP32
I2C
24
23
22
21
20
19
18
16
A
15
TP25
BICK
14
TP24
MCLK
13
LOUT2
48pin_3
R7 R8
100 100
17
48pin_1
B
27
PDN
CN2
ROUT1
30
TP22
A
31
ROUT1
TP39
24
TST2
TST4
23
DFS0
I2C
22
13
10
DIF1/SCL/CCLK
21
TP21
20
MCLK
TDM0/SDA/CDTI
PDN
AVDD1
33
TP37
TST3
100
VCOM
SDTO2
SDTI3
R5
9
B
100
R4
DVSS
TP20
10u
19
R3
TP19
8
100
VREFH
0.1u
18
R2
DVDD
C5
32
SDTI2
7
DVDD
33
SDTI1
C3
0.1u
34
AVDD
17
C4
10u
AVSS
SDTO1
16
+
TP18
PS
4
LRCK
TVDD
3
6
C
34
TP42
AVDD
CAD1
BICK
6
TP43
AVSS
CAD0
15
TP17
47
48
SMUTE
0.1u
DZF1
35
2
14
+
10u
SDTO2
TP44
+
5
TVDD
36
DZF1
1
5
DZF2
DZF2
+
+
100
+
100
+
TP16
C1
+
C2
+
SDTO2
+
R13 R14
4
+
TP15
SDTO1
TP45
+
3
CN3
RIN2-
2.2u
SDTO1
C9
PS
C10 2.2u
CAD1
TP14
PS
C11 2.2u
TP13
CAD1
2
U1
C12 2.2u
1
C13 2.2u
CAD0
C14 2.2u
TP12
CAD0
C15 2.2u
C16 2.2u
SMUTE
CN1
C
RIN2+
48pin_2
Title
AKD4627-A-MAIN
Size
MCLK
BICK
LRCK SDTI1
SDTI2 SDTI3 SDTI4 DFS0
A3
I2C
Date:
5
4
3
2
Document Number
Rev
AK4627
Wednesday, August 04, 2010 Sheet
1
0
1
of
6
5
D
4
1
C20
0.1u
2
L1 (short)
2
+3.3V
C21
+
R20
10u
OPT
470
J1
BNC_RX
1
+3.3V
+
PORT1
VCC 3
2
GND 1
OUT
TORX141
3
C18
0.1u
JP11
RX3
BNC
C22
D
C19
10u
R25
10k
C17
0.47u
+
R21
75
48
47
46
45
44
43
42
41
40
39
38
37
0.1u
1
2
3
4
5
6
7
8
9
10
11
12
+3.3V
C23
5p
2
DIF0
XTI
DIF1
X1
C24
DIF2
1
XTO
24.576MHz
PORT2
IN 3
VCC 2
GND 1
B
INT0
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
U2CM0/CDTO/CAD1
PDN
AK4118
XTI
XTO
DAUX
MCKO2
BICK
SDTO
36
35
34
33
32
31
30
29
28
27
26
25
C
XTI
XTO
OCKS0
OCKS1
CM1
CM0
PDN
JP14
DAUX
SDTO_SEL
JP15
4118_SDTO
JP16
+3.3V
JP12 OPT
T3
DA02
1:1
R22
150
C27
0.1u
B
LRCK_SEL
C28
0.1u
C29
10u
+3.3V
BNC
TX
4118_LRCK
4118_MCKO1
R24
TX
R23
C26 +
10u
4118_BICK
BICK_SEL
JP17
13
14
15
16
17
18
19
20
21
22
23
24
C25
0.1u
4118_MCKO2
MCLK_SEL
+3.3V
TOTX141
J2
BNC_TX
IPS0/RX4
NC
DIF0/RX5
TEST2
DIF1/RX6
VSS1
DIF2/RX7
IPS1/IIC
P/SN
XTL0
XTL1
VIN/GP0
+
5p
RX3
VSS4
RX2
TEST1
RX1
NC
RX0
VSS3
VCOM
R
AVDD
INT1
C
INT0
TVDD
GP1
TX0/GP2
TX1/GP3
BOUT/GP4
COUT/GP5
UOUT/GP6
VOUT/GP7
DVDD
VSS2
MCKO1
LRCK
RX
5.1
240
A
A
Title
Size
A4
Date:
5
4
3
2
AKD4627-A-Main
Document Number
Rev
0
AK4118
Wednesday, August 04, 2010Sheet
1
1
of
6
5
4
3
2
1
J3
LINA2
2
2
RCA
JP35 canon
RIN2+/RIN2
1
LIN2+
3
3
2
2
RIN2+
JP32
LIN2-
LIN2-
canon
GND
JP36 canon
J7 LINB2
2
3
1
RIN2-
RIN2-
2
3
1
GND
MR-552LS
J6
RINA1
2
3
JP37 canon
RIN1+/RIN1
2
RCA
1
RCA
2
RIN1+
1
LIN1+
3
JP38 canon
JP34 canon
LIN1-
LIN1-
2
3
1
GND
3
3
C
1
LIN1+/LIN1
2
1
JP33 canon
J8 RINB2
MR-552LS
J5
LINA1
C
D
1
1
RCA
D
3
3
1
JP31 canon
LIN2+/LIN2
J4
RINA2
J9 LINB1
RIN1-
RIN1-
2
3
1
GND
J10 RINB1
MR-552LS
MR-552LS
B
B
A
A
Title
<Title>
Size
A4
Date:
5
4
3
AKD4627-A-MAIN
Document Number
2
<Doc>
Rev
0
Analog Input
Wednesday, August 04, 2010Sheet
3
1
of
6
2
+12V
-12V
4
6 -
J11
ROUT1
8
C101
(short)
5 +
ROUT2
R45
10k
R115
(open)
6 -
U5B
R48 C102
OP275GPZ 220 (short)
7
330p C42
-12V
J12
ROUT2
+12V
C45
22u
5 +
ROUT3
R49
10k
R116
(open)
6 -
R46
4.7K
R50
4.7K
8
3 +
R93
10k
C48
330p
R90
4.7K
2 -
-12V
R119
(open)
+12V
C51
22u
8
LOUT2
J15
LOUT2
LOUT3
3 +
R97
10k
2 -
R94
4.7K
U6A
R113 C106
OP275GPZ 220
(short)
1
J16
LOUT3
R120
(open)
-12V
330p C50
R91
4.7k
C
4
-12V
R118
(open)
U5A
R96 C105
OP275GPZ 220 (short)
1
+
2 4
R89
10k
R87
4.7k
+12V
C49
22u
4
LOUT1
J14
LOUT1
+
8
+
3 +
U4A
R92 C104
OP275GPZ 220 (short)
1
D
330p C46
R47
4.7k
+12V
C47
22u
C
R43
4.7k
J13
ROUT3
R117
(open)
-12V
330p C44
R42
4.7K
U6B
R88 C103
OP275GPZ 220 (short)
7
4
R41
10k
U4B
R44
OP275GPZ 220
7
4
5 +
ROUT1
1
+12V
C43
22u
+
+
8
C41
22u
D
3
8
4
+
5
330p C52
R95
4.7k
R98
4.7K
R99
4.7k
B
B
A
A
Title
<Title>
Size
A4
Date:
5
4
3
2
AKD4627-A-MAIN
Document Number
<Doc>
Rev
0
Analog Output
Wednesday, August 04, 2010Sheet
4
1
of
6
5
L5V
D
10
8
6
4
2
PORT3
9
7
5
3
1
4
R51
10k
R52
10k
R53
10k
R54
R55
R56
CSN
SCL/CCLK
SDA/CDTI
SDA(ACK)/CDTO
R139 51
3
U3
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
100
100
100
1
19
SDA(ACK)/CDTO
R33
51
R57
18
17
16
15
14
13
12
11
SDTI1
SDTI2
SDTI3
SDTI4
JP61
DIF0/CSN
DIF0
R58
R140
L5V
10k
R34
51
U10A
2
74LS07
4
U10B
3
74LS07
TVDD
SEL1
100
1
1
CSN
100
DIF0
G1
G2
74HCT541
R32
51
CTRL
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
2
SCL/CCLK
R59
100
TDM0
SGL
I2C
DFS0
DZFE
PS
CAD1
CAD0
SDA/CDTI
R141
L5V
1
2
3
4
5
6
7
8
10k
SDA(ACK)/CDTO
SW2
16
15
14
13
12
11
10
9
D
MODE1
RP1
1
2
3
4
5
6
7
8
9
R35
51
TDM0
SGL
I2C
DFS0
DZFE
PS
CAD1
CAD0
47k
5
9
C
11
13
U10C
6
74LS07
U10D
8
74LS07
U10E
10
74LS07
U10F
12
74LS07
R61 100
4118_MCKO1
MCKO1
BICK
LRCK
SDTO
SDTI4
R62 100
4118_BICK
R63 100
4118_LRCK
1
3
5
7
9
R64 100
PORT4
10 MCKO2
8 GND
6 SDTI1
4 SDTI2
2 SDTI3
R66 100
4118_MCKO2
C
AK4118 Mode_setting
SW3
1
14
2
13
3
12
4
11
5
10
6
9
7
8
AC3
JP65
SDTI4
JP66
SDTI1
JP67
SDTI2
JP68
SDTI3
R65 100
4118_SDTO
RP2
1
2
3
4
5
6
7
MCLK
4118_MCKO1
R39
R38
R37
4118_BICK
4118_LRCK
B
SDTO1
SDTO2
U9
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
100
100
100
JP13
1
19
DIF2
DIF1
DIF0
OCKS1
OCKS0
CM1
CM0
+3.3V
DIF2
DIF1
DIF0
OCKS1
OCKS0
CM1
CM0
BICK
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
17
16
15
14
13
12
11
47K
LRCK
R36
100
DAUX
B
G1
G2
74HCT541
SDTO-SEL
TVDD
D1
1S1588
R67
10k
13
H
SDA/CDTI
SDA/CDTI
JP62
TDM0/SDA/CDTI
TDM0
SEL3
TDM0
SMUTE
SCL/CCLK
JP63
SCL/CCLK
DIF1/SCL/CCLK
DIF2
DIF1
SEL2
R60
SW1
PDN
L
U8F
12
11
74HCT14
U8E
10
PDN
74HCT14
C61
0.1u
TVDD
100k
JP64
SMUTE
A
A
Title
<Title>
Size
A3
Date:
5
4
3
2
AKD4627-A-MAIN
Document Number
<Doc>
Rev
0
Digital I/F
Wednesday, August 04, 2010 Sheet
1
5
of
6
5
4
3
2
C73
+
0.1u
2
D
C72
0.1u
3
OUT
L2
1
L5V
(Short)
C74
47u
-12V
for OP275GPZ x3
D
2
1
AVDD2
-12V
(short)
C84
47u
+
L3
1
+
2
L10
+
+
C71
47u
IN
1
+
1
+12V
GND
T1
NJM78M05FA
2
(Short)
C86
0.1u
L4
REG
JP82
JACK
AVDD
(short)
JP81
C90
0.1u
C91
10u
1
+12V
+ (short)
+
+
+
TVDD1
T-45(O)
R81
1k
DVDD1
T-45(O)
1
1
1
JP83
REG
(short)
JACK
DVDD
TVDD
C96
0.1u
C97
10u
C98
0.1u
C99
10u
C
L6
AVDD
C95
10u
LE1
2
AVDD1
T-45(O)
C94
0.1u
(short)
R85
DZF1
DVDD
DVDD
3
5.1
1
12V2
T-45(R)
1
L11
L5
C
1
C89
10u
DGND
C75
+
47u
-12V
C88
0.1u
for OP275GPZ x3
2
C85
47u
GND
+12V
+12V
AVDD1
AVDD
AGND
12V1
T-45(R)
R86
(Short)
C87
10u
AVDD2
TR1
RN1202
(10k,10k)
DZF1
DVDD
AGND1
T-45(B)
DGND1
T-45(B)
1
1
L7
C76
+
47u
(short)
L8
AGND
REG
JP84
JACK
TVDD
(short)
DGND
TVDD
B
R83
TVDD
(Short)
B
R82
1k
(short)
C78
0.1u
IN
GND
C77
47u
OUT
2
3
+
+3.3V
C79
0.1u
+
C80
47u
(Short)
AVDD2
TR2
RN1202
(10k,10k)
DZF2
for 74HCT14,
74HCT541x2, 74LS07
R84
1
3
1
DZF2
T2 LP2950A
L5V
LE2
2
L9
C81
+
47u
L5V
C82
0.1u
C83
0.1u
C109
0.1u
C110
0.1u
A
A
Title
<Title>
Size
A3
Date:
5
4
3
2
AKD4627-A-MAIN
Document Number
<Doc>
Rev
0
Power Supply
Wednesday, August 04, 2010 Sheet
1
6
of
6
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