AK4679EG

[AKD4679-A]
AKD4679-A
AK4679 Evaluation Board Rev.1
GENERAL DESCRIPTION
The AKD4679-A is an evaluation board for AK4679, 24bit stereo CODEC with Microphone/ Receiver/
Headphone/ Speaker/ Line amplifier as well as HF/Audio DSP. The AKD4679-A has the one Digital
Audio I/F and two PCM I/F. It can achieve the interface with digital audio systems via optical connector
and 10pin Port connector.
 Ordering Guide
AKD4679-A
---
Evaluation board for AK4679A
FUNCTION
 DIR/DIT with optical input/output
 10pin Header for Digital Audio I/F and PCM I/F (Baseband, Bluetooth)
 BNC connector for an external clock input
 10pin Header for I2C control mode
SVDD
TVDDA
DVDD
PVDD
AVDD
REG1
Regulator
TVDDE
Mini
Jack
LIN
LIN1
RIN1
LIN2
LIN3
LIN4
RIN2
RIN3
RIN4
RIN
LOUT
LOUT
PORT5
(CTRL)
PORT3
(Baseband)
AK4679
PORT6
(Bluetooth)
PORT4
(DSP)
(CODEC and DSP)
ROUT
ROUT
Mini
Jack
HPL/HPR
RCP/RCN Mini
Jack
RCP/RCN
Mini
Jack
SPP/SPN
HPL/HPR
Regulator
Opt In
SPP/SPN
AK4118A
(DIT/DIR)
Opt Out
Figure 1. AKD4679-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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 Operation Sequence
1) Set up the Power Supply Lines.
Name of
jack
Color of
jack
REG1
Red
SVDD
Orange
Used for
Open / Connect
Regulator T1:
AVDD, DVDD, PVDD and
TVDD of AK4679, VCC1 and
VCC2 of Digital Logic.
Should be always connected when
default setting.
SVDD of AK4679.
Should be always connected.
Default
Setting
+4.2V
+4.2V
AVDD
Orange
AVDD of AK4679.
DVDD
Orange
DVDD of AK4679.
PVDD
Orange
PVDD of AK4679.
TVDD1
Orange
TVDDA , TVDDE of AK4679.
VCC1
Orange
Digital Logic.
VCC2
Orange
Digital Logic.
D3V
Orange
Digital Logic and AK4118A.
Should be always connected when
AVDD of AK4679 is not supplied from
regulator T1.
In this case, “JP20” is set to “Open”.
Should be always connected when
DVDD of AK4679 is not supplied from
regulator T1.
In this case, “JP26” is set to “Open”.
Should be always connected when
PVDD of AK4679 is not supplied from
regulator T1.
In this case, “JP24” is set to “Open”.
Should be always connected when
TVDDA, TVDDE of AK4679 is not
supplied from regulator T1.
In this case, “JP29” is set to “Open” and
the supplied voltage should be the same
as TVDD1.
Should be always connected when
Digital Logic is not supplied from
regulator T1.
In this case, “JP31” is set to “Open” and
the supplied voltage should be the same
as TVDD1.
Should be always connected when
Digital Logic is not supplied from
regulator T1.
In this case, “JP66” is set to “Open” and
the supplied voltage should be the same
as TVDD1.
Should be always connected.
AGND
Black
Analog Ground
Should be always connected
GND
DGND
Black
Digital Ground
Should be always connected
GND
Open
Open
Open
Open
Open
Open
+3.3V
Table 1. Set up the power supply lines
Each supply line should be distributed from the power supply unit.
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2)
Setup the Audio I/F Evaluation Mode.
(a) Evaluation of A/D using DIT of AK4118A
(b) Evaluation of D/A using DIT of AK4118A
(c) Evaluation of A/D using interface signals are fed externally.
(b) Evaluation of D/A using interface signals are fed externally.
3)
Setup the PCM I/F evaluation mode.
(a) SYNCA and BICKA are fed from on-board clock generator.
(b) SYNCA and BICKA are fed externally via PORT3 (Baseband Module).
(c) SYNCB and BICKB are fed from on-board clock generator.
(d) SYNCB and BICKB are fed externally via PORT6 (Bluetooth Module).
4)
Jumper pins and SW Setting
5)
Power on.
The AK4679 should be reset once bringing SW2 (PDN) “L” upon power-up.
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2) Setup the Audio I/F Evaluation Mode.
■Clock Mode
External Slave Mode
In case of AK4679 evaluation using AK4118A, it is necessary to correspond to audio interface format for
AK4679 and AK4118A.
The AK4118A must be set to master mode.
AK4679(CODEC)
AK4118A
256fs, 512fs, or
1024fs
MCKI
MCLK
 32fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 2. EXT Slave Mode
PLL Slave Mode
In case of AK4679 evaluation using external clock, it is necessary to correspond to audio interface format for
AK4679.
DSP or P
AK4679 (CODEC)
MCKO
MCKI
BICK
32fs or 64fs
LRCK
1 fs
BICK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 3. PLL Slave Mode
(PLL Reference Clock: BICK pin)
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■Board Setting
1) R108, R109, R110, R111, R114, R115, R116, R117 must be set to open.
2) R108 pad and CL104 Pad (1) , R109 pad and CL105 Pad (1), R110 pad and CL106 Pad (1),
R111 pad and CL107 Pad (1) must be connected.
CL104 Pad (2), CL106 Pad (2), CL107 Pad (2) must be connected to GND.
Figure 4.
A/D and D/A board setting
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(a) Evaluation of A/D using DIT of AK4118A
(a-1) Clock Mode: Ext Slave Mode
(a-2) Jumper Setting
X2(X’TAL) and PORT2(DIT) are used. Nothing should be connected to PORT1(DIR), PORT4(DSP) and
J12(EXT).
JP36
MCLK
JP33
BICK
JP38
LRCK
JP35
PHASE
JP48
M/S
DIR
EXT
DIR
4040
DIR
4040
THR
INV Master
Slave
Figure 5. Setting of evaluation of A/D using DIT of AK4118A
* JP50, JP51, JP53~55, JP60~65: Open
(a-3) Board Setting: Figure 4
(a-4) Path Setting
Example of path Setting: LineIN1→ADC→SDTO
Register map
After volume control point is moved,
setting value is reflected.
The filter name is selected
The “Threshold Low Level” point is selected,
the movement operation is done while left
Figure 6. Example of A/D Path setting
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(b) Evaluation of D/A using DIR of AK4118A
(b-1) Clock Mode: Ext Slave Mode
(b-2) Jumper Setting
PORT1(DIR) is used. Nothing should be connected to PORT2(DIT), PORT4(DSP), X2(X’TAL) and
J12(EXT).
JP36
MCLK
JP33
BICK
JP47
LRCK
JP51
SDTI
JP35
PHASE
JP48
M/S
DIR
EXT
DIR
4040
DIR
4040
DIR
ADC
THR
INV
Master
Slave
Figure 7. Setting of D/A using DIR of AK4118A
*JP50, JP51, JP53~55, JP60~65: Open
(b-3) Board Setting: Figure 4
(b-4) Path Setting
Example of path Setting: SDTI→DAC→Lineout
Figure 8. Example of D/A Path setting
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(c) Evaluation of A/D using interface signals are fed externally.
(c-1) Clock Mode: PLL Slave Mode
(c-2) Jumper Setting
PORT3 (Baseband) and JP105 (DSP2) are used. Nothing should be connected to PORT1(DIR),
PORT2(DIT), PORT4(DSP), X2(X’TAL) and J12(EXT).
PORT3
Baseband
JP105
DSP2
MCLK2
BICKA
SDOUT3
SDIN3
LRCKA
SDTIA
SYCN3
JP62
BICKA
JP47
BICKA_PHASE
THR
INV
JP49
PLLBT
JP35
SYNCA
JP60
SDTIA
BICKA BICKB
BICK3
SDTOA
Figure 9. Setting of A/D using external clock
* JP33~JP38, JP43, JP45, JP48, JP51, JP53~55, JP61, JP64, JP65: Open
(c-3) Board Setting: Default
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(c-4) Path Setting
Example of path Setting: LineIN1→ADC→SDTOA
Figure 10. Example of A/D Path setting2
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(d) Evaluation of D/A using interface signals are fed externally.
(d-1) Clock Mode: PLL Slave Mode
(d-2) Jumper Setting
PORT3 (Baseband) is used. Nothing should be connected to PORT1(DIR), PORT2(DIT), PORT4(DSP),
X2(X’TAL) and J12(EXT).
PORT3
JP62
JP47
JP49
JP35
JP60
BICKA BICKA_PHASE
PLLBT
Baseband
SYNCA
SDTIA
MCLK2
BICKA
THR
INV BICKA BICKB
LRCKA
SDTIA
SDTOA
Figure 11. Setting of D/A using external clock
*JP33~JP38, JP43, JP45, JP48, JP51, JP53~55, JP61, JP64, JP65: Open
(d-3) Board Setting: Default
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(d-4) Path Setting
Example of path Setting : SDTIA→DAC→Lineout
Figure 12. Example of D/A Path setting2
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3) Setup the PCM I/F Evaluation Mode
■Clock Setting
AK4679
PORT3(Baseband)
SYNCA
BICKA
1fs2
 16fs2
SYNC
BICK
SDTOA
SDTI
SDTIA
SDTO
PORT6(Bluetooth)
SYNCB
BICKB
1fs3
16fs3 or  32fs3
SYNC
BICK
SDTOB
SDTI
SDTIB
SDTO
Figure 13. PCM I/F A and B
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■Board Setting
1) R108, R109, R110, R111, R114, R115, R116, R117 must be set to open.
2) CL108, CL109, CL110 must be set to open.
3) R108 pad and CL104 Pad (1), R109 pad and CL105 Pad (1), R110 pad and CL106 Pad (1),
R111 pad and CL107 Pad (1) must be connected.
CL104 Pad (2), CL106 Pad (2), CL107 Pad (2) must be connected to GND.
4)
R114 pad and CL108 Pad (1), R115 pad and CL109 Pad (1), R116 pad and CL110 Pad (1),
R117 pad and CN102 34pin must be connected.
Figure 14. PCM I/F board setting
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(3-1). PCM I/F A
(a) SYNCA and BICKA are fed from on-board clock generator.
X1(X’Tal) and PORT3(Baseband) are used. Nothing should be connected to PORT6(Bluetooth).
Please set JP42 (BCFS2) to the required frequency. Follows are setting in BICKA=32fs.
JP42
BCFS2
JP41
MCLK2
JP40
XTE
256fs2
128fs2
64fs2
XTL
EXT1
JP43
BICK2_SEL
JP45
LRCK2_SEL
BICKA BICKB
LRCKA LRCKB
32fs2
16fs2
JP62
BICKA
JP63
SYNCA
JP60
JP50
SDTIA SDTOA LOOP
JP47
BICKA PHASE
THR
INV
Figure 15. Setting of SYNCA and BICKA are fed from on-board clock generator.
JP47 (BICKA PHASE) is jumper which decides polarity of BICKA, “THR” or “INV” should be selected
according to the PCM I/F format.
In case of loop-back “SDTOA → SDTIA”, JP50 (SDTOA LOOP) is set to “SHORT”.
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(b) SYNCA and BICKA are fed externally via PORT3 (Baseband Module).
PORT3 (Baseband Module) is used.
SYNCA and BICKA should be supplied from PORT3.
JP41
MCLK2
JP40
XTE
JP43
BICK2_SEL
JP45
LRCK2_SEL
BICKA BICKB
LRCKA LRCKB
XTL
EXT1
JP62
BICKA
JP63
SYNCA
JP60
JP50
SDTIA SDTOA LOOP
JP47
BICKA PHASE
THR
INV
Figure 16. Setting of SYNCA and BICKA are fed externally via PORT3 (Baseband Module).
JP47 (BICKA PHASE) is jumper which decides polarity of BICKA, “THR” or “INV” should be selected
according to the PCM I/F format.
In case of loop-back “SDTOA → SDTIA”, JP50 (SDTOA LOOP) is set to “SHORT”.
(3-2). PCM I/F B
(a) SYNCB and BICKB are fed from on-board clock generator.
X1(X’Tal) and PORT6(Bluetooth) are used. Nothing should be connected to PORT3(Baseband).
Please set JP42 (BCFS2) to the required frequency. Follows are setting in BICKB=32fs.
JP42
BCFS2
JP41
MCLK2
JP40
XTE
256fs2
128fs2
64fs2
XTL
EXT1
JP43
BICK2_SEL
JP45
LRCK2_SEL
BICKA BICKB
LRCKA LRCKB
32fs2
16fs2
JP64
BICKB
JP65
SYNCB
JP61
JP55
SDTIB SDTOB LOOP
JP54
BICKB PHASE
THR
INV
Figure 17. Setting of SYNCB and BICKB are fed from on-board clock generator.
JP54 (BICKB PHASE) is jumper which decides polarity of BICKB, “THR” or “INV” should be selected
according to the PCM I/F format.
In case of loop-back “SDTOB → SDTIB”, JP55 (SDTOB LOOP) is set to “SHORT”.
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(b) SYNCB and BICKB are fed externally via PORT6 (Bluetooth Module).
PORT6 (Bluetooth Module) is used.
SYNCB and BICKB should be supplied from PORT6.
JP41
MCLK2
JP40
XTE
JP43
BICK2_SEL
JP45
LRCK2_SEL
BICKA BICKB
LRCKA LRCKB
XTL
EXT1
JP64
BICKB
JP65
SYNCB
JP61
JP55
SDTIB SDTOB LOOP
JP54
BICKB PHASE
THR
INV
Figure 18. Setting of SYNCA and BICKA are fed externally via PORT3 (Baseband Module).
JP54 (BICKB PHASE) is jumper which decides polarity of BICKB, “THR” or “INV” should be selected
according to the PCM I/F format.
In case of loop-back “SDTOB → SDTIB”, JP55 (SDTOB LOOP) is set to “SHORT”.
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4) Other Jumper pins Setup
[ JP16 (LOUT_SEL) ]: The selection of output signal to J1(BNC jack) connector.
LOUT : Connect to LOUT signal. (Default)
HPL
: Connect to HPL signal.
[ JP17 (HPL JACK) ]: The selection of analog signal of HPL pin
SHORT : Analog signal of HPL pin is output from J3 (mini jack) connector. (Default)
OPEN : Analog signal of HPL pin is output from J1 (BNC jack) connector.
[ JP19 (HPR JACK) ]: The selection of analog signal of HPR pin
SHORT : Analog signal of HPR pin is output from J3 (mini jack) connector. (Default)
OPEN : Analog signal of HPR pin is output from J4 (BNC jack) connector.
[ JP20 (AVDD_SEL) ]: The selection of AVDD.
SHORT : AVDD is supplied from the regulator (“AVDD” jack should be open). (Default)
OPEN : AVDD is supplied from “AVDD” jack.
[ JP21 (ROUT_SEL) ]: The selection of output signal to J4(BNC jack) connector.
ROUT : Connect to ROUT signal. (Default)
HPR : Connect to HPR signal.
[ JP23 (LIN_SEL) ]: The selection of input signal from J5(BNC jack) connector.
LIN2 : Connect to LIN2/IN2+ pin. (Default)
LIN3 : Connect to LIN3/IN3+ pin.
LIN4 : Connect to LIN4 pin.
[ JP24 (PVDD_SEL) ]: The selection of PVDD.
SHORT : PVDD is supplied from the regulator (“PVDD” jack should be open). (Default)
OPEN : PVDD is supplied from “PVDD” jack.
[ JP25 (RIN_SEL) ]: The selection of input signal from J7(BNC jack) connector.
RIN2 : Connect to RIN2/IN2- pin. (Default)
RIN3 : Connect to RIN3/IN3- pin.
RIN4 : Connect to RIN4 pin.
[ JP26 (DVDD_SEL) ]: The selection of DVDD.
SHORT : DVDD is supplied from the regulator (“DVDD” jack should be open). (Default)
OPEN : DVDD is supplied from “DVDD” jack.
[ JP29 (TVDD_SEL) ]: The selection of TVDD.
SHORT : TVDD is supplied from the regulator (“TVDD” jack should be open). (Default)
OPEN : TVDD is supplied from “TVDD” jack.
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[ JP30 (GND) ]: Analog ground and Digital ground
SHORT : Common. (The connector “DGND” can be open.)
OPEN : Separated. (Default)
[ JP31 (VCC_SEL) ]: The selection of VCC.
SHORT : VCC is supplied from the regulator (“VCC1” jack should be open). (Default)
OPEN : VCC is supplied from “VCC1” jack.
[ JP32 (MKFS) ]: The selection of MCLK frequency. (Open)
256fs : 256fs.
512fs : 512fs.
1024fs : 1024fs.
384/768fs: Not to use.
[ JP34 (BCFS) ]: The selection of BICK frequency. (Open)
64fs-384: Don’t use.
32fs-384: Don’t use.
64fs
: 64fs
32fs
: 32fs
[ JP66 (VCC2_SEL) ]: The selection of VCC2.
SHORT : VCC2 is supplied from the regulator (“VCC2” jack should be open). (Default)
OPEN : VCC2 is supplied from “VCC2” jack.
[ JP100 (INPUT SEL1) ]: The selection of input signal to LIN1/IN1+/DMDAT pin
LIN1/IN1+: Analog signal is input from J2 (mini jack) connector. (Default)
DMDAT : Digital microphone data is input to DMDAT pin.
[ JP101 (INPUT SEL2) ]: The selection of input signal to RIN1/IN1-/DMCLK pin
RIN1/IN1-: Analog signal is input from J2 (mini jack) connector. (Default)
DMCLK : DMCLK for digital microphone is supplied to CN5.
[ JP102 (MPWR1 SEL) ]: The selection of Mic-power1.
SHORT : MIC-power1 is supplied.
OPEN : MIC-power1 is not supplied. (Default)
[ JP103 (MPWR2 SEL) ]: The selection of Mic-power2.
SHORT : MIC-power2 is supplied.
OPEN : MIC-power2 is not supplied. (Default)
[ JP104 (DMIC PWR) ]: The selection of Mic-power for Digital MIC.
SHORT : MIC-power for Digital MIC is supplied to CN6.
OPEN : MIC-power for Digital MIC is not supplied. (Default)
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5) Setup the DIP SW.
Upper-side is “ON(H)” and lower-side is “OFF(L)”.
[S1] (SW DIP-6): Mode setting for AK4679 and AK4118A.
No.
1
2
3
4
5
Name
DIF2
DIF1
DIF0
OCKS1
CAD0
6
I2S
ON (“H”)
OFF (“L”)
AK4118A Audio Format Setting
See Table 3
AK4118A Master Clock Setting : See Table 4
Slave Address 0 Input pin
Control Interface Mode Select Pin
I2S
SPI
Default
ON
OFF
OFF
OFF
ON
ON
Table 2. Mode Setting for AK4679 and AK4118A
DIF2
L
L
L
L
H
H
H
H
DIF1
L
L
H
H
L
L
H
H
DIF0
L
H
L
H
L
H
L
H
DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
SDTO
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
LRCK
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
BICK
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
O
O
O
O
O
O
I
I
Default
Table 3. Setting for AK4118A Audio Interface Format
OCKS1
L
H
MCKO1
256fs
512fs
X’tal
256fs
512fs
Default
Table 4. Setting for AK4118A Master Clock
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 Function of the Toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (DIR)
: Resets the AK4118A. Keep “H” during normal operation.
The AK4118A should be resets once bringing “L” upon power-up.
[SW2] (PDN)
: Resets the AK4679. Keep “H” during normal operation.
The AK4679 should be resets once bringing “L” upon power-up.
 Indication for LED
[LED1] (UNLOCK): Monitor INT0 pin of the AK4118A.
LED turns on when some error has occurred to AK4118A.
■ Control Box
The AKD4679-A should be connected to a PC via an USB control box. The USB control box is connected to a PC with an USB
cable and the AKD4679-A with 10-pin flat cable.
Flat 10pin
USB
Figure 19. Connection of Control Box
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 Analog Input/Output Circuits
(1) Input Circuits
(1-1) LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuits
Figure 20. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuits
LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 share J5/J7.
JP23 (LIN_SEL) and JP25 (RIN_SEL) select each path.
(1-2) MIC Power1, MIC Power2 Input Circuits
Figure 21. MIC Power1, MIC Power2 Input Circuits
Supplying MIC power1 to LIN1/RIN1 and Supplying MIC Power2 to LIN2/RIN2
are selected by JP108 and JP 109.
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(2) Output Circuits
(2-1) LOUT/ROUT and HP Output Circuit
Figure 22. LOUT/ROUT and HP Output Circuit
LOUT/ROUT and HPL/HPR share J1/J4.
JP16 (LOUT_SEL) and JP21 (ROUT_SEL) select each path.
Figure 23. HP-amp Oscillation Prevention Circuit
HP-amp Oscillation Prevention Circuit is composed by C129 and R122.
R128 and R129 are load resistance for HP Output.
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(2-2) SPK and RCV Output Circuit
Figure 24. SPK and RCV Output Circuit
* AKM assumes no responsibility for the trouble when using the above circuit examples.
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Control Soft Manual
■ Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect the evaluation board to an Control Box by a 10wire flat cable. When running this control soft on the
Windows 2000/XP/Vista/7, the driver which is included in the CD must be installed. Refer to the “Driver Control
Install Manual for AKM Device Control Software” for installing the driver.
3. Then please evaluate according to the following descriptions.
[Support OS]
Windows 2000 / XP / Vista / 7 (32bit) (XP compatible mode is recommended for Vista / 7)
64bit OS’s are not supported.
Windows 95 / 98 / Me / NT are not supported.
■ Operation Screen
1. Start up the control program following the process above.
2. After the evaluation board’s power is supplied, the AK4679 must be reset once bring SW2 (PDN) “L” to “H”, and
Click [Dummy Command] button.
3. The operation screen is shown below.
Figure 25. Window of Control Soft
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■ Function Button
[ MIC_Input_Record ]
When [MIC_Input_Record] button is clicked,
[LIN2/RIN2  MICL/R  ADCL/R  ALC  Audio I/F  SDTO] sequence is set up.
Set up the evaluation board is referred to 2) (a) Evaluation of A/D using DIT of AK4118A.
[ HP_Out ]
When [HP_Out] button is clicked,
[SDTI  Audio I/F  5-band EQ  DATT-A  DACL/R  HPL/HPR] sequence is set up.
Set up the evaluation board is referred to 2) (b) Evaluation of D/A using DIR of AK4118A.
[ SPK_Out ]
When [SPK_Out] button is clicked,
[SDTI  Audio I/F  5-band EQ  DATT-A  DACL/R  SPP/SPN] sequence is set up.
Set up the evaluation board is referred to 2) (b) Evaluation of D/A using DIR of AK4118A.
[ Stereo_Line_Out ]
When [Stereo_Line_Out] button is clicked,
[SDTI  Audio I/F  5-band EQ  DATT-A  DACL/R  LOUT/ROUT] sequence is set up.
Set up the evaluation board is referred to 2) (b) Evaluation of D/A using DIR of AK4118A.
[ PCM IF_AtoB ]
When [PCMIF_AtoB] button is clicked,
[SDTIAPCM I/F ASRCAIDATT-CMIX3PCM I/F BSDTOB &
SDTIBPCM I/F BBIVOLMIX2AMIX2CSRCAOPCM I/F ASDTOA] sequence is set up.
Set up the evaluation board is referred to
3) (a) SYNCA and BICKA are fed from on-board clock generator (for PCM I/F A PCM I/F B)
or 3) (c) SYNCB and BICKB are fed from on-board clock generator (for PCM I/F B PCM I/F B)
[ RCV_Out ]
When [RCV_Out] button is clicked,
[SDTIAPCM I/F ASRCAIDATT-BMIX1R5-Band EQDATT-ADACRRCP/RCN]
sequence is set up.
Set up the evaluation board is referred to
3) (a) SYNCA and BICKA are fed from on-board clock generator
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■Operation
Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the
switching tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting.
1.
[Port Reset]: For when connecting to USB I/F board (AKDUSBIF-B)
Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-B).
2.
[Write Default]: Register Initializing
When the device is reset by a hardware reset (PDN pin = “L”), use this button to initialize the
registers.
3.
[All Write]: Executing write commands for all registers displayed.
4.
[All Read]: Executing read commands for all registers displayed.
5.
[Save]: Saving current register settings to a file.
6.
[Load]: Executing data write from a saved file.
7.
[All Reg Write]: “All Reg Write” dialog box is popped up.
8.
[Data R/W]: “Data R/W” dialog box is popped up.
9.
[Sequence]: “Sequence” dialog box is popped up.
10. [Sequence(File)]: “Sequence(File)” dialog box is popped up.
11. [Read]: Reading current register settings and display on to the Register area
(on the right of the main window).
This is different from [All Read] button, it does not reflect to a register map, only displaying
hexadecimal.
12. [Dummy Command]: Write a dummy command
After the evaluation board power is supplied, the AK4679 must be reset once bring SW2 (PDN) “L” to
“H”, and then the [Dummy Command] button should be clicked once to reset the register setting of the
AK4679.
*Refer to the board manual of AK7719 for a control setup of DSP.
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■ Tab Functions
1. [Function]: Function control
This tab is for function control.
Each operation is executed by the function buttons on the left side of the screen.
Figure 26. Window of [Function]
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1-1. Power Management Setting
When [Power Management Setting] button is clicked, the window as shown in Figure 27 opens.
This window is for Power Management Setting.
Refer to the datasheet for register settings of the AK4679.
Figure 27. Window of [Power Management Setting]
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1-2. Audio Mode Setting
When [Audio Mode] button is clicked, the window as shown in Figure 28 opens.
This window is for Audio Mode Setting.
Refer to the datasheet for register settings of the AK4679.
Figure 28. Window of [Audio Mode Setting]
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1-3. System Clock, Audio I/F Setting
When [PLL Setting] button is clicked, the window as shown in Figure 29 opens.
This window is for System Clock and Audio I/F Setting
Refer to the datasheet for register settings of the AK4679.
Figure 29. Window of [PLL Setting]
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1-4. MIC Setting
When [MIC Setting] button is clicked, the window as shown in Figure 30 opens.
This window is for MIC Setting.
Refer to the datasheet for register settings of the AK4679.
Figure 30. Window of [MIC Setting]
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1-5. ALC Setting
When [ALC Setting] button is clicked, the window as shown in Figure 31 opens.
This window is for ALC setting.
Refer to the datasheet for register settings of the AK4679.
Figure 31. Window of [ALC Setting]
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1-6. Volume Setting
When [Volume Setting] button is clicked, the window as shown in Figure 32 opens.
This window is for Volume setting.
Refer to the datasheet for register settings of the AK4679.
Figure 32. Window of [Volume Setting]
Register map
The volume can be controlled by slide bars.
Register writing is made on every slide bar move.
After the volume slide is moved, it is reflected on to the register map and data writing dialog box.
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Volume Control by Pull-down Menu
Slide bar is
moved to the
selected value
Figure 33. Volume Control by Pull-down Menu
The volume can also be changed by writing a value in a dialog box. The slide bar is moved to the value that written in
the dialog box. Use the mouse or arrow keys on the keyboard for small adjustments.
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1-7. Digital Filter Setting
When [Digital Filter Setting] button is clicked, the window as shown in Figure 34 opens.
Refer to the datasheet for register settings of the AK4679.
A calculation of a coefficient of Digital Programmable Filters such as HPF / LPF and EQ filters,
a register writing and a frequency response checking of HPF / LPF and EQ filter can be made.
Figure 35. Window of [Digital Filter Setting]
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1-7-1. Parameter Setting
(1) Please set a parameter of each Filter.
Parameter
Function
Sampling Rate
HPF
Cut Off Frequency
Sampling frequency (fs)
Setting Range
7350Hz ≤ fs ≤ 48000Hz
High pass filter cut off frequency
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
HPF2
Cut Off Frequency
Low pass filter cut off frequency
fs/1000 ≤ Cut Off Frequency
≤ (0.497 * fs)
FIL3
Cut Off Frequency
FIL3 cut off frequency
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-10≤ Gain < 0
Gain
Gain
EQ for Gain Compensation(EQ0)
EQ0 Pole Frequency
Pole Frequency
Zero-point Frequency
EQ0 Zero-point Frequency
Gain
3 Band Equalizer
EQ1-3 Center Frequency
EQ1-3 Band Width
EQ1-3 Gain
DAC 5-Band Equalizer
Center Frequency
Gain
Band Width
Gain
EQ2-4 Band Width
LPF1 EQ1-5 HPF1 Gain
EQ1-3 Center Frequency
EQ1-3 Band Width
EQ1-3 Gain
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-20≤ Gain < 12
(Note 1)
(Note 2)
LPF1 EQ1-5 HPF1 Center Frequency
0Hz ≤ Center Frequency < (0.497 * fs)
1Hz ≤ Band Width < (0.497 * fs)
-1≤ Gain < 3
fs/1000 ≤ Cut Off Frequency
< (0.497 * fs)
1Hz ≤ Band Width < (0.497 * fs)
-12 ≤ Gain ≤ 12
Note 1. Gain difference is a bandwidth of 3dB from center frequency.
Note 2. When the gain is smaller than 0, EQ becomes a notch filter.
(2) “HPFAD Enable”, “HPF Enable” , “LPF Enable” “FIL3 Enable”, “EQ0 Enable”, “EQ1”, “EQ2”, “EQ3”,
Please set ON/OFF of Filter with a check button. When checked it, Filter becomes ON. When “Notch Filter Auto
Correction” is checked, perform automatic correction of the center frequency of the notch filter is executed.
Figure 36. Filter ON/OFF setting button
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1-7-2. Calculation of Register
Register set value is displayed when push a [Register Setting] button. When a value out of a setting range is set, error
message is displayed, and a calculation of register setting is not carried out.
Figure 37. Register setting calculation result
Followings are the cases when a register set value is updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
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1-7-3. Indication of Frequency Characteristic
Frequency characteristic is displayed when push a [F Response] button. Then, a register set point is also updated.
Change “Frequency Range”, and indication of a frequency characteristic is updated when push a [UpDate] button.
Figure 38. A frequency characteristic indication result
Followings are the cases when a register set value is updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
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1-7-4. Filter Setting
(a) 3-band Equalizer, DAC 5-band Equalizer
The filter setting can be executed by dragging the number to each equalizers in the mouse.
Band Width can be adjusted in the operation of Center Frequency, K and Gain right-clicking in the operation of the
left-click.
After operating the mouse ,
the value of the center frequency
and the gain is updated.
The number is selected ,
the movement operation is done
while left-clicking.
Figure 39. Filter Setting (Right-clicking operation)
After operating the mouse ,
the value of the bandwidth is updated.
Figure 40. Filter Setting (Left-clicking operation)
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After operating the mouse ,
the value of the center frequency
and the gain is updated.
The number is selected ,
the movement operation is done
while left-clicking.
Figure 41. Filter Setting(Gain-Control operation)
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1-8. DRC Setting
When [DRC Setting] button is clicked, the window as shown in Figure 42 opens.
This window is for DRC setting.
Refer to the datasheet for register settings of the AK4679.
Figure 43. Window of [DRC Setting]
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1-8-1. Parameter Setting
(1)
Please set a parameter of each Filter and Gain.
Parameter
Function
Sampling Rate
Noise Suppression
LPF
Sampling frequency (fs)
HPF
High pass filter cut off frequency
Gain
Threshold Level
Reference Value Setting
Noise Suppression Threshold
Low/High Level
Low pass filter cut off frequency
Dynamic Volume Control
Low Frequency Range
LPF
Low pass filter cut off frequency
Volume Control
Middle Frequency Range
LPF
Volume point setting
Low Frequency Range
Low pass filter cut off frequency
HPF
High pass filter cut off frequency
Volume Control
High Frequency Range
HPF
Volume point setting
Volume Control
Volume point setting
Setting Range
7350Hz ≤ fs ≤ 48000Hz
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-9 ≤ Gain < -54 (Note 3)
-82.5≤ Threshold Level < -36.0
(Note 4)
High pass filter cut off frequency
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-70.5≤ Gain < 0 (Note 5)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-70.5≤ Gain < 0
fs/10000 ≤ Cut Off Frequency
≤ (0.497 * fs)
-70.5≤ Gain < 0
Note 3. Gain step of “Reference Value of Noise Suppression” is 3dB.
Note 4. Gain step of “Threshold level Value of Noise Suppression” is 3dB.
Note 5. Gain step of “Volume point Value of Dynamic Volume Control” is 3dB.
(2) When “NSLPF” button is checked, the filter is enabled. When “NSHPF” button is checked, the filter is enabled.
When “DVLC Enable” button is checked, the filters of Low/Middle/High Range are enabled according to setting of
pull-down menu. When “fc Auto” button is checked, the frequency response of low frequency and high frequency
ranges becomes flat automatically.
Figure 44. Filter ON/OFF setting button
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1-8-2. Frequency Response
Frequency characteristic is displayed when pushing a [F Response] button. Then, a register set point is also updated.
When changing “Frequency Range”, frequency characteristic indication window is updated after [UpDate] button is
pushed.
Figure 45. A frequency characteristic indication result
Followings are the cases when a register set value is updated.
(1).
(2).
(3).
(4).
When [Register Setting] button was pushed.
When [Frequency Response] button was pushed.
When [UpDate] button was pushed on a frequency characteristic indication window.
When set ON/OFF of a check button “fc Auto”
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1-8-3. Filter Setting
The filter setting can be executed by checking the “NSLPF”, “NSHPF” or “DVLC Enable” button.
Band width can be adjusted in the operation of Center Frequency in the operation of the left-click and Filter selecting in
the [DRC Setting] window.
After operating the mouse ,
the value of the cut-off frequency
is updated.
The filter name is selected ,
the movement operation is done
while left-clicking.
Figure 46. Filter Setting (Left-clicking operation)
The filter mode is selected ,
the movement operation is done.
Figure 47. Filter Setting (Filter Selecting)
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1-8-4. Noise Suppression
Noise Suppression Control is displayed when “NS” button is checked after [DRV Curve] button is pushed.
Then, a register set point is also updated.
Noise Suppression Threshold Low Level and Reference Value can be adjusted by the left-click.
Noise Suppression
Threshold Low Level
Reference Value
Register map
After “Threshold Low Level” point is moved,
setting value is reflected.
The “Threshold Low Level” point is selected,
the movement operation is done while left- clicking.
Figure 48. Noise Suppression Setting
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1-8-5. Dynamic Volume Control
Dynamic Volume is displayed when “Low”, ”Middle” or “High” buttons in “DVLC” is checked after [DRV Curve]
button is pushed.
Then, a register set point is also updated.
Dynamic Volume Control Points can be adjusted by the left-click.
Select the frequency range for
DVLV curve.
Red: LOW
Blue: MIDDLE
Green: HIGH
Register map
DVLC volume control point
in Low range
After volume control point is moved,
setting value is reflected.
The volume control point is selected,
the movement operation is done while
left-clicking.
Figure 49. DVLC Curve Setting
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1-8-6. Dynamic Range Control
Dynamic Range Control is displayed when “DRC” button is checked after [DRV Curve] button is pushed. Then, a
register set point is also updated.
Dynamic Range Compression Level can be adjusted by the left-click.
Register map
After “DRC Compression Level” is moved,
setting value is reflected.
The “DRC Compression Level” is selected, the
movement operation is done while left- clicking.
Figure 50. Dynamic Range Control Setting
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2. [REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Grayout registers are Read Only registers. They can not be controlled.
The registers which is not defined in the datasheet are indicated as “---”.
Figure 51. Window of [REG]
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[Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
Figure 52. Window of [Register Set]
[Read]: Data Read
Click [Read] button located on the right of the each corresponded address to execute register reading.
After register reading, the display will be updated regarding to the register status.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Please be aware that button statuses will be changed by Read command.
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[Repeat Test]: Repeat Test Dialog
Click [Repeat Test] button to open repeat test setting dialog box.
Figure 53. Window of [Repeat Test]
[Loop Setting]: Loop Setting Dialog
Click [Loop Setting] button to open loop setting dialog box.
Figure 54. Window of [Loop]
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Dialog Boxes
[All Reg Write]
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
Figure 55. Window of [All Register Write]
[Open (left)]
[Write]
[Write All]
[Help]
[Save]
[Open (right)]
[Close]
: Selecting a register setting file (*.akr).
: Executing register writing.
: Executing all register writings.
Writings are executed in descending order.
: Help window is popped up.
: Saving the register setting file assignment. The file name is “*.mar”.
: Opening a saved register setting file assignment “*. mar”.
: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register
settings.
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[Data R/W]
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Figure 56. Window of [Data Read/Write]
Address Box : Input data address in hexadecimal numbers for data writing.
Data Box
: Input data in hexadecimal numbers.
Mask Box
: Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write]
[Close]
: Writing to the address specified by “Address” box.
: Closing the dialog box and finish the process.
Data writing can be cancelled by this button instead of [Write] button.
*The register map will be updated after executing [Write] or [Read] commands.
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[Sequence]
Click [Sequence] button to open register sequence setting dialog box.
Register sequence can be set in this dialog box.
Figure 57. Window of [ Sequence ]
Sequence Setting
Set register sequence by following process bellow.
(1)Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use
: Not using this address
· Register
: Register writing
· Reg(Mask) : Register writing (Masked)
· Interval
: Taking an interval
· Stop
: Pausing the sequence
· End
: Finishing the sequence
(2)Input sequence
[Address]
[Data]
[Mask]
[ Interval ]
: Data address
: Writing data
: Mask
[Data] box data is ANDed with [Mask] box data. This is the actual writing data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
: Interval time
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Valid boxes for each process command are shown bellow.
· No_use
· Register
· Reg(Mask)
· Interval
· Stop
· End
: None
: [Address], [Data], [Interval]
: [Address], [Data], [Mask], [Interval]
: [Interval]
: None
: None
Control Buttons
The function of Control Button is shown bellow.
[Start]
[Help]
[Save]
[Open]
[Close]
: Executing the sequence
: Opening a help window
: Saving sequence settings as a file. The file name is “*.aks”.
: Opening a sequence setting file “*.aks”.
: Closing the dialog box and finish the process.
Stop of the Sequence
When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked.
Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence,
“Start Step” will return to “1”.
The sequence can be started from any step by writing the step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
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[Sequence(File)]
Click [Sequence(File)] button to open sequence setting file dialog box.
Those files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 58. Window of [ Sequence(File) ]
[Open (left)] : Opening a sequence setting file (*.aks).
[Start]
: Executing the sequence setting.
[Start All]
: Executing all sequence settings.
Sequences are executed in descending order.
[Help]
: Pop up the help window.
[Save]
: Saving sequence setting file assignment. The file name is “*.mas”.
[Open(right)] : Opening a saved sequence setting file assignment “*. mas”.
[Close]
: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog
“*.mas” should be stored in the same folder.
(2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click
“OK” to continue the process.
Figure 59. Window of [ Sequence Pause ]
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Measurement Result
[Measurement condition]
 Measurement Unit
 MCLK
 BICK
 fs
 Power Supply
 Band Width
 Measurement Mode
 Temperature
: Audio Precession System Two Cascade
: 11.2896MHz
: 64fs
: 44.1kHz
: AVDD=DVDD=PVDD=TVDD=TVDDE=1.8V, VDDE=1.2V, SVDD=4.2V
: 22Hz ~ 20kHz
: PLL Slave Mode
: Room Temperature
[Measurement Result]
1. ADC
a). LIN1, RIN1 pins, MGNL=MGNR=+18dB, single-ended mode
Result
Lch / Rch
Parameter
Unit
S/(N+D) (-1dBFS Input)
81.5
/
81.5
dB
D-Range (-60dBFS Input, A-weighted)
87.1
/
87.0
dB
S/N (A-weighted)
87.4
/
87.4
dB
b). LIN1, RIN1 pins, MGNL=MGNR=0dB, single-ended mode
Result
Lch / Rch
Parameter
Unit
S/(N+D) (-1dBFS Input)
82.7
/
82.3
dB
D-Range (-60dBFS Input, A-weighted)
92.3
/
92.3
dB
S/N (A-weighted)
93.3
/
93.2
dB
2. DAC
a) Line out (LOUT/ROUT pins, LVL=0dB, RL=10kΩ)
Result
Lch / Rch
Parameter
Unit
S/(N+D) (0dBFS Input)
81.2
/
81.1
dB
S/N (A-weighted)
93.3
/
93.3
dB
b) Mono Line Out (LOP/LON pins, LVL=0dB, RL=10kΩ)
Parameter
Result
Unit
S/(N+D) (0dBFS Input)
73.3
dB
S/N (A-weighted)
96.2
dB
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c) Mono Receiver Out (RCP/RCN pins, RCVG=-6dB, RL=32)
Parameter
Result
Unit
S/(N+D) (0dBFS Input)
59.7
dB
S/(N+D) (0dBFS Input, RCVG=0dB)
56.7
dB
S/N (A-weighted)
95.3
dB
-103.4
dBV
Output Noise Level (RCVG=-9dB)
d) HP Out (HPL/HPR pins, HPG=0dB, RL=32)
Result
Lch / Rch
Parameter
Unit
HPG=-4dB
1.58
1.58
HPG=0dB
2.521
2.50
HPG=-4dB
1.56
1.56
Vpp
HPG=0dB
0.83
0.83
Vrms
HPG=-4dB
71.6
71.8
HPG=0dB
70.8
70.9
HPG=-4dB
66.3
66.4
HPG=0dB
24.7
23.9
S/N (A-weighted)
95.8
95.7
Output Noise Level
(A-weighted, HPG=-14dB)
-106.7
-106.7
Vpp
Output Voltage (RL=32)
Output Voltage (RL=16)
dB
S/(N+D) (RL=32)
dB
S/(N+D) (RL=16)
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e) SPK Out (SPPL/SPNL, SPPR/SRNR pins, SPKG=0dB, RL=8+10uH)
Parameter
Output Power
Result
SVDD=5.0V THD+N=10%
SPKG=-3dB
1.52
SVDD=4.2V THD+N=10%
SPKG=-3dB
1.07
SVDD=4.2V THD+N=1%
SPKG=0dB
0.87
SVDD=3.7V THD+N=1%
SPKG=-6dB
0.67
Unit
W
Output Voltage (-3dBFS Input)
5.40
Vpp
S/(N+D) (SVDD=3.7V, Po=0.35W)
60.0
dB
Output Noise Level (A-Weighted)
-82.0
dBV
[KM111200]
2012/04
- 58 -
[AKD4679-A]
Revision History
Date
(YY/MM/DD)
12/04/04
Manual
Revision
KM111200
Board
Revision
1
Reason
Page
First edition
-
Contents
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or
third parties arising from the use of these information herein. AKM assumes no liability for infringement of any
patent, intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any
and all claims arising from the use of said product in the absence of such notification.
[KM111200]
2012/04
- 59 -
4679-AVDD
RIN4
E
4679-PVDD
D
LIN4
RIN3
LIN3
LIN2
RIN2
C
RIN1
B
LIN1
A
CN4
80pin_4
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
E
80
E
CN3
CN1
D
1
60
2
59
D
HPL
3
58
4
57
5
56
6
55
7
54
8
53
HPR
LOUT
ROUT
4679-TVDD
4679-SDTOB
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
4679-SYNCB
C
C
4679-BICKB
4679-SDTIB
4679-SDTI
4679-SDTO
4679-LRCK
4679-BICK
RCN
4679-MCKI
B
4679-MCKO
80pin_1
20pin
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
80pin_3
21
A
B
RCP
A
A
B
C
4679-SVDD
SPP
SPN
4679-SDTOA
-60-
4679-SYNCA
4679-BICKA
4679-SDTIA
4679-DVDD
CDTI/SDA
CCLK/SCL
CSN/CAD0
CDTO
4679-I2C
4679-PDN
CN2
80pin_2
Title
Size
A2
Date:
D
AKD4679-A
Document Number
Rev
Under SUB Board
Thursday, July 07, 2011
E
Sheet
1
0
of
5
A
B
C
D
E
T45_RED
E
C42 +
(open)
C41
0.33u
C43
2.2u
1
HPL
LOUT
T45_BK
J2
1
+
RIN1
JP17
R34
HPL JACK (short)
4679-SVDD
C45
(short)
JP58
C48
47u
JP20
AVDD_SEL
4679-AVDD
2
2
3
4
5
(short)
J5
LIN
1
C50
R39
(short) (short)
LIN2
JP23
LIN2
LIN3
LIN4
JP19
HPR JACK
LIN4
HPR
ROUT
HPR
ROUT
JP21
ROUT_SEL
+
2
T45_OR
1
1
1
PVDD
C52
47u
L4
JP24
PVDD_SEL
4679-PVDD
2
(short)
J7
RIN
1
C53
R42
(short) (short)
+
2
3
4
5
R41
(short)
RIN2
RIN3
RIN4
RIN3
1
1
1
+
2
T45_OR
C54
47u
L5
2
R36
Open
HP
C49
1u
R38
220
1
D
J4
ROUT
2
3
4
5
R40
20k
RCP
RIN_SEL
JP26
DVDD_SEL
C47
(short)
RIN2
JP25
1
RIN4
DVDD
J3
2
3
JP59
LIN_SEL
JP22
(short)
R37
(short)
LIN3
+
D
L2
+
+
2
T45_OR
1
2
3
4
5
R35
Open
1
C46
47u
1
1
AVDD
J1
LOUT
LIN1
LIN1/RIN1
1
1
R33
20k
+
2
T45_OR
2
R32
220
C44
1u
1
1
SVDD
JP16
LOUT_SEL
2
3
L1
(short)
HPL
LOUT
+
AGND
OUT
+
IN
1
1
2
REG1
GND
T1
TA48018BF
E
J6
2
3
RCN
RCV-OUT
4679-DVDD
(short)
1
SPP
C
J8
2
3
JP27
(short)
C
SPK-OUT
SPN
+
2
T45_OR
1
1
1
TVDD
C56
47u
JP30
GND
+
2
T45_OR
1
1
1
VCC1
C57
47u
B
1
+
2
T45_OR
1
1
VCC2
1
+
2
T45_OR
1
1
D3V1
DGND1
C96
47u
C58
47u
L7
2
JP29
TVDD_SEL
4679-TVDD
(short)
L8
JP31
VCC_SEL
2
VCC
(short)
L11
2
JP66
VCC2_SEL
B
VCC2
(short)
L9
2
D3V
(short)
1
T45_BK
A
A
-61-
Title
Size
A2
Date:
A
B
C
D
AKD4679-A
Document Number
Rev
Power Supply, I/O
Friday, April 06, 2012
E
Sheet
2
0
of
5
A
B
C
D
E
E
E
D3V
EXT_MCLK
EXT_BICK
4118A-BICK
JP32
14
C59
0.1u
JP39
EXT
D
7
11
MKFS
16
C60
0.1u
Vcc
8
GND
10
7
2
9
1
A
B
C
D
4040
JP37
LRCK
JP38
DIR LRCK_SEL
1
2
3
4
5
6
4118A-LRCK
14
13
12
11
15
QA
QB
QC
QD
Carry
JP35
INV PHASE
U4 74HC4040
U3 74AC74
3
4
5
6
EXT_LRCK
THR
BCFS
fs-384
fs
4040
A
MCLK
13
12
11
10
9
8
1CLR 2CLR
1D
2D
1CK
2CK
1PR
2PR
1Q
2Q
1Q
2Q
64fs-384
32fs-384
64fs
32fs
14
1A
1Y
2A
2Y
3A
3Y
4Y
4A
5Y
5A
6Y
6A
7
C62
0.1u
8
C61
0.1u
R47
10k
Vcc
D
4118A-INT0
4118A-PDN
D1
HSU119
GND
U6 74HC14
C63
0.1u
74AC163
L
H
SW1
DIR
2
U5
16
R46
1k
8
9
10
11
12
13
MCKO
ENT
ENP
Vcc
CLK
LOAD
CLR GND
LED1
ERF
K
R45
51
EXT
Q1
Q2
RST
Q3
Q4
Q5
Q6
Q7
Q8
VD
Q9
Q10
Q11
DGND Q12
K
1
2
3
4
5
6
JP36
DIR
1
9
7
6
5
3
2
4
13
12
14
15
1
CLK
A
J12
EXT
10
1
2
3
4
5
JP34
256fs
512fs
1024fs
384/768fs
MCKO
3
4118A-MCKO
JP33
DIR BICK_SEL
7
C65
0.1u
8
9
10
11
12
13
4679-PDN
C
K
14
C64
0.1u
4Y
4A
5Y
5A
6Y
6A
R48
10k
Vcc
D2
A
7
14
1
2
3
4
5
6
C
1A
1Y
2A
2Y
3A
3Y
HSU119
1
GND
Vcc
4Y
4A
5Y
5A
6Y
6A
1A
1Y
2A
2Y
3A
3Y
1
2
3
4
5
6
3
8
9
10
11
12
13
VCC
U7
74HCU04
GND
U8 74HC14
L
H
SW2
PDN
2
C66
0.1u
4.096MHz
X1
1
2
R49
1M
JP40
XTE
C67
5p
C68
5p
B
B
EXT_MCLK2
D3V
JP41
J13
EXT1
JP42
XTL
EXT1
R50
51
10
512fs2
11
MCLK2
16
JP44
EXT1
C69
0.1u
8
U9
CLK
Q1
Q2
RST
Q3
Q4
Q5
Q6
Q7
Q8
VD
Q9
Q10
Q11
DGND Q12
9
7
6
5
3
2
4
13
12
14
15
1
256fs2
128fs2
64fs2
32fs2
16fs2
BICKA
EXT_BICKA
BICKB
EXT_BICKB
JP43
BICK2_SEL
BCFS2
1fs2
74HC4040
A
LRCKA
EXT_LRCKA
LRCKB
EXT_LRCKB
A
JP45
LRCK2_SEL
Title
-62-
Size
A2
Date:
A
B
C
D
AKD4679-A
Document Number
Rev
CLOCK
Sheet
Thursday, July 07, 2011
E
0
3
of
5
A
B
C
D
E
D3V
E
PORT1
2
C70
0.1u
2
1
GND
OUT
E
L10 (short)
1
3
VCC
TORX
C71
0.1u
R51
470
C72 10u
+
C73
------OFF------
1
INT1
37
38
AVDD
R
VCOM
40
41
VSS3
42
RX0
NC
43
44
RX1
46
45
TEST1
S1
SW DIP-6
RX2
VSS4
47
48
1 2 3 4 5 6
IPS0/RX4
D
INT0
36
4118A-INT0
DIF2
DIF1
DIF0
OCKS1
CAD0
I2C
1
2
3
4
5
6
L
RX3
12
11
10
9
8
7
H
R52
10k
39
C74
0.47u
VCC
D
0.1u
2
3
4
CAD0
NC
OCKS0/CSN/CAD0
DIF0/RX5
OCKS1/CCLK/SCL
TEST2
CM1/CDTI/SDA
35
34
33
6
C
DIF1/RX6
CM0/CDTO/CAD1
U10
AK4118A
VSS1
RP1 47k
7
8
DIF2/RX7
PDN
XTI
IPS1/IIC
XTO
32
31
30
29
C
4118A-PDN
C75 5p
1
5
MCKO
JP46 4118A-MCKI
X2
11.2896MHz
2
7
6
5
4
3
2
1
4679-I2C
C76 5p
28
DAUX
27
26
4118A-BICK
B
25
LRCK
4118A-SDTO
24
MCKO1
23
VSS2
C78
0.1u
22
21
DVDD
VOUT/GP7
SDTO
20
UOUT/GP6
19
18
17
14
13
C77
0.1u
TX1/GP3
VIN/GP0
COUT/GP5
BICK
BOUT/GP4
XTL1
TVDD
12
MCKO2
16
B
XTL0
TX0/GP2
11
DAUX
15
10
P/SN
NC/GP1
9
C80
10u
+
+
4118A-LRCK
C79
10u
4118A-MCKO
PORT2
IN
VCC
A
GND
3
2
1
C81
0.1u
A
TOTX
Title
-63-
Size
A3
Date:
A
B
C
D
AKD4679-A
Document Number
Rev
DIR/DIT
Thursday, July 07, 2011
Sheet
E
0
4
of
5
A
B
C
D
VCC2
THR
EXT_BICKA
VCC
INV
D3V
E
JP47
BICKA PHASE
U12
U11
3
3
EXT_LRCK
4
EXT_BICK
5
E
6
7
7
6
5
4
3
2
1
R53
10k
1
3
5
7
9
PORT4
DSP
2 GND
4 GND
6
8
10 SDTO
9
10
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
21
4679-LRCK
20
4
EXT_LRCKA
4679-BICK
5
19
6
18
7
PORT3
7
6
5
4
3
2
1
16
15
14
EXT_MCLK2
MCLK2
BICKA
LRCKA
SDTIA
VCC
1
3
5
7
9
R54
10k
Baseband
RP3 47k
2
1
C83
0.1u
11
Master
12
JP48
M/S
DIR
OE
VCCA
VCCB
VCCB
22
GND
2 GND
4 GND
6
8
10 SDTOA
8
9
10
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
DIR
OE
BICKA
21
4679-BICKA
20
4679-SYNCA
19
JP63
SYNCA
18
1
C82
0.1u
11
C84
0.1u
12
SDTOA1
JP50
SDTOA LOOP
SDTIA
74AVC8T245
E
17
7
6
5
4
3
2
1
16
15
14
RP5 47k
2
23
13
B1
RP4 47k
D3V
24
GND
GND
7
6
5
4
3
2
1
17
RP2 47k
Slave
MCLK1
BICK1
LRCK1
SDIN1
VCC
8
A1
JP62
A1
VCCA
VCCB
VCCB
22
24
23
C85
0.1u
GND
GND
GND
13
74AVC8T245
VCC
U13
D
D
3
DAUX
4
5
D3V
6
VCC
7
8
JP51
ADC SDTI_SEL
4118A-SDTO
DIR
3
4
5
EXT_MCLK
6
7
EXT_MCLK2
8
JP52
I2C(CAD0) CTRL_SEL
CAD0
9
10
SPI
C
1
R56
10k
C89
0.1u
11
R57
10k
12
PORT5
10
8
6
4
2
9
7
5
3
1
CSN
CCLK/SCL
CDTI/SDA
CDTO/SDA(ACK)
R63
R59
R60
470
470
470
10
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
21
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
21
4679-SDTO
20
19
18
17
16
15
4679-MCKO
1
2
3
4
5
6
14
4679-SDTI
20
2
19
4679-MCKI
D3V
18
17
16
VCCA
OE
VCCB
VCCB
11
22
GND
CCLK/SCL
GND
23
13
C88
0.1u
C87
0.1u
JP49
SPI(CDTO)
4Y
4A
5Y
5A
6Y
6A
8
9
10
11
12
13
Vcc
7
74AVC8T245
14
14
D3V
24
GND
12
CSN/CAD0
15
DIR
1
C86
0.1u
1A
1Y
2A
2Y
3A
3Y
GND
U15 74HC14
CDTO
I2C(ACK)
C
2
R58
10k
9
MCKO
U14
A1
DIR
OE
VCCA
VCCB
VCCB
22
24
23
GND
GND
GND
13
C90
0.1u
74AVC8T245
VCC2
CTRL
A1-10PA-2.54DSA
U16
1
3
5
9
11
13
14
C91
0.1u
7
B
1A
2A
3A
4A
5A
6A
2
4
6
8
10
12
1Y
2Y
3Y
4Y
5Y
6Y
R61
1k
INV
EXT_BICKB
JP54
THR BICKB PHASE
CDTI/SDA
U17
3
4
EXT_LRCKB
Vcc
5
VCC2
6
GND
7
U18
74LVC07
7
6
5
4
3
2
1
PORT6
4
SDTIB
5
SDTIA
2
1A1
1B1
1A2
1B2
1DIR
1OE
2A1
2B1
JP61
SDTIB
13
EXT_MCLK2
4679-SDTIB
12
4679-SDTIA
JP60
SDTIA
15
MCLK2
BICKB
LRCKB
SDTIB
VCC
1
3
5
7
9
2 GND
4 GND
6
8
10 SDTOB
R62
10k
Bluetooth
8
9
10
7
SDTOA1
3
1
D3V
C95
0.1u
A
8
2A2
2B2
1
C92
0.1u
2DIR
2OE
VCCA
VCCB
GND
GND
4679-SDTOB
10
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
DIR
OE
JP64
BICKB
21
4679-BICKB
20
4679-SYNCB
19
JP65
SYNCB
18
B
17
7
6
5
4
3
2
1
16
15
14
RP7 47k
2
D3V
11
B1
RP6 47k
11
6
SDTOB1
A1
12
4679-SDTOA
VCCA
VCCB
VCCB
22
24
23
GND
GND
GND
13
C93
0.1u
74AVC8T245
SDTOB1
JP55
SDTOB LOOP
SDTIB
14
16
C94
0.1u
A
9
74AVC4T245
-64-
Title
Size
AKD4679-A
Document Number
Date:
A
B
C
D
Rev
LOGIC
A2
Thursday, July 07, 2011
E
Sheet
0
5
of
5
3
2
61
64
CN104
80pin_4
TEST159
MPWR1
TEST160
MPWR2
TEST163
DMDAT1
D
TEST167
VSS5
D-MIC PWR
CN103
+
TEST140
HPL
C125 2.2u
CN101
J7
G1
6
C143
0.1u
TVDD
TVDD
C144
0.1u
8
R148
H1
2 1
CL107 Cut Land (Open)
G5
F6
U102
C
53
DMCLK
RIN1/IN1JP101
INPUT SEL2
LIN1/IN1+
JP100
INPUT SEL1
R127 51
B9
RIN2
RIN3
LIN2
A9
D8
D9
RIN4
LIN3
E7
F7
LIN4
VEE
HPR
F8
E9
E8
HPL
VSS5
PVDD
F9
H9
G8
51
B7
50
B6
49
B4
48
R119
open
A4
47
D2
C3
R149
0
R140
51
46
43
TEST105
RCP
F3
42
C1
TEST165
VSS1
C123
2.2n
A1
41
VSS3
A3
80pin_3
20pin
C121
0.1u
B3
SPP
B1
D5
C122
10u
CL111
Cut Land short
35
34
33
TEST102
-653
CL102
Cut Land short
CL103
Cut Land short
A
TEST101
SPP
Title
Size
DVDD
CL101
Cut Land short
CL109
Cut Land (short)
32
30
29
28
CDTI/SDA
27
CCLK/SCL
26
CSN/CAD0
25
CDTO
24
44
E3
2
37
R158 51
B
TEST106
RCN
1 2
R117 51
SDTOA
A2
J2
SPN
SDTOA
SYNCA
R116 51
SYNCA
R115 51
BCLKA
G4
BCLKA
1 2
R114
SDTIA
51 E2
G2
SDTIA
SI_CAD1
SDA
51
R162
Open
R159
Open
SCLK
CL110
Cut Land (short)
SI
R160 51
SCL
CSN
Open R157
CAD0
SVDD
F4
open
VSS2
23
22
I2C
4
21
CN102
80pin_2
TEST166
SDOUT3/GP0
SDIN3
JX1_SYCN3
JX0_BCLK3
JP105
DSP2
51
0
0
0
SO
R155 Open
A
1 R118
CL108
Cut Land (short)
R161
+
CAD1
R163 51
1 2
C119
0.1u
C120
10u
R151
R139
R138
R137
B5
+
JP104
PDN
SVDD
31
G3
STO_RDY
TEST186
STO_RDY
1 2
PDNE
BCLK2
L
BCLK1
F2
80pin_1
20pin
JX0_BCLK3
SCLK_CAD0
D7
2
20
JX1_SYNC3
SYNC1
C6
NC
4
OUTY
GND
5
VCC
1
INA
TC7SG17FU
C131
H
0.1u
SDIN3
SDOUT1
SPFIL
3
A5
45
SDOUT3_GPO
SDIN1
C7
19
5
VCOM
C132 +
C133
0.1u
10u
A8
1 2
Cut Land (Open)
SO_SDAE
51
MCKI
SDIN4
MCKI
CSN_SCLE
R112
BICK
C5
18
BCLK1
SDOUT4_GP1
B8
17
51
C128
1u
A6
LRCK
2 1
F5
R111
LOUT/LOP 56
R121
(OPEN)
ROUT/LON 55
54
1 2
J3
RCN
RCP
DVDD
R110
57
1 2
BICK
CL106
ROUT
AK4679
SDTO
SDAA
16
R129
16
SVDD
LRCK
MCKI
B
R120
15
TEST143
40
H5
E1
51
SYNC1
R128
16
A7
VSS3
H6
SDTO
SCLA
SDIN1
U100
SDTI
VSS3
Cut Land (Open)
J4
SDTI
B2
SDOUT1
51
LOUT
SDTIB
SPN
2 1
Cut Land (Open)
2 1
R109
MPWR2
BICKB
CL104
J5
15
SYNCB
H7
14
MPWR1
36
SDTIB
13
51
58
R122
15
C9
39
BCLKB
CL105
R108
C127
0.22u
TEST142
TEST104
H3
SYNCB
SDTOB
G6
51
VSS1
PDNA
R107
TEST
59
C129
0.22u
C8
38
H4
J1
12
AVDD
G7
51
TVDDE
I2CE
R106
60
52
SDTOB
H2
11
VCOM
C2
51
VSSE
SDOUT2
R105
VDDE
SDIN2
10
51
RIN1
C4
R104
D1
TEST185
TEST1 E4
LIN1
VSS2
SYNC2
9
0
F1
TVDDA
D3
7
C117
0.1u
D6
5
C
+C118
10u
VEE
J6
TEST130
VSS2
2.2u
CNA
4
2.2u
G9
1.0u
C126
H8
C148
2
1.0uF
C124
TEST141
HPR
C130
0.1u
5
4
CPA
C146
+
Open
NC
CNB
C145
3
OUT
CE
J9
IN
3
J8
1
DVDD
GND
2
XC6210B-1.2
CPB
U101
C142
10u
DMDAT
1
TEST164
DMCLK1
TEST148
AVDD
AVDD
PVDD
65
66
67
68
69
TEST145
RIN4
1u C134
TEST153
AVSS
70
71
1u C135
TEST144
LIN4
1u C136
72
TEST147
RIN3
1
PVDD
R125
R126
TEST146
LIN3
1u C137
73
1u C141
74
TEST152
RIN2/IN2-
JP103 1u C138
MPWP2 SEL
LIN2
2.2k
RIN2
2.2k
1u
TEST151
LIN2/IN2+
R123
R124
D
75
76
C139
77
78
JP102 1u C140
MPWP1 SEL
LIN1
2.2k
RIN1
2.2k
79
80
AVDD
62
4
63
5
A2
SVDD
Date:
2
Document Number
AKD4679-A
Rev
AKD4679-A-78FBGA-SUB
Tuesday, July 05, 2011
1
Sheet
1
of
0
1
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