AK4705AEQ

[AKD4705A-A]
AKD4705A-A
AK4705A Evaluation Board Rev.0
GENERAL DESCRIPTION
AKD4705A-A is an evaluation board for quickly evaluating the AK4705A, 2ch DAC with AV SCART
switch. Evaluation requires audio/video analog analyzers/generators, a digital audio signal source, and a
power supply. AKM’s ADC evaluation board can be also used for the audio source. Also included is a
AK4112B digital audio interface receiver which receives S/PDIF compatible audio data. The digital audio
data is available via optical connector or BNC.
AKD4705A-A --- AK4705A Evaluation Board
(Cable for connecting with printer port of IBM-AT compatible PC
and a control software are enclosed with board. This control software dose not
support Windows NT.)
FUNCTION
BNC connectors for analog audio input/output
BNC connectors for analog video input/output
On-board clock generator
BNC connector for an external clock input
Compatible with 2 types of digital interface
1. Serial interface: Direct interface with evaluation boards for AKM’s A/D converter evaluation boards.
2. S/PDIF: On-board AK4112BVF as DIR that accepts optical input or BNC input
10pin header for serial control interface
D5V
VVD2
VVD1
+5V
JP10
Reg.
PORT3 UP-I/F
10pin Heder
+12V
Gnd
MONOOUT
Reg.
JP11
TVOUTL
JP8
(Digital)
Control Data
JP9
TVOUTR
AD DATA
ROM DATA
10pin Header
J2
VCROUTL
Port1 EXT
JP25~
RX
JP6
PORT2
Opt In
DIR
VCROUTR
RX
JP1
J1
EXT
AK4705A
Clock
Generator
EXT
RFV
TVINL
VCRVOUT
TVFB
JP12
VCRC
TVINR
TVVOUT
TVRC
VCRINL
TVG
TVB
ENCB
ENCRC
ENCG
ENCV
ENCC
TVVIN
ENCY
VCRFB
VCRVIN
VCRRC
VCRG
VCRINR
VCRB
VCRSB TVSB
Figure 1. AKD4705A-A Block Diagram
Note 1. Circuit diagram and PCB layout are attached at the end of this manual.
<KM091000>
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[AKD4705A-A]
Operation sequence
1) Set up the power supply lines.
Name
Color
Voltage
+12V
+5V
D5V
VVD1
VVD2
AGND
DGND
VVSS2
Orange
Red
Red
Red
Blue
Black
Black
(Black
+11.4 [V] ∼ +12.6[V]
+4.75[V] ∼ +5.25[V]
+4.75[V] ∼ +5.25[V]
+4.75[V] ∼ VVD2
VDD1 ∼ +5.25[V]
0[V]
0[V]
0[V]
Comments
Regulator, VP
VD
Logic
VVD1
VVD2
Analog Ground
Digital ground
Analog Ground
Attention
This jack should be always connected.
This jack is open when JP9 (REG) is short.
This jack is open when JP8 (D-A) is short.
This jack is open when JP10 (VDD1) is short.
This jack is open when JP11 (VDD2) is short.
This jack should be always connected.
This jack should be always connected.
This jack should be always connected.
Table 1. Set up of power supply lines
Note 2. Each supply line should be distributed from the power supply unit.
2) Set-up the evaluation modes, jumper pins and DIP-switches. (Refer next sections.)
3) Connect the PORT3 (µP-I/F) with PC by the enclosed 10-wire flat cable.
4) Set up the PC and execute the enclosed control software.
(Please refer to the Control Software Manual.)
5) Turn the power on.
6) Reset the AK4705A once by bringing the SW1 (PDN) “L”, and return it to “H”.
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[AKD4705A-A]
Evaluation mode
1) S/PDIF mode (Optical Link or BNC: default)
When the CM0 (DIP-switch S1_1 on board) is “L”, the AK4112B (DIR) generates MCLK, BICK, LRCK and
SDATA from the received bit stream through PORT2 (TORX176: optical link) or J2 (BNC). This mode is used
for the evaluation using CD test disk. The PORT1 (EXT) should be open.
1)-1. DIP-switch set-up
No.
1
2
3
4
CM0
“L”
“L”
“L”
“L”
DIF2
“L”
“L”
“H”
“H”
DIF0
“L”
“H”
“L”
“H”
Audio Data Format of AK4112B
16bit LSB justified
18bit LSB justified
24bit MSB justified
24bit I2S
Notes
1
2
3
4
(Default)
Table 2. DIP-switch set-up (DIF1=“L”)
Much the data format of the AK4705A via I2C-bus control as following notes.
Note 1. 16bit LSB justified
Set up the DIP-switch as follows.
S1
AK4112B
ON
1 2 3 4 5
(Reserved)
(Reserved)
CM0
DIF2
DIF0
OFF
Set up the control registers DIF1/0 of the AK4705A by enclosed software as follows.
Note 2. 18bit LSB justified
Set up the DIP-switch as follows.
S1
AK4112B
ON
1 2 3 4 5
(Reserved)
(Reserved)
CM0
DIF2
DIF0
OFF
Set up the control registers DIF1/0 of the AK4705A by enclosed software as follows.
<KM091000>
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[AKD4705A-A]
Note 3. 24bit MSB justified
Set up the DIP-switch as follows.
S1
AK4112B
ON
1 2 3 4 5
(Reserved)
(Reserved)
CM0
DIF2
DIF0
OFF
Set up the control registers DIF1/0 of the AK4705A by enclosed software as follows.
Note 4. 24bit I2S (Default)
Set up the DIP-switch as follows.
S1
AK4112B
ON
1 2 3 4 5
(Reserved)
(Reserved)
CM0
DIF2
DIF0
OFF
Set up the control registers DIF1/0 of the AK4705A by enclosed software as follows.
<KM091000>
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[AKD4705A-A]
1)-2. Jumper pins set up
JP1
JP2
JP3
JP4
JP5
EXT
MCLK
BICK
SDTI
LRCK
(Open)
(Short)
(Short)
(Short)
(Short)
(Default)
(Default)
(Default)
(Default)
(Default)
The JP6 selects the input port of S/PDIF bit stream form Port2 (TOTX176) or J2 (BNC RX).
JP6
JP6
RX
RX
TORX
TORX
BNC
BNC
(BNC)
(TORX)
(Default)
<KM091000>
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[AKD4705A-A]
2) On-board X’tal mode/ Feeding external MCLK via BNC
When the CM0 (DIP-switch S1_1 on board) is “H”, the AK4112B generates MCLK, BICK and LRCK from
on-board X’tal or external clock form J1. SDATA should be fed via PORT1.
2)-1. DIP-switch set-up
No.
1
CM0
“H”
DIF2
Don’t care
DIF0
Don’t care
Table 3. DIP-switch set-up (DIF1=“L”)
2)-2. Jumper pins set up
2)-2-a. Using on-board X’tal
JP1
JP2
JP3
JP4
JP5
EXT
MCLK
BICK
SDTI
LRCK
(Short)
(Open)
(Short)
(Open)
(Short)
JP6: Don’t care.
2)-2-b. Using external clock via BNC connector J1
JP1
JP2
JP3
JP4
JP5
EXT
MCLK
BICK
SDTI
LRCK
(Open)
(Short)
(Short)
(Short)
(Short)
JP6: Don’t care.
Remove the on-board X’tal.
<KM091000>
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[AKD4705A-A]
3) Feeding all clocks from external
Under the following set-up, all external signals can be fed to the AK4705A through POTR1 (EXT).
The AKM’s evaluation board for ADC can be used.
3)-1. DIP-switch set-up
No.
1
CM0
Don’t care
DIF2
Don’t care
DIF0
Don’t care
Table 4. DIP-switch set-up (DIF1=“L”)
3)-2. Jumper pins set up
JP1
JP2
JP3
JP4
JP5
EXT
MCLK
BICK
SDTI
LRCK
(Open)
(Open)
(Open)
(Open)
(Open)
JP6: Don’t care.
Other jumper pins set up
[JP12](VCRRC): Input Jack selection for the VCRRC pin of AK4705A
When the VCRC pin of the AK4705A outputs 0V by setting CIO bit to “1”, the signal can be fed through the
J27 (VCRCOUT) to VCRRC pin.
“I”:
The signal is fed through the J18 (VCRRC) to VCRRC pin. (Default)
“I/O”: The signal is fed through the J27 (VCRCOUT) to VCRRC pin.
The CIO bit of AK4705A should be set to “1”.
JP12
I
JP12
I/O
I
(I)
I/O
(I/O)
(Default)
[JP7](GND): Analog ground and digital ground
Open: separated. (Default)
Short: connected. (The jack “DGND” can be open.)
JP7
DGND AGND
(Open)
(Default)
<KM091000>
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[AKD4705A-A]
DIP-switch (S1) List
No.
1
2
3
4
5
Switch
Name
CM0
DIF2
DIF0
-
Default
Function
OFF
ON
ON
OFF
OFF
S/P DIF mode (Refer the evaluation mode)
24 bit I2S mode (Refer the evaluation mode)
(Reserved)
(Reserved)
Table 5. DIP-switch list (DIF1=“L”)
Jumper List
No.
Jumper Name
Function
MCLK source set-up when CM0=”H”.
1
2,3,
4,5
EXT
MCLK, BICK,
LRCK, SDTI
Open: X’tal (Default).
Short: External clock via BNC (J1). Remove the on-board X’tal.
Clock source set-up
Short: Connect the DIR (AK4112B). (Default)
Open: Separate the DIR. Supply clocks via Port1.
S/PDIF’s port set-up when CM0=”L”.
6
RX
TORX: Optical connector PORT2. (Default)
BNC: BNC connector J2.
Analog ground and digital ground
7
GND
Open: separated (Default).
Short: connected (The connector “DGND” can be open.).
Power supply source set-up for digital section of AKD4705A-A.
8
D-A
9
REG
Open: from the “D5V” Jack.
Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “D5V” Jack. (Default)
Power supply source set-up for VD of AK4705A.
Open: from the “+5V” Jack.
Short: from the regulator. Don’t connect anything the “+5V” Jack. (Default)
Power supply source set-up for VVD1 of AK4705A.
10
VVD1
11
VVD2
Open: from the “VVD1” Jack.
Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “VVD1” Jack. (Default)
Power supply source set-up for VVD1 of AK4705A.
Open: from the “VVD2” Jack.
Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “VVD2” Jack. (Default)
Input Selection for VCRRC
12
VCRRC
“I” side: Input to VCRRC from VCRRC jack. (Default)
“I/O” side: Input to VCRC from VCRC jack.
(Note: Refer CIO bit of AK4705A)
Table 6. Jumper list
<KM091000>
2007/09
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[AKD4705A-A]
Serial Control
The AK4705A-A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(µP-IF) with PC by 10 wire flat cable packed with the AKD4705A-A.
Be careful connector direction. Flat cable should be connected 10-pin header, red line put on 10pin header 5 and 6
pin.
1
10
SCL
Connect
SDA
PC
AKD4705A-A
SDA(ACK)
RED
10 wire flat cable
5
10 pin Connector
PORT3
µP-IF
6
Figure 2. Connection of 10 pin flat cable for PORT3
Input/Output port List
Input
Audio
Signal Name
Notes
J5 (VCRINL), J3 (VCRINR), J9 (TVINL), J8 (TVINR)
Max: 2Vrms
Slow
Blanking
Input
Output
J12 (VCROUTL), J10 (VCROUTR), J6 (TVOUTL), J7 (TVOUTR),
J4 (MONOOUT)
Port2 (TORX176) or J2 BNC (RX)
J13 (ENCB), J15 (ENCG), J17 (ENCRC), J19 (ENCC), J21 (ENCV),
J23(ENCY), J25(TVVIN), J14(VCRVIN), J18(VCRRC; Note),
J20(VCRG), J22(VCRB)
J27 (VCRCOUT; Note), J29 (TVVOUT), J30 (TVRC), J31 (TVG), J32
(TVB), J33 (RFV), J34 (VCRVOUT)
J24 (VCRSB)
J24 (VCRSB), J28 (TVSB)
Fast
Blanking
Input
Output
J16 (VCRFB)
J26 (TVFB)
Output
Digital
Input
Input
Video
Output
Max: 3Vrm
Max: D5V+0.3V
Max: 1.5Vp-p
Max: 3Vp-p
Max: VP+0.3V
Max: VP
Max: VVD1+0.3V
Max: VVD2
Table 7. Input / Output port List
Note 3. Please refer to JP12 and CIO bit of the AK4705A.
<KM091000>
2007/09
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[AKD4705A-A]
The indication content for LED
LED turns on during each output is “H”.
[LE1] Indicates unlock or parity error of S/PDIF. Connected to the ERF pin of DIR (AK4112B).
(Normally off.)
[LE2] Indicates the validity status of S/PDIF. Connected to the V pin of DIR (AK4112B).
(Normally off.)
Toggle switch (SW1 on board) operation
“H”: AK4705A is active.
“L”: AK4705A is powered down.
Note 4. When the power of AKD4705A-A is ON at first, SW1 should be switched from “L” to “H”.
<KM091000>
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[AKD4705A-A]
4) Control Software Manual
Set-up of evaluation board and control software
1. Set up the AKD4705A-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4705A-A by 10-line type flat cable (packed with AKD4705A-A). Take
care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AK4705A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4705a-a.exe” to set up the control program.
5. Then please evaluate according to the follows.
Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
Explanation of each buttons
1. [Port Reset]:
2. [Write default]:
3. [All Write]:
4. [Function1]:
5. [Function2]:
6. [Function3]:
7. [Function4]:
8. [Function5]:
9. [SAVE]:
10. [OPEN]:
11. [Write]:
Set up the USB interface board (AKDUSBIF-A) when using the board.
Initialize the register of AK4705A.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
<KM091000>
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[AKD4705A-A]
Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes
“H” or “1”. If not, “L” or “0”.
If you want to write the input data to the AK4705A, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog]: Dialog to write data by keyboard operation
Address Box:
Data Box:
Input registers address in 2 figures of hexadecimal.
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4705A, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog]: Dialog to evaluate DATT
There are dialogs corresponding to register of 02h.
Address Box:
Input registers address in 2 figures of hexadecimal.
Start Data Box:
Input starts data in 2 figures of hexadecimal.
End Data Box:
Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to AK4705A by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example]
Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example]
Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to the AK4705A, click [OK] button. If not, click [Cancel] button.
<KM091000>
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[AKD4705A-A]
4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
“akr”.
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is “akr”.
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK4705A. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
<KM091000>
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[AKD4705A-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button. The following is displayed.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file
name is “aks”.
Figure 3. Window of [F3]
<KM091000>
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[AKD4705A-A]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 2 opens.
Figure 4. [F4] window (1)
<KM091000>
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[AKD4705A-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is
“DAC_Stereo_ON.aks”)
Figure 5. [F4] window (2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is
“*.ak4”.
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the
change.
<KM091000>
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[AKD4705A-A]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens.
Figure 6. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 7. [F5] windows (2). (In case that the selected file name
is “DAC_Output.akr”)
(2) Click [WRITE] button, then the register setting is executed.
<KM091000>
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[AKD4705A-A]
Figure 7. [F5] windows (2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file
name is “*.ak5”.
[OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be
loaded again in order to reflect the change.
<KM091000>
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[AKD4705A-A]
REVISION HISTORY
Date
Manual
Board
Reason
(yy/mm/dd) Revision Revision
07/09/26 KM091000
0
First Edition
Page
Contents
IMPORTANT NOTICE
These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or
strategic materials.
AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all
claims arising from the use of said product in the absence of such notification.
<KM091000>
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1
37
38
39
2
40
41
42
43
44
45
3
46
47
4
48
5
CN1
D
D
CN3
1
C17
0.1u
C16
+
CN4
10u
36
VVSS
10u
3
TVVOUT
0.1u
4
+
REFI
TVINL
28
10
ENCB
TVINR
27
11
ENCG
VCRINL
26
VCRINR
25
10u
34
0.1u
33
C20
+C21
C
10u
32
31
30
29
TVSB
VCRSB
28
B
24
23
VCRB
VCRG
INT
22
21
20
VCRFB
VCRRC
19
13
18
ENCRC
ENCC
12
VCRVIN
9
+
37
VSS
38
VD
MCLK
39
40
BICK
42
41
SDTI
SCL
LRCK
43
44
SDA
45
46
47
29
VVD1
C19
0.1u
VCROUTR
0.1u
10
B
MONOOUT
33
AK 4705A
0.1u
C18
30
TVB
8
9
34
VCROUTL
7
10k
VP
TVOUTR
TVG
10u
TVVIN
R555
DVCOM
35
32
17
8
C14
36
31
+
7
35
TVOUTL
16
C15
10u
(VSS) C12
PVCOM
U3
TVRC
6
ENCY
5
6
VVD2
15
C22
ENCV
5
C
2
14
C23
VCRC
C13
+
1
4
PDN
3
RFV
TVFB
(VVSS)
VCRVOUT
48
2
27
11
26
12
25
24
23
22
21
20
19
18
17
16
15
14
13
CN2
A
A
Title
-20Size
A4
Date:
5
4
3
2
AKD4705A-A-48LQFP
AK4705A
Document Number
1
Sheet
1
of
1
Rev
0
CN1
MCLK
BICK
SDTI
LRCK
SCL
2
1
VD
CN3
37
38
39
40
41
42
43
44
45
46
47
TVFB
48
VCRC
PDN
VCRVOUT
3
SDA
4
RFV
5
1
CN4
D
D
36
2
(VVSS2)
35
TVVOUT
3
VVD2
4
TVRC
5
TVG
6
34
VP
33
MONOOUT
32
TVOUTL
31
TVOUTR
30
VCROUTL
29
VCROUTR
C
C
TVB
7
VVD1
8
ENCB
9
ENCG
10
ENCRC
11
28
27
TVINL
26
TVINR
25
VCRINL
B
B
CN2
Analog Ground
24
VCRINR
VCRSB
INTRUPT
VCRB
VCRG
VCRRC
VCRFB
VCRVIN
TVVIN
ENCY
GND
TVSB
ENCV
JP7
23
22
21
20
19
18
17
16
15
14
12
13
ENCC
Digital Ground
A
A
Title
-21Size
A4
Date:
5
4
3
2
Document Number
AKD4705A-A
AK4705A
2
Sheet
1
Rev
of
6
0
5
4
C24
2
R15
+
VCRINR
D
R17 0.47u
(open)
J5
VCRINL
R16
10u
300
1
J4
MONOOUT
MONOOUT
D
R18
300
10k
(VVSS)
(VVSS)
C26
R19
+
VCRINL
R21 0.47u
C27
R20
10u
300
+
(VVSS)
C25
+
J3
VCRINR
3
(VVSS)
J6
TVOUTL
TVOUTL
R22
300
10k
(open)
(VVSS)
(VVSS)
C29
R24
+
(open)
J9
TVINL
(VVSS)
C30
300
(VVSS)
J7
TVOUTR
R25
10k
C
(VVSS)
(VVSS)
R27
+
TVINL
R29 0.47u
10u
C31
R28
10u
300
+
(VVSS)
R23
TVOUTR
From
Analog
output
300
C
FOR Analog
input
TVINR
R26 0.47u
C28
+
(VVSS)
J8
TVINR
J10
VCROUTL
VCROUTL
R30
300
10k
(open)
(VVSS)
(VVSS)
C33
R32
10u
300
+
(VVSS)
(VVSS)
J12
VCROUTR
VCROUTR
R34
B
B
10k
(VVSS)
(VVSS)
A
A
Title
AKD4705A-A
-22Size
A4
Date:
5
4
3
2
Document Number
Rev
Analog
Input/Output
Circuit
Thursday, September 13, 2007
3
6
Sheet
of
1
0
5
4
J13
ENCB
R70
3
J14
VCRVIN
C50
2
R77
C51
(short)
0.1u
ENCB
(short)
R46
75
J15
ENCG
VCRVIN
R47
75
0.1u
(VVSS2)
(VVSS2)
D
(VVSS2)
R71
(VVSS2)
D
J16
VCRFB
C52
R78
ENCG
R48
(short)
VCRFB
R49
75
0.1u
75
(VVSS2)
(VVSS2)
J17
ENCRC
(VVSS2)
R72
300
(VVSS2)
JP12
J18
VCRRC
C53
I
R79
C54
(short)
0.1u
ENCRC
R50
75
(short)
1
VCRRC
I/O
VCRRC
R51
75
0.1u
VCRCOUT
(VVSS2)
C
(VVSS2)
J19
ENCC
(VVSS2)
R73
(VVSS2)
J20
VCRG
C55
R80
ENCC
R52
75
(VVSS2)
(short)
J21
ENCV
VCRG
R53
75
0.1u
(VVSS2)
(VVSS2)
R74
(short)
0.1u
R81
C58
(VVSS2)
J22
VCRB
C57
ENCV
R54
75
(VVSS2)
B
(short)
J23
ENCY
VCRB
R55
75
0.1u
(VVSS2)
(VVSS2)
R75
(short)
B
R56
ENCY
R57
75
(VVSS2)
(short)
J25
TVVIN
VCRSB
R58
10K
0.1u
(VVSS2)
(VVSS)
R76
0.1u
(VVSS2)
J24
VCRSB
C59
C
C56
300
(VVSS)
C60
TVVIN
R59
75
(VVSS2)
(short)
0.1u
(VVSS2)
A
A
Title
AKD4705A-A
-23Size
A4
Date:
5
4
3
2
Document Number
Rev
Video Block Input
Circuit
5
6
Sheet
of
1
0
5
4
3
R61
J27
75
VCRCOUT
2
R67
300
VCRC
J33
1
RFV
RFV
VCRCOUT
(VVSS2)
D
R63
75
(VVSS2)
D
J29
TVVOUT
R60
TVVOUT
J26
75
TVFB
R62
J28
300
TVSB
TVFB
(VVSS2)
R64
75
J30
(VVSS2)
TVRC
TVRC
TVSB
(VVSS2)
C
R65
J31
75
TVG
(VVSS2)
C
TVG
(VVSS2)
R66
75
J32
TVB
TVB
(VVSS2)
R68
75
B
J34
VCRVOUT
B
VCRVOUT
(VVSS2)
A
A
Title
AKD4705A-A
-24Size
A4
Date:
5
4
3
2
Document Number
Rev
Video Block Output
Circuit
6
6
Sheet
of
1
0
5
4
3
2
R1
4112B-3.3V
C1
5.1
0.1u
10u
C3
U2A
1
2
JP1
EXT
22p
2
74HCU04
C5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J1
BNC
X1
22p
12.288MHz
1
C6
R3
75
PORT1
10
9
8
7
6
1
2
3
4
5
Logic
U1
0.1u
Logic
D
CM0
C4
+
10u
MCLK
BICK
LRCK
SDATA
C2
+
DVDD
DVSS
TVDD
V/TX
XTI
XTO
PDN
R
AVDD
AVSS
RX1
DIF0/RX2
DIF1/RX3
DIF2/RX4
CM0/CDTO
CM1/CDTI
OCKS1/CCLK
OCKS0/CSN
MCK01
MCK02
DAUX
BICK
SDTO
LRCK
ERF
FS96
P/S
AUTO
1
R2
EXT
Logic
10k
D
R82
10k
R83
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INTRUPT
JP2
JP3
JP4
JP5
MCLK
R9
300
BICK
SDTI
LRCK
100
R12
100
R11
100
MCLK
BICK
SDTI
R10
100
LRCK
Logic
3
LE1
R4
U2B
AK4112BVF
4
74HCU04
ERF
1k
C
C
U2C
DIF2
PDN
DIF0
R6
18k
4112B-3.3V
C7
1
2
3
4
5
10
9
8
7
6
6
74HCU04
1k
V
U2D
Logic
9
5
4
3
2
1
Logic
L1
47u
CM0
DIF2
DIF0
U2E
11
6
5
6
5
GND
VCC
GND
OUT
10
74HCU04
PORT2
B
8
74HCU04
RP1
0.1u
10u
CM0
DIF2
DIF0
5
SW DIP-5
C8
+
S1
AK4112B
LE2
R5
U2F
4
3
2
1
R-PACK5R
C9
TORX176
0.1u
R7
12
B
74HCU04
C10
+
10u
JP6
RX
J2
470
TORX
BNC(RX)
C11
BNC
R8
13
0.1u
75
A
A
Title
-25Size
A4
Date:
5
4
3
2
Document Number
AKD4705A-A
AK4112B
1
Sheet
1
Rev
of
6
0
5
4
R35
U4
R36
Logic
PORT3
D
1
2
3
4
5
10k
470
R39
R40
10k
10
9
8
7
6
470
SCL
SDA
SDA(ACK)
3
R41
51
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
1
19
G1
G2
2
R37
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
17
16
15
14
13
12
11
SCL
Logic
D1
100
R38
10k
U5A
1
H
L
U5B
2
3
74HCT14
4
PDN
D
74HCT14
C34
SW1
0.1u
PDN
74HCT541
R42
6
1
9
74HCT14
U5D
8
U6A
2
74LS07
3
11
74HCT14
U5E
10
U6B
4
74LS07
9
13
74HCT14
U5F
12
U6D
8
74LS07
11
U6E
10
74LS07
13
U6F
12
74LS07
Logic
10k
U6C
6
74LS07
5
U5C
uP-I/F
5
1
R43
SDA
(short)
SDA(ACK)
C
74HCT14
D5V
+5V
R44
JP9
L2
3
Logic
D-A
REG
10u
C37
C38
+C39
47u
OUT
IN
1
VP
+
C35
2
+
+12V
T1
NJM78M05FA
GND
JP8
C36
47u
Logic
(short)
1
4112B-3.3V
C49
JP10
R14
0.1u
C46
47u
OUT
+
IN
3
C41
C42
C43
C44
C45 + C40
0.1u
0.1u
0.1u
0.1u
0.1u
B
47u
Logic
C47
+
C48
47u
0.1u
2
VVD1
GND
T2
LP2950A
VD
VVD1
(short)
47u
0.1u
0.1u
R45
B
C
for 74HCT14, 74HCU04, 74LS07,
74HCT541
VDD1
5.1
VVD2
R13
JP11
(short)
VDD2
VVD2
A
A
Title
-26Size
A4
Date:
5
4
3
2
AKD4705A-A
POWER SUPPLY
Document Number
4
Sheet
1
of
Rev
6
0
-27-
-28-
-29-
-30-
-31-
-32-
-33-
-34-
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