AK4710EN

ASAHI KASEI
[AKD4710-A]
AKD4710-A
AK4710 Evaluation Board Rev.2
GENERAL DESCRIPTION
AKD4710 is an evaluation board for quickly evaluating the AK4710, Single SCART Driver.
Evaluation requires audio/video analog analyzers/generators and a power supply.
 Ordering guide
AKD4710-A ---
AK4710 Evaluation Board
(Control software and USB cable are packed with this.)
FUNCTION
 RCA connectors for analog audio output
 XLR connectors for analog audio input
 RCA connectors for SD video input/output
 USB connector for serial control interface
VP
+12V → +3.3V
Regulator
+12V → +3.3V
Regulator
VD1
VVD
AGND VSS2
VVD
VD2
AINL-
VD1
VP
AINL+
VD2
AINR+
AINR-
AK4710
ENCB
ENCC
TVOUTL
CINCHOUTL
TVOUTR
CINCHOUTR
TVVOUT
TVRC
TVG
TVB
ENCG
RCAVOUT
ENCV
TVFB
ENCY
TVSB
ENCRC
USB
PORT
5.0V
PIC4550
Regulator
3.3V
Figure 1. AKD4710 Block Diagram
※Circuit diagram and PCB layout are attached at the end of this manual.
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
EVALUATION BOARD MANUAL
 Operation sequence
1) Set up the power supply lines.
Name of
Jack
VP
Color of
Jack
Yellow
Voltage
Used for
Comment and attention
+10.8+13.2V
VP of AK4710
VD1
Red
+3.13+3.47
VD1 of AK4710
VD2
Red
+3.13+3.47V
VD2 of AK4710
VVD
Red
+3.13+3.47V
VVD of AK4710
D3.3V
Red
+3.13  3.47V
Power supply of
logic
AGND
VSS2
Black
Black
0V
0V
Analog Ground
Analog Ground
DGND
Black
0V
Digital Ground
Should be always connected
Should be connected when jp5 (VD1_SEL) is
set to REG side.
Should be open when JP5 (VD1_SEL) is set to
VD1 side.
Should be connected when R 51(VD2_SEL) is
set to REG side.
Should be open when R51 (VD2_SEL) is set to
VD2 side.
Should be connected when JP6 (VVD_SEL) is
set to REG side.
Should be open when JP6(VVD_SEL) is set to
VVD side.
Should be connected when JP7 (VCC_SEL) is
set to REG side.
Should be open when JP7 (VCC_SEL) is set to
D3.3V side.
Should be always connected
Should be always connected
Should be connected when JP4 (GND_SEL) is
set to AGND side.
Should be open when JP4 (GND_SEL) is set to
DGND side.
Default of
Jack
+12V
open
open
open
open
0V
open
open
Table 1. Power supply lines
Each supply line should be distributed from the power supply unit.
2) Set-up jumper pins. (See the followings.)
3) Power on.
The AK4710 should be reset once bringing SW1 “L” upon power-up.
 Jumper pins set up
[JP1] (GND): AINL- pin input select
OPEN:
J5 (AINL): 3pin <Default>
SHORT: GND (Not to use)
[JP2] (GND): AINR- pin input select
OPEN:
J13 (AINR): 3pin <Default>
SHORT: GND (Not to use)
[JP3] Not to use
[JP4] (GND): Analog ground and Digital ground
OPEN:
Separated
SHORT: Common. (The connector “DGND” can be open.) <Default>
[JP5] (VD1): Regulator (+3.3V) or VD1 connector
OPEN:
VD1 pin is supplied from VD1 connector.
SHORT: VD1 pin is supplied to regulator (+3.3V). (The connector “VD1” can be open.) <Default>
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
[JP6] (VVD): Regulator (+3.3V) or VVD connector
OPEN:
VVD pin are supplied from VVD connector.
SHORT: VVD pin are supplied from regulator (+3.3V)
(The connector “VVD” can be open.) <Default>
[JP7] (D3.3V): Regulator (+3.3V) or D3.3V connector
OPEN:
Logic voltage is supplied from D3.3V connector.
SHORT: Logic voltage is supplied form regulator (+3.3V). (The connector “VCC” can be open.) <Default>
The regulator can be supplied 3.3V to all circuits by shorting JP5, JP6 and JP7 and supplying 12V to VP connector.
 The function of the toggle SW
[S1] (PDN): Resets the AK4710. Keep “H” during normal operation.
 Bord Control
The AK4710 can be controlled USB PORT of PC. Connect PORT1 with PC by USB cable packed with the AKD4710-A.
The control software packed with this evaluation board
 Analog Input/Output List
Audio
Video
Input
Output
Input
Output
Fast Blanking
SlowBlanking
Output
Output
Signal Name
J5(AINL+, AINL-), J13(AINR+, AINR-)
J4 (TVOUTL), J9 (TVOUTR), J6 (CHINOUTL),
J14 (CHINOUTR)
J2 (ENCV), J7 (ENCY), J10 (ENCRC),
J15 (ENCC),J17 (ENCG), J19(ENCB)
J3 (TVVOUT), J8 (TVRC), J11(TVG),
J16(TVB), J18 (RCAVOUT)
J22 (TVFB),
J24 (TVSB)
Note
Max. 2Vrms
Max. 2.15Vrms
Max. 1.25Vpp
Max. 2.5Vpp
Max. VVD
Max. VP
Table 2. Analog Input/Output List
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
Control Soft Manual
■ Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect Evaluation board to PC with USB cable.
USB control is recognized as HID (Human Interface Device) on the PC.
When it can not be recognized correctly please reconnect Evaluation board to PC with USB cable.
3. Proceed evaluation by following the process below.
[Support OS]
Windows 2000 / XP
64bit OS’s are not supported.
Windows 95 / 98 / Me / NT are not supported.
■ Operation Screen
1. Start up the control program following the process above.
2. After the evaluation board’s power is supplied, the AK4710 must be reset once bring S1 (AK4710-PDN) “L” to “H”.
3. The operation screen is shown below
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
■ Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting.
1. [Port Reset]: For when connecting to PC with USB cable
Click this button after the control soft starts up when connecting to PC with USB cable.
2. [Write Default]: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executing write commands for all registers displayed.
4. [All Read]: Executing read commands for all registers displayed.
5. [Save]: Saving current register settings to a file.
6. [Load]: Executing data write from a saved file.
7. [All Reg Write]: [All Reg Write] dialog box is popped up.
8. [Data R/W]: [Data R/W] dialog box is popped up.
9. [Read]: Reading current register settings and display on to the Register area (on the right of the main window).
This is different from [All Read] button, it does not reflect to a register map, only displaying hexadecimal.
<KM105903>
2012/02
- 5 -
ASAHI KASEI
[AKD4710-A]
■ Tab Functions
1. [REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Grayout registers are Read Only registers. They can not be controlled.
The registers which is not defined in the datasheet are indicated as “---”.
Figure 2. Window of [ REG]
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
1-1. [Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When the checkbox is checked, the data will be “H” or “1”. When the checkbox is not checked, the data will be “L”
or “0”. Click [OK] to write setting values to the registers, or click [Cancel] to cancel this setting.
Figure 3. Window of [ Register Set ]
1-2. [Read]: Data Read
Click [Read] button located on the right of the each corresponded address to execute a register read.
After register reading, the display will be updated regarding to the register status.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Please be aware that button statuses will be changed by a Read command.
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
2. [Tool]: Testing Tools
Evaluation testing tools are available in this tab.
Click buttons for each testing tool.
Figure 4. Window of [ Tool ]
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
2-1. [Repeat Test]: Repeat Test Dialog
Click [Repeat Test] button in the Test tab to open a repeat test dialog shown below.
Repeat writing test can be executed by this dialog.
Figure 5. Window of [ Repeat Test ]
[Start] Button
: Starts the repeat test.
A dialog for saving a file of the test result will open when clicking this button.
Name the file.
Test will start after specifying a saving file.
[Close] Button
: Closes this dialog and finishes the process.
[Address] Box
: Data writing address in hexadecimal numbers.
[Start Data] Box
: Start data in hexadecimal numbers.
[End Data] Box
: End data in hexadecimal numbers.
[Step] Box
: Data write step interval.
[Repeat Count] Box : Repeat count of the test writing.
[Up and Down] Box : Data write flow is changed as below.
• Checked: Writes in step interval from the start data to the end data and turn back from the end data to
the start data.
[Example]
Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count.
Data flow:
[00→01→02→03→04→05→05→04→03→02→01→00] x Repeat Count Number
• Not checked: Writes in step interval from the start data to the end data and finishes writing.
[Example]
Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count.
Data flow:
[00→01→02→03→04→05] x Repeat Count Number
[Sampling Frequency] Box: Selects sampling frequency 44.1kHz/48kHz
[Count] Box
: Indicates the count number during a repeat test.
[Lch Level] Box : Indicates the Lch Level during a repeat test.
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
2-2. [Loop Setting]: Loop Dialog
Click [Loop Setting] button in the Tool tab to open loop setting dialog as shown below.
Writing test can be executed.
Figure 6. Window of [ Loop ]
[ OK ] Button
[ Cancel ] Button
[ Address ] Box
[ Start Data ] Box
[ End Data ] Box
[ Interval ] Box
[ Step ] Box
[ Mode Select ] Box
: Starts the test.
: Closes the dialog and finishes the process.
: Data writing address in hexadecimal numbers.
: Start data in hexadecimal numbers.
: End data in hexadecimal numbers.
: Data write interval time.
: Data write step interval.
: Mode select check box.
• Checked:
Writes in step interval from the start data to the end data and turn back from the end data to
the start data.
[Example]
Start Data = 00, End Data = 05, Step = 1
Data flow:
00→01→02→03→04→05→05→04→03→02→01→00
• Not Checked: Writes in step interval from the start data to the end data and finishes writing.
[Example]
Start Data = 00, End Data = 05, Step = 1
Data flow:
00→01→02→03→04→05
<KM105903>
2012/02
- 10 -
ASAHI KASEI
[AKD4710-A]
■ Dialog Boxes
1. [All Req Write]: All Reg Write dialog box
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
Figure 7. Window of [ All Reg Write ]
[Open (left)]: Selects a register setting file (*.akr).
[Write]: Executes register writing by the setting of selected file.
[Write All]: Executes all register writings.
Selected files are executed in descending order.
[Help]: Opens a help window.
[Save]: Saves a register setting file assignment. The file name is “*.mar”.
[Open (right)]: Opens a saved register setting file assignment “*. mar”.
[Close]: Closes the dialog box and finish the process.
~ Operating Suggestions ~
1.
2.
Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
When register settings are changed by [Save] button in the main window, re-read the file to reflect new register
settings.
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
2. [Data R/W]: Data R/W Dialog Box
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Figure 8. Window of [ Data R/W ]
[Address] Box: Input data address in hexadecimal numbers for data writing.
[Data] Box : Input data in hexadecimal numbers.
[Mask] Box : Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write]: Writs the data generated from Data and Mask values to the address specified by “Address” box.
[Read]: Reads data from the address specified by “Address” box.
The result will be shown in the Read Data Box in hexadecimal numbers.
[Close]: Closes the dialog box and finishes the process.
Data writing can be cancelled by this button instead of executing a write command.
*The register map will be updated after executing [Write] or [Read] commands.
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
MEASUREMENT RESULTS
 Audio
[Measurement condition]
 Measurement unit: Audio Precision SYS-2722
 BW
: 20Hz20kHz
 Power Supply
: VP=12V, VD1=3.3V, VD2=3.3V, VVD=3.3V
 Interface
: Input: Cannon, Output: BNC
 Temperature
: Room
 Volume Gain : 0dB
 Measurement signal line path: AINL±/AINR±  Volume→ TVOUTL/TVOUTR
Parameter
Input signal
Measurement filter
20kLPF
Results
Lch [dB]
96.7
Results
Rch [dB]
96.7
S/(N+D)
(At 2Vrms Output)
DR
S/N
1kHz, 0dBFS
1kHz, -60dBFS
“no-input
22kLPF, A-weighted
22kLPF, A-weighted
101.2
101.2
101.3
101.3
Plots
Figure 1-1. FFT (1kHz, 0dBFS input) at 2Vrms output
Figure 1-2. FFT (1kHz, -60dBFS input)
Figure 1-3. FFT (Noise floor)
Figure 1-4. THD+N vs. Input Level (fin=1kHz)
Figure 1-5. THD+N vs. fin (Input Level=0dBFS)
Figure 1-6. Linearity (fin=1kHz)
Figure 1-7. Frequency Response (Input Level=0dBFS)
Figure 1-8. Crosstalk (Input Level=0dBFS)
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
 Video
[Measurement condition]
 Signal Generator : Tektronix TG2000
: Tektronix TG700 (for S/N measurement)
 Measurement unit: Tektronix VM700T
 Power Supply
: VP=12V, VD1=3.3V, VD2=3.3V, VDD1=3.3V, VDD2=3.3V
 Interface
: Input: BNC, Output: BNC
 Temperature
: Room
 Measurement signal line path: S/N: ENCV  TVVOUT
Y/C Crosstalk: ENCV  TVVOUT, ENCRC  TVRC
DG, DP: ENCV  TVVOUT
Parameter
S/N
Input Signal
0% Flat Field
Y/C Crosstalk
(Measured at TVVOUT)
DG
100% Red Field
(YENCV, CENCRC)
Modulated 5 step
DP
Modulated 5 step
Measurement Filter
BW=15kHz to 5MHz
Filter=Uni-Weighted
BW=15kHz to Full
Results
76.4
-57.8
(Note1)
Min: -0.18
Max: 0.00
Min: -1.05
Max: 0.09
Unit
dB
dB
%
deg.
Plots
Figure 2-1. Noise spectrum (Input=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted)
Figure 2-2. Y/C Crosstalk (Measured at TVVOUT, Input= 100% Red, ENCV=Y, ENCRC=C), BW=15kHz to Full)
Figure 2-3. DG, DP (Input= Modulated 5 step)
(Note1) Y/C Crosstalk: Reference Measurement: Results: 1.8dB (Vp-p)
Composite signalENCV, no inputENCRC, TVRC is terminated by 75Ohm.
Y/C Crosstalk: Measurement: Results: -56.0dB (p-p)
YENCV, CENCRC, TVRC is terminated by 75Ohm.
Y/C Crosstalk calculation: -56.0dB (p-p) – 1.8dB (p-p) = -57.8dB (p-p)
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
Plots (Audio)
AK4710 AINL/AINR  TVOUTL/TVOUTR: FFT: fin=1KHz, Input Level=0dB
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure1-1. FFT (fin=1kHz, Input Level=0dB)
AK4710 AINL/AINR  TVOUTL/TVOUTR: FFT: fin=1KHz, Input Level=-60dB
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure-1-2. FFT (fin=1kHz Input Level=-60dB)
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
AK4710 AINL/AINR  TVOUTL/TVOUTR: FFT: No-Input
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure1-3. FFT (Noise Floor)
AK4710 AINL/AINR  TVOUTL/TVOUTR: THD+N Amplitude vs Input Amplitude: fin=1KHz
-80
-82
-84
-86
-88
-90
-92
d
B
r
-94
-96
A
-98
-100
-102
-104
-106
-108
-110
-140
-120
-100
-80
-60
-40
-20
+0
dBr
Figure1-4. THD+N vs. Input level (fin=1kHz)
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
AK4710 AINL/AINR  TVOUTL/TVOUTR: THD+N Amplitude vs Input Frequency: Input Level=0dB
-80
-82
-84
-86
-88
-90
-92
d
B
r
-94
-96
A
-98
-100
-102
-104
-106
-108
-110
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure1-5. THD+N vs. Input Frequency (Input level=0dB)
AK4710 AINL/AINR  TVOUTL/TVOUTR: Linearity: fin=1KHz
+0
T TTTTTTTTTTTTTTTTTTTTTTT
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBr
Figure1-6.Linearity (fin=1kHz)
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
AK4710 AINL/AINR  TVOUTL/TVOUTR: Frequency Response: Input Level=0dBr
+1
+0.8
+0.6
+0.4
+0.2
+0
-0.2
-0.4
-0.6
d
B
r
A
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
-2.2
-2.4
-2.6
-2.8
-3
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure1-7. Frequency Response (Input level=0dB)
AK4710 AINL/AINR  TVOUTL/TVOUTR: Crosstalk: fin=1KHz, Input Level=0dBr / No-input
-70
-75
-80
-85
-90
-95
-100
d
B
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure1-8. Crosstalk (Input level=0dB)
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
Plots(Video)
AK4710 ENCV  TVVOUT: S/N: Input Signal=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted
Figure 2-1. Noise spectrum (Input=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted)
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
AK4710 ENCV  TVVOUT / ENCRCTVRC: Y/C Crosstalk: Input Signal=100% Red Field,
YENCV, CENCRC, BW=15kHz to Full
Figure 2-2 Crosstalk (Measured at TVVOUT, Input= 100% Red Field, YENCV, CENCRC, BW=15kHz to Full)
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
AK4710 ENCV  TVVOUT: DG, DP: Input Signal=Modulated 5 step
Figure 2-3 DG, DP (Input Signal= Modulated 5 step)
<KM105903>
2012/02
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ASAHI KASEI
[AKD4710-A]
Revision History
Date
(YY/MM/DD)
11/01/14
Manual
Revision
KM105900
11/02/03
KM105901
11/06/21
KM105902
12/02/16
KM105903
Board
Reason
Revision
First Edition
0
Modification
0
Contents
Update of measurement results and Plots
1
Modification
Update of measurement results and Plots
2
Modification
Update of measurement results and Plots
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
 The PCB layout diagram above is an example only. Asahi Kasei
Microdevices Corporation (AKM) assumes no responsibility for any losses
incurred by you or third parties arising from the use of the information herein.
You are fully responsible for your PCB layout design. Please double
check the mounting capability when designing PCB layout.
<KM105903>
2012/02
- 22 -
SCL
PDN
2
1
VD2
3
SDA
4
HDVDD
5
CN1
VSS2
C3
C6
5
6
6
6
TVVOUT
7
8
7
TVRC
8
7
TVFB
1
2
28
CN
VEE
29
30
CP
31
32
VD2
SCL
TVRC
9
TVG
AINLN
25
26
27
CN
VEE
28
29
CP
AINRP
U2
TVVOUT
TVOUTL
TVFB
TVOUTR
TVRC
VD1
TVG
VSS1
TVB
TVSB
9
8
VSS2
AINRN
VSS3
VVD
TVFB
CN3
27
AINLP
26
AINRN
25
AINRP
24
TVOUTL
23
TVOUTR
22
VD1
21
24
9
AINL-
8
AINL+
7
AINR-
6
AINR+
5
TVOUTL
4
TVOUTR
3
VD1
C
23
22
21
20
19
18
17
C7
VP
VSS3
AGND
TVVOUT
U1
16
4
5
5
RCAVOUT
ENCY
3
ENCV
RCAVOUT
AINLP
15
4
4
PDN
14
2
RCAVOUT
33
34
SDA
35
1
ENCC
HDPB
ENCRC
3
open
13
R3
open
open
12
3
HDPR
30
HDPB
2
31
2
C4
AINLN
VD2
HDPR
open
HDY
SCL
1
ENCG
open
ENCB
R2
11
open
10
R1
1
32
HDY
SDA
C
HDVDD
CN2
PDN
36
open
VSS2
C5
C1
open
+
open
+
C2
3
4
5
6
7
8
D
9
D
VSS1
20
TVSB
19
open
C8
+
open
2
B
B
VVD
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
VP
11
12
13
14
15
16
17
18
open
C10
1
TVSB
open
+
C9
TVB
9
10
AGND
TVG
+
C11
open
C12
open
9
8
7
6
5
4
3
2
1
R4
open
A
A
CN4
VP
ENCY
ENCV
ENCC
ENCRC
ENCG
ENCB
VVD
TVB
Title
AKD4711-A / AKD4710-A_MAIN
Size
A3
- 23 5
4
3
Date:
2
Document Number
Rev
1
AK4710/AK4711
Thursday, February 16, 2012
Sheet
1
1
of
4
4
C14
0.1u
R5
75
1
ENCV
J3
TVVOUT
1
TVVOUT
R8
75
2
3
4
5
Audio Intput
J1
AINL+
2
3
4
5
C13
0.47u
Audio Output
R6
300
1
C15
(short)
AINL+
R9
10k
D
AGND
3
C17
0.1u
R11
75
ENCY
J8
TVRC
1
TVRC
R12
75
1
R10
300
2
3
4
5
JP1
AGND
C18
(short)
AGND
R13
300
J9
TVOUTR
1
1
ENCRC
1
TVG
AGND
J11
TVG
R16
75
J12
AINR+
2
3
4
5
C20
0.47u
1
ENCC
1
TVB
R19
75
AGND
1
2
3
4
5
1
C
3
J16
TVB
3
R18
75
J14
CINCHOUTR
2
3
4
5
AGND
AGND
C22
0.47u
R20
300
AINR-
+
2
3
4
5
C21
0.1u
AGND
J13
AINR
1
AGND
AGND
J15
ENCC
AGND
AINR+
AGND
C
R17
300
1
2
AGND
2
3
4
5
2
3
4
5
R14
10k
2
R15
75
+
2
3
4
5
C19
0.1u
+
TVOUTR
AGND
J10
ENCRC
2
3
4
5
AINL-
GND
AGND
J6
CINCHOUTL
AGND
C16
0.47u
+
1
2
3
4
5
1
AGND
3
AGND
J4
TVOUTL
1
AGND
J7
ENCY
2
3
4
5
R7
300
TVOUTL
J5
AINL
1
AGND
AGND
1
+
D
2
3
4
5
Video Output (SD)
2
J2
ENCV
2
2
Video Intput
3
+
5
AGND
JP2
GND
AGND
J17
ENCG
2
3
4
5
C23
0.1u
R21
75
1
ENCG
J18
RCAVOUT
1
RCAVOUT
R22
75
AGND
J19
ENCB
2
3
4
5
AGND
AGND
AGND
B
2
3
4
5
Video Output (HD)
C24
0.1u
B
1
ENCB
R23
75
J20
HDY
AGND
1
HDY
AGND
2
3
4
5
AGND
Blanking Output
J21
HDPB
1
HDPB
R24
75
J22
TVFB
1
TVFB
A
2
3
4
5
AGND
R25
470
1
TVSB
A
J23
HDPR
AGND
J24
TVSB
2
3
4
5
1
HDPR
2
3
4
5
2
3
4
5
Title
AGND
AKD4711-A / AKD4710-A_MAIN
Size
A3
AGND
- 24 5
4
3
Date:
2
Document Number
Rev
1
Audio Video Input / Output
Thursday, February 16, 2012
Sheet
1
2
of
4
5
4
3
R26
C25
10
8
6
4
2
4.7k
2.2u
2
1
PORT2 A1-10PA-2.54DSA(open)
9
7 SCL
5 SDA
3 SDA(ACK)
1
10pin-CTRL
DGND
C28
C
17
16
15
14
11
10
9
8
DGND
38
39
40
41
2
3
4
5
7
6
28
VSS0
1
2
3
4
5
0.1u
VDD1
JP3
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
PIC18F4550
TQFP 44-PIN
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
OSC1/CLKI
OSC2/CLKO/RA6
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
U3
VUSB
32
35
36
PORT1
VUSB
DD+
GND
USB(B type)
1
2
3
4
R44
R45
42
43
44
1
0
0
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
DGND
R35
470
R39
470
R38
MCLR_N/Vpp/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
D3.3V
R30
R31
R32
C29
0.1u
VSS1
SILK-SCREEN
1:VDD
2:MCLR
3:PGD
4:PGC
5:GND
C27
10u
VDD0
1u
29
C30
DGND
10k
10k
10k
51(open)
51(open)
51(open)
+
+
C26
10u
D
D3.3V
R27
R28
R29
NC
NC
Vin
Vout
Vcont PCL
NC
GND
T1
5V => 3.3V
DGND
8
7
6
5
TK73633AME
1
2
3
4
DGND
D
18
0
12
13
33
34
14
C32
0.1u
7
D3.3V
R40
0.1u
100k
R34
10k
10k
U4
1
3
5
9
11
13
USB-RST
C31
R33
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
2
4
6
8
10
12
R36
51
R37
51
SCL
SDA
Vcc
GND
74HC07
C
DGND
30
31
XTI
XTO
25
26
27
37
19
20
21
22
23
24
C33
22p
X1
20MHz
C34
22p
C35
470n
R41
R42
R43
51
51
51
DGND
SCL
SDA
SDA(ACK)
PIC18F4550
B
B
K
D3.3V
A
3
1
R46
D1
HSU119
10k
PDN
PDN
L
2
ATE1D-2M3
H
S1
U6
C36
0.1u
A
DGND
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
D3.3V
A
C37
0.1u
74HC14
Title
AKD4711-A / AKD4710-A_MAIN
Size
A3
DGND
- 25 5
4
3
Date:
2
Document Number
Rev
1
uP-I/F
Thursday, February 16, 2012
Sheet
1
3
of
4
5
4
3
2
1
VP
L1
(short)
1
2
VP
D
D
C38
+
47u
AGND
VD1
JP4
GND
DGND
T3
LM1117
1
JP5
VD1
OUT
L2
(short)
3
1
2
VD1
2
1
DGND
IN
GND
AGND
1
VP
C44
10u
C45
0.1u
C46
0.1u
C47
0.1u
+
C43
47u
+
2
+
VP
AGND
TJ563_Y
VD2
VD1
C
1
VD1
L3
(short)
R51
1
TJ563-R
VD2
1
0
VD2
1
VD2
C
2
AGND
+
C48
47u
2
TJ563-R
VVD
VSS2
1
VVD
TJ563-R
D3.3V
D3.3V
D3.3V
JP7
D3.3V
1
L6
(short)
1
AGND
DGND
D3.3V
+
C50
47u
1
TJ563-BK
B
2
2
AGND
TEST1 TEST2 TEST3 TEST4
(open) (open) (open) (open)
1
TJ563-R
TEST5
(open)
DGND
B
1
TJ563-BK
DGND
TEST6
(open)
T4
LM1117
VVD
JP6
VVD
1
1
TJ563-BK
OUT
L4
(short)
3
1
C54
1
C52
0.1u
C53
10u
+
2
HDVDD
+
C49
47u
2
10u
C51
0.1u
VVD
1
+
2
L5
(short)
2
VSS2
IN
GND
VSS2
AGND
AGND
A
A
Title
AKD4711-A / AKD4710-A_MAIN
Size
A3
- 26 5
4
3
Date:
2
Document Number
Rev
1
Power Supplly
Thursday, February 16, 2012
Sheet
1
4
of
4
- 27 -
- 28 -
- 29 -
- 30 -
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