AK4951EN

[AKD4951EN-B]
AKD4951EN-B
Evaluation board Rev.2 for AK4951EN
GENERAL DESCRIPTION
The AKD4951EN-B is an evaluation board for the AK4951EN 24bit CODEC with built-in PLL and MIC/HP/SPK
Amplifier. The AKD4951EN-B has the interface with AKM’s A/D evaluation boards. Therefore, it’s easy to
evaluate the AK4951EN. The AKD4951EN-B also has the digital audio interface and can achieve the interface
with digital audio systems via opt-connector.
 Ordering Guide
AKD4951EN-B ---
Evaluation board for AK4951EN
(Control software is included in this package.)
FUNCTION
 Compatible with 2 types of interface
- Direct interface with AKM’s A/D converter evaluation boards
- DIT/DIR with optical input/output
 USB port for board control
TVDD DVDD AVDD SVDD GND1
3.3V
1.8V
3.3V
3.3V
REG1
5V
0V
3.3V
REG
1.8V
REG
LDO
LIN1
Digital
MIC
(T3)
RIN1
PIC4550
USB
LIN2
Mini
Jack
AK4951EN
RIN2
External
Clock
Opt In
LIN3
AK4118A
(DIT/DIR)
RIN3
SPP SPN
SPK
LINEOUT
Jack
Opt Out
HP
Jack
Figure 1. AKD4951EN-B Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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 Operation Sequence
(1) Set up the power supply lines.
(1-1) In case of supplying the power from regulator. <Default>
JP3
JP17
SVDD
USB5V
1.8V
5V
3.3V
Name of
Jack
REG1
GND1
Color
red
black
Using
Default Setting
for regulator input
5V
ground
0V
Table 1. Set up of power supply lines
(1-2) In case of using the power supply connectors.
JP3
SVDD
JP17
USB5V
1.8V
5V
3.3V
(2) Set up the evaluation mode, jumper pins and DIP switch. (See the followings.)
(3) Power on.
The AK4951EN and AK4118A must be reset after the power supplies are applied.
The AK4951EN and AK4118A should be reset once by bringing SW1 (PDN) “L” upon power-up. Click the
Dummy Command button on the control software after releasing the reset by SW1= “H”.
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 Evaluation mode
In case of using the AK4118A when evaluating the AK4951EN, audio interface format of both devices must be
matched.
Reter to the datasheet for audio interface format of the AK4951EN, and Table 2 for audio interface format of the
AK4118A.
The AK4118A operates at fs of 32kHz or more. If the fs is slower than 32kHz, please use other mode.
In addition, MCLK of AK4118A supports 256fs and 512fs. When evaluating in a condition except above, please use
other mode.
Refer to the datasheet for register setting of the AK4951EN.
Applicable Evaluation Mode
(1) A/D Evaluation using the AK4118A (DIT).
(1-1) Setting in External Slave Mode
(2) D/A Evaluation using the AK4118A (DIR). <Default>
(2-1) Setting in External Slave Mode
(3) Evaluation of A/D or D/A using the external clock.
(3-1) Setting in PLL Master Mode
(3-2) Setting in PLL Slave Mode
(3-3) Setting in External Slave Mode
(4) Evaluation of Loop-back.
(4-1) Setting in PLL Master Mode
(4-2) Setting in PLL Slave Mode
(4-3) Setting in External Slave Mode
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(1) A/D Evaluation using the AK4118A (DIT)
(1-1) Setting in External Slave Mode
X1 (X’tal: 12.288MHz) and PORT2 (DIT) are used. Do not connect anything to PORT1 (DIR).
Registers of the AK4951EN should be set to “EXT Slave Mode”. MCKI, BICK and LRCK are supplied from the
AK4118A, and SDTO of the AK4951EN is output to the AK4118A.
The jumper pins should be set as follows.
JP11
MCKI
EXT
JP14
BICK
DIR
EXT
JP12
LRCK
DIR
EXT
JP15
SDTO
DIR
(2) Evaluation of D/A using DIR of AK4118A. <Default>
(2-1) Setting in External Slave Mode
PORT1 (DIR) is used. Do not connect anything to PORT2 (DIT).
Registers of the AK4951EN should be set to “EXT Slave Mode”.
The jumper pins should be set as follows.
JP11
MCKI
EXT
JP14
BICK
DIR
EXT
DIR
JP12
LRCK
EXT
<KM117404>
DIR
JP13
SDTI
EXT
DIR
JP10
SDTI-SEL
ADC
DIR
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(3)
A/D or D/A Evaluation using the external clock.
External clocks are used. Do not connect anything to PORT1 (DIR) and PORT2 (DIT).
(3-1) Setting in PLL Master Mode
The master clock is input from the MCKI pin of JP11. An internal PLL circuit generates BICK and LRCK.
Registers of the AK4951EN should be set to “PLL Master Mode”.
BICK, LRCK SDTI and SDTO are input into and output from JP14, JP12, JP13 and JP15.
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or P
AK4951EN
MCKI
BICK
LRCK
32fs, 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 2. PLL Master Mode
.
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(3-2) Setting in PLL Slave Mode
A reference clock of PLL is selected among the input clocks that are supplied to the BICK pin. The required clock
to operate the AK4951EN is generated by an internal PLL circuit.
Registers of the AK4951EN should be set to “PLL Slave Mode” (Reference Clock = BICK).
BICK, LRCK SDTI and SDTO are input into and output from JP14, JP12, JP13 and JP15.
DSP or P
AK4951EN
MCKI
32fs, 64fs
BICK
1fs
LRCK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 3. PLL Slave Mode 2(PLL Reference Clock: BICK pin)
The jumper pins should be set as follows.
JP11
MCKI
DIR
EXT
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(3-3) Setting in External Slave Mode
Registers of the AK4951EN should be set to “EXT Slave Mode”.
MCLK, BICK, LRCK SDTI and SDTO are input into and output from JP11, JP14, JP12, JP13 and JP15.
AK4951EN
DSP or P
256fs,384fs
512fs or 1024fs
MCKI
MCLK
 32fs
BICK
BCLK
1fs
LRCK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 4. EXT Slave Mode
(4)
Evaluation in Loop-back Mode.
(4-1) Setting in PLL Master Mode
Do not connect anything to PORT1 (DIR), PORT2 (DIT).
Registers of the AK4951EN should be set to “PLL Master Mode”.
(4-1-1) In case of supplying MCLK to JP11
The jumper pins should be set as follows.
JP15
SDTO
JP13
SDTI
EXT
<KM117404>
DIR
JP10
SDTI-SEL
ADC
DIR
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(4-2) Setting in PLL Slave Mode
Registers of the AK4951EN should be set to “PLL Slave Mode” (Reference Clock: BICK).
Do not connect anything to PORT1 (DIR) and PORT2 (DIT).
(4-2-1) In case of supplying BICK and LRCK from the external clock
The jumper pins should be set as follows.
JP11
MCKI
EXT
JP13
SDTI
JP15
SDTO
EXT
DIR
DIR
JP10
SDTI-SEL
ADC
DIR
(4-3) Setting in External Slave Mode
Registers of the AK4951EN should be set to “EXT Slave Mode”.
Do not connect anything to PORT1 (DIR), PORT2 (DIT).
(4-3-1) In case of using clocks from AK4118A
Use X1 (12.288MHz).
The jumper pins should be set as follows.
JP11
MCKI
EXT
JP14
BICK
DIR
EXT
DIR
JP12
LRCK
EXT
JP15
SDTO
DIR
<KM117404>
JP13
SDTI
EXT
DIR
JP10
SDTI-SEL
ADC
DIR
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 DIP Switch Setting
[S1] (SW DIP-4): Mode setting of the AK4118A.
No.
1
2
3
4
Name
OCKS1
DIF0
DIF1
DIF2
ON (“H”)
OFF (“L”)
AK4118A Master Clock Setting : See Table 4
AK4118A Audio Format Setting
See Table 3
Default
L
L
L
H
Table 2. Mode Setting of the AK4118A
Mode
DIF2
DIF1
DIF0
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
SDTO
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
BICK
64fs
64fs
64fs
64fs
64fs
64fs
64 -128fs
64 -128fs
I/O
O
O
O
O
O
O
I
I
Default
Table 3. AK4118A Audio Interface Format Setting
OCKS1
MCKO1
X’tal
Default
0
256fs
256fs
1
512fs
512fs
Table 4. AK4118A Master Clock Setting
 Toggle SW Function
*Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Power downs AK4951EN and AK4118A. Keep “H” during normal operation.
 Control Port
It is possible to control AKD4951EN-B via general USB port. Connect cable with the USB connection(PORT3) on
the board and PC.
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 Analog Input/Output Circuits
(1) Input Circuits
Figure 5. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 Input Circuits
(1-1) LIN1/RIN1Input Circuit <Default>
LIN1 and RIN1are input to J1.
When the Mic Power is not used, JP6 and JP7 should be set to open.
JP1
LIN-SEL
JP2
LIN3
RIN3
LIN2
RIN2
LIN1
RIN1
JP4
JP5
JP6
JP7
DMDT
DMCK
MP-LIN1
MP-RIN1
RIN-SEL
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(1-2)
LIN2/RIN2 Input Circuit <Default>
LIN2 and RIN2 are input to J2 and J3.
When the Mic Power is not used, JP8 and JP9 should be set to open.
JP1
JP2
LIN3
RIN3
LIN2
RIN2
LIN1
RIN1
LIN-SEL
JP8
JP9
MP-LIN2
MP-RIN2
RIN-SEL
(1-3) LIN3/RIN3 Input Circuit
LIN3 and RIN3 are input to J2 and J3.
JP1
JP2
LIN3
RIN3
LIN2
RIN2
LIN1
RIN1
LIN-SEL
RIN-SEL
(1-4) Digital Mic Input Circuit
DMCK is output from JP5 and DMDT is input to JP4.
JP4
JP5
DMDT
DMCK
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(2) Output Circuits
(2-1) HPL/HPR Output Circuit
3
HPR
J2 HP-OUT
2
1
HPL
C29
0.22u
C28
0.22u
R18
33
R17
33
VSS1
Figure 6. HPL/HPR Output Circuit
HPL and HPR are output from J2
(2-2) SPP/SPN Output Circuit
1
TP1
SPP
SPP
1
TP2
SPN
SPN
Figure 7. SPP/SPN Output Circuit
SPP and SPN are output from TP1 and TP2.
(2-3) Stereo Line Output Circuit
+
3
+
C25 1u
2
1
ROUT
LOUT
J3 LINE-OUT
C24 1u
R15
22k
R16
22k
VSS3
Figure 8. LOUT/ROUT Output Circuit
LOUT and ROUT are output from J3.
* AKM assumes no responsibility for the trouble when using the above circuit examples.
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AK4951EN Control Software Manual
■Evaluation Board and Control Software Settings
1. Set up the evaluation board as needed, according to the previous terms.
2. Connect the evaluation board and PC with a USB cable.
3. The USB control is recognized as HID (Human Interface Device) on the PC.
4. Double-click the icon “akd4951en-b.exe” to open the control program. (Note 1)
5. When the screen does not display “AKDUSBIF-B” at bottom left, reconnect the PC and the USB cable, and push the
[Port Reset] button.
6. Begin evaluation by following the procedure below.
Figure 9. Window of Control Soft
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■Operation Overview
Function and Register map are controlled by this control software. These controls may be selected by the upper tabs.
Frequently used Buttons, such as the register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “■ Dialog Box” section for details of each dialog box setting.
1. [Port Reset]: Resets the connection to PC.
Click this button when connecting USB cable after the control software set up.
2. [Write Default]: Register Initialization.
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executes write commands for all registers displayed.
4. [All Read]: Executes read commands for all registers displayed.
5. [Save]: “Save Address of Register” dialog box pops up.
6. [Load]: Executes data write from a saved file.
7. [All Reg Write]: “All Reg Write” dialog box pops up.
8. [Sequence]: “Sequence” dialog box pops up.
9. [Sequence (File)]: “Sequence (File)” dialog box pops up.
10. [Read]: Reads current register settings and displays to the register area (on the right of the main window).
This is different from [All Read] button as it does not reflect to the register map. It only displays register
values in hexadecimal numbers.
11. [Dummy Command]: The dummy command is written (Note 1)。
Note 1. The AK4951 should be reset by the PDN pin (“L” -> “H”) after the power supplies are applied.
After that, “Dummy Command” button should be pushed.
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■Tab Functions
1. [Function] Tab: Function Control
When a button in the “Function” frame is clicked, a sequential process is executed.
When other button is clicked, the setting dialog opens.
(Refer to the “■ Sequential process” section for details of each dialog box setting, or “■ Dialog Box” section for
details of each dialog box setting.)
Figure 10. [Function] Window
[Function] button
Setting dialog button
: Executes a sequential process shown on each button. (Refer to 1- 1)
: Opens a setting dialog. (Refer to 1- 2)
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1- 1. [Function] Button
Figure 11. [Function] Button
A function button executes the sequence process shown on the each button and updates several registers.
These functions are mainly for path settings.
Function Name
Recording_MIC+18dB
(ALC, AHPF ON)
Recording_DigitalMIC
(AHPF, ALC ON)
Playback_Headphone
Playback_Speaker
(ALC ON)
Playback_Lineout
Loopback_Headphone
(ALC, AHPF ON)
Description
MIC Input Recording
(Stereo)
Digital MIC Input
Recording (Stereo)
Input
LIN1,
RIN1
DMDAT
Output
SDTO
Headphone Output
SDTI
SPK Output
SDTI
Stereo Line Output
SDTI
LOUT,
ROUT
SPP
SPN
LOUT,
ROUT
HPL
HPR
SDTO
Path
LIN1,RIN1→MIC-AMP(+18dB)→ADC
→Digital Filter→SDTO
DMDAT→Digital Filter→SDTO
(When Digital MIC used, LIN1 changes to
DMDAT.)
SDTI→DAC→HPL,HPR
SDTI→ALC→DAC→SPP,SPN
SDTI→DAC→LOUT,ROUT*
(It goes via a digital filter.)
LIN1,RIN1→ADC→Digital Filter→DAC
→HPL,HPR
Loopback
LIN1,
(MIC Input Recording, RIN1
Headphone Output)
Table 5. Sequence Process Setting
※ The Setting of Clock mode and I/F mode are not changed. The default values are follows.
Clock Mode
：EXT mode (slave)
I/F mode
：24bit MSB Justified
Sampling Frequency ：48 kHz
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1- 2. Setting Dialog Button
Figure 12. Setting Dialog button
[System Clock Audio I/F] button : Opens “System Clock & Audio I/F” dialog box.
[MIC – ADC Setting] button
: Opens “MIC_ADC Setting” dialog box.
[Digital MIC Setting] button
: Opens “Digital MIC Setting” dialog box.
[Digital Filter] button
: Opens “Filter Setting” dialog box.
[ALC Setting] button
: Opens “ALC Setting” dialog box.
[DAC Setting] button
: Opens “DAC_LINE/SPK Setting” dialog box.
[BEEP Setting] button
: Opens “BEEP Setting” dialog box.
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2. [REG] Tab: Register Map
This tab is for register read and write.
Each bit on the register map is a push-button switch. The register is updated by mouse operation.
Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray)
Grayed out registers are Read-Only registers. They cannot be controlled.
The registers which are not defined on the datasheet are indicated as “---”.
Figure 13. [REG] Window
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2-1. [Write]: Data Write Dialog
Select the [Write] button located on the right of the each corresponding address when changing two or more bits
on the same address simultaneously.
Click the [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When the checkbox next to the bit name is checked, the data will become “1”. When the checkbox is not checked,
the data will become “0”.
Click [OK] to write the set values to the registers, or click [Cancel] to cancel this setting.
Figure 14. [Register Set] Window
2-2. [Read]: Data Read
Click the [Read] button located on the right of the each corresponding address to execute a register read.
The current register value will be displayed in the register window as well as in the upper right hand DEBUG
window.
Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray).
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■Dialog Box
1. [Save]: [Save Address of Register] Dialog Box
Click the [Save] button in the main window for save address setting dialog box.
Figure 15. [Save] Window
[All Address] check box
[Start Address] edit box
[End Address] edit box
[OK] button
[Cancel] button
: When the [All Address] checkbox is checked, all register settings will be saved.
: When the [All Address] check box is not checked, set starts register address to save.
: When the [All Address] check box is not checked, set end register address to save.
: Selects a file to save and saves register settings.
: Cancel and finish this process.
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2. [All Reg Write]: [All Register Write] Dialog Box
Click the [All Reg Write] button in the main window to open register setting file window show below.
Register setting files saved by the [Save] button may be applied.
Figure 16. [All Reg Write] Window
[Open (left)] button : Selects a register setting file (*.akr).
[Write] button
: Executes register write with selected file setting.
[Help] button
: Opens a help window.
[Save] button
: Saves a register setting file assignment. File name is “*.mar”.
[Open (right)] button
: Opens a saved register setting file assignment “*. mar”.
[Close] button
: Closes the dialog box and finish the process.
[All Write] flame
: Executes all register write.
Selected files are executed in descending order.
[Start] button
: Start the register writing.
[Stop] button
: Stop the register writing.
[Interval time] edit box : Set interval time to start next register setting file. (5msec ~ 10,000msec)
[Current No] edit box : The file number which is being processed is displayed. (File number is assigned 1-10
from top to bottom.)
~ Operating Suggestions ~
1. Files saved by the [Save] button and opened by the [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
2. hen register settings are changed by the [Save] button in the main window, re-read the file to reflect new
register settings.
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3. [Sequence]: [Sequence] Dialog Box
Click the [Sequence] button in the main window to open register sequence setting dialog box
Register sequence can be set in this dialog box.
Figure 17. [Sequence] Window
~ Sequence Setting ~
Set register sequence according to the following process.
1.
Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select items>
・No use
・Register
・Reg_Mask
・Interval
・Stop
・End
: Not using this address
: Register write
: Register write (Masked)
: Takes an interval
: Pauses the sequence
: Ends the sequence
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2.
Input sequence
[Address] : Data address
[Data]
: Write data
[Mask]
: Mask
This value “ANDed” with the write data becomes the input data. The bits which corresponding
Mask bit = “0” are not changed. At this time, data read is not executed, and the storage data of this
software is used. “Write Default” must be executed after power up the AK4958 or when the AK4958
is reset by the PDN pin since the storage data and register values are different.
This is the actual write data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask = 0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
[Interval] : Interval time
Valid boxes for each process command are shown below.
・No use
: None
・Register
: [ Address ], [ Data ], [ Interval ]
・Reg_Mask
: [ Address ], [ Data ], [ Mask ], [ Interval ]
・Interval
: [ Interval ]
・Stop
: None
・End
: None
~ Control Buttons ~
Functions of Control Button are shown below.
[DEL] button
: Checked step is deleted.
[INS] button
: The last deleted step is inserted to checked step.
[Start Step] select : Select start step.
No.1 Step
: Start from No.1 step.
Checked Step : Start from checked step.
[Start] button
: Executes the sequence.
[Stop] button
: Stops the sequence.
[Help] button : Opens a help window.
[Save] button
: Saves sequence settings as a file. The file name is “*.aks”.
[Open] button : Opens a sequence setting file “*.aks”.
[Close] button : Closes the dialog box and finishes the process.
~ Stop of the Sequence ~
When “Stop” is selected in the sequence, the process is paused at this step and restart step number is checked.
It starts again from the checked step by clicking the [Start] button. When the process at the end of sequence is
finished, “Step No.1” of [start step] is selected automatically.
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4. [Sequence (File)]:[Sequence by *.aks file] Dialog Box
Click the [Sequence (File)] button to open sequence setting file dialog box shown below.
Files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 18. [Sequence (File)] Window
[Open (left)] button
[Start] button
[Start All] button
: Opens a sequence setting file (*.aks).
: Executes the sequence by the setting of selected file.
: Executes all sequence settings.
Selected files are executed in descending order.
[Stop] button
: Stops the sequence process.
[Help] button
: Opens a help window.
[Save] button
: Saves a sequence setting file assignment. The file name is “*.mas”.
[Open (right)] button : Opens a saved sequence setting file assignment “*. mas”.
[Close] button
: Closes the dialog box and finishes the process.
~ Operating Suggestions ~
1. Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be
stored in the same folder.
2. When “Stop” is selected in the sequence, the process will be paused and a pop-up message will appear. Click
“OK” to continue the process.
Figure 19. [Sequence Pause] Window
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5. [System Clock Audio I/F]: [System Clock & Audio I/F] Dialog Box
Click the [System Clock Audio I/F] button in the main window to open system clock and Audio I/F setting dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 20. [System Clock Audio I/F] Window
When clock mode is changed to “PLL Mode” from “EXT Mode”, PMVCM bit is set to "1" automatically.
Even if “Clock Mode” returns to “EXT Mode”, PMVCM bit is not set to “0”. Please operate a register map directly.
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6. [MIC – ADC Setting]: [MIC – ADC Setting (Recording)] Dialog Box
Click the [MIC-ADC Setting] button in the main window to open MIC and ADC setting dialog box.
MIC/Line input, ADC, MIC gain and sensitivity setting are available.
“MIC Gain Adjustment”, fine tuning of a gain can be performed.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register demotions.)
Figure 21. [MIC-ADC Setting] Window
In the following cases, PMVCM bit is set to “1” automatically.
Since PMVCM bit is not set to “0” even if it returns each setup, please operate a register map directly.
① When MIC Power (PMMP bit) is Power-up
② When MIC Amp Power (PMADL/R bit) is Power-up (Note 2)
Note 2. When the path of a digital filter is selected, “1” is set to PMPFIL bit.
Since a PMPFIL bit is not set to “0” even if it returns each setup, please operate a register map directly.
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~ Gain Control by Slider ~
The volume can also be changed by slider.
When a value is input in the edit box, the slide bar is moved to the value that selected by the edit box.
Use the mouse or arrow keys on the keyboard for small adjustments.
Slide bar is
moved to the
selected value
The value which can be set up is chosen
automatically.
Figure 22. Volume Slider Control
7. [Digital MIC Setting]: [Digital MIC Setting] Dialog Box
Click the [Digital MIC Setting] button in the main window to open Digital MIC setting dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 23. [Digital MIC Setting] Window
When choice other than [All”0”, All”0”] are chosen by combo box of “Input Signal Select (PMDML/R bit)”, PMVCM
bit is set to “1” automatically.
Since PMVCM bit is not set to “0” even if it returns each setup, please operate a register map directly.
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8. [Digital Filter]: [Filter Setting] Dialog Box
Click the [Digital Filter] button in the main window to open Digital Filter setting dialog.
Coefficient and frequency of digital filter are calculated on this dialog.
(Refer to the datasheet for register definitions.)
Figure 24. [Digital Filter] Window
[Register Setting] button
: Opens the register setting dialog.
Register writes of a filter factor are also executed.
[F Response] button
: Opens the frequency response plot dialog [Filter Plot].
Register writes of a filter factor are also executed.
[Write] button
: Calculation of all the filters and coefficient writing are executed.
[Reg Map to Fc/Plot] check box :
When [Reg Map to Fc/Plot] is checked, the coefficient currently written in the register
map is reflected to each parameter.
Gain of HPF and LPF should be set to 1.0. When carrying out coefficient writing by
[Coefficient Write] etc. on this dialog, Gain of HPF and LPF is always 1.0.
EQ Sequence for Noise [ON/OFF] button : ON: EQCx bit, EQxT bits and EqxG bits are set for noise processing.
OFF: The bits will return to the state of before the button is set to ON.
[Close] button
: Closes the dialog box and finishes the process.
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8-1. Parameter Setting
Please set a parameter of each Filter
Parameter
Sampling Rate
Detail
Setting Range
Sampling Frequency (fs)
8, 11.025, 12, 16, 22.05, 24
32, 44.1 or 48kHz
HPF
HPF1 Cut Off Frequency
HPF2 Cut Off Frequency
High Pass Filter 1 cut off frequency
High Pass Filter 2 cut off frequency
3.7×fs/48 ～ 236.8×fs/48 (kHz)
0.0001 ≦ fc/fs < 0.497
AHPF
AHPF Detection Level
AHPF Suppressor Level
Auto High Pass Filter Detection Level
Auto High Pass Filter Suppressor Level
0.5(weak) ～ 4.0(strong)
weak, medium1, medium2, strong
LPF
Cut Off Frequency
Low Pass Filter cut off frequency
0.05 ≦ fc/fs < 0.497
FIL3
Cut Off Frequency
Filter type
Gain
FIL3 cut off frequency
The selection of filter type
Gain
0.0001 ≦ fc/fs < 0.497
LPF or HPF
-10dB ≦ Gain ≦ 0dB
EQ0
Pole Frequency
Zero-point Frequency
Gain
EQ0 Pole frequency
EQ0 Zero-point frequency
Gain
Gain2
Gain2
0.0001 ≦ fc/fs < 0.497
0.0001 ≦ fc/fs < 0.497
-20dB ≦ Gain ≦ +12dB
0 / +12 / +24dB
5 Band Equalizer
EQ1-5 Center Frequency
EQ1-5 Band Width
EQ1-5 Gain
EQ1-5 Center frequency
EQ1-5 Band width
EQ1-5 Gain
(Note 3)
(Note 4)
0.003 < fc/fs < 0.497
fc/fs < 0.497
-1 ≦ Gain < 3
Table 6. Parameter Setting of [Filter Setting]
Note 3. A gain difference is a bandwidth of 3dB from center frequency.
Note 4. When a gain is “-1”, EQ becomes a notch filter.
“HPF1 Enable”, “AHPF Enable”, “HPF2 Enable”, “LPF Enable”, “FIL3 Enable”, “EQ0 Enable”, “EQ1”, “EQ2”,
“EQ3”, “EQ4”, “EQ5” Please set ON/OFF of Filter with a check button.
When checked it, Filter becomes ON. When “Notch Filter Auto Correction” is checked, perform automatic
correction of the center frequency of the notch filter is executed.
Figure 25. Filter ON/OFF Check Box
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8-2. [Register Setting]: [Register Setting for Filter] Dialog Box
Click the [Register Setting] button, a register set value is displayed. When a value out of a setting range is set, error
message is displayed, and a calculation of register setting is not carried out.
Figure 26. [Register Setting for Filter] Window
Followings are the cases when a register set value is updated.
1. When [Register Setting] button was pushed.
2. When [F Response] button was pushed.
3. When [Write] button was pushed.
4. When [UpDate] button was pushed on a frequency characteristic indication window.
5. When Enter or the Tab key is pressed after setting each parameter.
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8-3. [F Response]: [Filter Plot] Dialog Box
A frequency characteristic is displayed when push a [F Response] button. Then, a register set point is also updated.
Change Frequency Range, and indication of a frequency characteristic is updated when push a [UpDate] button.
Figure 27. [F Response] Window
[Frequency Range] edit box
: The width of the frequency display is specified.
[UpDate] button
: It draws in the graph again.
[Gain/Phase] radio button : Switch of “Gain/Phase” display.
[Log View] check button
: Switch of “Linear/Log” display.
[Close] button
: Closing the dialog box and finish the process.
~ Adjustment of vertical range ~
1．[ Y-axis Ref ] edit box
: Display setting of center value.
2．[Vertical slider]
: Movement of vertical display.
3．[Horizontal slider]
: Adjustment of the horizontal display.
(The left side reduces, and the right side expands.)
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8-4. 5-BandEQ operation on Filter Plot screen
When EQ (1~5) is turning “ON”, a green number is displayed on the Filter Plot dialog box.
This number shows the setting of the center frequency and the gain of each EQ.
(The horizontal coordinates of a number is the center frequency of EQ, and the vertical ordinate is a gain of EQ
(-1 ～ 2.99).)
The number under the display is operated with the mouse, and it is possible to set the filter characteristic on this
screen.
The center frequency and the gain setting are changed by moving the mouse while left-clicking.
The setting of the bandwidth is changed by moving the mouse while right-clicking.
After operating the mouse
the value of the center frequency and the gain is
updated.
The number is selected.
The movement operation is done while
left-clicking.
Figure 28. Filter Setting (Left-clicking operation)
After operating the mouse
the value of the bandwidth is updated.
Figure 29. Filter Setting (Right-clicking operation)
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8-5. Simulation of Fil3 Filter
Setting of Stereo-MIC
[L-ch Level] / [R-ch Level]
[Distance]
[Angle]
Default Fil3: OFF
: Gain mismatch of stereo MIC sensitivity are set.
: The distance between the sound source and the MIC is set.
: The angle between the sound source and the MIC is set.
FIL3: ON, Filter Type: LPF, EQ0: ON
Figure 30. Stereo Separation Emphasis Operation
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8-6. About “Notch Auto Correct”
If the gain of 5-Band EQ is set to “-1”, Equalizer becomes a notch filter.
When the center frequency of two or more notch filters is adjacent, the gap is generated in the center frequency.
(Figure 31) When “Notch Auto Correct” button is checked, the center frequency of the notch filter is automatically
corrected. The gain setting of the automatic correction function is effective and only EQ of “-1” is effective.
(Figure 32)
This automatic compensation is effective to EQ which set the gain as “-1”. (Note 5)
Note 5. There is a possibility that the automatic compensation is not correctly done when the width of the
center frequency is smaller than that of the bandwidth setting.
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth: 200Hz (EQ2~4))
Figure 31. 5Band Equalizer Operation (Not Check of “Notch Auto Correct”)
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Bandwidth: 200Hz (EQ2~4))
Figure 32. 5Band Equalizer Operation (Checked of “Notch Auto Correct”)
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8-7. Common Gain Sequence for Noise
If “EQ Sequence for Noise (ON/OFF)” button is pushed, setup bit about EQ2-5 shown below are changed.
When the button pushed to OFF, each setup is returned the state of before pushing a button.
Please use the button when it expected that a noise continues.
Figure 33. Equalizer Gain Setting
Button ON: EQCx bit: OFF, EqxG5-0 bits: 0x3F (-0.03dB), EqxT1-0 bits: 00 (256/fs)
Figure 34. Equalizer Gain Setting (Setting for Noise button is “ON”)
Button OFF: the state of before pushing a button.
Figure 35. Equalizer Gain Setting (Setting for Noise button is “OFF”)
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9. [ALC Setting]: [ALC Setting] Dialog Box
Click the [ALC Setting] button in the main window to open ALC setting dialog.
ALC parameters are controlled in this dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 36. [ALC Setting] Window
~ Volume Read ~
When the [Start] button on the bottom right of the dialog is clicked, reading “VOL” register is executed periodically.
This interval time is set by the edit box beside the button. This reading continues until the stop button is pushed.
The read value is displayed on the progress control and
edit box.
The Interval of read-out can set up in 100~1000 msec.
Figure 37. Volume Progress Control
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10. [DAC Setting]: [DAC_LINE/SPK/HP Setting(Playback)] Dialog Box
Click the [DAC Setting] button in the main window to open DAC setting dialog.
Output mode, DAC and output gain setting are available.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 38. [DAC Setting] Window
In the following cases, PMVCM bit is set to “1” automatically.
Since PMVCM bit is not set to “0” even if it returns each setup, please operate a register map directly.
①
②
③
④
When DAC Power (PMDAC bit) is Power-up (Note 6)
When SPK-Amp (PMSPK, SPPSN, DACS bit) are Enable
When Line Out (PMLO, LOPS, DACL bit) are Enable
When DAC_HeadphoneAmp (PMHPL bit, PMHPR bit) are Power-up
Note 6. When the path of a digital filter is selected, “1” is set to PMPFIL bit.
Since a PMPFIL bit is not set to “0” even if it returns each setup, please operate a register map directly.
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11. [BEEP Setting]: [BEEP Setting] Dialog Box
Click the [BEEP Setting] button in the main window to open BEEP setting dialog.
The settings on this dialog are interlocked with the settings on register map.
(Refer to the datasheet for register definitions.)
Figure 39. [BEEP Setting] Window
When BEEP Input Power (PMBP bit) is Power-up, PMVCM bit is set to “1” automatically.
Since PMVCM bit is not set to “0” even if it returns the setup, please operate a register map directly.
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■Sequential process
1. [Recording_MIC+18dB (ALC, AHPF ON)]
When [Recording_MIC+18dB] button in the main window is clicked, the sequence for MIC input Settings (stereo) is
executed. (Note 7)
[MIC-ADC Setting] Window
[ALC Setting] Window
[Filter Setting] Window
Figure 40. [Recording_MIC+18dB] Setting
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2. [Recording_DigitalMIC (AHPF, ALC ON)]
When [Recording_DigitalMIC] button in the main window is clicked, the sequence for Digital MIC input Settings
(stereo) is executed. (Note 7)
[Digital MIC Setting] Window
[ALC Setting] Window
[Filter Setting] Window
Figure 41. [Recording_DigitalMIC] Setting
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3. [Playback_Headphone]
When [Playback_Headphone] button in the main window is clicked, the sequence for Headphone output Settings is
executed.
[DAC_LINE/SPK/HP Setting] Window
Figure 42. [Playback_Headphone] Setting
4. [Playback_Speaker (ALC ON)]
When [Playback_Speaker] button in the main window is clicked, the sequence for Speaker output Settings is
executed. (Note 7)
[DAC_LINE/SPK/HP Setting] Window
[ALC Setting] Window
Figure 43. [Playback_Speaker] Setting
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5. [Playback_Lineout]
When [Playback_Lineout] button in the main window is clicked, the sequence for Line output Settings is
executed. (Note 7)
[DAC_LINE/SPK/HP Setting] Window
Figure 44. [Playback_Lineout] Setting
5. [Loopback_Headphone]
When [Loopback_Lineout] button in the main window is clicked, the sequence of Loopback settings is executed.
[MIC-ADC Setting] Window
[ALC Setting] Window
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[Filter Setting] Window
[DAC_LINE/SPK/HP Setting] Window
Figure 45. [Loopback_Headphone] Setting
Note 7. The register setting of ALC by the sequence of [Recording_MIC+18dB], [Recording_DigitalMIC],
[Playback_Speaker] or [Loopback_Headphone] is same.
The register setting of Digital Filter is also the same among the above except [Playback_Speaker].
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MEASUREMENT RESULTS
[Measurement Condition]
・
・
・
・
・
・
・
・
・
・
Measurement unit
MCKI
BICK
fs
Bit
Measurement Mode
Power Supply
Input Frequency
Measurement Frequency
Temperature
: Audio Precision, System two Cascade
: 256fs (12.288MHz)
: 64fs
: 48kHz
: 24bit
: EXT Slave Mode
: AVDD = SVDD = TVDD = 3.3V, DVDD = 1.8V
: 1kHz
: 20 ~ 20kHz
: Room
[Measurement Results]
1. ADC
Result
Lch
ADC: LIN1/RIN1 → ADC → IVOL, IVOL=0dB, ALC=OFF
MGAIN = +18dB
S/(N+D)
(-1dBFS)
82.8
DR
(-60dBFS, A-Weighted)
89.0
S/N
(A-weighted)
88.9
MGAIN = 0dB
S/(N+D)
(-1dBFS)
84.0
DR
(-60dBFS, A-Weighted)
96.1
S/N
(A-weighted)
96.3
Rch
Unit
82.8
89.0
89.0
dB
dB
dB
84.0
96.0
96.2
dB
dB
dB
2. DAC
Result
Unit
Lch
Rch
Headphone-Amp: DAC  HPL/HPR, IVOL=DVOL=0dB, RL=16Ω
fs=48kHz, BW=20kHz
S/(N+D)
81.4
79.1
dB
S/N
(A-weighted)
97.5
97.6
dB
Speaker-Amp: DAC  SPP/SPN, IVOL=DVOL=0dB, SPKG=+8.4dB, RL=8
fs=48kHz, BW=20kHz
S/(N+D)
(-0.5dBFS)
77.2
dB
S/N
(A-weighted)
100.4
dB
Stereo Line Output: DAC  LOUT/ROUT, IVOL=DVOL=0dB, RL=22kΩ
LVCM1-0 bits = “01”, fs=48kHz, BW=20kHz
(0dBFS)
79.6
81.5
dB
S/(N+D)
(-3dBFS)
86.4
88.0
dB
S/N
(A-weighted)
95.9
95.8
dB
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[Plot]
1. ADC (LIN1/RIN1  ADC) (Ceramic Capacitor)
[MGAIN=+18dB]
AK4951EN ADC FFT (-1dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 46. FFT (Input level= -1dBFS)
AK4951EN ADC FFT (-60dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 47. FFT (Input level= -60dBFS)
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AK4951EN ADC FFT (No signal)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 48. FFT (No signal)
AK4951EN ADC THD+N vs Input Level (fin=1kHz)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 49. THD+N vs. Input Level
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AK4951EN ADC THD+N vs Frequency (-1dBFS)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 50. THD+N vs. Input Frequency
AK4951EN ADC Linearity (fin=1kHz)
+0
T T
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 51. Linearity
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AK4951EN ADC Crosstalk (-1dBFS)
-60
TTTTTTTTTT TTTTT T T TT T
T TTTTT TT T T T T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
18k
20k
Hz
Figure 52. Crosstalk
AK4951EN ADC Frequency Response (-1dBFS)
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2k
4k
6k
8k
10k
12k
14k
16k
Hz
Figure 53. Frequency Response
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[MGAIN=0dB]
AK4951EN ADC FFT (-1dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 54. FFT (Input level= -1dBFS)
AK4951EN ADC FFT (-60dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 55. FFT (Input level= -60dBFS)
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AK4951EN ADC FFT (No signal)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 56. FFT (No signal)
AK4951EN ADC THD+N vs Input Level (fin=1kHz)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 57. THD+N vs. Input Level
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AK4951EN ADC THD+N vs Frequency (-1dBFS)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 58. THD+N vs. Input Frequency
AK4951EN ADC Linearity (fin=1kHz)
+0
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 59. Linearity
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AK4951EN ADC Crosstalk (-1dBFS)
-60
TTT
TTTTTTTTTTTT
T TT
T
T TTT
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
18k
20k
Hz
Figure 60. Crosstalk
AK4951EN ADC Frequency Response (-1dBFS)
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2k
4k
6k
8k
10k
12k
14k
16k
Hz
Figure 61. Frequency Response
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2. ADC (LIN3/RIN3  ADC) (Electrolytic Capacitor)
[MGAIN=+18dB]
AK4951EN ADC FFT (-1dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 62. FFT (Input level= -1dBFS)
AK4951EN ADC FFT (-60dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 63. FFT (Input level= -60dBFS)
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AK4951EN ADC FFT (No signal)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 64. FFT (No signal)
AK4951EN ADC THD+N vs Input Level (fin=1kHz)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 65. THD+N vs. Input Level
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AK4951EN ADC THD+N vs Frequency (-1dBFS)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 66. THD+N vs. Input Frequency
AK4951EN ADC Linearity (fin=1kHz)
+0
TT
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 67. Linearity
<KM117404>
2015/11
- 55 -
[AKD4951EN-B]
AK4951EN ADC Crosstalk (-1dBFS)
-60
TTTTTTT
TTTT
TTTTTT
T
TT
T TT TT TTT
TT T T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
18k
20k
Hz
Figure 68. Crosstalk
AK4951EN ADC Frequency Response (-1dBFS)
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2k
4k
6k
8k
10k
12k
14k
16k
Hz
Figure 69. Frequency Response
<KM117404>
2015/11
- 56 -
[AKD4951EN-B]
[MGAIN=0dB]
AK4951EN ADC FFT (-1dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 70. FFT (Input level= -1dBFS)
AK4951EN ADC FFT (-60dBFS)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 71. FFT (Input level= -60dBFS)
<KM117404>
2015/11
- 57 -
[AKD4951EN-B]
AK4951EN ADC FFT (No signal)
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 72. FFT (No signal)
AK4951EN ADC THD+N vs Input Level (fin=1kHz)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 73. THD+N vs. Input Level
<KM117404>
2015/11
- 58 -
[AKD4951EN-B]
AK4951EN ADC THD+N vs Frequency (-1dBFS)
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 74. THD+N vs. Input Frequency
AK4951EN ADC Linearity (fin=1kHz)
+0
TT
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 75. Linearity
<KM117404>
2015/11
- 59 -
[AKD4951EN-B]
AK4951EN ADC Crosstalk (-1dBFS)
-60
TTTTTTT
TTT
TT T T
TT
TT
T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
18k
20k
Hz
Figure 76. Crosstalk
AK4951EN ADC Frequency Response (-1dBFS)
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2k
4k
6k
8k
10k
12k
14k
16k
Hz
Figure 77. Frequency Response
<KM117404>
2015/11
- 60 -
[AKD4951EN-B]
3. DAC (DAC  Headphone (HPL/HPR))
AK4951EN DAC=>HP FFT (0dBFS)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 78. FFT (Input level= 0dBFS)
AK4951EN DAC=>HP FFT (-60dBFS)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 79. FFT (Input level= -60dBFS)
<KM117404>
2015/11
- 61 -
[AKD4951EN-B]
AK4951EN DAC=>HP FFT (No signal)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 80. FFT (No signal)
AK4951EN DAC=>HP Out of band noise
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k 100k
Hz
Figure 81. FFT (Out-of-band Noise)
<KM117404>
2015/11
- 62 -
[AKD4951EN-B]
AK4951EN DAC=>HP THD+N vs Input Level (fin=1kHz)
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 82. THD+N vs. Input Level
AK4951EN DAC=>HP THD+N vs Frequency (0dBFS)
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 83. THD+N vs. Input Frequency
<KM117404>
2015/11
- 63 -
[AKD4951EN-B]
AK4951EN DAC=>HP Linearity (fin=1kHz)
+0
-10
-20
-30
-40
d
B
r
A
-50
-60
-70
-80
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 84. Linearity
AK4951EN DAC=>HP Crosstalk (0dBFS)
-40
-50
-60
-70
d
B
-80
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 85. Crosstalk
<KM117404>
2015/11
- 64 -
[AKD4951EN-B]
AK4951EN DAC=>HP Frequency Response (0dBFS)
+0.5
+0.4
+0.3
+0.2
d
B
r
+0.1
A
-0.1
+0
-0.2
-0.3
-0.4
-0.5
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 86. Frequency Response
<KM117404>
2015/11
- 65 -
[AKD4951EN-B]
4. DAC (DAC  Speaker (SPP/SPN))
AK4951EN DAC=>SPK FFT (-0.5dBFS; SPKG=01)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 87. FFT (Input level= 0dBFS)
AK4951EN DAC=>SPK FFT (-60dBFS; SPKG=01)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 88. FFT (Input level= -60dBFS)
<KM117404>
2015/11
- 66 -
[AKD4951EN-B]
AK4951EN DAC=>SPK FFT (No signal; SPKG=01)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 89. FFT (No signal)
AK4951EN DAC=>SPK Out of band noise (SPKG=01)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k 100k
Hz
Figure 90. FFT (Out-of-band Noise)
<KM117404>
2015/11
- 67 -
[AKD4951EN-B]
AK4951EG
vs Frequency
(-0.5dBFS;SPKG=01)
SPKG=01)
AK4951ENDAC=>SPK
DAC=>SPK THD+N
Frequency
Response
Response (-0.5dBFS;
(-0.5dBFS;
SPKG=01)
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 91. THD+N vs. Input Frequency
AK4951EN DAC=>SPK Linearity (-0.5dBFS; SPKG=01)
+0
-10
-20
-30
-40
d
B
r
A
-50
-60
-70
-80
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 92. Linearity
<KM117404>
2015/11
- 68 -
[AKD4951EN-B]
AK4951EN DAC=>SPK Fequency Response (-0.5dBFS; SPKG=01)
+0
-0.1
-0.2
-0.3
d
B
r
-0.4
A
-0.6
-0.5
-0.7
-0.8
-0.9
-1
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 93. Frequency Response
AK4951EN DAC=>SPK THD+N vs Output Power (fin=1kHz; SPKG=00)
d
B
-40
200m
-45
180m
-50
160m
-55
140m
-60
120m
-65
100m W
-70
80m
-75
60m
-80
40m
-85
20m
-90
-40
0
-35
-30
-25
-20
-15
-10
-5
+0
dBFS
Figure 94. THD+N vs. Output Power (SPKG=00)
<KM117404>
2015/11
- 69 -
[AKD4951EN-B]
AK4951EN DAC=>SPK THD+N vs Output Power (fin=1kHz; SPKG=00)
d
B
-40
300m
-45
275m
-50
250m
-55
225m
-60
200m
-65
175m
-70
150m W
-75
125m
-80
100m
-85
75m
-90
50m
-95
25m
-100
-40
-35
-30
-25
-20
-15
-10
-5
+0
0
dBFS
Figure 95. THD+N vs. Output Power (SPKG=01)
AK4951EN DAC=>SPK THD+N vs Output Power (fin=1kHz; SPKG=10)
d
B
+0
500m
-10
450m
-20
400m
-30
350m
-40
300m
-50
250m W
-60
200m
-70
150m
-80
100m
-90
50m
-100
-40
-35
-30
-25
-20
-15
-10
-5
+0
0
dBFS
Figure 96. THD+N vs. Output Power (SPKG=10)
<KM117404>
2015/11
- 70 -
[AKD4951EN-B]
AK4951EN DAC=>SPK THD+N vs Output Power (fin=1kHz; SPKG=11)
d
B
+0
1.2
-10
1.1
-20
1
-30
.9
-40
800m
-50
700m
-60
600m W
-70
500m
-80
400m
-90
300m
-100
200m
-110
100m
-120
-40
-35
-30
-25
-20
-15
-10
-5
+0
0
dBFS
Figure 97. THD+N vs. Output Power (SPKG=11)
<KM117404>
2015/11
- 71 -
[AKD4951EN-B]
5. DAC (DAC  Line-out (LOUT/ROUT))
AK4951EN DAC=>Line-out FFT (0dBFS; LVCM=01)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 98. FFT (Input level= 0dBFS)
AK4951EN DAC=>Line-out FFT (-3dBFS; LVCM=01)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 99. FFT (Input level= -3dBFS)
<KM117404>
2015/11
- 72 -
[AKD4951EN-B]
AK4951EN DAC=>Line-out FFT (-60dBFS; LVCM=01)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 100. FFT (Input level= -60dBFS)
AK4951EN DAC=>Line-out FFT (Nosignal; LVCM=01)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 101. FFT (No signal)
<KM117404>
2015/11
- 73 -
[AKD4951EN-B]
AK4951EN DAC=>Line-out Out of band noise (LVCM=01)
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k 100k
Hz
Figure 102. FFT (Out-of-band Noise)
AK4951EN DAC=>Line-out THD+N vs Input Level (fin=1kHz; LVCM=01)
-60
-65
-70
-75
-80
d
B
r
A
-85
-90
-95
-100
-105
-110
-115
-120
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 103. THD+N vs. Input Level
<KM117404>
2015/11
- 74 -
[AKD4951EN-B]
AK4951EN DAC=>Line-out THD+N vs Frequency (-3dBFS; LVCM=01)
-60
-65
-70
-75
-80
d
B
r
A
-85
-90
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 104. THD+N vs. Input Frequency
AK4951EN DAC=>Line-out Linearity (fin=1kHz; LVCM=01)
+0
-10
-20
-30
-40
d
B
r
A
-50
-60
-70
-80
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 105. Linearity
<KM117404>
2015/11
- 75 -
[AKD4951EN-B]
AK4951EN DAC=>Line-out Frequency Response (-3dBFS; LVCM=01)
-2.5
-2.6
-2.7
-2.8
d
B
r
-2.9
A
-3.1
-3
-3.2
-3.3
-3.4
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Figure 106. Frequency Response
<KM117404>
2015/11
- 76 -
[AKD4951EN-B]
REVISION HISTORY
Date
(YY/MM/DD)
14/04/15
14/04/28
Manual
Revision
KM117400
KM117401
Board
Revision
0
1
14/08/21
14/09/11
KM117402
KM117403
2
2
15/11/17
KM117404
2
Reason
Page
First edition
Board change
Error
correction
Board change
Description
addition
Change
1
Change
Change
29
1
44-76
26
39
42
Correction
44
Correction
44
Correction
44
Correction
44
44
Correction
<KM117404>
Contents
AK4951EN: Rev.A → Rev.B
EQ1-5 Band width
0.05 ≦ fc/fs → fc/fs < 0.497
AK4951EN: Rev.B → Rev.C
Measurement data were added.
Figure 21 was changed.
Figure 40 [MIC-ADC Setting] Window was
changed.
Figure 45 [MIC-ADC Setting] Window was
changed.
MCKI : 256fs (11.2896MHz, 24.576MHz)
→ 256fs (12.288MHz)
Speaker-Amp: DAC
SPKG=+6.26dB →SPKG=+8.4dB
Speaker-Amp: DAC S/(N+D) (-0.5dBFS):
77.7 → 77.2
Speaker-Amp: DAC S/N : dBV → dB
Stereo Line Output: DAC S/(N+D)(-3dBFS)
(89.4 , 91.0) → (86.4 , 88.0)
2015/11
- 77 -
[AKD4951EN-B]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this document.
You are fully responsible for use of such information contained in this document in your product design or
applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD
PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR
APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life,
bodily injury, serious property damage or serious public impact, including but not limited to, equipment used
in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for
automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control
combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by
AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in this
document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not be
used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or extend
in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
<KM117404>
2015/11
- 78 -
3
2
J2 HP-OUT
J3 LINE-OUT
1
2
4
3
5
USBGND USB5V
1
T1
R1 0
SVDD
D
R15
22k
C24
1u
TP1
SPP
TP2
SPN
2.2u
VSS3
C
MRF
SDA
+
J1
MIC-IN
2
1
LIN3
LIN2
LIN1
VSS1
C17 C16
open 1u
JP1
LIN-SEL
C14
1u
C12
1u
C15
open
R7
2.2k
VSS1
R6
2.2k
VSS1
C13
open
A
VSS1
C10
1u
R5
2.2k
R4
2.2k
VSS2
C
TVDD
R14
51
15
MCKI
R13
51
14
BICK
R12
51
13
LRCK
R11
51
12
SDTO
R10
51
11
SDTI
1
R9
1k
10
TP3
SDA
SDA
1
R8
1k
9
TP4
SCL
B
SCL
PDN
MPWR2
4
JP9
MP-RIN2
RIN3
RIN2
RIN1
3
1
JP2
RIN-SEL
LIN2
RIN2
C18
1u
SCL
C20
10u
16
8
RIN3
VSS1
3
+
SDTI
LIN3
C19
open
32
VCOM
LIN1/DMDAT
+
B
SDTO
7
31
VSS1
DMDT
VSS1
C35
2.2u
LRCK
U1
AK4951EN
JP4
C34
2.2u
30
AVDD
RIN1/DMCLK
C33
0.1u
29
6
+
BICK
2
C32
10u
CN
DMCK
28
AVDD
C21
0.1u
MCKI/OVF
MPWR1
C31
2.2u
27
CP
5
open
26
VSS3
TVDD
JP8
MP-LIN2
VSS2
R20
C23
0.1u
VSS2
JP7
MP-RIN1
25
C22
10u
VSS3
open
C30
C25
1u
SVDD
17
R19
21
C7
100u
DVDD
10u
C27
0.1u
+
HPL
VSS1
C26
10u
D3V
22
GND
2
23
C6
0.1u
TK73633AME
+
L1
HPR
1
DVDD
24
C5
0.1u
1
VSS1
TVDD
VEE
GND1
NC GND
VcontPCL
Vin Vout
NC
NC
4
3
2
1
SPP/LOUT
R3 5.1
T2
5
6
7
8
20
AVDD
R16
22k
18
R17
33
SVDD
C28
0.22u
R18
33
19
R2 0
C29
0.22u
SPN/ROUT
SVDD
JP5
1.8V
5V
3.3V
1
VSS2
JP6
MP-LIN1
JP3
D
3
R33 open
1
TK73618AME
+
C4
100u
2
1
DVDD
C3
0.1u
+
+
C1 C2
100u 0.1u
4
3
2
1
+
VDD
NC GND
VcontPCL
Vin Vout
NC
NC
+
5
6
7
8
1
REG1
PDN
C8
1u
C9
open
A
VSS1
C11
open
VSS1
Title
AKD4951EN-B
Size
5
4
- 79 3
A3
Date:
2
Document Number
Rev
0
AK4951EN
Monday, March 17, 2014
Sheet
1
1
of
3
5
4
3
2
1
PORT2
JP11
MCKI
MCKI
C38
0.1u
DIR
2
3
EXT
SDTI
ADC
26
VCC
IN
D
13
C40
0.1u
TVDD
14
NC/GP1
15
TX0/GP2
16
TX1/GP3
17
BOUT/GP4
18
COUT/GP5
SDTO
19
20
DVDD
VOUT/GP7
21
22
23
C42
0.1u
UOUT/GP6
JP10
SDTI-SEL
EXT
DIR
BICK
25
DIR
DIR
VSS2
JP13
SDTI
24
EXT
GND
OPT-OUT
C39
10u
+
DIR
+
LRCK
C41
10u
MCKO1
JP12
LRCK
LRCK
VIN/GP0
BICK
XTL1
MCKO2
XTL0
DAUX
P/SN
12
11
EXT
27
28
OCKS0/CSN/CAD0
NC
R22
10k
1
H
3
L
C48
0.1u
6
S1
SW DIP-4
H (ON)
L(OFF)
OCKS1
DIF0
DIF1
DIF2
8
7
6
5
5
4
3
2
RP1
47k
B
RX3
1
48
VSS4
47
46
45
VSS3
7
C47
0.47u
C45 0.1u
+
2
SW1
RESET
RX2
IPS0/RX4
TEST1
INT0
41
R24
10k
8
1
2
3
4
DIF0/RX5
37
A
D1
HSU119
OCKS1/CCLK/SCL
INT1
K
36
TEST2
VCOM
B
CM1/CDTI/SDA
40
35
DIF1/RX6
R
34
CM0/CDTO/CAD1
39
33
VSS1
AVDD
32
DIF2/RX7
PDN
38
31
PDN
IPS1/IIC
U2
AK4118A
XTI
RX1
1
30
C44 5p
USB-PDN
9
1
2
3
4
XTO
C43 5p
R23 2.2k
10
C
29
44
2
C
X1
12.288MHz
NC
JP15
SDTO
43
SDTO
RX0
JP14
BICK
42
D
1
D3V
C46
10u
R21 470
C36
0.1u
PORT1
1
2
3
OUT
GND
VCC
OPT-IN
A
A
Title
AKD4951EN-B
Size
A3
- 80 5
4
3
Date:
2
Document Number
Rev
0
DIR/DIT
Monday, March 17, 2014
Sheet
1
2
of
3
5
4
3
2
1
5
4
3
2
1
GND
ID
D+
DVBUS
PORT3
USB Connector
T3
5
6
7
8
JP17
USB5V
USB5V
D
NC GND
VcontPCL
Vin Vout
NC
NC
4
3
2
1
C50 C51
0.1u 10u
D
+
C49
1u
TK73633AME
USBGND
C
2
RD4/SPP4
3
4
5
7
1
2
A
SCL
3
SDA
4
EN
VREF1 VREF2
RE1/AN6/CK2SPP
RB1/AN10/INT1/SCK/SCL
RE0/AN5/CK1SPP
SCL1
SCL2
SDA1
SDA2
R29
1k
C59 22p
31
XTO
30
XTI
X2
20MHz
C58 22p
29
C57
0.1u
28
C56
10u
27
26
B
25
24
RA3/AN3/Vref+
23
R30
51
22
RA2/AN2/Vref-/CVref
RA1/AN1
20
19
RA4/T0CKI/C1OUT/RCV
32
R26
100k
C55
0.1u
VDD
1
MCLR
2
PGD
3
PGC
4
GND
5
JP16 PIC
6
RA0/AN0
MCLR_N/Vpp/RE3
18
RB7/KBI3/PGD
17
RB6/KBI2/PGC
RB5/KBI1/PGM
R25 4.7k
16
14
NC/ICCK/ICPGC
12
15
RB4/AN11/KBI0/CSSPP
RA5/AN4/SS_N/HLVDIN/C2OUT
8
7
34
RB0/AN12/INT0/FLT0/SDI/SDA
RB3/AN9/CPP2/VPO
R27
100k
R28
1k
VDD1
RE2/AN7/OESPP
PCA9306DP1
GND
NC/ICPORTS
U3
PIC18F4550
RB2/AN8/INT2/VMO
11
C54
0.1u
VSS1
21
10
U4
OSC1/CLKI
NC/ICDT/ICPGD
+
9
C60 0.1u
RD6/SPP6/P1C
VDD0
8
B
OSC2/CLKO/RA6
VSS0
33
C
RC0/T1OSO/T13CKI
RD5/SPP5/P1B
13
C53
0.1u
NC/ICRST_N/ICVpp
RD7/SPP7/P1D
6
C52
10u
35
36
RC7/RX/DT/SDO
RC1/T1OSI/CCP2/UOE_N
VUSB
RC2/CCP1/P1A
37
38
RD0/SPP0
39
RD1/SPP1
40
RD2/SPP2
41
RD3/SPP3
42
RC4/D-/VM
RC5/D+/VP
43
44
RC6/TX/CK
1
C65
0.47u
R31
0
+
R32
0
A
5
Title
AKD4951EN-B
USB-PDN
Size
A3
- 81 5
4
3
Date:
2
Document Number
Rev
0
Control I/F (USB)
Monday, March 17, 2014
Sheet
1
3
of
3
- 82 -
- 83 -
- 84 -
- 85 -