AK5384VF

ASAHI KASEI
[AKD5384]
AKD5384
AK5384 Evaluation Board Rev.A
GENERAL DESCRIPTION
AKD5384 is an evaluation board for the digital audio 24bit 96kHz 4ch A/D converter, AK5384. The
AKD5384 includes the input circuit and also has a digital interface transmitter. Further, the AKD5384 can
achieve the interface with digital audio systems via opt-connector.
„ Ordering guide
AKD5384
---
AK5384 Evaluation Board
FUNCTION
• DIT with optical output
• BNC connector for an external clock input
AVDD,DVDD
AGND,DGND
TVDD
Opt
Out
LIN1/2
RIN1/2
Input
Buffer
AK5384
Clock
Generator
AK4101
(DIT)
Opt
Out
DSP Data
10pin Header
Figure 1. AKD5384 Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM070101>
2005/10
-1-
ASAHI KASEI
[AKD5384]
„ Operation sequence
1) Set up the power supplies lines.
[AVDD] (red)
= 4.75 ∼ 5.25V
[DVDD] (red)
= 4.75 ∼ 5.25V
[TVDD] (orange) = 3.0 ∼ 5.25V
[+15V]
(green)
= +15V
[−15V]
(blue)
= −15V
[VCC]
(red)
= 5V
[AGND] (black)
= 0V
[DGND] (black)
= 0V
: for AVDD of AK5384 (typ. 5.0V)
: for DVDD of AK5384 (typ. 5.0V)
: for TVDD of AK5384 (typ. 5.0V)
: for Op-amp
: for Op-amp
: for logic
: for analog ground
: for logic ground
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK5384 and AK4101 should be reset once bringing SW1 = “L” upon power-up.
Note: When the AK5384 is TDM mode, the AK4101 does not support TDM mode. So, PORT1 (DIT1)
and PORT2 (DIT2) are not used. PORT3 (DSP) should be used.
„ Evaluation mode
(1) Slave Mode
(1-1) A/D evaluation using DIT function of AK4101
PORT1 (DIT1) and PORT2 (DIT2) are used. DIT generates audio bi-phase signal from received data and which
is output through optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation
boards on the digital-amplifier, which equips DIR input. Nothing should be connected to PORT3 (DSP). In case
of using external clock through a BNC connector (J5), select EXT on JP8 (CLK) and short JP5 (XTE) and open
JP10 (EXT).
JP3
BICK
JP4
JP5
JP8
JP10
LRCK
XTE
CLK
EXT
XTL
EXT
(1-2) Feeding all clocks from PORT3 (DSP)
Under the following set-up, all external clocks (MCLK, BICK, LRCK) can be fed through PORT3 (DSP). The
A/D converted data is output from SDTO1/SDTO2 of PORT3 (DSP). Also, the A/D converted data is output
through optical connector (TOTX176).
JP3
BICK
JP4
JP5
JP8
JP10
LRCK
XTE
CLK
EXT
XTL
<KM070101>
EXT
2005/10
-2-
ASAHI KASEI
[AKD5384]
(2) Master Mode
(2-1) A/D evaluation using DIT function of AK4101
PORT1 (DIT1) and PORT2 (DIT2) are used. DIT generates audio bi-phase signal from received data and which
is output through optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation
boards on the digital-amplifier, which equips DIR input. Nothing should be connected to PORT3 (DSP). In case
of using external clock through a BNC connector (J5), select EXT on JP8 (CLK) and short JP5 (XTE) and open
JP10 (EXT).
JP3
BICK
JP4
JP5
JP8
JP10
LRCK
XTE
CLK
EXT
XTL
EXT
„ Other jumper pins set up
1. JP1 (GND) : Analog ground and Digital ground
OPEN : Separated.
SHORT : Common. (The connector “DGND” can be open.) <Default>
2. JP2 (AVDD) : Select AVDD for AK5384
AVDD : Supply from AVDD connector <Default>
REG : Supply from regulator. AVDD connector should be supplied +15V.
3. JP6 (BCFS) : Select BICK frequency
64 : In case of MCLK=256fs/512fs/768fs <Default>
128 : In case of MCLK=384fs or BICK frequency of TDM128 mode
256 : BICK frequency of TDM256 mode
4. JP7 (MCLK) : Supply MCLK frequency for 74HC4040
256 : In case of MCLK=256fs
512 : In case of MCLK=512fs <Default>
384/768 : In case of MCLK=384fs/768fs
5. JP9 (LRFS) : Select LRCK frequency
256 : In case of MCLK=256fs/512fs/768fs <Default>
384 : In case of MCLK=384fs
<KM070101>
2005/10
-3-
ASAHI KASEI
[AKD5384]
„ Clock Setting
Mode
fs
8kHz
32kHz
Normal
44.1kHz
48kHz
88.2kHz
96kHz
TDM256
8kHz
32kHz
44.1kHz
48kHz
8kHz
32kHz
TDM128
44.1kHz
48kHz
88.2kHz
96kHz
MCLK
JP6(BCFS) JP7(MCLK)
256fs = 2.048MHz
64
256
384fs = 3.072MHz
128
384/768
512fs = 4.096MHz
64
512
768fs = 6.144MHz
64
384/768
256fs = 8.192MHz
64
256
384fs = 12.288MHz
128
384/768
512fs = 16.384MHz
64
512
768fs = 24.576MHz
64
384/768
256fs = 11.2896MHz
64
256
384fs = 16.9344MHz
128
384/768
512fs = 22.5792MHz
64
512
768fs = 33.8688MHz
64
384/768
256fs = 12.288MHz
64
256
384fs = 18.432MHz
128
384/768
512fs = 24.576MHz
64
512
768fs = 36.864MHz
64
384/768
256fs = 22.5792MHz
64
256
384fs = 33.8688MHz
128
384/768
256fs = 24.576MHz
64
256
384fs = 36.864MHz
128
384/768
512fs = 4.096MHz
256
512
512fs = 16.384MHz
256
512
512fs = 22.5792MHz
256
512
512fs = 24.576MHz
256
512
256fs = 2.048MHz
128
256
512fs = 4.096MHz
128
512
256fs = 8.192MHz
128
256
512fs = 16.384MHz
128
512
256fs = 11.2896MHz
128
256
512fs = 22.5792MHz
128
512
256fs = 12.288MHz
128
256
512fs = 24.576MHz
128
512
256fs = 22.5792MHz
128
256
256fs = 24.576MHz
128
256
Table 1. Clock Setting
<KM070101>
JP9(LRFS)
256
384
256
256
256
384
256
256
256
384
256
256
256
384
256
256
256
384
256
384
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Default
2005/10
-4-
ASAHI KASEI
[AKD5384]
„ DIP Switch set up
[SW2] (MODE): Setting the evaluation mode for AK5384 and AK4101
ON is “H”, OFF is “L”.
No.
1
2
3
4
5
6
7
Name
DIF
TDM1
TDM0
M/S
CKS
CKS1
CKS0
OFF (“L”)
MSB justified
ON (“H”)
I2S Compatible
See Table 3
Slave mode
MCLK = 256fs
Master mode
MCLK = 512fs
See Table 4
Default
OFF (“L”)
OFF (“L”)
OFF (“L”)
OFF (“L”)
ON (“H”)
ON (“H”)
OFF (“L”)
Table 2. Mode Setting
TDM1
L
L
H
H
Mode
0
1
2
3
TDM0
Mode
BICK
L
Normal
48 ∼ 128fs
H
TDM256
256fs
L
N/A
N/A
H
TDM128
128fs
Table 3. Mode Setting of AK5384
Default
CKS1
CKS0
MCLK
fs
L
L
256fs
∼ 96kHz
L
H
N/A
N/A
H
L
512fs
∼ 48kHz
H
H
384fs
∼ 48kHz
Table 4. MCLK Frequency Setting of AK4101
Default
Note: AK4101 does not support MCLK=768fs.
„ The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Resets the AK5384 and AK4101. Keep “H” during normal operation.
<KM070101>
2005/10
-5-
ASAHI KASEI
[AKD5384]
„ Input Circuit
Analog signal is input to LIN1-2/RIN1-2 pins via J1 ∼ J4 connectors.
R11, R18, R25 and R32 should be changed depending on the output impedance of signal source.
R6
4.7k
R7
5.1k
OP_AMP1-
3
R12
330
+
C28
10u
R13
4.7k
R14
5.1k
OP_AMP1-
U3A
NJM5532
2
3
R19
330
R18
560
OP_AMP1+
OP_AMP1+
C31
10u
+
RIN1-
+
4
1
J2
RIN1
C29
22u
8
5
R15
10k
8
+
6
+
U3B
NJM5532
-
7
+
C30
10u
R16
4.7k
-
R17
330
RIN1+
4
OP_AMP1-
R20
4.7k
R21
5.1k
OP_AMP1-
3
R26
330
R25
560
OP_AMP1+
OP_AMP1+
C43
10u
+
LIN2-
+
4
1
U4A
NJM5532
J3
LIN2
C32
22u
8
5
R22
10k
8
+
6
+
U4B
NJM5532
-
7
2
+
LIN2+
C33
10u
R23
4.7k
-
R24
330
4
OP_AMP1-
R27
4.7k
R28
5.1k
OP_AMP12
3
J4
RIN2
C44
22u
+
4
U5A
NJM5532
R32
560
OP_AMP1+
OP_AMP1+
C46
10u
+
R33
330
1
8
5
R29
10k
8
+
6
+
U5B
NJM5532
-
7
+
C45
10u
R30
4.7k
-
R31
330
RIN2+
4
OP_AMP1-
RIN2-
R11
560
OP_AMP1+
OP_AMP1+
LIN1-
+
4
1
U2A
NJM5532
J1
LIN1
C17
22u
8
5
R8
10k
8
+
6
+
U2B
NJM5532
-
7
2
+
LIN1+
C18
10u
R9
4.7k
-
R10
330
4
OP_AMP1-
Figure 2. LIN1-2/RIN1-2 Input circuits
* AKM assumes no responsibility for the trouble when using the circuit examples.
<KM070101>
2005/10
-6-
ASAHI KASEI
[AKD5384]
MEASUREMENT RESULTS
[Measurement condition]
• Measurement unit
• MCLK
• BICK
• fs
• Bit
• Power Supply
• Interface
• Temperature
: Audio Precision, System Two Cascade
: 256fs
: 64fs
: 48kHz, 96kHz
: 24bit
: AVDD = DVDD = TVDD = 5.0V
: DIT
: Room
[Measurement Results]
Parameter
ADC Analog Input Characteristics
S/(N+D)
(fs=48kHz, −1dBFS)
(fs=96kHz, −1dBFS)
D-Range
(fs=48kHz, −60dBFS, A-weighted)
(fs=96kHz, −60dBFS)
S/N
(fs=48kHz, A-weighted)
(fs=96kHz)
Interchannel Isolation
<KM070101>
Result
LIN1 / RIN1
LIN2 / RIN2
Unit
100.8 / 100.7
96.4 / 95.1
101.3 / 101.2
95.4 / 94.4
dB
dB
107.6 / 107.5
102.4 / 102.4
107.6 / 107.4
102.4 / 102.4
dB
dB
107.6 / 107.5
102.4 / 102.4
119.5 / 122.4
107.6 / 107.4
102.4 / 102.4
120.5 / 124.0
dB
dB
dB
2005/10
-7-
ASAHI KASEI
[AKD5384]
[ADC Plot : fs=48kHz]
AKM
AK5384 THD+N vs. Input Level
AVDD=DVDD=TVDD=5.0V, fs=48kHz, fin=1kHz
-90
-91
-92
-93
-94
-95
-96
-97
-98
d
B
F
S
-99
-100
-101
-102
-103
-104
-105
-106
-107
-108
-109
-110
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 1. THD+N vs. Input Level
AKM
AK5384 THD+N vs. Input Frequency
AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-1.0dBr
-90
-91
-92
-93
-94
-95
-96
-97
-98
d
B
F
S
-99
-100
-101
-102
-103
-104
-105
-106
-107
-108
-109
-110
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 2. THD+N vs. Input Frequency
<KM070101>
2005/10
-8-
ASAHI KASEI
[AKD5384]
AKM
AK5384 Linearity
AVDD=DVDD=TVDD=5.0V, fs=48kHz, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 3. Linearity
AKM
AK5384 Frequency Response
AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-1.0dBr
-0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 4. Frequency Response
<KM070101>
2005/10
-9-
ASAHI KASEI
[AKD5384]
AKM
AK5384 Crosstalk
AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-1.0dBr
-80
-85
-90
-95
-100
-105
-110
-115
d
B
-120
-125
-130
-135
-140
-145
-150
-155
-160
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 5. Crosstalk
AKM
AK5384 FFT Plot
AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-1.0dBr, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 6. FFT Plot
<KM070101>
2005/10
- 10 -
ASAHI KASEI
[AKD5384]
AKM
AK5384 FFT Plot
AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-60dBr, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 7. FFT Plot
AKM
AK5384 FFT Plot
AVDD=DVDD=TVDD=5.0V, fs=48kHz, fin=None
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 8. FFT Plot
<KM070101>
2005/10
- 11 -
ASAHI KASEI
[AKD5384]
[ADC Plot : fs=96kHz]
AKM
AK5384 THD+N vs. Input Level
AVDD=DVDD=TVDD=5.0V, fs=96kHz, fin=1kHz
-90
-91
-92
-93
-94
-95
-96
-97
-98
d
B
F
S
-99
-100
-101
-102
-103
-104
-105
-106
-107
-108
-109
-110
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 9. THD+N vs. Input Level
AKM
AK5384 THD+N vs. Input Frequency
AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-1.0dBr
-90
-91
-92
-93
-94
-95
-96
-97
-98
d
B
F
S
-99
-100
-101
-102
-103
-104
-105
-106
-107
-108
-109
-110
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 10. THD+N vs. Input Frequency
<KM070101>
2005/10
- 12 -
ASAHI KASEI
[AKD5384]
AKM
AK5384 Linearity
AVDD=DVDD=TVDD=5.0V, fs=96kHz, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 11. Linearity
AKM
AK5384 Frequency Response
AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-1.0dBr
-0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 12. Frequency Response
<KM070101>
2005/10
- 13 -
ASAHI KASEI
[AKD5384]
AKM
AK5384 Crosstalk
AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-1.0dBr
-80
-85
-90
-95
-100
-105
-110
-115
d
B
-120
-125
-130
-135
-140
-145
-150
-155
-160
20
50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 13. Crosstalk
AKM
AK5384 FFT Plot
AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-1.0dBr, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 14. FFT Plot
<KM070101>
2005/10
- 14 -
ASAHI KASEI
[AKD5384]
AKM
AK5384 FFT Plot
AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-60dBr, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 15. FFT Plot
AKM
AK5384 FFT Plot
AVDD=DVDD=TVDD=5.0V, fs=96kHz, fin=None
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 16. FFT Plot
<KM070101>
2005/10
- 15 -
ASAHI KASEI
[AKD5384]
Revision History
Date
(YY/MM/DD)
Manual
Revision
Board
Revision
Reason
02/11/01
05/10/17
KM070100
KM070101
0
1
First edition
Circuit Change
Contents
Condenser: Capacitance Value Change:
C57,C58: open Æ 5p
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or
use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or
other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with
the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any
and all claims arising from the use of said product in the absence of such notification.
<KM070101>
2005/10
- 16 -
A
B
C
D
E
E
E
JP1
GND
DGND
CN1
LIN2+
+15V
LIN1+
28
28
LIN1+
27
LIN1-
26
RIN1+
C2
1.5n
2
2
3
3
LIN2-
LIN1-
27
RIN1+
26
D
4
RIN2-
RIN1-
25
25
RIN1-
5
5
TEST
M/S
24
24
M/S
VCOM
CKS
23
CKS
6
1
AVSS
PDN
AVDD
DVSS
22
21
2
DIF
9
DIF
DVDD
+ C11
47u
21
C13
10u
20
1
9
2
TDM1
10
TDM0
11
12
R3
MCLK
10
11
12
TDM1
TVDD
TDM0
SDTO1
TDMIN
SDTO2
19
18
17
TVDD
L3
(short)
13
MCLK
BICK
16
14
OVF
LRCK
15
R1
51
R2
51
R4
51
R5
51
2
+ C16
47u
SDTO1
18
SDTO2
17
5384_SBICK
JP3
BICK
BICK
16
B
14
1
19
51
13
C
20
C15
0.1u
+ C14
47u
2
1
8
C12
0.1u
AVDD
1
PDN
22
C10
0.1u
2
8
+
JP2
AVDD
L2
(short)
DVDD
L1
(short)
7
7
C9
10u
23
+ C8
0.1u
1
C7
2.2u
REG
C6
1.5n
4
6
AVDD
RIN2+
C5
1.5n
2
RIN2+
C4
0.1u
2
GND
LIN2+
1
IN
RIN2-
C
CN2
+
C3
0.1u
1
1
LIN2-
D
OUT
U1
C1
1.5n
T1
NJM78M05FA
3
AGND
B
15
5384_SLRCK
TEST1
OVF
JP4
LRCK
AK5384
LRCK
A
A
Title
Size
A3
Date:
A
B
C
D
AKD5384
Document Number
Rev
AK5384
Monday, October 17, 2005
Sheet
E
A
1
of
4
A
B
C
D
R6
4.7k
R7
5.1k
E
OP_AMP1OP_AMP1-
3
+
4
U2A
NJM5532
2
R11
560
8
4
5
1
E
J1
LIN1
C17
22u
8
+
U2B
NJM5532
6
+
7
-
C18
10u
R8
10k
+
R9
4.7k
-
R10
330
LIN1+
E
OP_AMP1+
OP_AMP1+
-15V
for NJM5532
OP_AMP1+
+
+
LIN1R13
4.7k
D
C20 C21 C22 C23 C24 C25 C26 C27
10u 0.1u 10u 0.1u 10u 0.1u 10u 0.1u
R14
5.1k
D
OP_AMP1OP_AMP1-
3
+
4
1
U3A
NJM5532
R18
560
8
4
5
J2
RIN1
C29
22u
8
+
6
+
U3B
NJM5532
-
7
RIN1+
R15
10k
2
+
C30
10u
-
R17
330
R16
4.7k
+
C19
47u
+
C28
10u
+
R12
330
OP_AMP1+
OP_AMP1+
R19
330
C31
10u
RIN1-
C
+
C
R20
4.7k
R21
5.1k
OP_AMP1-
OP_AMP1-
3
+
4
1
U4A
NJM5532
R25
560
8
4
5
J3
LIN2
C32
22u
8
+
6
+
U4B
NJM5532
-
7
LIN2+
R22
10k
2
+
C33
10u
-
R24
330
R23
4.7k
OP_AMP1+
OP_AMP1+
+15V
for NJM5532
OP_AMP1+
B
R26
330
C43
10u
C34
47u
+
LIN2R27
4.7k
OP_AMP1-
3
+
B
+
J4
RIN2
C44
22u
+
4
U5A
NJM5532
2
R32
560
8
4
5
1
+
8
+
6
+
U5B
NJM5532
-
7
+
C45
10u
R29
10k
-
R31
330
RIN2+
R30
4.7k
+
C35 C36 C37 C38 C39 C40 C41 C42
10u 0.1u 10u 0.1u 10u 0.1u 10u 0.1u
R28
5.1k
OP_AMP1-
+
OP_AMP1+
OP_AMP1+
A
R33
330
C46
10u
Title
+
A
Size
RIN2-
A3
Date:
A
B
C
D
AKD5384
Document Number
Rev
INPUT
Monday, October 17, 2005
A
Sheet
E
2
of
4
A
B
C
D
E
VCC
1
2
VCC
D1
HSU119
R34
10k
U6A
E
1
U6B
2
3
74HC14
PDN
C47
10u
H
2
1
1
+
3
L
E
4
74HC14
C48
0.1u
C49
0.1u
2
SW1
PDN
1
G1
VCC
20
DIF0
34
35
VDD
36
DIF1
37
DIF2
38
U1
39
U2
40
U3
41
U4
42
V12
43
V34
VCC
TRANS
U8
44
DIF
U7
PORT1
1
PDN
TXP1
33
2
MCLK
TXN1
32
SDTI1
TXP2
31
SDTI2
TXN2
30
SDTI3
VSS
4
3
2
1
C50
0.1u
D
19
SDTO1
2
SDTO2
3
BICK
4
LRCK
5
G2
GND
10
A1
Y1
18
3
A2
Y2
17
4
A3
Y3
16
5
A4
Y4
A5
Y5
MCLK
C51
0.1u
R35
1k
IN
VCC
IF
GND
5
5
6
6
D
DIT1
VCC
PORT2
BICK
TXP4
LRCK
TXN4
FS0
CKS1
2
C54
10u
5
6
6
1
DIT2
27
26
25
24
VSS
23
22
CKS0
21
BLS
20
ANS
19
C4
FS1
12
18
11
74ACT541
C3
10
17
11
C2
9
16
12
C1
Y8
TXN3
15
A8
VSS
FS3
Y7
TXP3
28
R36
1k
5
C
8
2
A7
13
VDD
14
9
Y6
VDD
C52
0.1u
IN
VCC
IF
GND
C55 C56
10u 0.1u
FS2
8
A6
C53
0.1u
AK4101
SDTI4
13
+
C
7
7
1
14
6
29
+
6
VCC
15
4
3
2
1
B
B
PORT3
MCLK
MCLK
BICK
LRCK
SDTO1
SDTO2
1
2
3
4
5
VCC
10
9
8
7
6
DIF
TDM1
TDM0
M/S
CKS
CKS1
CKS0
DSP
SW2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
MODE
RP1
6
5
4
3
2
1
A
DIF
TDM1
TDM0
M/S
CKS
A
Title
47k
Size
A3
Date:
A
B
C
D
AKD5384
Document Number
Rev
DIT
Monday, October 17, 2005
A
Sheet
E
3
of
4
A
B
C
D
E
E
E
X1
24.576MHz
MCLK
R37
VCC
1M
256
U9B
2
3
74HCU04
4
74HCU04
4
U9A
1
XTL
2
C58
5p
JP8
CLK
D
3
D
JP7
256
512
384/768
5
Q
CLK
256fs 10
CLK
11
RST
6
Q
1
EXT
U10
MCLK
CL
C57
5p
U11A
74AC74
PR
JP5
XTE
J5
EXT
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
9
7
6
5
3
2
4
13
12
14
15
1
JP6
BCFS
128
64
384
64fs
JP9
LRFS
D
fs
256
74HC4040
R38
51
VCC
U12
VCC
U13
JP10
EXT
3
4
5
6
7
10
2
9
1
C
A
B
C
D
14
13
12
11
15
QA
QB
QC
QD
RCO
20
VCC
DIR
GND
G
1
M/S
C59
0.1u
10
ENP
ENT
CLK
LOAD
CLR
18
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
B8
A8
19
2
C
74AC163
17
6
3
RP2
5
RP3
6
5
4
3
2
1
U6C
74HC14
16
15
6
5
4
3
2
1
4
5
47k
47k
14
13
6
7
U9C
VCC
8
5
B
12
6
C63
0.1u
C64
0.1u
U9D
C65
0.1u
11
9
11
8
10
C62
0.1u
74HCU04
U6E
74HC14
12
D
U9E
12
13
11
10
11
5384_SLRCK
9
5384_SBICK
9
Q
8
74ACT245
13
U9F
13
Q
CLK
74HCU04
U6F
74HC14
U11B
74AC74
PR
C61
0.1u
+
8
74HCU04
U6D
74HC14
10
C60
47u
9
VCC
for 74HC14, 74HCU04, 74HC4040, 74AC74
74AC163
CL
B
12
74HCU04
A
A
Title
Size
A3
Date:
A
B
C
D
AKD5384
Document Number
Rev
LOGIC
Monday, October 17, 2005
A
Sheet
E
4
of
4
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