AK7601AVQ

ASAHI KASEI
[AKD7601A-A]
AKD7601A-A
AK7601AVQ Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD7601A-A is an evaluation board for AK7601AVQ,which is a highly integrated audio processor
including a stereo ADC, three stereo DAC and digital function(equalizers, digital filters, delay, etc). It is
possible to control the setting of the board via an USB port. RCA connectors are used for inputs and
outputs of analog signals. This board also has a digital interface and can achieve the interface with a
digital audio system through an optical connector.
 Ordering guide
AKD7601A-A
---
Evaluation board for AK7601AVQ
USB cable and control software are packed with this board
FUNCTION
 Read/Write access to control registers of AK7601AVQ
 Digital audio interface： Optical output (x1) ,Optical input (x1) ,
External output (x1), External input (x1)
 ADC 8ch input, DAC 6ch output
 USB port for the board control
DVDD
+12V
AVDD AGND
REG(5v)
REG(5v)
REG(3.3v)
MONOIN
SDTO1/SDTO3
AIN-L1/ L2
SDTO2
AIN-R1/ R2
SDTI4
PIC18
USB
AK4118
AIN-L3/ L4
OBICK
OLRCK
F4550
AIN-R3/ R4
MCKO
AK7601A
U8
AK4118
PORT1
DIN(OPT)
MCKO
SDTI
PORT3
DOUT(DSP)
IBICK2
ILRCK2
SDTI2
U9
IBICK3
ILRCK3
SDTI3
AOUT-R1
AOUT-L2
AOUT-R2
AOUT-L3
XTI
PORT2
DOUT(OPT)
BICK
LRCK
U3
XTO
SDTO
AOUT-L1
IBICK1
ILRCK1
SDTI1
AOUT-R3
BICK
LRCK
SDTI
PORT4
DIN(DSP)
X’tal
EXT-Clock
figure 1.AKD7601A-A Block Diagram
KM110900
2012/ 04
- 1 -
ASAHI KASEI
[AKD7601A-A]
Board Diagram
Board Diagram
USB
U6
PORT1
PORT2
AK4118A
U2
AK4118A
U4
LE1(PDN)
REG2
PIC18
F4550
U5
JP24
PORT3
(IIS-out)
()
JP22
PORT4
(IIS-out)
REG3
LE2(DZF)
SW1
DGND
DGND
AGND
+12V
X101
AGND
AK7601A
U1
AOUT3
REG1
DVDD
AVDD
AOUT2
MONO
AIN(D)
AIN(S)
AOUT1
figure 2. Block Diagram
 Description
(1) MONO/AIN(D)/AIN(S)/AOUT1/AOUT2/AOUT3（Analog Data）
RCA Jack. The white jacks are used for left channels and the red ones are for right channels.
(2) PORT1/PORT4（Digital Data）
PORT1：Optical input connector
PORT4：IIS input connector
(3) PORT2/PORT3（Digital Data）
PORT2：Optical output connector
PORT3：IIS output connector
(4) U2/U4(AK4118A)
U2：AK4118A outputs digital data to AK7601A as DIR.
U4：AK4118A inputs digital data of AK7601A as DIT.
KM110900
2012/ 04
- 2 -
ASAHI KASEI
[AKD7601A-A]
(5) Power supply （+12V、DVDD、AVDD、AGND、and DGND）
The AK7601A can be powered by external power supply or via Regulator (REG1) on the evaluation board. When
using regulator (REG1) on the evaluation board, Short JP29 and JP26, open DVDD and AVDD, and connect to 12V,
AGND and DGND (Default), when powered by external power supply directly, connect to DVDD and AVDD as well
as 12V, AGND and DGND. JP29、JP26 must be open.
(6) AK7601A (U101)
This device is a CODEC (3ch ADC, 6ch DAC) with a delay line memory and digital filters such as EQ. It operates
in master mode and the internal sampling rate is 44.1 kHz.
(7) PIC18F4550(U5)
USB control chip. It is possible to set up the registers of AK7601A and AK4118A from PC via the USB port.
(8) SW1(Switch)
Push type button. It is used to mute the AK7601A..
(9) Other setting of JP
Refer to the JP setting.
(10) LE1(PDN)/LE2(DZF)
LE1：This is the sign of output for PDN pin.
Hi：Turn off
Lo：Turn on
LE2：This is the sign of output for DZF pin.
Hi：Turn on
Lo：Turn off
(11) USB PORT(U6)
A computer can control AK7601A and AK4118A on this board by the AK7601A control software through this USB
port.
KM110900
2012/ 04
- 3 -
ASAHI KASEI
[AKD7601A-A]
Evaluation Board Manual
 Operation sequence
(1) Set up Power Supplies (The power should be separated from the source of a power supplier.)
Name of
Color of
Voltage
Used for
Comment and attention
connector
connector
Make sure to be connected by +12V power
supplier. This connector is used when AVDD and
DVDD of AK7601A are supplied from regulator
Regulator REG1
REG1 and when D3.3V, D5V for logic circuit on
Regulator REG2
+12V
Red
+12V
the evaluation board around AK7601A are
Regulator REG3
supplied from regulator REG2 and REG3. In this
case JP26 and JP29 should be SHORT. The
connector for DVDD(J5) and the connector for
AVDD(J1) should be OPEN(Default).
This connector is used when AVDD of AK7601A
AVDD of
AVDD
Yellow
+5V
is power supplied without regulators. In this case
AK7601A
JP1 should be OPEN.
This connector is used when DVDD of
AK7601A is power supplied without regulators.
In this case, JP5 should be OPEN.
If the power supply is other than 5V, it is
necessary to adjust the power supply for
DVDD of
DVDD
Yellow
+3.0+5V
the peripheral circuit.
AK7601A
AGND
Black
0V
DGND
Black
0V
JP40(VDD-SEL)
1-2：D3.3V
2-3：D5V (default)
Make sure to be connected to the ground
connection. When WIRE1 is SHORT, AGND
Analog ground
and DGND are connected to the same GND
（Default：OPEN）.
When WIRE1 is OPEN, Make sure to be
Digital ground
connected to the ground connection.
Table 1 Power supply lines
Default
Setting
+12V
Open
Open
0V
0V
(2) Set up the jumper pins (Refer to the explanations of JP setting)
(3) USB Connect
Connect the board to PC with the USB cable.
(4) Power on
Power the board on and start up the AK7601A control software.
(5) Setup the control register
Refer to the explanations of control software.
KM110900
2012/ 04
- 4 -
ASAHI KASEI
[AKD7601A-A]
 Evaluation Mode
When evaluating AK 7601A with AK4118A, make sure to match audio interface of AK7601A and AK4118A. Refer to the
AK7601A data sheet for the information about audio interface format of AK7601A. About audio interface format of
AK4118A, refer to Table5. As AK4118A can receive fs=32kHz and over, fs must be greater than or equal to 32kHz.
MCLK for AK4118A must be 256fs or 512fs.
Refer to the AK7601A data sheet for the information about the register setting of AK7601A.
(1) Jumper pins default setting
Jumper
Setting (Default)
JP3
1-2Short
JP10
Open
JP19
1-2Short
JP22
Open
JP23
2-3Short
JP24
JP25
JP26
JP29
JP27
JP28
JP30
JP31
JP32
JP33
JP34
JP35
JP36
JP37
JP38
JP39
Open
Open
Short
Short
Short
Short
Short
Short
Short
Short
Short
Short
Short
Short
Short
Short
JP40
2-3Shor
JP41
Short
JP42
Short
JP43
Short
Note
Switching for the clock for AK7601A
1-2：XTL(X103)（Default）
2-3：EXT-CLK(External Clock)
Do not use
Power supply selector for PIC
1-2：D3.3V/D5V
2-3：USB-5V(Do not use)
PORT4
SDTO1/SDTO3、SDTO2/SDTI4 selector
Open：When using SDTI4
1-2：When using SDTO2
2-3：When using SDTO1/SDTO3
PORT3
Do not use
AK7601A-AVDD
AK7601A-DVDD
AK7601A-SDA
AK7601A-SCLK
AINL1
AINL2
GNDIN1
GNDIN2
AINR1
AINR2
AINL3
AINL4
AINR3
AINR4
Switching for D3.3V/D5V
1-2：D3.3V
2-3：D5V （Default）
Switching for SRC1 input signal
Open：PORT4
Short：DIR （Default）
Switching for SRC2 input signal
Open：PORT4
Short：DIR （Default）
Switching for SRC3 input signal
Open：PORT4
Short：DIR （Default）
KM110900
2012/ 04
- 5 -
ASAHI KASEI
[AKD7601A-A]
SRC1 input
Open：Off
Short：On （Default）
SRC2 input
Open：Off
Short
Short：On （Default）
SRC3 input
Open：Off
Short
Short：On （Default）
Switching for EXT-CLK
1-2：PORT4
Open
2-3：DIR
*Make sure to be Open, when not using
EXT-CLK.
Open
OBICK of AK7601A
Open
OLRCK of AK7601A
Switching for SDTI4
1-2：PORT4
Open
2-3：DIR
*Make sure to be Open, when not using SDTI4.
table 2. Jumper pins setting
JP44
Short
JP45
JP46
JP47
JP48
JP49
JP50
(2) Power Supply setting
DVDD(Digital Power Supply) for the AK7601A is 3.3V or 5Ｖ. Corresponding to it, power supply voltage
for The peripheral circuit on the evaluation board can be adjusted.
（2-1)When DVDD is 5V(Default)
JP40
VVD-SEL
5V
3.3V
（2-2）When DVDD is 3.3V
JP40
VVD-SEL
5V
3.3V
(3) Clock Setting
MCLK source of AK7601A is selectable from external Clock and X’ tal.
Only 22.579MHz MCLK is needed
OLRCK
fs
44.1 kHz
MCLK (MHz)
512fs
22.579
table 3.System Clocks
KM110900
OBICK (MHz)
64fs
2.8224
2012/ 04
- 6 -
ASAHI KASEI
[AKD7601A-A]
(3-1) MCLK from X1(X’ tal) (Default)
JP3
XTI-SEL
JP47
MCLK-SEL
(3-2) MCLK from PORT4
JP3
XTI-SEL
XTL
JP47
MCLK-SEL
EXT
PORT4
DIR
(3-3) MCLK from AK4118A
JP3
XTI-SEL
XTL
JP47
MCLK-SEL
EXT
PORT4
DIR
(4) A/D Evaluation
Digital output of AK7601A is SDTO1,SDTO2 and SDTO3, which is output from PORT2(OPT)
and PORT3(DSP).When using PORT3, JP setting is not necessary.
(4-1) Output SDTO1 and SDTO3 from PORT2（OPT）
JP23
SDTO-SEL
SDTO2
/SDTI4
SDTO1
/SDTO3
(4-2) Output SDTO2 from PORT2（OPT）
JP23
SDTO-SEL
SDTO2
/SDTI4
SDTO1
/SDTO3
(5) D/A Evaluation
Digital input of AK7601A consists of 4 circuits. Three of them include SRC with a selector which can
Receive asynchronous input. The other one does not include SRC. Either one can be selected, and
It is possible to input digital data from PORT1 (OPT) or PORT4 (DSP).
It corresponds to 8 kHz~96 kHz.
Contain SRC： SDTI1,SDTI2,SDTI3
Does not contain SRC： SDTI4
KM110900
2012/ 04
- 7 -
ASAHI KASEI
[AKD7601A-A]
(5-1) Input SDTI1, SDTI2 and SDTI3 from PORT1
JP44
SRC1-SEL
JP41
DIR-SEL
JP45
SRC2-SEL
JP42
DIR-SEL
JP46
SRC1-SEL
JP43
DIR-SEL
SHORT
SHORT
SHORT
SHORT
SHORT
SHORT
SDTI1
SDTI2
SDTI3
（* If it want to no input, SRC xx-SEL is made open.）
(5-2) Input SDTI1, SDTI2 and SDTI3 from PORT4
JP44
SRC1-SEL
JP41
DIR-SEL
JP45
SRC2-SEL
JP42
DIR-SEL
JP46
SRC1-SEL
JP43
DIR-SEL
SHORT
SHORT
SHORT
SHORT
SHORT
SHORT
SDTI1
SDTI2
SDTI3
（* If it want to no input, SRC xx-SEL is made open）
(5-3) Input SDTI4 from PORT1
JP48
SDTO2/ SDTI4-SEL
PORT1
PORT4
JP49
OBICK
JP50
OLRCK
SHORT
SHORT
（* SDTI4 is synchronized with OBICK and OLRCK.）
(5-4) Input SDTI4 from PORT4
JP48
SDTO2/ SDTI4-SEL
JP49
OBICK
JP50
OLRCK
PORT1
OPEN
OPEN
PORT4
（* SDTI4 is synchronized with OBICK and OLRCK.）
KM110900
2012/ 04
- 8 -
ASAHI KASEI
[AKD7601A-A]
Control Soft Manual
 Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect PC (IBM-AT compatible) and evaluation board with the usb cable.
The board is recognized as HID (Human Interface Device) on the PC.
3. Start up the control program.
When the screen does not display “AKUSBIF-B” at bottom left, reconnect the PC and the board,
4. Proceed evaluation by following the process below.
* Two or more Evaluation Board is not connected with PC.
 Operational procedure of control software
The following procedure is defended.
1. "AK7601A.exe" is executed and the control software of AK7601A is started up.
2. "Board Init" The button is pushed, and the evaluation board is initialized.
3. The dialog is started up, and each setting is properly input and evaluated.
* When the USB line comes off while operating, software is ended.
And, it does all over again.
KM110900
2012/ 04
- 9 -
ASAHI KASEI
[AKD7601A-A]
Figure 3．Window of [Control Soft]
■Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
・[PDN Pin]：Control of AK7601A PDN Pin
(ON=High /OFF＝Low)
・[CLKMODE Pin] ： Control of AK7601A CLKMODE Pin (ON=High /OFF＝Low)
・[TRXPDN Pin]： Control of AK7601A TRXPDN Pin
(ON=High /OFF＝Low)
・[RSTN]：Control of AK7601A RSTN register
(ON=Normal(Default)/OFF＝Reset )
・[Board Init]：Initialization of AKD7601A-A
・[READ]：Reads current register settings and displays on to the register area (on the right of the main window).
・[REG SAVE]：Saves current register settings to a file.
It can not set the file name and the preservation folder.
It will be created automatically in the folder that contains this software.
・[REG SAVE(file)]：Saves current register settings to a file.
It can set the file name and preservation folder.
・[EXIT]：End of software
KM110900
2012/ 04
- 10 -
ASAHI KASEI
[AKD7601A-A]
■Tab Functions
(1) Resister setting (REG1-REG3)
This tab is for a register writing and reading.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or “0”
Refer to the datasheet of AK7601A for details.
Command
01H
D7
D6
D5
D4
CONT1
0
0
0
FCHA
02H
CONT2
CONT3
RMUTE
04H
CONT4
CONT5
LOUT1
Volume Control
ROUT1
Volume Control
LOUT2
Volume Control
ROUT2
Volume Control
LOUT3
Volume Control
ROUT3
Volume Control
MONOIN L
Volume Control
MONOINR
Volume Control
SWCONT1
SWCONT2
DZD2
FMU
TE
BICK
DZD1
03H
DZD3
MOMU
TE
LRCK
MCKO1
DZLH
SWMUT
E
MCKO0
0
0
0
ATT7
ATT6
ATT7
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Register Name
D3
PMADC
M
ODIF
D2
D1
D0
PMADC
PMDAC
RSTN
0
MCONT
SMUTEN
IDIF41
IDIF40
IDIF1
IDIF0
DO21
DO20
DO11
DO10
0
SEL11
SEL10
SEL01
SEL00
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
0
0
SW51
0
SW50
0
SW4
SWSW
SW31
RSW
SW30
FSW
SW2
EQSW1
SW1
EQSW0
table 4．AK7601A Resister Map
The following registers can be set on each screen.
REG1:CONT00-CONT04
REG2:CONT05-CONT0D
REG3:CONT0E-CONT0F
KM110900
2012/ 04
- 11 -
ASAHI KASEI
[AKD7601A-A]
Figure 4．Window of [REG1]
KM110900
2012/ 04
- 12 -
ASAHI KASEI
[AKD7601A-A]
Figure 5．Window of [REG2]
KM110900
2012/ 04
- 13 -
ASAHI KASEI
[AKD7601A-A]
Figure 6．Window of [REG3]
KM110900
2012/ 04
- 14 -
ASAHI KASEI
[AKD7601A-A]
(2) AK4118A Setting
The setting of AK4118A can be executed.
Figure 7． Window of [AK4118A]
KM110900
2012/ 04
- 15 -
ASAHI KASEI
[AKD7601A-A]
AK4118A
MCLK
CM
DIF
Setting
Frequency of main clock output from AK4118A
0 : 256fs
1 : 256fs
2 : 512fs
3 : 128fs
Master clock operation mode of AK4118A
0 : CM = 00
1 : CM = 01
2 : CM = 10
3 : CM = 11
Format setup of AK4118A I/O
0 : 16bit Right ( Output )
1 : 18bit Right ( Output )
2 : 20bit Right ( Output )
3 : 24bit Right ( Output )
4 : 24bit Left ( Output )
5 : 24bit I2S ( Output )
6 : 24bit Left ( Input )
7 : 24bit I2S ( Input )
Table 5．AK4118A Set-up
KM110900
2012/ 04
- 16 -
ASAHI KASEI
[AKD7601A-A]
(3) Equalizer
It is a set screen of Equalizer
The function of each button is shown below.
[LG/RG]: Dialog box for setting of LG1/RG1 and LG2/RG2 is opened.
[Mute]:Setting of MUTE1/MUTE2. (Mute: OFF / Unｍute: ON)
[SpeAna]: Dialog box for setting of Spectrum Analyzer is opened.
[Function1-5]: Dialog box for setting of Function1-5 is opened.
[EQ]: Dialog box for setting of Equalizer is opened.
[Delay]: Dialog box for setting of Delay is opened.
[X’ over]: Dialog box for setting of is opened.
[MOMUTE] [FMUTE] [RMUTE] [SWMUTE]: Setting of Each MUTE. (Mute: OFF / Unmute:ON)
*Block Diagram Click to enlarge
・Please push [Enter] button when you set the coefficient.
・Please push the [Send] button after inputting the numerical value when you set the coefficient.
Figure 8．Window of [Equalizer]
KM110900
2012/ 04
- 17 -
ASAHI KASEI

[AKD7601A-A]
LG/RG Setting
The setting of LG1, RG1, LG2 and RG2 can be executed.
Figure 9．Window of [LG/RG]
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
80H
LG1
RG1
LG2
RG2
Dummy
Shift Setting
2bit left x 4
2bit left x 4
2bit left x 4
2bit left x 4
-
KM110900
R/W
R/W
R/W
R/W
R/W
-
Default
0x 2000
0x 2000
0x 2000
0x 2000
-
2012/ 04
- 18 -
ASAHI KASEI

[AKD7601A-A]
Spectrum Analyzer setting
The setting of Spectrum Analyzer can be executed.
*Block Diagram Click to enlarge
Figure 10．Window of [SpeAna]
KM110900
2012/ 04
- 19 -
ASAHI KASEI
[AKD7601A-A]
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
CFH
SAIIR1_a02
SAIIR1_a00
SAIIR1_b02
SAIIR1_b01
Dummy
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
-
R/W
R/W
R/W
R/W
R/W
-
Default
0x 0FFE2D4D
0x 0001D2B3
0x 0C009B92
0x 07FF1150
-
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
D0H
SAIIR2_a02
SAIIR2_a00
SAIIR2_b02
SAIIR2_b01
Dummy
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
-
R/W
R/W
R/W
R/W
R/W
-
Default
0x 0FF51627
0x 000AE9D9
0x 0C03A349
0x 07F72D4D
-
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
D1H
SASIIR_a51
SASIIR_a50
SASIIR_b51
Dummy
Dummy
Shift Setting
-
R/W
R/W
R/W
R/W
-
Default
0x 00031773
0x 00031773
0x 07FBA0B8
-
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
9FH
SAIIR3_a22
SAIIR3_a20
SAIIR3_b22
SAIIR3_b21
Dummy
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
-
R/W
R/W
R/W
R/W
R/W
-
Default
0x FD52
0x 02AE
0x C0E5
0x 79FB
-
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
A0H
SAIIR4_a32
SAIIR4_a30
SAIIR4_b32
SAIIR4_b31
Dummy
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
-
R/W
R/W
R/W
R/W
R/W
-
Default
0x F779
0x 0887
0x C2D8
0x 3449
-
Reading of each level data of Spectrum Analyzer.
Command
Data1 (2byte)
50H
125Hz (default)
R/W
RD
Command
Data1 (2byte)
51H
500Hz (default)
R/W
RD
Command
Data1 (2byte)
52H
2kHz (default)
R/W
RD
Command
Data1 (2byte)
53H
8kHz (default)
R/W
RD
KM110900
2012/ 04
- 20 -
ASAHI KASEI

[AKD7601A-A]
Function1 Setting
The setting of Function1 can be executed.
*Block Diagram Click to enlarge
Figure 11．Window of [Function1]
KM110900
2012/ 04
- 21 -
ASAHI KASEI
[AKD7601A-A]
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
81H
ThrGainL
ThrGainR
Dummy
Dummy
Dummy
Shift Setting
1bit left x 2
1bit left x 2
-
R/W
R/W
R/W
-
Default
0x 4000
0x 4000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
82H
HighGainL
HighGainR
Multiplier1
Multiplier2
Multiplier3
Shift Setting
1bit left x 2
1bit left x 2
-
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
84H
HiIn_a02
HiIn_a01
HiIn_a00
HiIn_b02
HiIn_b01
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
85H
HiOut_a12
HiOut_a11
HiOut_a10
HiOut_b12
HiOut_b11
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
KM110900
-
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
2012/ 04
- 22 -
ASAHI KASEI

[AKD7601A-A]
Function2 setting
The setting of Function2 can be executed.
*Block Diagram Click to enlarge
Figure 12．Window of [Function2]
KM110900
2012/ 04
- 23 -
ASAHI KASEI
[AKD7601A-A]
Command
C0H
Data 1 (4byte)
LPF_a02
Shift
Setting
1bit Left x 2
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
LPF_a01
LPF_a00
LPF_b02
LPF_b01
1bit Left
1bit Left
1bit Left
1bit Left
Command
88H
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
LPF_a21
LPF_a20
LPF_b21
Dummy
Dummy
Shift
Setting
1bit Left x 2
1bit Left x 2
1bit Left x 2
-
Command
8CH
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
Thr_G
Dummy
Dummy
Dummy
Dummy
Command
8DH
Data 1 (2byte)
Compressor1
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
Compressor2
Compressor3
Compressor4
Dummy
x2
x2
x2
x2
Shift
Setting
1bit Left x 2
Shift
Setting
4bit Left x
16
1bit Left x 2
1bit Left x 2
-
KM110900
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
Default
0x
00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Default
0x 0000
0x 0000
0x 0000
-
Default
0x 4000
-
Default
0x 0000
0x 0000
0x 0000
0x 0000
-
2012/ 04
- 24 -
ASAHI KASEI

[AKD7601A-A]
Function3 setting
The setting of Function3 can be executed.
*Block Diagram Click to enlarge
Figure 13．Window [Function3]
KM110900
2012/ 04
- 25 -
ASAHI KASEI
[AKD7601A-A]
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
90H
F3ThrG
F3OutL
F3OutR
Dummy
Dummy
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
-
R/W
R/W
R/W
R/W
-
Default
0x 4000
0x 0000
0x 0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
91H
F3InL
F3InR
F3D
F3FBG
Dummy
Shift Setting
-
R/W
R/W
R/W
R/W
R/W
-
Default
0x 0000
0x 0000
0x 0000
0x 0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
92H
F3IIR_a02
F3IIR_a01
F3IIR_a00
F3IIR_b02
F3IIR_b01
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
KM110900
-
-
2012/ 04
- 26 -
ASAHI KASEI

[AKD7601A-A]
Function4 setting
The setting of Function4 can be executed.
*Block Diagram Click to enlarge
Figure 14．Window of [Function4]
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
93H
F4ThrL
F4ThrR
F4InL
F4InR
Dummy
Shift Setting
1bit left x 2
1bit left x 2
-
R/W
R/W
R/W
R/W
R/W
-
Default
0x 4000
0x 4000
0x 0000
0x 0000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
C2H
F4IIR_a02
F4IIR_a01
F4IIR_a00
F4IIR_b02
F4IIR_b01
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
KM110900
-
2012/ 04
- 27 -
ASAHI KASEI

[AKD7601A-A]
Function5 Setting
The setting of Function5 can be executed.
*Block Diagram Click to enlarge
Figure 15．Window of [Function5]
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
94H
F5ThrG
F5OutG
Dummy
Dummy
Dummy
Shift Setting
1bit left x 2
1bit left x 2
-
R/W
R/W
R/W
-
Default
0x 4000
0x 0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
95H
F5IIR_a02
F5IIR_a01
F5IIR_a00
F5IIR_b02
F5IIR_b01
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
KM110900
-
2012/ 04
- 28 -
ASAHI KASEI

[AKD7601A-A]
Equalizer setting
The setting of Equalizer can be executed.
Figure 16．Window of [Equalizer]
When the Enable check box of each EQ is selected, the figure is output in the graph.
An arbitrary numerical value can be specified by dragging the figure with the mouse.
Writing in the register is done by pushing the Send button.
EQGain1 EQGain2: It is written in pushing the Send button after a set value is input.
Command
Data 1 (2byte)
40H
EQGain1
Shift Setting
1bit left x 2
R/W
R/W
Default
0x 4000
Command
Data 1 (2byte)
41H
EQGain2
Shift Setting
1bit left x 2
R/W
R/W
Default
0x 4000
KM110900
2012/ 04
- 29 -
ASAHI KASEI
[AKD7601A-A]
EQBand1-14: It is written in pushing the Send button after a set value is input.
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
C3H
EQBand1_a2
EQBand1_a1
EQBand1_a0
EQBand1_b2
EQBand1_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
96H
EQBand2_a2
EQBand2_a1
EQBand2_a0
EQBand2_b2
EQBand2_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
C4H
EQBand3_a2
EQBand3_a1
EQBand3_a0
EQBand3_b2
EQBand3_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
C5H
EQBand4_a2
EQBand4_a1
EQBand4_a0
EQBand4_b2
EQBand4_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
97H
EQBand5_a2
EQBand5_a1
EQBand5_a0
EQBand5_b2
EQBand5_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
98H
EQBand6_a2
EQBand6_a1
EQBand6_a0
EQBand6_b2
EQBand6_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
99H
EQBand7_a2
EQBand7_a1
EQBand7_a0
EQBand7_b2
EQBand7_b1
Shift Setting
1bit left x 2
1bit left x 2
2bit left x 4
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 2000
0x 0000
0x 0000
KM110900
2012/ 04
- 30 -
ASAHI KASEI
[AKD7601A-A]
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
C6H
EQBand8_a2
EQBand8_a1
EQBand8_a0
EQBand8_b2
EQBand8_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
9AH
EQBand9_a2
EQBand9_a1
EQBand9_a0
EQBand9_b2
EQBand9_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
C7H
EQBand10_a2
EQBand10_a1
EQBand10_a0
EQBand10_b2
EQBand10_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
C8H
EQBand11_a2
EQBand11_a1
EQBand11_a0
EQBand11_b2
EQBand11_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
9BH
EQBand12_a2
EQBand12_a1
EQBand12_a0
EQBand12_b2
EQBand12_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
9CH
EQBand13_a2
EQBand13_a1
EQBand13_a0
EQBand13_b2
EQBand13_b1
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
9DH
EQBand14_a2
EQBand14_a1
EQBand14_a0
EQBand14_b2
EQBand14_b1
Shift Setting
1bit left x 2
1bit left x 2
2bit left x 4
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 2000
0x 0000
0x 0000
KM110900
2012/ 04
- 31 -
ASAHI KASEI

[AKD7601A-A]
Delay Setting
The setting of Delay can be executed.
*Block Diagram Click to enlarge
Figure 17．Window of [Delay]
KM110900
2012/ 04
- 32 -
ASAHI KASEI
[AKD7601A-A]
Delay Block
(1/fs = 1/44100 = about 0.0226ms)= One unit
Command
45H
Data 1 (2byte)
Front L1 out delay time
Set range (0x0000~0x031A)
Command
46H
Data 1 (2byte)
Front R1 out delay time
Set range (0x0000~0x031A)
Command
47H
Data 1 (2byte)
Rear L2 out delay time
Set range (0x0000~0x031A)
Command
48H
Data 1 (2byte)
Rear R2 out delay time
Set range (0x0000~0x031A)
Command
49H
Data 1 (2byte)
SW L3 out delay time
Set range (0x0000~0x031A)
Command
4AH
Data 1 (2byte)
SW R3 out delay time
Set range (0x0000~0x031A)
Command
Data 1 (2byte)
Data 1 (2byte)
Data 1 (2byte)
Data 1 (2byte)
Data 1 (2byte)
A1H
Front L Gain Setting
Coefficient
Front R Gain Setting
Coefficient
Rear L Gain Setting
Coefficient
Rear R Gain Setting
Coefficient
Dummy
Setting Unit
Delay time:
1/fs unit
Setting Unit
Delay time:
1/fs unit
Setting Unit
Delay time:
1/fs unit
Setting Unit
Delay time:
1/fs unit
Setting Unit
Delay time:
1/fs unit
Setting Unit
Delay time:
1/fs unit
Shift Setting
1bit left x2
1bit left x2
1bit left x2
1bit left x2
-
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
Default
0x 0000
R/W
R/W
Default
0x 0000
R/W
R/W
Default
0x 0000
R/W
R/W
Default
0x 0000
R/W
R/W
Default
0x 0000
R/W
R/W
Default
0x 0000
Default
0x 4000
0x 4000
0x 4000
0x 4000
-
Command
Data 1 (2byte)
A2H
Shift Setting
R/W
Default
SW L Gain Setting
1bit left x2
0x 4000
R/W
Coefficient
Data 1 (2byte)
SW R Gain Setting
1bit left x2
0x 4000
R/W
Coefficient
Data 1 (2byte)
Dummy
Data 1 (2byte)
Dummy
Data 1 (2byte)
Dummy
Note: All data are R/W.
When the delay time is set over its limit, it will be set to the maximum value.
KM110900
2012/ 04
- 33 -
ASAHI KASEI
[AKD7601A-A]
< Delay Amount Setting Example>
SWSW, RSW and FSW bits in 0FH control input source setting.
Lch input 1
Example1. Input1 → L1, L2, L3
Input2 → No data
FL
RL
NL
Delay Memory 1word=24bit
18ms Delay = 794word (44.1kHz x 0.018)
<< 1
L1 out (Front)
L2 out (Rear)
<< 1
L3 out (SW)
<< 1
Example2. Input1 →L2, L3
Input2 → L1
Lch input 1
Lch input 2
FL
RL
NL
Delay Memory 1word=24bit
18ms Delay = 794word (44.1kHz x 0.018)
<< 1
<< 1
L1 out (Front)
L2 out (Rear)
L3 out (SW)
<< 1
KM110900
2012/ 04
- 34 -
ASAHI KASEI

[AKD7601A-A]
Cross Over setting
The setting of Cross Over can be executed.
*Block Diagram Click to enlarge
Figure 18．Window of [Cross Over]
When the Enable check box is selected, the figure is output in the graph.
An arbitrary numerical value can be specified by dragging the figure with the mouse.
Writing in the register is done by pushing the Send button.
KM110900
2012/ 04
- 35 -
ASAHI KASEI
[AKD7601A-A]
Command
Data 1 (2byte)
42H
Fout Gain
Shift Setting
1bit left x 2
R/W
R/W
Default
0x 4000
Command
Data 1 (2byte)
43H
Rout Gain
Shift Setting
1bit left x 2
R/W
R/W
Default
0x 4000
Command
Data 1 (2byte)
44H
SWout Gain
Shift Setting
1bit left x 2
R/W
R/W
Default
0x 4000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
C9H
XO1IIR_a02
XO1IIR_a01
XO1IIR_a00
XO1IIR_b02
XO1IIR_b01
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
CAH
XO2IIR_a02
XO2IIR_a01
XO2IIR_a00
XO2IIR_b02
XO2IIR_b01
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
CBH
XO3IIR_a02
XO3IIR_a01
XO3IIR_a00
XO3IIR_b02
XO3IIR_b01
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
CCH
XO1IIR_a12
XO1IIR_a11
XO1IIR_a10
XO1IIR_b12
XO1IIR_b11
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
CDH
XO2IIR_a12
XO2IIR_a11
XO2IIR_a10
XO2IIR_b12
XO2IIR_b11
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
CEH
XO3IIR_a12
XO3IIR_a11
XO3IIR_a10
XO3IIR_b12
XO3IIR_b11
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 00000000
0x 00000000
0x 04000000
0x 00000000
0x 00000000
KM110900
2012/ 04
- 36 -
ASAHI KASEI
[AKD7601A-A]
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)

9EH
XO1IIR_a22
XO1IIR_a21
XO1IIR_a20
XO1IIR_b22
XO1IIR_b21
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x 0000
0x 0000
0x 4000
0x 0000
0x 0000
Filter Setting
When the Filter button is pressed, the following dialog is displayed.
LPF0/BPF0/BPF1/HPF0 of Function2 and EQ01-14 of EQ can be confirmed.
Figure 19．Window of [Filter Set]
・The writing object is specified with Filter Select. Biquad / Double is switched.
・The last calculation value of the coefficient under the selection is displayed.
・Biquad：The coefficient is input by the hexadecimal number of four digits.
Double：The coefficient is input by the hexadecimal number of eight digits.
Writing the Filter Select specification in the register is executed by pushing the Send button.
The written data is displayed in the DEBUG frame.
・When the Read button is pushed, reading the register of the Filter Select specification is executed.
The reading data is displayed in the DEBUG frame.
KM110900
2012/ 04
- 37 -
ASAHI KASEI
[AKD7601A-A]
(3) Execution of script
It is a screen where the script file that can do the sequential processing is executed.
It can write AK7601A and AK4418 together.
[REG SAVE] button and the [REG SAVE (File)] button will generate a file that can be performed on this screen.
Figure 20．Window of [Script]
[Refer]: Specify the script file and run.
[Repeat]: Re-run the file in the specified.
Displays the file name specified in the left panel of the button.
[Refer] :It can also run scripts by dropping a script file in the left panel of the button.
KM110900
2012/ 04
- 38 -
ASAHI KASEI
[AKD7601A-A]
MEASUREMENT RESULTS
[Measurement condition]
 Measuring instrument: Audio Precision System Two Cascade
 MCLK
: 512fs
 BICK
: 64fs
 Fs
: 44.1 kHz
 Bit
: 24bit
 Power Supply（REG）: AVDD = 5.0V, DVDD = 5.0V
 Interface
: DSP Data (PSIA for ADC, PSIA for DAC)
 Temperature
: Room temperature
Spec
Parameter
min typ max Units
ADC Analog Input Characteristics (Pseudo differential inputs)
AINL1/R1→SDTO1
24
Resolution
Bits
83
90
S/(N+D)
BW=20kHz
-1dBFS
dB
35
-60dBFS
dB
90
97
DR (-60dBFS with A-weighted)
dB
90
97
S/N (A-weighted)
dB
ADC Analog Input Characteristics (Single-ended input)
Resolution
S/(N+D)
Measured
L
R
92.5
92.5
34.6
34.7
97.2
97.4
97.3
97.4
AINL3/R3→SDTO1
24
-1dBFS
-60dBFS
83
DR (-60dBFS with A-weighted)
S/N (A-weighted)
ADC Analog Input Characteristics (Monaural inputs)
Resolution
S/(N+D)
BW=20kHz
-1dBFS
-60dBFS
DR (-60dBFS with A-weighted)
S/N (A-weighted)
DAC Analog Output Characteristics (single output)
Resolution
S/(N+D)
BW=20kHz
0dBFS
-60dBFS
DR (-60dBFS with A-weighted)
S/N (A-weighted)
ADC to DAC Characteristics
90
S/(N+D)
80
BW=20kHz
BW=20kHz
-1dBFS
-60dBFS
90
83
90
90
83
93
93
87
DR (-60dBFS with A-weighted)
S/N (A-weighted)
SRC Characteristics
Resolution
THD+N (Input=1kHz, 0dBFS)
FSI=48kHz
DR (Input=1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
DR (Input=1kHz, -60dBFS with A-weighted)
FSO/FSI=44.1kHz/48kHz
87
120
KM110900
Bits
92.4
dB
35
34.1
dB
97
96.8
dB
97
96.9
dB
MONOIN→SDTO1
24
Bits
90
93.1
dB
35
35.4
dB
97
98.4
dB
97
98.4
dB
SDTI4→AOUTL1/R1
24
Bits
90
91.7
dB
39
40
dB
102
102.5
dB
102
102.6
dB
AINL1/R1→AOUTL1/R1
24
Bits
87
90.0
dB
34
33.3
dB
96
95.9
dB
96
96.0
dB
SRC1→SDTO1
24
Bits
-130
-100
-130.3
dB
90
92.4
34.2
96.9
96.9
93.1
35.5
98.4
98.4
91.8
40
102.5
102.6
90.0
33.3
96.0
96.0
-130.4
136
dB
136.9
136.9
140
dB
140.0
140.0
2012/ 04
- 39 -
ASAHI KASEI
[AKD7601A-A]
[ADC Plots]
Path ：AINL1/R1→SDTO1
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
2k
5k
10k
20k
Hz
FFT (fin=1 kHz, Input level = ‐1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
Hz
FFT (fin=1 kHz, Input level = ‐60dBFS)
KM110900
2012/ 04
- 40 -
ASAHI KASEI
[AKD7601A-A]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FFT (fin=1 kHz, Input level = No Input)
-70
-75
-80
-85
-90
d
B
F
S
-95
-100
-105
-110
-115
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
THD+N VS. Input level (fin=1 kHz)
KM110900
2012/ 04
- 41 -
ASAHI KASEI
[AKD7601A-A]
-70
-75
-80
-85
-90
d
B
F
S
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
THD+N VS. Input Freq (Input level = -1dBFS)
+0
T TT T T
T
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Linearity (fin=1 kHz)
KM110900
2012/ 04
- 42 -
ASAHI KASEI
[AKD7601A-A]
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
d
B
F
S
-1.4
-1.6
-1.8
-2
-2.2
-2.4
-2.6
-2.8
-3
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Frequency Response (Input level = ‐1dBFS)
-50
TTTTTT
TTT TTT
TTTT
TT
TT
TT
-60
-70
-80
-90
d
B
-100
-110
-120
-130
-140
-150
20
50
100
200
500
1k
2k
Hz
Crosstalk (Input level = ‐1dBFS)
KM110900
2012/ 04
- 43 -
ASAHI KASEI
[AKD7601A-A]
[DAC Plots]
Path ：SDTI4→DAC→AOUTL1/R1
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
FFT (fin=1 kHz, Input level = 0dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
FFT (fin=1 kHz, Input level = ‐60dBFS)
KM110900
2012/ 04
- 44 -
ASAHI KASEI
[AKD7601A-A]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FFT (fin=1 kHz, Input level = No Input)
-70
-75
-80
-85
-90
d
B
r
-95
A
-100
-105
-110
-115
-120
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
THD+N VS. Input level (fin=1 kHz)
KM110900
2012/ 04
- 45 -
ASAHI KASEI
[AKD7601A-A]
-70
-75
-80
-85
-90
d
B
r
-95
A
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
THD+N VS. Input Freq (Input Level = 0dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
A
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Linearity (fin=1 kHz)
KM110900
2012/ 04
- 46 -
ASAHI KASEI
[AKD7601A-A]
+1
+0.8
+0.6
+0.4
+0.2
d
B
r
+0
A
-0.2
-0.4
-0.6
-0.8
-1
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Frequency Response (Input level = 0dBFS)
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
d
B
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
Hz
Crosstalk (Input level = 0dBFS)
KM110900
2012/ 04
- 47 -
ASAHI KASEI
[AKD7601A-A]
[SRC Plots]
Path ：SRC1→SDTO1、 FSI/FSO=48kHz/44.1kHz
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
FFT (fin=1 kHz, Input level =0dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
20
50
100
200
500
1k
2k
Hz
FFT (fin=1 kHz, Input level = －60dBFS)
KM110900
2012/ 04
- 48 -
ASAHI KASEI
[AKD7601A-A]
-90
-95
-100
-105
-110
-115
d
B
F
S
-120
-125
-130
-135
-140
-145
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
THD+N VS. Input level (fin=1 kHz)
-90
-95
-100
-105
-110
-115
d
B
F
S
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
THD+N VS. Input Freq (Input Level = 0dBFS)
KM110900
2012/ 04
- 49 -
ASAHI KASEI
[AKD7601A-A]
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Linearity (fin=1 kHz)
+1
+0.8
+0.6
+0.4
+0.2
d
B
r
+0
A
-0.2
-0.4
-0.6
-0.8
-1
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Frequency Response (Input level = 0dBFS)
KM110900
2012/ 04
- 50 -
ASAHI KASEI
[AKD7601A-A]
Revision History
Date
(yy/mm/dd)
12/04/05
Manual
Revision
KM110900
Board
Revision
0
Reason
Page
Contents
First Edition
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
KM110900
2012/ 04
- 51 -
1
CLKMODE
MUTEN
2
MONOIN
AINL1
GNDIN1
AINR1
AINL2
3
GNDIN2
4
AINR2
5
37
38
39
40
41
42
43
44
45
46
47
48
48pin_4
CN4
MUTEN
CLKMODE
MONOIN
AINL1
GNDIN1
AINR1
AINL2
GNDIN2
D
AINR2
D
C1 2.2uF(A)
+
C2 0.1uF
37
38
39
40
41
42
43
44
45
46
C4
12pF
X1
AINL3
MUTEN
VSS3
CLKMODE
REF18
VSS4
AINL1
GNDIN1
AINR1
MONOIN
1
AINL2
AINR2
AINL3
1
GNDIN2
48pin_3
CN1
AINL3
47
48
C3
12pF
22.5792MHz
XTO
36
36
JP3
JMP3_1_1
XTL
AINR3
AINR3
2
2
AINR3
XTI
35
EXT
3 : XTL
1 : EXT
EXT-CLK
R1
100
R2
100
R3
100
EXT-CLK
35
XTI-SEL
AINL4
C
AINL4
ILRCK1
3
3
AINL4
ILRCK1
34
AINR4
AINR4
ILRCK1
34
ILRCK2
4
4
AINR4
ILRCK2
VCOM
ILRCK3
33
ILRCK2
33
ILRCK3
5
5
2.2uF(A) +
C5
AVDD
AVDD
C6
0.1uF
6
6
+ C8
10uF(A)
R54
7
7
C10
10uF(A)
VREFH
+
short
IBICK2
IBICK3
AOUT1L
SDTI1
29
AOUT1R
SDTI2
R7
100
R8
100
R9
100
R10
100
IBICK3
28
SDTI1
28
SDTI2
10
10
IBICK2
29
AOUT1R
AOUT1R
100
30
SDTI1
9
9
R6
30
AOUT1L
AOUT1L
IBICK1
IBICK3
VREFH
100
31
IBICK2
LQFP 48pin
VSS1
ILRCK3
R5
31
C11
0.1uF
8
8
IBICK1
100
32
IBICK1
AK7601AVQ
AVDD
C9
0.1uF
R4
32
27
C
SDTI2
27
B
B
AOUT2L
11
SDTI3
26
SDTI3
25
DVDD
DVDD
DVDD
VSS2
OLRCK
OBICK
MCKO
SCL
SDA
PDN
DZF
AOUT3R
26
25
C12
0.1uF
+
C13
10uF(A)
R11
100
TP3
R12
100
R13
100
R14
100
24
22
21
20
19
18
17
16
15
14
13
CN3
R15
100
24
SDTO1
23
SDTO2
22
OLRCK
21
OBICK
20
MCKO
19
SCL
18
SDA
17
PDN
16
DZF
15
AOUT3R
14
13
AOUT3L
1
GND
AOUT3L
AOUT2R
U1
AK7601A
48pin_1
SDTO2/SDIT4
12
12
AOUT2R
SDTO1/SDTO3
AOUT2L
AOUT2R
23
11
AOUT2L
SDTI3
A
A
SDTO1/SDTO3
- 52 -
SDTO2/SDTI4
OLRCK
OBICK
MCKO
SCL
SDA
PDN
DZF
AOUT3R
AOUT3L
CN2
48pin_2
Title
<AKD7601A-A>
Size
A3
Date:
5
4
3
2
Document Number
<AK7601A>
Monday, March 05, 2012
Rev
<0>
Sheet
1
1
of
6
5
4
3
2
1
D
D
RCA1
R16
C15
0.47uF(A)
+
T
B
S
MONOIN
R17
open
C16
short
R73
T
B
S
AOUT1L
+
MONO
MR-552LS(BLACK)
22uF(A)
(short)
R18
10k(DIP)
C17
(open)
RCA6
MR-552LS(W HITE)
DAC1
R19
C18
0.47uF(A)
AINL1
AINL1
JP31
AINL2
AINL2
+
T
B
S
R20
open
C19
JP30
short
R74
T
B
S
AOUT1R
+
RCA2
22uF(A)
AINL-SEL1
MR-552LS(W HITE)
(short)
R21
10k(DIP)
C20
(open)
RCA7
MR-552LS(RED)
R66
0
R22
C
C21
0.47uF(A)
GNDIN1
GNDIN1
JP33
GNDIN2
GNDIN2
+
JP32
short
AIN(D)
C
C22
GNDIN-SEL
R67
0
RCA3
R25
R26
open
T
B
S
+
22uF(A)
C24
0.47uF(A)
JP34
AINR1
AINR1
JP35
AINR2
AINR2
+
T
B
S
R75
AOUT2L
GNDIN
JP10
short
R24
(short)
10k(DIP)
C23
(open)
RCA8
MR-552LS(W HITE)
DAC2
C25
AINR-SEL1
MR-552LS(RED)
R76
+
AOUT2R
22uF(A)
R27
(short)
10k(DIP)
C26
(open)
T
B
S
RCA9
MR-552LS(RED)
R28
B
C27
0.47uF(A)
JP36
AINL3
AINL3
JP37
AINL4
AINL4
+
T
B
S
R29
open
short
C28
R77
T
B
S
AOUT3L
AINL-SEL2
+
RCA4
MR-552LS(W HITE)
22uF(A)
R30
(short)
10k(DIP)
C29
(open)
RCA10
B
MR-552LS(W HITE)
AIN(S)
DAC3
RCA5
R31
0.47uF(A)
JP38
+
JP39
R32
open
AINR3
AINR3
AINR4
AINR4
short
C31
R78
T
B
S
AOUT3R
+
T
B
S
C30
AINR-SEL2
22uF(A)
MR-552LS(RED)
TP (Black)
TP4
(short)
R33
10k(DIP)
C32
(open)
RCA11
MR-552LS(RED)
TP (Black)
TP5
AVSS
AVSS
1
A
1
A
Title
<AKD7601A-A>
Size
A3
- 53 -
Date:
5
4
3
2
Document Number
<Analog>
Monday, March 05, 2012
Rev
<0>
Sheet
1
2
of
6
4
3
2
1
D3.3V
D3.3V
5
C36
C33
L1
JP48
+
C34
10uH
D
22pF
10uF
SPDIF-IN
SDTO2/SDTI4
X2
11.2896MHz
C39
0.1uF
D
SDTO2/SDTI4_SEL
PORT1
VCC
GND
OUT
3
2
1
R34
470
C35
DIF-RX
22pF
R35
10k(m)
0.1uF
SRC1
U8
TORX147
13
14
15
16
17
18
19
20
21
22
23
24
C40
0.1uF
C42
PC-CS4N
PC-SCLK
PC-SI
JP49
JP50
10uF
15
1
10k
10k
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
STN VCC
SEL GND
4
SDTI1
7
IBICK1
9
ILRCK1
12
16
8
74HC157
PC-TRXPND
R51
SRC2
OLRCK
U3
2
3
5
6
11
10
14
13
D3.3V / 5.0V
R59
R60
15
1
10k
10k
+
+
C43
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
STN VCC
SEL GND
4
SDTI2
7
IBICK2
9
ILRCK2
12
16
8
R63
SRC2-SEL
DIR-SEL
D3.3V
JP42
D3.3V / 5.0V
0
D3.3V / 5.0V
C85
0.1uF
B
SRC3
U9
2
3
5
6
11
10
14
13
D3.3V
D3.3V / 5.0V
R61
R62
15
1
10k
10k
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
STN VCC
SEL GND
4
SDTI3
7
IBICK3
9
ILRCK3
12
16
8
R64
74HC157
JP43
SRC3-SEL
DIR-SEL
C45
100uF(A)
JP46
TP6
TP (Black)
+
JP45
R50
0
DVSS
D3.3V / 5.0V
OBICK
74HC157
B
0
C44
0.1uF
C
SDTIDIR
SDTIA
BICKDIR
BICKA
LRCKDIR
LRCKA
AK4118A
0.1uF C41
10uF
R57
R58
DIR-SEL
AK4118A
D3.3V / 5.0V
36
35
34
33
32
31
30
29
28
27
26
25
JP41
INT0
CSN
CCLK
CDTI
CDTO
PDN
XTI
XTO
DAUX
MCKO2
BICK
SDTO
SRC1-SEL
C
RX4
NC
RX5
TEST2
RX6
VSS1
RX7
IIC
P/SN
XTL0
XTL1
VIN
JP44
1
2
3
4
5
6
7
8
9
10
11
12
RX3
VSS4
RX2
TEST1
RX1
NC
RX0
VSS3
VCOM
R
AVDD
INT1
U2
48
47
46
45
44
43
42
41
40
39
38
37
C37
10uF
TVDD
NC
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
VSS2
MCKO1
LRCK
+
C38
0.1uF
2
3
5
6
11
10
14
13
0
D3.3V / 5.0V
C86
0.1uF
JP47
MICKDIR
A
A
EXT-CLK
MICKA
PORTA
MCLK_SEL
R68
R69
R70
10k
10k
10k
MICKA
BICKA
LRCKA
SDTIA
1
3
5
7
9
2
4
6
8
10
Title
<AKD7601A-A>
Size
A3
- 54 -
JP22
HEADER 5X2
Date:
5
4
3
2
Document Number
<DIR>
Monday, March 05, 2012
Rev
<0>
Sheet
1
3
of
6
4
3
2
1
D3.3V
5
C46
+
D
D
C47
10uF
0.1uF
C48
D3.3V
R36
10k(m)
0.1uF
U10
RX4
NC
RX5
TEST2
RX6
VSS1
RX7
IIC
P/SN
XTL0
XTL1
VIN
13
14
15
16
17
18
19
20
21
22
23
24
L2
AK4118A
INT0
CSN
CCLK
CDTI
CDTO
PDN
XTI
XTO
DAUX
MCKO2
BICK
SDTO
36
35
34
33
32
31
30
29
28
27
26
25
INA
VCC
GND
OUTY
NC
TC7SZ04AFS
1
MCKO
2
3
C88
0.1uF
PC-CS3N
PC-SCLK
PC-SI
JP23
JMP3_1_1
SDTO2/SDTI4
PC-TRXPND
OBICK
C
SDTO2/SDTI4
SDTO1/SDTO3
SDTO1/SDTO3
STDO_SEL
TVDD
NC
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
VSS2
MCKO1
LRCK
1
2
3
4
5
6
7
8
9
10
11
12
D3.3V
C
4
RX3
VSS4
RX2
TEST1
RX1
NC
RX0
VSS3
VCOM
R
AVDD
INT1
U4
48
47
46
45
44
43
42
41
40
39
38
37
5
AK4118A
10uH
OLRCK
PORT2
SPDIF-OUT
IN
VCC
GND
3
2
1
DIF-TX
C49
0.1uF
0.1uF C50
C53
10uF
10uF
PORTB
TOTX147
C51 +
0.1uF
C52
10uF
C54
+
+
MCLKB
BICKB
LRCKB
SDTO1
SDTO2
R52
0
1
3
5
7
9
2
4
6
8
10
JP24
HEADER 5X2
B
TP7
TP (Black)
DVSS
+
C55
100uF(A)
D3.3V
D3.3V / 5.0V
D3.3V
B
A
A
Title
<AKD7601A-A>
Size
A3
- 55 -
Date:
5
4
3
2
Document Number
<DIT>
Monday, March 05, 2012
Rev
<0>
Sheet
1
4
of
6
5
4
3
2
1
USB-VDD
+
C56
10uF
C57
10uF
18
R38
100k
C59
0.1uF
12
13
33
34
VSS1
VDD1
6
VSS0
VDD0
7
U5
C60
0.1uF
28
C58
0.1uF
JP25
MCLR_N/Vpp/RE3
1
2
3
4
5
17
16
15
14
11
10
9
8
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
SILK-SCREEN
1: VDD
2: MCLR
3: PGD
4: PGC
5: GND
29
R37
10k
D
D3.3V / 5.0V
+
D
JP19
JMP3_1_1
DVDD-3.3V / 5.0V
HEADER 5
USB-5V
USB-VDD-SEL
C61 22pF
D3.3V / 5.0V
C
30
31
XTI
XTO
C62 22pF
X3
20MHz
25
26
27
C65
TP8
SDA
1
R39
10k
JP27
SDA-SEL
R40
37
0.47uF
19
20
21
22
23
24
R42
100
1
JP28
SCL-SEL
SCL
PIC18F4550
TQFP 44-PIN
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
38
39
40
41
2
3
4 R72
5
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
PC-CS3N
C63
PC-CS4N
PC-TRXPND
PC-SCLK
PC-SI
PDN
CLKMODE
0
+
C64
10uF
C
0.1uF
VUSB
100
SDA
TP9
SCL
OSC1/CLKI
OSC2/CLKO/RA6
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
32
35
36
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
U6
42
43
44
1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
R41
R43
1
2
3
4
VUSB
DD+
GND
22
22
VUSB
DD+
GND
USB(B type)
PIC18F4550
PDN
R44
1k
D3.3V / 5.0V
R53
0
D3.3V / 5.0V
B
C83
14
2
1
7
1k
74HC14
U7A
10
D3.3V / 5.0V
TP10
TP (Black)
11
+ C66
7
DZF
DVSS
0.1uF
DZF
B
14
LE2
R45
D3.3V / 5.0V
D3.3V / 5.0V
LE1
74HC14
U7E
100uF(A)
K
14
D3.3V / 5.0V
Release
A
ATE1D-2M3
APE 1F
1
6
7
5
R71
7
14
14
4
7
3
74HC14
U7B
13
open
PDN
H
8
C87
9
0.1u
1
Reset
74HC14
U7F
74HC14
U7C
7
SW 1
L
10k
14
SW 2
TP11
MUTEN
3
A
MUTEN
2
PDN
R46
10k
12
R65
D1
HSU119
MUTEN
A
74HC14
U7D
(default : Release)
R47
10k
Title
DGND
<AKD7601A-A>
Size
A3
- 56 -
Date:
5
4
3
2
Document Number
<PC-IF>
Monday, March 05, 2012
Rev
<0>
Sheet
1
5
of
6
4
DVDD
5
3
YELLOW (+3.3V/+5V)
J5
L3
2
1
OPEN :+3.3V/+5V
SHORT:REG
JP29
10uH
DVDD
+ C84
100uF(A)
D
D
OPEN :+5V
SHORT:REG
J1
REG1
J2
LM1084-5V
JP26
2
(SHORT)
+ C72
100uF(A)
AVDD
+ C67
C68
10uF
0.1uF
OUT
GND
L4
HeatSink
IN
(+12V)
Red
(AGND)
Black
1
C71
+ C73
+ C74
3
AVDD
YELLOW (+5V)
0.1uF
J3
10uF
100uF(A)
W IRE1
D3.3V
WIRE OPEN
C
JMP3_1_1
REG2
R48
2
LM1084-3.3V
C76
(DGND)
B
Black
1
C77
0.1uF
0.1uF
D5.0V
10uF
IN
3
+ C75
OUT
VDD-SEL
+ C78
10uF
HeatSink
REG3
B
LM1084-5V
2
+ C79
C80
OUT
GND
0
TP12
TP (Black)
IN
1
C81
3
R49
J4
0
GND
JP40
D3.3V / 5.0V
C
HeatSink
+ C82
1
AVSS
0.1uF
0.1uF
10uF
TP13
TP (Black)
A
DVSS
1
A
10uF
Title
<AKD7601A-A>
Size
A3
- 57 -
Date:
5
4
3
2
Document Number
<POW ER>
Monday, March 05, 2012
Rev
<0>
Sheet
1
6
of
6
- 58 -
- 59 -
- 60 -
- 61 -