AK7734XQ

[AKD7734-A]
AKD7734-A
AK7734 Evaluation Board Rev.1
GENERAL DESCRIPTION
The AKD7734-A is an evaluation board for AK7734, which is an audio processor including a stereo ADC,
a stereo SRC and an audio DSP. This board is composed of a main board and a sub board. It is possible
to control the setting of board via USB port. RCA connector is used for the input and output of analog
signal. This board also has digital interface and can achieve the interface with digital audio system via
optical connector.
„ Ordering guide
AKD7734-A
---
Evaluation board for AK7734
Control software and USB cable are packed with this.
FUNCTION
† Read/Write access to PRAM, CRAM, OFFRAM and registers of AK7734
† Compatible with 2 types of digital audio interface
- Optical input (x1) / Optical output (x1)
- 10pin header for interface with external data source (x2)
† ADC 2ch input (single-end), DAC 8ch output
(Note: There is no DAC within AK7734. 8ch DAC AK4359 is equipped.)
† USB port for board control
+12V
Regulator
Regulator
USB 3.3V
-12V GND
Regulator
3.3V
3.3V
PIC4550
USB
Amp
FPGA
AIN 2ch
AK7734
Regulator
Opt In
(XC95144)
5V
AK4114
AOUT 8ch
AK4359
Opt Out
SMUX1
SMUX2
10 Pin Header
(Note) AK4114 has DIR, DIT and X’tal oscillator.
Figure 1. AKD7734-A Block Diagram
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Evaluation Board Diagram
„ Board Diagram
9
DVSS
TP5
1
9
2
SMUX
PORT1
10
1
9
1
JTAG
2
TP3
10
2
74HC
221A
DGND
D1
Color led
REG1
7734
USB
XILINX
PIC18F
4550
2
W
S
k
n
i
S
t
a
e
H
k
n
i
S
t
a
e
H
2
G
E
R
GND
10
3
G
E
R
+12V
SMUX
PORT2
Header5
-12V
XTAL2
SPDIF
OUT
4114
74HCT541
1
L
A
T
X
AGND
1
W
S
74HCT243
SPDIF
IN
AK4359
REG4
DAC1-L
DAC1-R
DAC2-L
DAC2-R
DAC3-L
DAC3-R
DAC4-L
DAC4-R
AIN-R
TP6
AIN-L
5532
TP2
Figure 2. AKD7734-A Board Diagram
„ Description
(1) AIN/DAC (RCA-JACK)
AIN: These are analog signal input Jacks. The signals are input to AIN pins.
(The white Jack is used for left channel, and the red one is used for right channel.)
DAC: These are analog signal output Jacks. The signals are output from AK4359.
(2) AK4114
AK4114 has DIR, DIT and X’tal oscillator. It transports digital data to AK7734 when working in master mode and
outputs data from AK7734 when working in slave mode.
(3) SPDIF-IN/ SPDIF-OUT
SPDIF-IN: Optical input connector. It supports sampling frequencies from 32kHz to 96kHz for input. It is used as
digital data source for AK7734.
SPDIF-OUT: Optical output connector. It outputs the data from whichever among SDOUT1~4.
(4) Power supply
Connect to +12V, GND and -12V. Current of about 250mA is consumed when normal operation.
(5) PIC18F4550
USB control chip. It is possible to set up the registers of AK7734, Xilinx, AK4359 and AK4114 from PC via USB
port.
(6) SW2
Push type button. It is used to initialize the PICIF4550. When connecting the board to PC, it is required to push down
the button for initialization.
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(7) Xilinx
Xilinx used for data path control. It is possible to run a variety of tests by way of controlling the data path via control
software.
(8) SW1
The SW1 is used to select clock source between [EXT] and [XTL] to change the clock mode of AK7734. The setting
of other jumper pins is according to Table 3 and Table 4.
(9) SMUX port
10 pin header for interface with external data source. Two ports are equipped and available to achieve with other
audio system.
Pin I/O Function
pin
I/O Function
1
I/O MCLK
2
P
GND
3
I/O BITCLK
4
P
GND
5
I/O LRCLK
6
P
GND
7
I
SDTI
8
P
GND
9
P
VDD
10
O
SDTO
Table 1. The assignments of the SMUX port
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Evaluation Board Manual
„ Operation sequence
(1) Set up the power supply lines.
[The jumper pins should be set as following]
JP2
JP1
7734-AVDD 7734-DVDD
(Short)
(Short)
JP6
P-DVDD
JP5
PIC-VDD-SEL
(Short)
5V
Set up the power supply lines.
Name Color
Voltage
+12V
Red
+9∼+12V
-12V
Blue
-9∼-12V
GND
Black
0V
3.3V DVDD
Comment
Regulator,
Power supply for op-amp
Power supply for op-amp
Ground
Table 2. Set up of power supply lines
Attention
This jack is always needed.
Power line
This jack is always needed.
Power line
This jack is always needed.
Each supply line should be distributed from the power supply unit. The power of AK7734 and peripheral device is
supplied by two regulators equipped on the board convert from 12V to 3.3V.
(2) Set up the evaluation mode, jumper pins and connectors. ( according to the follows )
(3) Connect the board to PC with the USB cable packed.
It is required to push down the button (SW2) to initialize the USB control chip.
(4) Power On
(5) Start the control soft and setup the register. ( according to the follows )
„ Evaluation Mode
In case of AK7734 evaluation using AK4114, it is necessary to correspond to audio interface format for
AK7734 and AK4114. About AK7734’s audio interface format, refer to datasheet of AK7734. About
AK4114’s audio interface format, refer to Table 9 in this manual.
Applicable Evaluation Mode
(1)
(2)
(3)
(4)
Evaluation mode of ADC using DIT of AK4114 : CKM Master Mode = 0 (Default)
Evaluation mode of DSP using DIR/DIT of AK4114 : CKM Slave Mode = 2/3
Evaluation mode of SRC using SMUX port : CKM Slave Mode = 3 – 5, 9 – D
Evaluation mode of sound ［tone］ quality using DAC of AK4359
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(1) Evaluation mode of ADC using DIT of AK4114: CKM Master Mode = 0 (Default)
SPDIF-OUT is used. SPDIF-IN should be open. Set the clock mode of AK7734 to Master Mode (12.288MHz).
AK7734 supplies MCLK, BICK, and LRCK to AK4114 and AK4114 outputs the data from SDOUT1.
[The jumper pins should be set as following]
JP101
AK7734 CLKI
EXT-XTI
CRY-XTI
[Set up SW1]
Toggle should be set to “EXT”.
1. Connection of connector
For analog single-end input, AIN-L(W)/AIN-R(R) are available.
For digital output, optical connector PORT2 (SPDIF-OUT) is available.
2. Set up the Xilinx and AK7734/AK4114 control register via PC. (See the Page.11)
(2) Evaluation mode of DSP using DIR/DIT of AK4114: CKM Slave Mode = 2/3
SPDIF-IN and SPDIF-OUT are used. Set the clock mode of AK7734 to Slave Mode (12.288MHz). AK4114
supplies MCLK, BICK, LRCK and digital data to AK7734.
[The jumper pins should be set as following]
JP101
AK7734 CLKI
EXT-XTI
CRY-XTI
[Set up SW1]
Toggle should be set to “XTL”.
1. Connection of connector
For digital input, optical connector PORT1 (SPDIF-IN) is available.
For digital output, optical connector PORT2 (SPDIF-OUT) is available.
2. Set up the FPGA and AK7734 control register via PC. (See the Page.11)
(3) Evaluation mode of SRC using SMUX port: CKM Slave Mode = 3 – 5, 9 – D
PORT1 and PORT2 are used, leave the SPDIF-IN and SPDIF-OUT open.
Set the clock mode of AK7734 to CKM Slave Mode. The necessary clocks for AK7734 are generated by the PLL
based on the clock input to BICK.
[The jumper pins should be set as following]
JP101
AK7734 CLKI
EXT-XTI
CRY-XTI
1. Connection of connector
For digital input, SMUX PORT1 (10pin header) is available. (Each Clock should be connected respectively.)
For digital output, SMUX PORT2 (10pin header) is available.
2. Set up the FPGA and AK7734 control register via PC. (See the Page.11)
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(4) Evaluation mode of sound ［tone］ quality using DAC of AK4359
AK4359 is used. AK7734 supplies MCLK, BICK, LRCK and digital data to AK4359, which converts digital
data to analog signal and output it.
1. Connection of connector
For analog output, RCA3-10 (DAC1-4) is available.
2. Set up the FPGA and AK7734 control register via PC. (See the Page.11)
„ Board control
It is possible to control AKD7734-A via general USB port. Connect the USB port on board to PC with the packed
cable.
Control software is packed with this board. The software operation sequence is included in the evaluation board
manual.
„ Indication for LED
[LED] U9:
[LED] D1:
When power is supplied, LED is lighted to red. Monitor the PC-RQN clock signal and change green
when the board is communicating with PC.
The status of AK7734’s STO pin is displayed. ‘H’ → Light off; ‘L’ → Light on.
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„ Setting of Jumper Pins
(Main board)
Jumper
SW1 (AK4114 Clock)
JP1 (7734-AVDD)
JP2 (7734-DVDD)
JP3 (AGND-GND)
JP5 (PIC-VDD-SEL)
JP6(P-DVDD)
Setting (Default)
Note
AK4114 Clock Source
“XTL”: Crystal Clock
“EXT”: External Clock
Short
AK7734 AVDD
Short
AK7734 DVDD
Short
Short of AGND and DVSS
USB chip power supply
“USB-5V”: USB 5V
“USB-3.3V”
“USB-3.3V”: USB 3.3V
“DVDD”: Peripheral DVDD 3.3V
Short
Peripheral DVDD
Table 3. Setting of jumper pins on main board
“XTL”
(Sub board)
Jumper
JP101(Clock)
JP102(TESTI2)
Setting (Default)
Note
AK7734 Clock Source
“CRY-XTI”: Crystal Clock
“EXT-XTI”: External Clock
Setup of the test pin of AK7734
Short
Please set it to be shorted.
Table 4. Setting of jumper pins on sub board
“EXT-XTI”
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„ Analog Input Circuit
AMP-PW-
C15 +
0.1uF
RCA1
C19
R9
10k
+
T
B
S
R8
10k
C16
10uF
22uF(A)
C23
68pF
MR-552LS(R)
4
SILK-SCREEN
AINR
C17
1
+
+
3
-
2
U2A
NJM5532D
AINR
8
4.7uF(A)
+
C21
0.1uF
C22
10uF
AMP-PW+
RCA2
C20
R10
10k
R11
10k
+
T
B
S
22uF(A)
C24
68pF
C18
7
+
5
U2B
NJM5532D
+
6
-
SILK-SCREEN
AINL
4
MR-552LS(W)
AINL
8
4.7uF(A)
Figure 3. AINL, AINR Input Circuit
For analog single-ended input, RCA1 (AIN-R) / RCA2 (AIN-L) are available.
The input range of each channel is [email protected].
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„ Analog Output Circuit
LOUT1
RCA4
+
C39
22uF
R23
22k
T
B
S
MR-552LS(W)
DAC1
ROUT1
RCA3
+
C40
22uF
R24
22k
T
B
S
MR-552LS(R)
LOUT2
RCA5
+
C41
22uF
R25
22k
T
B
S
MR-552LS(W)
DAC2
RCA6
+
C42
ROUT2
22uF
R26
22k
T
B
S
MR-552LS(R)
RCA7
+
C43
LOUT3
22uF
R27
22k
T
B
S
MR-552LS(W)
DAC3
ROUT3
RCA8
+
C44
22uF
R28
22k
T
B
S
MR-552LS(R)
LOUT4
RCA10
+
C45
22uF
R29
22k
T
B
S
MR-552LS(W)
DAC4
ROUT4
RCA9
+
C46
22uF
R30
22k
T
B
S
MR-552LS(R)
Figure 4. AK4359(DAC) Analog Output Circuit
For analog output, RCA3/4(DAC1), RCA5/6(DAC2), RCA7/8(DAC3) and RCA9/10(DAC4) are available.
The analog output circuit supports single-ended mode and the output range is 3.4Vpp@5V.
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„ Digital Input Circuit (External DIR:PORT1)
Figure 5. Digital Input Circuit (AK4114)
For digital input SPDIF-IN, optical connector PORT1 is available.
„ Digital Output Circuit (External DIT:PORT2)
Figure 6. Digital output circuit (AK4114)
For digital output SPDIF-OUT, optical connector PORT2 is available.
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[AKD7734-A]
Control Software Manual
„ Set-up of the evaluation board and control software
(1) Set up the AKD7734-A according to previous term.
(2) Connect AKD7734-A to PC with the cable packed Push down the reset button (SW1) to initialize the USB chip.
(3) Insert the CD-ROM labeled “AKD7734-A Evaluation Kit” into the CD-ROM drive.
(4) Access the CD-ROM drive and double-click the icon of “AK7734.exe” to set up the program.
(5) Then please evaluate according to the follows.
„ Operation flow
Keep the following flow
1. Set up the control program according to the explanation above.
2. Click “Board Init” button to initialize the board.
3. Select the needed dialogue to evaluate by changing the setting.
If the USB cable is removed when control software is used, please close the software and set up it again when operation
is needed again.
Figure 7. The image of control software
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Control software is possible to execute program downloading, to set up the registers, to set up the FPGA and to process
script file. They can be selected by the tab items above. The buttons of control signals which are frequently used and the
initialization buttons are placed outside the tab dialogue.
[INIT_RESET]:
[S_RESET]:
[ADC]:
[SRC]:
[CK]:
[I2CSEL]
[Board Init]:
[READ]:
Initial Reset. It is used to initialize the AK7734.
System Reset. DSP/ADC/DAC will be set to reset mode but the register will not be initialized.
ADC Reset.
SRC Reset.
Clock Reset. Clock Reset is required when changing the clock mode or the frequency of input clock
without initial reset. The register will not be initialized.
Selector for 3-wire serial control mode or I2C control mode. I2C control mode is selected when the
button is pushed down and 3-wire serial mode is selected when button is released.
The setting of registers of AK7734, FPGA and AK4114 is written to board together.
Read back CONT register or TEST register decided by [Read Select] button and show the result on
register column.
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(1) Download
Figure 8. [Download] Dialogue
File of Source column, Program column, CRAM column or OFFSET column can be selected by clicking the [refer]
button of each column or by way of dropping or tracking files from desktop.
CRAM file or OFFSET file can be selected and be written to CRAM or OFF-RAM by clicking the [refer] button of
CRAM write@operation column or OFF-RAM write@operation column when system is running. The data will be
written to specific address of CRAM or OFF-RAM when the [write] button at right side is clicked.
[Assemble]:
[Write]:
[Assemble Write]:
[PRAM read]:
[CRAM read]:
[Offset read]:
[CRAM SAVE]:
[Offset SAVE]:
[MICR1]:
[MICR2]:
[MICR3]:
[MICR4]:
[JX]:
Compile the source file and the output file will be selected to the download file automatically.
Download the program to AK7734.
Compile the source file and then download the file to AK7734.
Read the data of PRAM to temporary file.
Read the data of CRAM to temporary file.
Read the data of OFF-RAM to temporary file.
Read the data of CRAM and save to file.
Read the data of OFF-RAM and save to file.
Read the data of register MICR1 when program is running and show the result to dialogue.
Read the data of register MICR2 when program is running and show the result to dialogue.
Read the data of register MICR3 when program is running and show the result to dialogue.
Read the data of register MICR4 when program is running and show the result to dialogue.
JX code setting column.
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(2) Register Set up
Figure 9. [REG1] Dialogue
Tab Dialogues of REG1/REG2/REG3 are used to regulate the registers’ setting. (It is prohibited to process test and
reserved items.)
As the checkbox is clicked, the data is written to the register after system reset.
The reference pages of registers in datasheet are as following:
Register
CONT00
CONT01
CONT02
CONT03
CONT04
CONT05
Reference page
Register
Reference page
27
CONT06
33
28
CONT07
34
29
CONT08
35
30
CONT09
36
31
CONT0A
37
32
CONT10-11
38
Table 5. Reference page of registers
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(3) FPGA Set up
Figure 10. [FPGA1] Dialogue
The FPGA1/FPGA2 dialogues are used to regulate the data path of AK7734 and the setting of AK4114 via FPGA.
FPGA Set up (It is prohibited to process test and reserved items.)
ADDRESS = 0 (A [1:0] = 00)
Bit
Function
D[13:12]
TX-DAT
D[11:10]
SDIN1
D[9:7]
SDIN2/JX0
Default: bold type
Description
Output data source for AK4114
00 : SDOUT1
01 : SDOUT2
10 : SDOUT3
11 : SDOUT4
Input data source to SDIN1 pin of AK7734
00 : AK4114 IN (RX_DAT)
01 : SMUX1_DAT1
10 : SMUX2_DAT1
11 : Low
Input data source to SDIN2/JX0 pin of AK7734
000 : AK4114 IN (RX_DAT)
001 : SMUX1_DAT1
010 : SMUX2_DAT1
011 : Low
100 : Low
101 : High
110 : Low
111 : Low
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D[6:4]
SDIN3/JX1
D[3:1]
SDIN4/JX2
D[0]
DAC-PDN
ADDRESS = 1 (A [1:0] = 01)
Bit
Function
D[15:12]
CKM[3:0]
D[11:10]
BICK1/LRCK1
D[9:8]
BICK2/LRCK2
D[7:6]
EXT-XTI
Input data source to SDIN3/JX1 pin of AK7734
000 : AK4114 IN (RX_DAT)
001 : SMUX1_DAT1
010 : SMUX2_DAT1
011 : Low
100 : Low
101 : High
110 : Low
111 : Low
Input data source to SDIN4/JX2 pin of AK7734
000 : AK4114 IN (RX_DAT)
001 : SMUX1_DAT1
010 : SMUX2_DAT1
011 : Low
100 : Low
101 : High
110 : Low
111 : Low
Power Switch of AK4359
0 : Low
1 : High
Table 6. FPGA Set up table1
Description
Clock mode of AK7734
Mode-0: XTI - MASTER 12.288MHz
Mode-1: XTI - MASTER 18.432MHz
Mode-2: XTI - SLAVE 12.288MHz
Mode-3: BICK1 - SLAVE 64fs ( fs = 48kHz )
Mode-4: BICK1 - SLAVE 32fs ( fs = 8kHz )
Mode-5: BICK1 - SLAVE 64fs ( fs = 8kHz )
Mode-6: TEST N/A
Mode-7: TEST N/A
Mode-8: TEST N/A
Mode-9: BICK1 – SLAVE 48fs ( fs = 48kHz )
Mode-A: BICK1 – SLAVE 48fs ( fs = 8kHz )
Mode-B: BICK2 – SLAVE 64fs ( fs = 48kHz )
Mode-C: BICK2 – SLAVE 32fs ( fs = 8kHz )
Mode-D: BICK2 – SLAVE 64fs ( fs = 8kHz )
Mode-E: TEST N/A
Mode-F: TEST N/A
Input switch of AK7734’s BICK1/LRCK1
00 : AK4114 BICK/LRCK
01 : SMUX1_BICK/LRCK
10 : SMUX2_BICK/LRCK
11 : Low
Input switch of AK7734’s BICK2/LRCK2
00 : AK4114 BICK/LRCK
01 : SMUX1_BICK/LRCK
10 : SMUX2_BICK/LRCK
11 : Low
Input switch of AK7734’s XTI
00 : AK4114 RX_CLK
01 : SMUX1_MCLK
10 : SMUX2_MCLK
11 : Low
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D[5]
D[4]
D[3]
D[2]
TRXPDN
Power Switch of AK4114
0 : Low
1 : High
TRX-BICK/LRCK
Switch of I/O direction of the AK4114’s BICK/LRCK
0 : BIT, LR input
1 : BITCLKO/LRCLKO output
SMUX2 In/Out
Switch of I/O direction of the SMUX2’s BICK/LRCK
0 : BIT, LR input
1 : BITCLKO/LRCLKO output (7734)
SMUX1 In/Out
Switch of I/O direction of the SMUX1’s BICK/LRCK
0 : BIT, LR input
1 : BITCLKO/LRCLKO output (7734)
Table 7. FPGA Set up table2
ADDRESS = 2 ( A[1:0] = 10 )
Bit
Function
D[15:14]
SMUX2_DAT2
D[13:12]
SMUX1_DAT2
D[11:10]
TX-CLK
D[9]
SETSRC
D[8:7]
CAD[1:0]
D[6:5]
SMUX2_MCLK
D[4:3]
SMUX1_MCLK
D[2:0]
Reserved
Description
Output data source for DAT2 pin of port SMUX2
00 : SDOUT1
01 : SDOUT2
10 : SDOUT3
11 : SDOUT4
Output data source for DAT2 pin of port SMUX1
00 : SDOUT1
01 : SDOUT2
10 : SDOUT3
11 : SDOUT4
Input switch of AK4114’s CLK
00 : AK7734 CLKO
01 : SMUX1_MCLK
10 : SMUX2_MCLK
11 : Low
Low/High setup of AK7734’s SETSRC pin
0 : Low
1 : High
Set up of AK7734’s CAD1-0 pins
00 : Low, Low
01 : Low, High
10 : High, Low
11 : High, High
Input switch of SMUX2’s MCLK
01 : AK7734-CLKO
10 : AK4114_RX_CLK
11 : SMUX1_MCLK
Input switch of SMUX1’s MCLK
01 : AK7734-CLKO
10 : AK4114_RX_CLK
11 : SMUX2_MCLK
Table 8. FPGA Set up table3
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Function
MCLK
CM
DIF
Description
Frequency of main clock output from AK4114
00: 265fs
01: 256fs
10: 512fs
11: 128fs
Master clock operation mode of AK4114
00: CM = 00
01: CM = 01
10: CM = 10
11: CM = 11
Format setup of AK4114 I/O
000: 16bit Right( O )
001: 18bit Right( O )
010: 20bit Right( O )
011: 24bit Right( O )
100: 24bit Left( O )
101: 24bit I2S( O )
110: 24bit Left( I )
111: 24bit I2S( I )
Table 9. AK4114 Set up
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(4) Script
Figure 11. [SCRIPT] Dialogue
As the script file is selected, it is executed directly. If [Repeat] button is clicked, the selected script file will be executed
once again.
The script commands are listed as follow.
Command
[SCRIPT]
;Comment
W,<address>,<data>
W,0xC0,0x00
WL,<command>,<address>,<data>,…
WL,0x82,0x0022,0x4000,0x4000,0x4000,
D,<address>,<data>
X,<address>,<data>
P,<message>
RI: H / RI:L
RA:H / RA:L
RD:H / RD:L
R2:H / R2:L
T,<wait>
T,50mS
LP:<filename>
LC:<filename>
LO:<filename>
Description
Header of script file. The script file will be compiled to error without this header.
The content after semicolon is ignored as comment.
Write data to register. Both address and data must be BYTE(8bit).
Write data continuously. It can be used when CRAM is running. The command
must be BYTE(8bit) and the data below must be WORD(16bit).
Write data to AK4114.
Write data to the register of FPGA.
Show message and pause the processing of script.
Init reset.
ADC reset.
DSP reset.
Select for I2C bus mode
Wait some milliseconds.
When actual operation, it is possible to wait longer than this.
Download program file to DSP.
Download CRAM file to DSP.
Download OFRAM file to DSP.
Table 10. Script Command
<KM094003>
2011/07
- 19 -
[AKD7734-A]
Measurement Results
[Measurement condition]
・ Measurement unit
・ MCKI
・ BICK
・ fs
・ Bit
・ Measurement Mode
・ Power Supply
・ Input Frequency
・ Measurement Frequency
・ Temperature
: Audio Precision, System two Cascade
: 12.288MHz
: 64fs
: 8kHz/48kHz
: 24bit
: Master Mode, CKM Mode 0
: +12V, -12V, GND
: 1kHz
: 20 ~ 20kHz
: Room
[Measurement Results]
1. ADC BW=20Hz∼4kHz@fs=8kHz
Result
ADC: AIN => ADC
S/(N+D) (-1dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
Lch
Rch
92.6
97.6
97.7
92.6
97.6
97.7
Unit
dB
dB
dB
2. ADC BW=20Hz∼20kHz@fs=48kHz
Result
ADC: AIN => ADC
S/(N+D) (-1dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
<KM094003>
Lch
Rch
83.6
97.2
97.3
83.6
97.2
97.3
Unit
dB
dB
dB
2011/07
- 20 -
[AKD7734-A]
[Plot Data]
1. FFT Input -1dB (fs=8kHz)
AK7734 AIN=>ADC=>SDTO FFT
fs=8kHz, fin=1kHz,-1dB
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
4k
1k
2k
4k
Hz
Figure 1. FFT ( 1kHz, -1dBFS )
2. FFT Input -60dB (fs=8kHz)
AK7734 AIN=>ADC=>SDTO FFT
fs=8kHz, fin=1kHz,-60dB
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
Hz
Figure 2. FFT ( 1kHz, -60dBFS )
<KM094003>
2011/07
- 21 -
[AKD7734-A]
3. FFT No Input (fs=8kHz)
AK7734 AIN=>ADC=>SDTO FFT
fs=8kHz, No Signal
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
4k
Hz
Figure 3. FFT ( No Input )
4. THD+N vs. Input Level (fs=8kHz)
AK7734 AIN=>ADC=>SDTO THD+N vs. Input Level
fs=8kHz, fin=1kHz
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 4. THD+N vs. Input Level
<KM094003>
2011/07
- 22 -
[AKD7734-A]
5. THD+N vs. Input Frequency (fs=8kHz)
AK7734 AIN=>ADC=>SDTO THD+N vs. Input Freq
fs=8kHz, fin=-1dB
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
4k
Hz
Figure 5. THD+N vs. Input Frequency
6. Linearity (fs=8kHz)
AK7734 AIN=>ADC=>SDTO Linearity
fs=8kHz, fin=1kHz
+0
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-100
-80
-60
-40
-20
+0
dBr
Figure 6. Linearity
<KM094003>
2011/07
- 23 -
[AKD7734-A]
7. Frequency Response (fs=8kHz)
AK7734 AIN=>ADC=>SDTO FrequencyResponse
fs=8kHz, fin=-1dB
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
3k
1k
2k
3k
Hz
Figure 7. Frequency Response
8. Crosstalk (fs=8kHz)
AK7734 AIN=>ADC=>SDTO Crosstalk
fs=8kHz, fin=1kHz,-1dB
-60
TTTT
TTTTT
TTTT
TTTT T
T
T
T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
Hz
Figure 8. Crosstalk
<KM094003>
2011/07
- 24 -
[AKD7734-A]
9. FFT Input -1dB (fs=48kHz)
AK7734 AIN=>ADC=>SDTO FFT
fs=48kHz, fin=1kHz,-1dB
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 9. FFT ( 1kHz, -1dBFS )
10. FFT Input -60dB (fs=48kHz)
AK7734 AIN=>ADC=>SDTO FFT
fs=48kHz, fin=1kHz,-60dB
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
Hz
Figure 10. FFT ( 1kHz, -60dBFS )
<KM094003>
2011/07
- 25 -
[AKD7734-A]
11. FFT No Input (fs=48kHz)
AK7734 AIN=>ADC=>SDTO FFT
fs=48kHz, No Signal
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k
20k
-10
+0
Hz
Figure 11. FFT ( No Input )
12. THD+N vs. Input Level (fs=48kHz)
AK7734 AIN=>ADC=>SDTO THD+N vs. Input Level
fs=48kHz, fin=1kHz
-70
-72.5
-75
-77.5
-80
d
B
F
S
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 12. THD+N vs. Input Level
<KM094003>
2011/07
- 26 -
[AKD7734-A]
13. THD+N vs. Input Frequency (fs=48kHz)
AK7734 AIN=>ADC=>SDTO THD+N vs. Input Freq
fs=48kHz, fin=-1dB
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 13. THD+N vs. Input Frequency
14. Linearity (fs=48kHz)
AK7734 AIN=>ADC=>SDTO Linearity
fs=48kHz, fin=1kHz
+0
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-100
-80
-60
-40
-20
+0
dBr
Figure 14. Linearity
<KM094003>
2011/07
- 27 -
[AKD7734-A]
15. Frequency Response (fs=48kHz)
AK7734 AIN=>ADC=>SDTO Frequency Response
fs=48kHz, fin=-1dB
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 15. Frequency Response
16. Crosstalk (fs=48kHz)
AK7734 AIN=>ADC=>SDTO Crosstalk
fs=48kHz, fin=1kHz,-1dB
-60
TT
T
T TTTTTTTTTT
T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 16. Crosstalk
<KM094003>
2011/07
- 28 -
[AKD7734-A]
REVISION HISTORY
Date
(yy/mm/dd)
08/09/08
Manual
Revision
KM094001
Board
Revision
0
Reason
Page
Contents
First edition
10/02/01
KM094002
1
Device Rev. changed
1
Error Correction
6
AK7734: Rev.A → Rev.B
The logic of the lighting LED_D1 was reversed:
‘H’ → Light off; ‘L’ → Light on.
11/07/06
KM094003
1
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
<KM094003>
2011/07
- 29 -
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
CN103
48pin_3
C123
0.1uF
1
1
TP123
SCK
TP124
SDA
TP125
SI
TP126
RQN
TP127
SDIN4
TP128
BICKI2
TP129
TP130
LRCKI2 SO
TP131
STO
R122
51
R123
51
R124
51
R125
51
R126
51
R127
51
R129
51
D
R130
51
All test pins don't need to be mounted
26
25
R128
51
27
28
29
30
31
32
33
35
36
34
+
1
(open)
TP121
AVDRV
U100
1
C118
1
C120
1
10uF
1
1uF(DIP)
1
1
C119
1
C117
1
+
100uF
TP122
DVDD3
DGND
D
CN102
STO
SO/RDY
LRCLKI2
BITCLKI2
JX2/SDIN4
RQN/CAD1
SRCLFLT
SI/CAD0
SDA
SCLK/SCL
37
37
DVDD
TP132 1
SRCLFLT
VSS3
AVDRV
48pin_4
CLKO
C110
1uF(DIP)
38 VSS4
38
C109
10uF
BITCLKO
+
39
39
DVDD
LRCLKO
40
CKM3
22
22
CKM0
SETSRC
INITRSTN
21
20
R116 51
42
42
TESTI2
I2CSEL
1
TP104 AINR
19
19
TP116 1
DVDD2
AK7734
43
43
AINR
DVDD
18
18
1
TP103 AINL
C115 +
0.1uF
44
44
AINL
VSS2
45
45
46
100uF
SDOUT1
46
+
C103
2.2uF
VCOM
SDOUT2
47
VSS5
SDOUT3
XTI
VSS1
DVDD
LRCLKI1
R111 51
TP114 1
SDOUT2
R112 51
TP113 1
SDOUT3
R113 51
TP112 1
SDOUT4
17
15
14
B
14
13
13
XTO
SDOUT4
BITCLKI1
JX0/SDIN2
SDIN1
CKM1
CKM2
TESTI1
LFLT
JX1/SDIN3
48
R110 51
15
C101
12nF
48
100uF
TP115 1
SDOUT1
+
16
C102
0.1uF
47
C125
16
C104 TP102 1
0.1uF VCOM
10uF
B
AVDD
C116
10uF
17
1
TP101 AVDD
+
TP117 1
RSTN
20
R132 51
C105
C
21
R117 51
41
+
TP118 1
LRCKO
23
R103 51
41
C121
R119 51
23
R118 51
40
JP102
TESTI2
TP119 1
BICKO
24
R101 51
C
R120 51
24
C108
0.1uF
+
TP111 1 C122
DVDD4 100uF
R121 51
TP120 1
CLKO
12
11
10
9
8
7
6
5
4
3
1
2
48pin_2
CN104
C111
0.1uF
C114
+
C112
R109
51
TP105
TP106
TP107
TP108
TP110
SDIN1
SDIN2
SDIN3
BICKI1
LRCKI1 DVDD1
1
TP109
10uF
CRY-XTI
R108
51
EXT-XTI
R107
51
1
R106
51
1
R105
51
1
R104
51
1
R102
51
1
R131
51
JP101
XTI-SEL
R115
A
22pF(DIP)
Y101
12.288MHz
0
C113
R114
51
A
22pF(DIP)
+
C124
AGND
12
11
10
9
8
7
6
5
4
3
2
1
100uF
CN101
48pin_1
Title
- 30 -
Size
A3
Date:
5
4
3
2
AKD7734-SUB-48LQFP
Document Number
Rev
0
AK7734
Friday, May 09, 2008
Sheet
1
1
of
1
5
4
3
7734-DVDD
SCLK
PC-SDA
SI
2
RQN
SDIN4
BICKI2
LRCKI2
SO
1
STO
25
26
27
28
29
30
31
32
33
34
35
36
CN3
48pin_3
DGND
D
D
DVDD
JP2
7734-DVDD
->7734-DVDD
CN2
48pin_4
Show direction
using the arrow
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
13
CLKO
7734-DVDD
BICKO
CKM3
C
LRCKO
SETSRC
C
CKM0
TESTI2
RSTN
I2CSEL
AINR
7734-DVDD
AINL
AVDD
JP1
SDOUT1
->7734-AVDD
B
SDOUT2
Show direction
using the arrow
B
SDOUT3
SDOUT4
48pin_2
CN4
A
A
12
11
10
9
8
7
6
5
4
3
2
1
AGND
Title
- 31 -
CN1
48pin_1
TESTI1
CKM2
CKM1
SDIN1
SDIN2
SDIN3
BICKI1
LRCKI1
Size
A3
7734-DVDD
EXT-XTI
Date:
5
4
3
2
AKD7734-A
Document Number
Rev
0
AK7734
Friday, May 09, 2008
Sheet
1
1
of
1
5
4
3
2
1
D
D
RCA4
+
C39
22uF
U5
MR-552LS(W)
DAC1
U3
C26
0.1uF
+ C28
10uF
1
U4
51
2
BICK
DZF2
29
51
3
SDTI1
AVDD
28
R15
51
4
LRCK
AVSS
27
R16
51
5
RSTB
VCOM
26
R21
51
6
SMUTE/CSN/CAD0
LOUT1
25
R17
51
7
ACKS/CCLK/SDL
ROUT1
24
R22
51
8
DIF0/CDTI/SDA
P/S
23
R18
51
9
SDTI2
LOUT2
22
R19
51
10
SDTI3
ROUT2
21
R20
51
11
SDTI4
LOUT3
20
12
DIF1
ROUT3
19
13
DEM0
LOUT4
18
C43
NC
GBA
13
3
1A
NC
12
PC-CS4N
4
2A
1B
11
PC-SCLK
5
3A
2B
10
PC-SI
6
4A
3B
09
7
GND
4B
08
DAC-PDN
C27
0.1uF
14
DVDD
ROUT4
17
15
DVSS
DEM/I2C
16
+ C29
10uF
+ C30
10uF
C25
0.1uF
C32
0.1uF
+ C31
10uF
C34
0.1uF
C33
10uF
22uF
R24
22k
T
B
S
MR-552LS(R)
C41
RCA5
22uF
R25
22k
T
B
S
MR-552LS(W)
DAC2
C
C42
RCA6
22uF
R26
22k
T
B
S
MR-552LS(R)
22uF
RCA7
R27
22k
T
B
S
MR-552LS(W)
DAC3
AK4359
C44
RCA8
+
2
30
DZF1
R14
DVDD-DAC
14
MCLK
R13
C
VCC
RCA3
+
20
10
51
DVDD-DAC
GAB
C40
VDD-DAC
R12
74HCT541
1
R23
22k
+
VCC
GND
18
17
16
15
14
13
12
11
+
G1
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
+
1
19
A1
A2
A3
A4
A5
A6
A7
A8
+
2
3
4
5
6
7
8
9
CLKO
BICKO
SDOUT1
LRCKO
SDOUT2
SDOUT3
SDOUT4
T
B
S
22uF
74HCT243
R28
22k
T
B
S
MR-552LS(R)
JP3
GND
C45
RCA10
+
B
22uF
R29
22k
B
T
B
S
MR-552LS(W)
DAC4
DVDD-DAC
AMP-PW+
VDD-DAC
C46
LM1117-5V
RCA9
10
2
+ C38
10uF
OUT
3
R31
GND
+
REG4
C36
0.1uF
IN
1
22uF
C35
0.1uF
+ C37
10uF
R30
22k
T
B
S
MR-552LS(R)
SILK-SCREEN
AGND
TP2
TP(BLACK)
A
1
A
Title
- 32 -
Size
A3
Date:
5
4
3
2
AKD7734-A
Document Number
Rev
0
DAC
Thursday, May 01, 2008
Sheet
1
1
of
1
5
4
3
2
1
D
D
DVDD-3.3V
DVDD-3.3V
C1
+
SILK-SCREEN
SPDIN-IN
C2
L1
10uF
10uH
0.1uF
PORT1
SPDIF-IN
3
2
1
VCC
GND
OUT
R2
470
C3
R1
DIF-RX
0.1uF
18k
TORX141
SPDI/F Optical in
1
2
3
4
5
6
7
8
9
10
11
12
DVDD-3.3V
SILK-SCREEN
SPDIN-OUT
RX4
NC1
RX5
TEST2
RX6
NC3
RX7
IIC
P/SN
XTL0
XTL1
VIN
AK4114
13
14
15
16
17
18
19
20
21
22
23
24
L2
36
35
34
33
32
31
30
29
28
27
26
25
INT0
CSN
CCLK
CDTI
CDTO
PDN
XTI
XTO
DAUX
MCKO2
BICK
SDTO
EXT
TX-CLK
XTL
R3
R4
R5
100
100
100
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
XTAL1
22pF
C6
22pF
C7
AK4114
10uH
IN
VCC
GND
SW1
TRX-PDN
12.288MHz
PORT2
SPDIF-OUT
C
PC-CS3N
PC-SCLK
PC-SI
TVDD
NC4
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
DVSS
MCKO1
LRCK
C
RX3
NC6
RX2
TEST1
RX1
NC5
RX0
AVSS
VCOM
R
AVDD
INT1
U1
48
47
46
45
44
43
42
41
40
39
38
37
C5
10uF
+
C4
0.1uF
R6
100
R7
100
TRX-LRCK
RX-CLK
DIF-TX
3
2
1
C8
0.1uF
0.1uF C9
C12
10uF
10uF
TOTX141
SPDI/F Optical out
C10 +
0.1uF
C11
10uF
DVDD-3.3V
SILK-SCREEN
DVSS
DVSS
C13
B
+
+
B
DVDD-3.3V
DVDD-3.3V
1
TP1
TP(BLACK)
+
C14
100uF/16V(A)
A
A
Title
- 33 -
Size
A3
Date:
5
4
3
2
AKD7734-A
Document Number
AK4114
Friday, May 02, 2008
Rev
0
Sheet
1
2
of
8
5
4
3
2
1
AREA : SHORTEST WIRING
D
D
AMP-PW-
C15 +
0.1uF
C19
RCA2
R9
10k
22uF(A)
C20
T
B
S
+
T
B
S
R8
10k
C23
68pF
R10
10k
R11
10k
+
RCA1
C16
10uF
22uF(A)
C24
68pF
MR-552LS(W)
4
6
U2B
NJM5532D
C18
7
-
5
AINL
C
4.7uF(A)
8
+
AINR
+
1
+
3
SILK-SCREEN
AINL
C17
-
2
U2A
NJM5532D
+
C
SILK-SCREEN
AINR
4
MR-552LS(R)
8
4.7uF(A)
+
C21
0.1uF
C22
10uF
AMP-PW+
B
B
A
A
Title
- 34 -
Size
A3
Date:
5
4
3
2
AKD7734-A
Document Number
Rev
0
ANALOG-IN
Wednesday, May 21, 2008
Sheet
1
4
of
8
5
4
3
2
1
R32 10k
+
+
USB-VDD
C49
10uF
C61
10uF
D
R50
100k
D
C50
0.1uF
R33
10k
18
12
13
33
34
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
30
31
OSC1/CLKI
OSC2/CLKO/RA6
25
26
27
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
1
2
3
4
5
17
16
15
14
11
10
9
8
SILK-SCREEN
1: USB-5V
3: USB-3.3V
5: DVDD
2
4
6
29
JP4
MCLR_N/Vpp/RE3
SILK-SCREEN
1: VDD
2: MCLR
3: PGD
4: PGC
5: GND
1
3
5
USB-RST
VSS1
APE 1F
VDD1
VSS0
6
7
VDD0
SW2
Up
:Release
Down :Push Down
C48
0.1uF
28
C47
0.1uF
U6
default 3-4 pin short
JP5
PIC-VDD-SEL
DVDD-3.3V
HEADER 5
C51 22pF
C
DVDD-3.3V
R34
10k
R35
C57
470nF
37
PIC18F4550
TQFP 44-PIN
19
20
21
22
23
24
PC-SCL
PC-SO
38
39
40
41
2
3
4
5
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
32
35
36
PC-CS3N
PC-INITRSTN
PC-CS4N
PC-I2CSEL
PC-SCLK
PC-SI
PC-RQN
PC-CS2N
REG1
LM1117-3.3V
1
+
VUSB
100
PC-SDA
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
C55
C53
10uF
0.1uF
GND
C52 22pF
IN
OUT
2
C
C54
3
XTI
XTO
XTAL2
20MHz
C56
+
0.1uF
10uF
U7
R39
R40
42
43
44
1
VUSB
DD+
GND
22
22
1
2
3
4
VUSB
DD+
GND
USB(B type)
PIC18F4550
B
B
DVDD-3.3V
SILK-SCREEN
DVSS
DVDD-3.3V
DVDD-3.3V
TP3
TP(BLACK)
U8A
+
R36
C60
0.1uF
LED-IND
10k
VCC
CEXT
15
REXT/CEXT
U8B
16
6
C58
33uF(A)
1
2
3
8
A
B
CLR
GND
U9
13
Q
4
Q
R37
R38
100
100
1
3
7
GREEN
COM
2
9
10
11
8
RED
BICOLOR LED
74HC221
C59
+
VCC
CEXT
100uF/16V(A)
1
16
14
REXT/CEXT
A
B
CLR
GND
74HC221
Q
5
Q
12
A
A
Title
- 35 -
Size
A3
Date:
5
4
3
2
AKD7734-A
Document Number
PC I/F
Friday, May 02, 2008
Sheet
1
Rev
0
6
of
8
5
4
3
2
1
D
D
AMP-PW+
DVDD
AVDD
2
C63
0.1uF
+ C66
10uF
OUT
C64
0.1uF
TM1
1
IN
1
C65
0.1uF
3
+ C62
10uF
LM1084-3.3V
GND
SILK-SCREEN
CHIP-DGND
TP4
TP(BLACK)
REG2
L3
10uH
+ C67
10uF
+
i
RED(+12V)
TJ-563
C68
100uF/16V(A)
1
TM2
1
i
BLACK(GND)
TJ-563
+
C69
100uF/16V(A)
TM3
1
SILK-SCREEN
P-DVDD
2 PIN: [->]
C
i
BLUE(-12V)
TJ-563
AMP-PWC
DVDD-3.3V
JP6
P-DVDD
REG3
TP5
TP(BLACK)
2
1
+ C70
10uF
C71
0.1uF
OUT
SILK-SCREEN
AGND
LM1084-3.3V
IN
TP6
TP(BLACK)
1
C72
0.1uF
1
2
1
GND
default short
3
SILK-SCREEN
DVSS
+ C73
10uF
B
B
A
A
Title
- 36 -
Size
A3
Date:
5
4
3
2
AKD7734-A
Document Number
Rev
0
POWER
Wednesday, April 30, 2008
Sheet
1
7
of
8
5
4
3
2
1
DVDD-3.3V
SMUX-DVDD
SMUX PORT1
C74
0.1uF
+ C75
10uF
JP7
D
SMUX-MCLK
SMUX-BICK
SMUX-LRCK
SMUX-DAT1
1
3
5
7
9
D
2
4
6
8
10
SILK-SCREEN
SMUX PORT/SMUX PORT2
1: MCLK
3: BIT
5: LR
7: DI
10: DO
HEADER 5X2
SMUX-DAT2
SMUX PORT2
U10
TESTI1
CKM2
CKM1
SDIN1
SDIN2
SDIN3
BICKI1
LRCKI1
EXT-XTI
DAC-PDN
TRX-PDN
TX-CLK
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
TRX-LRCK
RX-CLK
C
PC-SO
PC-SCL
PC-SDA
PC-INITRSTN
PC-I2CSEL
PC-SI
PC-RQN
PC-CS2N
LED-IND
R64
R61
R60
R59
R65
R66
R67
51
51
51
51
51
51
51
R63
R62
51
51
R56
R58
51
51
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
25
28
29
30
32
33
34
35
36
37
39
40
41
42
43
46
49
50
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
JP8
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
I/O72
52
53
54
55
56
58
59
60
61
63
64
65
66
67
68
70
71
72
73
74
76
77
78
79
80
81
82
85
86
87
89
90
91
92
93
94
95
96
97
VINT0
VINT1
VINT2
5
57
98
VIO0
VIO1
VIO2
VIO3
26
38
51
88
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
21
31
44
62
69
75
84
100
SMUX2-MCLK
SMUX2-BICK
SMUX2-LRCK
SMUX2-DAT1
1
3
5
7
9
C87
0.1uF
2
4
6
8
10
HEADER 5X2
SMUX2-DAT2
R55
R54
R53
R52
51
51
51
51
R51
51
R49
51
R42
R43
R44
51
51
51
R45
R46
R47
R48
51
51
51
51
SO
LRCKI2
BICKI2
SDIN4
RQN
SI
C
DVDD-3.3V
SCLK
CKM3
SETSRC
TESTI2
CLKO
BICKO
LRCKO
CKM0
RSTN
I2CSEL
D1
STO
2
1
R41
2
470
1
LEAD RED LED
SDOUT1
SDOUT2
SDOUT3
SDOUT4
DVDD-3.3V
B
PC-SCLK
R57
51
99
2
1
4
3
27
23
22
GSR
GTS4
GTS3
GTS2
GTS1
GCK3
GCK2
GCK1
JP9
1
3
5
7
9
TCK
TDI
TDO
TMS
C77
0.1uF
C78
0.1uF
+ C79
10uF
C80
0.1uF
C81
0.1uF
C82
0.1uF
C83
0.1uF
+ C84
10uF
DVDD-3.3V
JTAG
C85
48
45
83
47
2
4
6
8
10
C76
0.1uF
B
0.1uF
TP8
DVSS
1
TP7
DVSS (BLACK)
XC95144XL
DVDD (RED)
1
A
DVDD-3.3V
+ C86
100uF/16V(A)
A
Title
- 37 -
Size
A3
Date:
5
4
3
2
Document Number
AKD7734-A
XILINX
Wednesday, May 21, 2008
Sheet
1
Rev
0
8
of
8
- 38 -
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