AK7736BVQ

[AKD7736B-A]
AKD7736B-A
AK7736B Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD7736B-A is an evaluation board for the AK7736B that is an audio processor with a 2ch SRC. This
board consists of a main board and a sub board. It is possible to control by a PC via USB port. This board
has digital interfaces enabling to interface with digital audio systems via optical connector, ADC-Port,
DAC-Port and EXT-Port.
■ Ordering guide
AKD7736B-A ---
AK7736B Evaluation board
The AK77XX-HF-CONTROL-BOX, Control software and USB cable are
included in this package.
FUNCTION
† Read/Write access to PRAM, CRAM, OFFRAM and registers of the AK7736B
† Compatible with 2 types of digital audio interface
- Optical input (x1) / Optical output (x1)
- 10-pin header (x2) and 44-pin header (x1) for interface with external data source
† USB port for board control
+3.3V GND
Regulator
1.8V
10 Pin Header
CONTROL
FPGA
Opt In
AK7736B
EXT
(XC95288XL)
AK4118A
Opt Out
44 Pin Header
ADC
DAC
10 Pin Header
Figure 1. AKD7736B-A Block Diagram
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Evaluation Board Diagram
■ Board Diagram
(4)
(3)
(5)
(6)
(7)
(2)
(8)
(1)
(9)
(10)
(11)
(12)
(19)
(18)
(17)
(16) (15)
(14)
(13)
Figure 2. AKD7736B-A Board Diagram
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■ Description
No.
(1)
(2)
Name
AKD7736B-A-SUB
Interface select
(3-pin header x 13)
Function
Connector for the AKD7736B-A-SUB board.
Interface selector of the AK7736B.
EXT: EXT port;
Xilinx: ADCport, DACport
No
Name
AK7736B
JP15
DI4
SDIN4
JP18
DI3
SDIN3
JP11
DI2C
SDIN2C
JP10
DI2B
SDIN2B
JP9
DI2A
SDIN2A
JP8
DI1
SDIN1
JP20
LR3
LRCLKI3
JP19
BTI3
BITCLKI3
JP17
LR2
LRCLKI2/JX2
JP16
BTI2
BITCLKI2/JX1
JP14
LR1
LRCLK1
JP13
BT1
BITCLK1
JP12
XT1
XTI
(3)
EXT port
J1 (44-pin header)
XC95288XL
U6(xilinx)
DAC port
JP3 (10-pin header)
44-pin header for external interface
When using this connector, jumper pins of (2) must be shorted to Xilinx.
FPGA for data path controlling
Various operations are available by setting the control software.
10-pin header for external interface
Interfacing to external digital audio devices.
Pin
I/O Function
Pin
I/O Function
1
O
MCLK
2
P
GND
3
O
BITCLK
4
P
GND
5
O
LRCLK
6
O
SDTI1
7
Open
8
O
SDTI2
9
O
SDTI4
10
O
SDTI3
ADC port
JP2 (10-pin header)
10-pin header for external interface
Interfacing to external digital audio devices.
Pin
I/O Function
Pin
1
I/O MCLK
2
3
I/O BITCLK
4
5
I/O LRCLK
6
7
I
SDTO1
8
9
I
SDTO2
10
(4)
(5)
(6)
(7)
(8)
JTAG port
JP21(10-pin header)
CONTROL port
JP1 (10-pin header)
I/O
P
P
-
Function
GND
GND
Open
Open
open
10-pin header for Xilinx access
Do not use.
10-pin header for AK7736B control
Normally, connect the AKD77XX-HF-CONTROL-BOX to interface to a PC
via USB port.
Pin
I/O Function
Pin
I/O Function
1
P
GND
2
P
+3.3V
3
I
HOST
4
I
RQN
5
I
SCK/SCL
6
I
SI
7
I/O XCS/SDA
8
O
SO
9
I
CSN
10
RESET
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(9)
5 DIP Switches
S2
(10)
VDD Jumper
JP6 (2-pin header)
(11)
P-TVDD Jumper
JP5 (3-pin header)
(12)
Optical Connector
PORT1, PORT2
(13)
AK4118A
U1
7 DIP Switches
S1
(14)
(15)
Toggle Switch
SW1
(16)
P-DVDD Jumper
JP7 (2-pin header)
(17)
+3.3V power supply
TM1
GND
TM2
TVDD Jumper
JP4 (2-pin header)
(18)
(19)
DIP switches for the AK7736B pin setting (L/H).
No
Name
AK7736B
1
TESTI3
TESTI3(6 pin)
2
TESTI1
TESTI1(1 pin)
3
TESTI2
TESTI2(46 pin)
4
JX0
JX0(43 pin)
5
I2C
I2CSEL(19 pin)
Jumper pin for VDD power supply of the AK7736B.
Open: Supply from the VDD test pin
Short: +3.3V
Jumper pin for S2 and level shifter power supply
3.3VShort: +3.3V
1.8VShort: +1.8V
SPDIF-IN (Input): Optical digital signal (Fs: 8~48kHz) is input to the AK4118A.
SPDIF-OUT (Output): Optical digital signal (Fs: 8~48kHz) is output from the
AK4118A.
AK4118A (Digital Audio Transceiver)
DIP Switch for pin settings (L/H) of the AK4118A.
Refer to the “AK4118A Setting” for details
No
Name
AK4118A
1
CM0
CM0(32 pin)
2
CM1
CM1(33 pin)
3
OCKS0
OCKS0(35 pin)
4
OCKS1
OCKS1(34 pin)
5
DIF0
DIF0(3 pin)
6
DIF1
DIF1(5 pin)
7
DIF2
DIF2(7 pin)
Toggle Switch for selecting clock source to the AK4118A-XTI.
XTL: Crystal Clock
TX-CLK: External Clock
Jumper Pin for selecting power supply to IC’s except the AK7736B.
Open: Supply from the P-DVDD test pin
Short: +3.3V
Power Supply Connector
Supply +3.3V.
Connect to GND
Jumper pin for selecting power supply to the TVDD pin of the AK7736B
Open: Supply from the TVDD test pin
Short: P-TVDD
Table 1. Main Board Functions (Bold: Default Setting)
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Evaluation Board Manual
■ Operation Sequence
(1) Set up the power supply lines.
[The jumper pins should be set as following]
JP6
JP4
VDD
TVDD
(Short)
(Short)
JP7
P-DVDD
(Short)
Set up the power supply lines.
Name Color
Voltage
+3.3V
Red
+3.3V
GND
Black
0V
JP5
PIC-VDD-SEL
3.3V
Comment
Regulator,
Input/Output buffer
Ground
Table 2. Set Up of Power Supply Lines
1.8V
Attention
Should always be connected.
Should always be connected.
Each supply line should be distributed separately from the power supply unit. The regulator on the board that
converts 3.3V to 1.8V can also supply TVDD of the AK7736B.
(2) Set up the evaluation mode, jumper pins and connectors. (according to the following section)
(3) Connect the board to a PC with a USB cable via the AKD77XX-HF-CONTROL-BOX (called
“CONTROL-BOX” hereafter) which is included in this package. It is required to push down the reset button
(yellow) of the CONTROL-BOX to initialize the USB control chip.
(4) Power On
(5) Start the control software and set up registers by PC. (according to the following section)
■ Evaluation Mode
In case of evaluating theAK7736B by using the AK4118A, it is necessary that audio interface format of both
devices are matched. Refer to the datasheet for audio interface format of the AK7736B, and refer to
“Jumper Pin and Switch Setting” for audio interface format of the AK4118A.
Applicable Evaluation Mode
(1) Digital-to-Digital Evaluation using ADC-Port and DAC-Port: CKM Master Mode = 0/1
(2) Digital-to-Digital Evaluation using ADC-Port and DAC-Port: CKM Slave Mode = 2/3/4/5
Refer to the “Control Software” section of this manual and the datasheet of the AK7736B for FPGA, the AK4118A
and control register setting of the AK7736B.
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(1) Digital-to-Digital Evaluation using ADC Port and DAC Port: CKM Master Mode = 0/1
ADC-Port and DAC-Port are used on this evaluation. Set the clock mode of the AK7736B to CKM Master Mode
0 (12.288MHz) or CKM Master Mode 1 (18.432MHz). The AK7736B outputs BICK and LRCK to the ADC-Port
and DAC-Port by setting the FPGA. The ADC-Port inputs data to the SDIN1, SDIN2A, SDIN2B, SDIN2C,
SDIN3 or SDIN4 pin. The DAC-Port output data from the SDOUT1, SDOUT2A, SDOUT2B, SDOUT3 or
SDOUT4 pin.
[Jumper Pins Setting]
JP1
XTI-SEL
EXT
CRY
For digital output, optical connector PORT2 (SPDIF-OUT) is also available. The following setting must be made
and the FPGA setting should be changed when using the SPDIF-OUT instead of the DAC-Port. Refer to
“AK4118A Setting” for detail setting of the AK4118A.
Main Board
Jumper / Switch
Setting (Default)
SW1 (AK4118A
“TX-CLK”
Clock)
S1(AK4118A Setting)
1->7=LHLLLHH
Table 3. Configuration of the AK4118A switch in Master Mode
(2) Digital-to-Digital Evaluation using ADC Port and DAC Port: CKM Slave Mode = 2/3/4/5
ADC-Port and DAC-Port are used on this evaluation. Set the clock mode of AK7736B to CKM Slave Mode
2/3/4/5. ADC-Port supplies MCLK, BICK, LRCK and digital data to the AK7736B. (MCLK is needed in CKM
Slave Mode 2 only)
[Jumper Pins Setting]
JP10
XTI-SEL
EXT
CRY
(MCLK is needed in CKM Slave Mode 2 only)
For digital input and output, optical connector PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT) are available,
respectively. The following setting must be made and the FPGA setting should be changed when using these
connectors. Refer to “AK4118A Setting” for detail setting of the AK4118A.
Main Board
Jumper / Switch
Setting (Default)
SW1 (AK4118A
“XTL”
Clock)
S1(AK4118A Setting)
1->7=LHLLLLH
Table 4. Configure the AK4118A switch at the Slave Mode
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■ Board control
The AKD7736B-A can be controlled by a PC via USB port. Connect the CONTROL-BOX included in this package to
the AKD7736B-A with a 10-pin flat cable, and connect the CONTROL-BOX to a PC with a USB cable. The 10-pin flat
cable should be connected in the direction that the side with a bump meets a marking, that says “CONTROL”, on the
main board of the AKD7736B-A.
CONTROL
Figure 1. Direction of the 10-pin Flat Cable
The interface setting is made by jumper pins of the CONTROL-BOX and the I2CSEL pin of the AK7736B.
SPI(Serial) Setting
I2C Setting
Short
Open
Open
Open
Short
Short
Open
Short
Figure 2. Configuration of the CONTROL-BOX
Control software is different depending on the interface setting.
The software operation sequence is shown in this manual.
■ Indication for LED
[LED] D1:
The status of AK7736B’s PDN pin is shown. “H” → Light off; “L” → Light on.
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■ Jumper Pin and Switch Setting
<Main board>
Jumper / Switch
Setting (Default)
SW1 (AK4118A
Clock)
“TX-CLK”
Note
AK4118A Clock Source
“XTL”: Crystal Clock
“TX-CLK”: External Clock
Refer to “AK4118A Setting”
Refer to (9) in Table 1
AK7736B TVDD
Refer to (11) in Table 1
AK7736B VDD
Peripheral DVDD
S1(AK4118A Setting)
1->7=LHLLLHH
S2(AK7736B Setting)
1->5=LLLLL
JP4 (TVDD)
Short
JP5 (P-TVDD)
“3.3V”
JP6 (VDD)
Short
JP7 (P-DVDD)
Short
“Xilinx”
JP8 (DI1)
“Xilinx”
JP9 (DI2A)
“Xilinx”
JP10 (DI2B)
“Xilinx”
JP11 (DI2C)
“Xilinx”
JP12 (XTI)
“Xilinx”
JP13 (BTI1)
“Xilinx”
Refer to (2) in Table 1
JP14 (LR1)
“Xilinx”
JP15 (DI4)
“Xilinx”
JP16 (BTI2)
“Xilinx”
JP17 (LR2)
“Xilinx”
JP18 (DI3)
“Xilinx”
JP19 (BTI3)
“Xilinx”
JP20 (LR3)
Table 5. Setting of Jumper Pins on Main Board
<Sub board>
Jumper/ Switch
JP1 (XTI-SEL)
Setting (Default)
Note
AK7736B Clock Source
“CRY”: Crystal Clock
“EXT”: External Clock
Table 6. Setting of Jumper Pins on Sub Board
“CRY”
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<AK4118A Setting>
OCKS1
OCKS0
MCKO1
MCKO2
X’tal
Fs(max)
0
0
256fs
L
256fs
96kHz
0
1
256fs
L
256fs
96kHz
1
0
512fs
L
512fs
48kHz
1
1
128fs
L
128fs
192kHz
default
Table 7. AK4118A-OCKS[1:0]
CM1
CM0
Clock
source
MCKO1
MCKO2
SDTO
0
0
PLL
PLL
L
RX
0
1
X’tal
X’tal
X’tal
DAUX
1
0
PLL
PLL
L
RX
1
1
X’tal
X’tal
X’tal
DAUX
default
Table 8. AK4118A-CM[1:0]
DIF2
DIF1
DIF0
DAUX
SDTO
0
0
0
24bit,Left justified
16bit,Right justified
H/L
O
64fs
O
0
0
1
24bit,Left justified
18bit,Right justified
H/L
O
64fs
O
0
1
0
24bit,Left justified
20bit,Right justified
H/L
O
64fs
O
0
1
1
24bit,Left justified
24bit,Right justified
H/L
O
64fs
O
24bit,Left justified
L/H
O
64fs
O
24bit,Left justified
LRCK
BICK
1
0
0
1
0
1
24bit,I2S
24bit,I2S
H/L
O
64fs
O
1
1
0
24bit,Left justified
24bit,Left justified
L/H
I
64fs
I
1
1
1
24bit,I2S
24bit,I2S
H/L
I
64fs
I
default
Table 9. AK4118A-DIF[2:0]
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■ Digital Input Circuit (External DIR: PORT1)
Figure 3. Digital Input Circuit
For digital input SPDIF-IN, optical connector PORT1 is available.
■ Digital Output Circuit (External DIT: PORT2)
Figure 4. Digital Output Circuit
For digital output SPDIF-OUT, optical connector PORT2 is available.
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[AKD7736B-A]
Control Software Manual
■ Evaluation Board and Control Software Settings
(1) Set up the AKD7736B-A as needed, according to the previous terms.
(2) Connect the AKD7736B-A to a PC via the CONTROL BOX with a 10-pin flat cable on the evaluation board side
and a USB cable on the PC side. After power on the evaluation board, press the reset button (yellow) of the
CONTROL BOX to initialize the USB chip.
(3) Insert the CD-ROM labeled “AKD7736B-A Evaluation Kit” into the CD-ROM drive.
(4) Access the CD-ROM drive and double-click the icon of “AK7736B.exe” according to the interface setting to set
up the program. (AK7736B.exe: Control software of the AKD7736B-A)
(5) Begin evaluation by following the procedure below.
■ Operation Flow
Evaluation flow is shown below.
1. Start up the control program following the above procedure.
2. Open dialogues to set necessary settings for evaluation and evaluate the AK7736B.
(The control software must run again when disconnecting a USB control box from the PC.)
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[AKD7736B-A]
■ Operation Screen
(1) Main Window
Figure 5. Startup Screen
Program download, register setting, FPGA setting and script processing are executed by this control software. These
controls may be selected by the upper tabs. Frequently used buttons, such as register initializing and control buttons are
located outside of the switching tab window. Supported control interface format is shown in the Control I/F box as
“Serial” (SPI) or “I2C”.
[JX]:
[Board Init]:
[PDN Pin]:
[SRESET]:
[DSP]:
[CK]:
[DLRDY]:
[READ]:
JX Code Setting.
Reset the evaluation board, and the register values set by the control software are written again.
Power Down. The AK7736B is initialized.
System Reset.
DSP Reset.
Clock Reset.
Clock reset is required when changing the clock mode or the frequency of input clock without
power downing the AKD7736B. Register values are not initialized by this reset.
Down loads DSP programs. It is required when down loading a DSP program without system clocks.
Reads out register values and shows them on the register column.
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[AKD7736B-A]
(2) Download
Figure 6. [Download] Dialogue
Click each [refer] button next to the Source, Program, CRAM or OFREG column to select a file, or drag and drop a file to
the each column.
CRAM file or OFREG file can be selected and be written to CRAM or OFREG by clicking the [refer] button of CRAM
[email protected] column or OFREG [email protected] column when the system is running. The data will be written to
specific address of CRAM or OFREG when the [write] button at right side is clicked.
[Assemble]:
[Write]:
[Assemble Write]:
[PRAM read]:
[CRAM read]:
[OFREG read]:
[CRAM SAVE]:
[OFREG SAVE]:
[MICR1~4]:
[CRC-Check]:
[Auto RUN]:
Compiles a source file, and the output file will be selected as a download file automatically.
Downloads the program to the AK7736B.
Compiles a source file and then downloads the file to the AK7736B.
Reads out the PRAM data to a temporary file.
Reads out the CRAM data to a temporary file.
Reads out the OFREG data M to a temporary file.
Reads out the CRAM data, and save them to a file.
Reads out the OFREG data, and save them to a file.
Reads out the register data of MICR1~4 during run, and shows them into the box next to each button.
By checking this checkbox, simple error detection by CRC (cyclic redundancy check) is executed
when down loading a file.
By checking this checkbox, the downloaded file will be run automatically when finish downloading.
If not checked, the AK7736B will be in system reset state when finish downloading.
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[AKD7736B-A]
(3) Register Set up
Figure 7. [REG1] Dialogue
Tab dialogues of REG1/REG2/REG3/REG4 are used to set registers. (TEST and Reserved items are prohibited to
change.) As the checkbox is clicked, the data is written to the register. Release the reset state after setting CKM mode
since SRESET and CKRST are on by CKM mode setting.
Refer to the AK7736B’s datasheet for details of the register setting.
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(4) FPGA Set up
Figure 8. [FPGA1] Dialogue
The FPGA1/FPGA2 dialogues are used to control the data path of the AK7736B.
FPGA Setting Table: (The default setting is shown in bold.)
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[AKD7736B-A]
Bit
D[47:36]
D[35:34]
SEL20
Function
EXT-XTI
D[33]
SEL19
BICK1/LRCK1
In/Out
D[32:31]
SEL18
BICK1/LRCK1
D[30:29]
SEL17
BICK2/JX1
D[28:27]
SEL16
LRCK2/JX2
D[26:25]
SEL15
BICK3/LRCK3
D[24:23]
SEL14
SDIN1
D[22:21]
SEL13
SDIN2A
D[20:19]
SEL12
SDIN2B
D[18:17]
SEL11
SDIN2C
D[16:15]
SEL10
SDIN3
Description
Reserved
Input data source to the XTI pin of the AK7736B in Slave mode.
00: AK4118A-RX-CLK
01: ADC-MCLK
10: Low
11: Low
In/Out setting of the BITCLK1/LRCLK1 pin of the AK7736B.
0: output
1: input
Input clock select to the BITCLK1/LRCLK1 pin of the
AK7736B.
00: AK4118A-BICK/LRCK
01: ADC-BICK/LRCK
10: Low
11: Low
Input data source to the BITCLKI2/JX1 pin of the AK7736B.
00: AK4118A-BICK
01: ADC-BICK
10: Low
11: High
Input data source to the LRCLKI2/JX2 pin of the AK7736B.
00: AK4118A-LRCK
01: ADC-LRCK
10: Low
11: High
Input clock to the BITCLKI3/LRCLKI3 pin of the AK7736B.
00: AK4118A-BICK/LRCK
01: ADC-BICK/LRCK
10: Low
11: Low
Input data source to the SDIN1 pin of the AK7736B.
00: AK4118A
01: ADC-SDTO1
10: ADC-SDTO2
11: Low
Input data source to the SDIN2A pin of the AK7736B.
00: AK4118A
01: ADC-SDTO1
10: ADC-SDTO2
11: Low
Input data source to the SDIN2B pin of the AK7736B.
00: AK4118A
01: ADC-SDTO1
10: ADC-SDTO2
11: Low
Input data source to the SDIN2C pin of the AK7736B.
00: AK4118A
01: ADC-SDTO1
10: ADC-SDTO2
11: Low
Input data source to the SDIN3 pin of the AK7736B.
00: AK4118A
01: ADC-SDTO1
10: ADC-SDTO2
11: Low
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[AKD7736B-A]
D[14:13]
SEL9
SDIN4
D[12:11]
SEL8
CAD[1:0]
D[10]
SEL7
TRX-PDN
D[9]
SEL6
TX-CLK
D[8]
SEL5
TRX-BICK/LRCK
In/Out
D[7:5]
SEL4
TX-DAT
D[4]
SEL3
ADC-MCLK In/Out
D[3]
SEL2
ADC-BICK/LRCK
In/Out
D[2:1]
SEL1
ADC-BICK/LRCK
D[0]
SEL0
DAC-SDTI2
Input data source to the SDIN4 pin of the AK7736B.
00: AK4118A
01: ADC-SDTO1
10: ADC-SDTO2
11: Low
The CAD pin setting of the AK7736B.
00: Low,Low
01: Low,High
10: High,Low
11: High,High
The PDN pin setting of the AK4118A
0: Low
1: High
Input clock select to the XTI pin of the AK4118A.
0: AK7736B-CLKO
1: Low
In/Out setting of the BICK/LRCK pin of the AK4118A
0: output
1: AK7736B-BITCLKO/LRCLKO input
Input data source to the DAUX pin of the AK4118A
000: AK7736B-SDOUT1
001: AK7736B-SDOUT2A
010: AK7736B-SDOUT2B
011: AK7736B-SDOUT3
100: AK7736B-SDOUT4
101: Low
110: Low
111: Low
In/Out setting of the MCLK pin of the ADC-Port
0: MCLK output
1: AK7736B-CLKO input
In/Out setting of the BICK/LRCK pin of the ADC-Port
0: output
1: input
Input clock select to the BICK/LRCK pin of the ADC-Port
00: AK7736B-BITCLKO/LRCLKO
01: AK7736B-BITCLK1/LRCLK1
10: Low
11: Low
Input data source to the SDTI pin of the DAC-Port.
0: AK7736B-SDOUT2A
1: AK7736B-SDOUT2B
Table 10. FPGA
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(5) Script
Figure 9. [SCRIPT] Dialogue
As a script file is selected, the program is executed automatically. By clicking the [Repeat] button, the selected script file
will be executed once again.
The script commands are listed below.
Command
[SCRIPT]
;Comment
W,< command>,<data>
W,0xC0,0x00
WL,<command>,<address>,<data>,…
WL,0x82,0x0022,0x4000,0x4000,0x4000
WS,<command>,<address>,<data>,…
WS,0x81,0x00,0x22,0x40,0x00,0x40,0x00
RI: H, RI: L
RS: H, RS: L
RD: H, RD: L
RC: H, RC: L
X,<address>,<data>
P,<message>
T,<wait>
T,50mS
LP:<filename>
LC:<filename>
LO:<filename>
Description
Header of script file. A data error will be detected without this header.
The line following a semicolon is ignored as a comment.
Register Write. Both command and data are BYTE (8bit) assigned.
Continuous Data Write. This command can be used during CRAM run.
Command is byte assigned, the data is word assigned.
Continuous Data Write. This command can be used during CRAM run.
Command, address and data are byte assigned.
PDN control
SRESET control
DSP-RESET control
CKRESET control
FPGA register write command.
Displays a message and poses the script.
Wait some micro seconds.
In an actual operation, it is possible to wait longer than this period.
Program file download to PRAM of the DSP.
Coefficient file download to CRAM of the DSP.
Off-set file download to OFREG of the DSP.
Table 11. Script Command
<KM115102>
2013/08
- 18 -
[AKD7736B-A]
REVISION HISTORY
Date
(yy/mm/dd)
12/07/27
Manual
Revision
KM110501
Board
Revision
0
Reason
Page
First edition
12/12/10
KM113102
0
Renamed
AK7736 -> AK7736A
13/08/21
KM115102
0
Renamed
AK7736A -> AK7736B
<KM115102>
Contents
2013/08
- 19 -
[AKD7736B-A]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this
document. You are fully responsible for use of such information contained in this document in your product
design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR
THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT
DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
equipment used to control combustions or explosions, safety devices, elevators and escalators, devices
related to electric power, and equipment used in finance-related fields. Do not use Product for the above use
unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not
be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or
extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
<KM115102>
2013/08
- 20 -
5
4
3
2
1
EXT-SDIN1
EXT-SDIN2A
EXT-SDIN2B
EXT-SDIN2C
EXT-SDIN3
EXT-SDIN4
D
EXT-CLKO
EXT-BITCLKO
EXT-LRCLKO
EXT-SDOUT1
EXT-SDOUT2A
EXT-SDOUT2B
EXT-SDOUT3
EXT-SDOUT4
EXT-EXTCLK
ADC-MCLK
ADC-BICK
ADC-LRCK
ADC-SDTO1
ADC-SDTO2
DAC-SDTI2
DAC-SDTI1
EXT-XTI
EXT-BITLK1
EXT-LRLK1
EXT-BITCLKI2/JX1
EXT-LRCLKI2/JX2
EXT-BITCLKI3
EXT-LRCLKI3
EXT
D
EXT
X-TRX-PDN
TX-CLK
TX-DAT
TRX-BICK
TRX-LRCK
X-TX-CLK
X-TX-DAT
X-TRX-BICK
X-TRX-LRCK
RX-CLK
RX-CLK2
RX-DAT
X-RX-CLK
X-RX-CLK2
X-RX-DAT
X-SDIN2A
X-SDIN2C
X-SDIN3
X-SDIN4
SEL-X-SDIN2A
SEL-X-SDIN2C
SEL-X-SDIN3
SEL-X-SDIN4
X-XTI
X-BITCLKI2/JX1
X-LRCLKI2/JX2
X-BITCLKI3
X-LRCLKI3
SEL-X-XTI
SEL-X-BITCLKI2/JX1
SEL-X-LRCLKI2/JX2
SEL-X-BITCLKI3
SEL-X-LRCLKI3
AK7736B
SEL-EXT-XTI
SEL-EXT-BITCLK1
SEL-EXT-LRCLK1
SEL-EXT-BITCLKI2/JX1
SEL-EXT-LRCLKI2/JX2
SEL-EXT-BITCLKI3
SEL-EXT-LRCLKI3
TRX-PDN
SELECTOR
SEL-EXT-SDIN1
SEL-EXT-SDIN2A
SEL-EXT-SDIN2B
SEL-EXT-SDIN2C
SEL-EXT-SDIN3
SEL-EXT-SDIN4
XILINX
X-EXTCLK
X-ADC-MCLK
X-ADC-BICK
X-ADC-LRCK
X-ADC-SDTO1
X-ADC-SDTO2
X-DAC-SDTI2
AK4118A
SEL-SDIN2A
SEL-SDIN2C
SEL-SDIN3
SEL-SDIN4
SEL-XTI
SEL-BITCLKI2/JX1
SEL-LRCLKI2/JX2
SEL-BITCLKI3
SEL-LRCLKI3
DSP-SDIN2A
DSP-SDIN2C
DSP-SDIN3
DSP-SDIN4
DSP-XTI
DSP-BITCLKI2/JX1
DSP-LRCLKI2/JX2
DSP-BITCLKI3
DSP-LRCLKI3
LEVELSHIFT
AK4118A
C
X-BITCLK1
X-LRCLK1
X-CONFIG-BITLRIO
X-SDIN1
X-SDIN2B
LS-X-BITCLK1
LS-BITCLK1
LS-X-LRCLK1
LS-LRCLK1
LS-X-CONFIG-BITLRIO
LS-X-SDIN1
LS-SDIN1
LS-X-SDIN2B
LS-SDIN2B
SEL-LS-BITCLK1
SEL-LS-LRCLK1
SEL-BITCLK1
SEL-LRCLK1
DSP-BITCLK1
DSP-LRCLK1
SEL-LS-SDIN1
SEL-LS-SDIN2B
SEL-SDIN1
SEL-SDIN2B
DSP-SDIN1
DSP-SDIN2B
C
SELECTOR
X-SDOUT1
X-SDOUT2B
LS-X-SDOUT1
LS-X-SDOUT2B
LS-SDOUT1
LS-SDOUT2B
DSP-SDOUT1
DSP-SDOUT2B
LEVELSHIFT
X-SDOUT2A
X-SDOUT3
X-SDOUT4
DSP-SDOUT2A
DSP-SDOUT3
DSP-SDOUT4
X-RQN/CAD1
X-SI/CAD0
X-SCLK/SCL
X-SO
X-SDA
DSP-RQN/CAD1
DSP-SI/CAD0
DSP-SCLK/SCL
DSP-SO
DSP-SDA
X-RDY
X-STO
X-EXPDN
X-PDN
B
DSP-RDY
DSP-STO
DSP-EXPDN
DSP-PDN
B
DSP-JX0
DSP-TESTI1
DSP-TESTI2
DSP-TESTI3
DSP-CLKO
DSP-BITCLKO
DSP-LRCLKO
DSP-I2CSEL
X-CLKO
X-BITCLKO
X-LRCLKO
AK7736B
X-I2CSEL
POWER
X-CTRL-SCLK/SCL
X-CTRL-SI
X-CTRL-RQN
X-CTRL-CSN
X-CTRL-RESET
X-CTRL-HOST
CTRL-SCK/SCL
CTRL-SI
CTRL-RQN
CTRL-CSN
CTRL-RESET
CTRL-HOST
X-CTRL-SO
X-CTRL-XCS/SDA
CTRL-SO
CTRL-XCS/SDA
DIP-I2C
CONTROL
DIP-JX0
DIP-TESTI1
DIP-TESTI2
DIP-TESTI3
A
A
POWER
XILINX
CONTROL
Title
Size
A3
Date:
5
4
3
2
AKD7736B-A-MAIN
Document Number
Rev
0
TOP
Monday, August 19, 2013
Sheet
1
1
of
9
5
4
3
2
1
D
D
DVDD-3.3V
DVDD-3.3V
C1
+
C2
L1
SILK-SCREEN
SPDIN-IN
10uF
10uH(500mA)
0.1uF
PORT1
SPDIF-IN
VCC
GND
OUT
3
2
1
R2
470
C3
R1
DIF-RX
0.1uF
10k
C5
10uF
RX3
VSS4
RX2
TEST1
RX1
NC
RX0
VSS3
VCOM
R
AVDD
INT1
U1
1
2
3
4
5
6
7
8
9
10
11
12
C
DIP-4118A-DIF0
DIP-4118A-DIF1
DIP-4118A-DIF2
DVDD-3.3V
IPS0/RX4
NC
DIF0/RX5
TEST2
DIF1/RX6
VSS1
DIF2/RX7
IPS1/IIC
P/SN
XTL0
XTL1
VIN/GP0
L2
36
35
34
33
32
31
30
29
28
27
26
25
C
DIP-4118A-OCKS1
DIP-4118A-OCKS0
DIP-4118A-CM1
DIP-4118A-CM0
R3
R4
R5
TX-CLK
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
51
51
51
XTAL1
12.288MHz(DIP)
22pF
10uH(500mA)
IN
VCC
GND
TX-CLK
XTL
R6
R7
51
51
C6
22pF
C7
TRX-LRCK
RX-CLK
PORT2
SPDIF-OUT
SW1
TRX-PDN
13
14
15
16
17
18
19
20
21
22
23
24
SILK-SCREEN
SPDIN-OUT
INT0
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
PDN
AK4118A
XTI
XTO
DAUX
MCKO2
BICK
SDTO
TVDD
NC/GP1
TX0/GP2
TX1/GP3
BOUT/GP4
COUT/GP5
UOUT/GP6
VOUT/GP7
DVDD
VSS2
MCKO1
LRCK
+
C4
0.1uF
48
47
46
45
44
43
42
41
40
39
38
37
PLR135_T9
3
2
1
DIF-TX
C8
0.1uF
0.1uF C9
C12
10uF
10uF
PLT133_T9
C11
10uF
C13
+
+
B
DVDD-3.3V
DVDD-3.3V
DVDD-3.3V
DIF2
DIF1
DIF0
OCKS1
OCKS0
CM1
CM0
DVSS
DVDD-3.3V
TP1
BLACK
C14
100uF/16V(A)
7
6
5
4
3
2
1
SW DIP-7
DIP-4118A-DIF2
DIP-4118A-DIF1
DIP-4118A-DIF0
DIP-4118A-OCKS1
DIP-4118A-OCKS0
DIP-4118A-CM1
DIP-4118A-CM0
10k
10k
10k
10k
10k
10k
10k
1
+
S1
8
9
10
11
12
13
14
R8
R9
R10
R11
R12
R13
R14
C10 +
0.1uF
B
A
A
Title
Size
A3
Date:
5
4
3
2
AKD7736B-A-MAIN
Document Number
Rev
0
AK4118A
Monday, August 19, 2013
Sheet
1
2
of
9
5
4
3
2
1
DSP-RQN/CAD1
DSP-SI/CAD0
DSP-SDIN4
DSP-SDA
DSP-BITCLKI2/JX1
DSP-SCLK/SCL
DSP-LRCLKI2/JX2
VDD
D
D
DSP-SO
25
26
27
28
29
30
31
32
33
34
35
36
DSP-STO
48pin_3
CN1
CN3
48pin_4
DSP-SDIN3
37
24
DSP-CLKO
38
23
DSP-BITCLKO
39
22
DSP-LRCLKO
DSP-BITCLKI3
40
21
DSP-SDIN2A
DSP-LRCLKI3
41
20
DSP-PDN
DSP-SDIN2C
42
19
VDD
C
C
DSP-I2CSEL
VDD
DSP-JX0
43
18
DSP-EXPDN
44
17
45
16
DSP-RDY
46
15
DSP-SDOUT2A
47
14
DSP-SDOUT3
48
13
DSP-SDOUT4
DSP-TESTI2
B
B
48pin_2
12
11
10
9
8
7
6
5
4
3
2
48pin_1
CN4
1
CN2
DSP-TESTI1
DSP-SDOUT2B
TVDD
A
DSP-SDOUT1
DSP-XTI
DSP-SDIN1
DSP-LRCLK1
DSP-SDIN2B
DSP-BITCLK1
A
DSP-TESTI3
Title
Size
A3
Date:
5
4
3
2
AKD7736B-A-MAIN
Document Number
Rev
0
AK7736B
Monday, August 19, 2013
Sheet
1
3
of
9
4
3
R15 R16 R17
C15
1
2
2
2
1
DVDD-3.3V
2
DVDD-3.3V
D
2
0.1uF
2
D
2
5
R18 R19
2
4
6
8
10
10k 10k
1
1
3
5
7
9
CTRL-HOST
CTRL-SCK/SCL
CTRL-XCS/SDA
CTRL-CSN
1
1
1
1
JP1
4.7k 4.7k 10k
CTRL-RQN
CTRL-SI
CTRL-SO
CTRL-RESET
HEADER 5X2
CONTROL
DVSS
C
C
1
TP2
BLACK
DVDD-3.3V
P-TVDD
B
S2
6
7
8
9
10
5
4
3
2
1
B
10k
10k
10k
10k
10k
SW DIP-5
DIP-I2C
DIP-JX0
DIP-TESTI2
DIP-TESTI1
DIP-TESTI3
R20
R21
R22
R23
R24
I2C
JX0
TESTI2
TESTI1
TESTI3
A
A
Title
Size
A4
Date:
5
4
3
2
AKD7736B-A-MAIN
Document Number
Rev
0
CONTROL
Monday, August 19, 2013
Sheet
4
1
of
9
5
4
3
2
1
J1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
XTI
BIT1
LR1
BIT2
LR2
BIT3
LR3
DI1
DI2A
DI2B
DI2C
DI3
DI4
CLKO
BITO
LRO
DO1
DO2A
DO2B
DO3
DO4
EXTCLK
D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
51
51
51
51
51
51
51
51
51
51
51
51
51
R38
51
EXT-XTI
EXT-BITLK1
EXT-LRLK1
EXT-BITCLKI2/JX1
EXT-LRCLKI2/JX2
EXT-BITCLKI3
EXT-LRCLKI3
EXT-SDIN1
EXT-SDIN2A
EXT-SDIN2B
EXT-SDIN2C
EXT-SDIN3
EXT-SDIN4
EXT-CLKO
EXT-BITCLKO
EXT-LRCLKO
EXT-SDOUT1
EXT-SDOUT2A
EXT-SDOUT2B
EXT-SDOUT3
EXT-SDOUT4
EXT-EXTCLK
D
C
C
HEADER 22X2
EXT
DVSS
B
MCLK
GND
BICK
GND
LRCK
DO1
DO2
JP2
ADC-MCLK
ADC-BICK
ADC-LRCK
ADC-SDTO1
ADC-SDTO2
R39
R40
R41
R42
R43
51
51
51
51
51
TP3
BLACK
MCLK
GND
BICK
GND
LRCK
DI1
DI2
DI4
DI3
1
1:
2:
3:
4:
5:
7:
9:
1:
2:
3:
4:
5:
6:
8:
9:
10:
B
JP3
1
3
5
7
9
2
4
6
8
10
EXT-CLKO
EXT-BITCLKO
EXT-LRCLKO
EXT-SDOUT4
HEADER 5X2
1
3
5
7
9
2
4
6
8
10
EXT-SDOUT3
DAC-SDTI1
DAC-SDTI2
SDOUT1
SDOUT2A or 2B
HEADER 5X2
ADC
DAC
A
A
Title
Size
A4
Date:
5
4
3
2
AKD7736B-A-MAIN
Document Number
Rev
0
EXT
Monday, August 19, 2013
Sheet
5
1
of
9
5
4
3
2
DVDD-3.3V
1
P-TVDD
C16 0.1uF C17 0.1uF
U2
D
D
1
LS-X-BITCLK1
LS-X-LRCLK1
R44
0
2
R46
0
3
4
VCCA
A1
A2
GND
VCCB
B1
B2
DIR
8
7
R45
0
6
R47
0
5
LS-BITCLK1
LS-LRCLK1
LS-X-CONFIG-BITLRIO
SN74AVCH2T45DCU
L:A←B
H:A→B
DVDD-3.3V
P-TVDD
C18 0.1uF C19 0.1uF
C
C
U3
1
LS-X-SDOUT1
LS-X-SDOUT2B
R48
51
2
R49
51
3
4
VCCA
A1
A2
GND
VCCB
B1
B2
DIR
8
7
LS-SDOUT1
6
LS-SDOUT2B
5
SN74AVCH2T45DCU
A←B
B
B
DVDD-3.3V
P-TVDD
C20 0.1uF C21 0.1uF
U4
1
2
LS-X-SDIN1
3
LS-X-SDIN2B
4
VCCA
A1
A2
GND
VCCB
B1
B2
DIR
8
7
R50
51
6
R51
51
LS-SDIN1
LS-SDIN2B
5
DVDD-3.3V
SN74AVCH2T45DCU
A
A→B
A
Title
Size
A4
Date:
5
4
3
2
AKD7736B-A-MAIN
Document Number
Rev
0
LEVEL SHIFT
Monday, August 19, 2013
Sheet
6
1
of
9
5
4
AK7736B
TVDD
P-TVDD
TP4
TP5
YELLOW
->
D
open : VDD = VDDテストピン入力
short : VDD = 3.3V
BLOWN
2
1
default short
AK7736B
open : P-TVDD = P-TVDDテストピン入力
3.3Vshort :P-TVDD = 3.3V
1.8Vshort :P-TVDD = REG1.8V
VDD
JP5
TP6
RED
3.3V-TVDD
1.8V-TVDD
open : TVDD = TVDDテストピン入力
short : TVDD = P-TVDD
VDD
default short
1.8V ← 3.3V
TVDD-SEL
JP6
VDD
U5
2PIN
2
1
TM1
1
C25
0.1uF
1
IN
->
1
+
2
C22
0.1uF
3
+ C24
10uF
C
OUT
GND
TA48018BF
2
1
2PIN
1
P-TVDD
1
TVDD
JP4
TVDD
2
LEVELSHIFT
DIPSW
1
D
3
C26
+ C27
10uF
10u/16V(A)
C23
0.1uF
+
+3.3V
i
TJ-563-R
C28
100uF/16V(A)
C
TM2
1
GND
i
TJ-563-B
xilinx
SPDIF
LEVELSHIFT
DIPSW
DVSS
TP7
BLACK
1
P-DVDD
open : P-DVDD = P-DVDDテストピン入力
short : P-DVDD = 3.3V
TP8
ORANGE
1
DVDD-3.3V
JP7
P-DVDD
B
B
2
1
L3
10uH(500mA)
default short
+ C29
10uF
C30
0.1uF
A
A
Title
Size
A3
Date:
5
4
3
2
AKD7736B-A-MAIN
Document Number
Rev
0
POWER
Monday, August 19, 2013
Sheet
1
7
of
9
5
4
3
2
1
EXT
xilinx
D
JP8
JP9
SEL-EXT-SDIN1
SEL-EXT-SDIN2A
SEL-SDIN2A
SEL-X-SDIN2A
10k
SDI2A-SEL
10k
SDI1-SEL
R52
SEL-LS-SDIN1
R53
SEL-SDIN1
JP10
JP11
SEL-EXT-SDIN2B
SEL-EXT-SDIN2C
SEL-SDIN2C
SEL-X-SDIN2C
10k
SDI2C-SEL
10k
JP12
C
JP13
SEL-EXT-XTI
JP14
SEL-EXT-BITCLK1
SEL-BITCLK1
SEL-LRCLK1
SEL-LS-LRCLK1
LR1-SEL
10k
BIT1-SEL
R57
SEL-LS-BITCLK1
10k
XTI-SEL
R56
SEL-X-XTI
C
SEL-EXT-LRCLK1
SEL-XTI
R58
SDI2B-SEL
R54
SEL-LS-SDIN2B
R55
SEL-SDIN2B
10k
D
FSCONV
JP15
JP16
JP17
SEL-EXT-BITCLKI2/JX1
SEL-EXT-LRCLKI2/JX2
SEL-LRCLKI2/JX2
SEL-X-LRCLKI2/JX2
LR2-SEL
10k
BIT2-SEL
R61
SEL-X-BITCLKI2/JX1
10k
SDI4-SEL
R59
SEL-X-SDIN4
SEL-BITCLKI2/JX1
R60
SEL-SDIN4
10k
SEL-EXT-SDIN4
B
B
SRC
JP18
JP19
JP20
SEL-EXT-BITCLKI3
SEL-EXT-LRCLKI3
SEL-LRCLKI3
SEL-X-LRCLKI3
LR3-SEL
10k
BIT3-SEL
R64
SEL-X-BITCLKI3
10k
SDI3-SEL
R62
SEL-X-SDIN3
SEL-BITCLKI3
R63
SEL-SDIN3
10k
SEL-EXT-SDIN3
A
A
Title
Size
A3
Date:
5
4
3
2
AKD7736B-A-MAIN
Document Number
Rev
0
SELECTOR
Monday, August 19, 2013
Sheet
1
8
of
9
5
4
3
2
1
DVDD-3.3V
DVDD-3.3V
C31
C32
C33
C34
C35
C36
C43
C37
C38
C39
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
+
C40 +
C41 +
C44 +
C42
DVDD-3.3V
10uF(T) 10uF(T) 10uF(T) 10uF(T)
SCLK/SCL
SDA
DVDD-3.3V
D1
X-PDN
2
1
R72
2
LEAD RED LED
470
1
X-SCLK/SCL
X-SDA
X-SI/CAD0
X-RQN/CAD1
X-SDIN4
X-BITCLKI2/JX1
X-LRCLKI2/JX2
X-SO
X-STO
X-BITCLKO
X-LRCLKO
X-SDIN2A
X-PDN
X-RDY
X-SDOUT2A
X-SDOUT3
X-SDOUT4
X-SDIN3
X-BITCLKI3
X-LRCLKI3
X-SDIN2C
X-EXPDN
C
R66
51
R67
R68
R69
51
51
51
R71
51
R73
R74
R75
R76
51
51
51
51
X-TRX-PDN
X-TX-CLK
X-TX-DAT
X-RX-CLK2
X-TRX-BICK
X-RX-DAT
R78
R79
R80
R81
51
51
51
51
R82
51
R84
R85
51
51
B
135
136
137
138
139
140
142
9
10
11
12
13
14
15
16
17
19
20
21
22
23
24
25
26
27
28
31
X-TRX-LRCK
X-RX-CLK
R86
51
2
3
5
6
30
38
143
VCCINT
VCCINT
VCCINT
VCCINT
109
127
55
37
1
73
D
IO14-15
IO14-14
IO14-11
IO14-10
IO14-8
IO14-6
IO14-5
IO14-3
IO10-2
IO10-3
IO10-5
IO10-6
IO10-8
IO10-10
IO10-11
IO10-12
IO10-14
IO10-17
IO16-12
IO16-11
IO16-10
IO16-8
IO16-6
IO16-5
IO16-3
IO16-2
IO8-2
IO8-3
IO8-5
IO8-8
IO8-10
IO6-2
IO6-3
IO6-5
IO6-6
IO6-8
IO6-10
IO6-14
IO15-17
IO15-15
IO15-14
IO15-12
IO15-11
IO15-10
IO15-8
IO15-3
IO15-2
XC95288XL
IO13-17
IO13-15
IO13-14
IO13-11
IO13-8
IO13-2
IO4-6
IO4-14
IO2-2
IO2-3
IO2-5
IO2-6
IO2-8
IO2-10
IO2-12
IO2-14
IO2-15
IO2-17
IO11-17
IO11-14
IO11-12
IO11-11
IO11-10
IO11-5
IO11-3
IO9-17
IO9-14
IO9-12
IO9-11
IO9-8
IO9-6
IO9-5
IO9-3
IO9-2
IO1-5
IO1-6
IO1-8
IO1-10
IO1-12
IO1-14
IO1-15
IO1-17
IO7-15
IO7-12
IO7-5
IO7-3
IO3-2
IO3-12
GTS3
GTS4
GTS1
GTS2
GCK1
GCK3
GSR
32
33
X-EXTCLK
X-CTRL-SCLK/SCL
130
131
132
133
134
4
7
X-SDOUT2B
X-SDOUT1
X-SDIN1
X-SDIN2B
X-BITCLK1
X-LRCLK1
X-CONFIG-BITLRIO
X-XTI
117
118
119
120
121
124
125
126
128
129
(141)
IO5-17
IO5-15
IO5-14
IO5-12
IO5-10
IO5-5
IO5-2
107
106
105
104
103
102
101
100
98
97
96
95
94
93
92
91
88
87
86
85
83
82
81
80
79
78
77
76
75
74
71
70
69
68
66
64
61
60
59
58
57
56
54
53
52
51
50
C
R77
R83
51
X-DAC-SDTI2
X-ADC-SDTO2
X-ADC-SDTO1
X-ADC-LRCK
X-ADC-BICK
X-ADC-MCLK
X-CTRL-CSN
X-CTRL-RQN
X-CTRL-SI
X-I2CSEL
X-CTRL-RESET
X-CTRL-XCS/SDA
X-CTRL-HOST
51
X-CTRL-SO
TP9
TP10 TP11 TP12
49
48
46
45
B
44
43
41
40
39
35
34
TCK
TDI
TDO
TMS
4.7k(DIP)
4.7k(DIP)
(84)
67
63
122
65
R70
R65
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
X-SCLK/SCL
X-SDA
GCK2
IO3-15
DVDD-3.3V
IO12-2
IO12-3
IO12-5
IO12-8
IO12-10
IO12-12
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
U6
110
111
112
113
115
116
18
29
114
123
144
36
47
62
72
89
90
99
108
D
(42)
141
8
42
84
(8)
X-CLKO
JTAG
A
TCK
TDI
TDO
TMS
VDD
DVSS
JP21
1
3
5
7
9
HEADER 5X2
C46
TP13
BLACK
2
4
6
8
10
DVDD-3.3V
+ C45
100uF/16V(A)
1
2:
4:
6:
8:
10:
A
DVDD-3.3V
0.1uF
Title
Size
A3
Date:
5
4
3
2
AKD7736B-A-MAIN
Document Number
Rev
0
XILINX
Monday, August 19, 2013
Sheet
1
9
of
9
5
4
3
2
1
TP1
25
26
27
28
29
30
31
32
33
34
35
36
CN1
48pin_3
VSS
TP2
TP3
TP4
TP5
TP6
VDD2
SDA
RQN/CAD1
TP9
BITCLKI2/JX1
TP10
SO
VSS
D
TP7
TP8
SCLK/SCL
SI/CAD0
SDIN4
D
TP11
LRCLKI2/JX2
STO
+
C1
10uF
TP12
C2
AVDRV
C3
1u(DIP)
0.1uF
CN3
48pin_4
TP14
SDIN3
37
R2
R1 R3
51
51
TP13
CLKO
TP17
BITCLKO
TP15
LRCLKO
TP18
SDIN2A
TP20
PDN
TP22
I2CSEL
TP24
VDD1
24
51
VDD4
TP30
TESTI2
R7
43
44
51
45
46
44
47
48
C9
45
+
C8
25
27
26
SO
STO
BITCLKI2/JX1
LRCLKI2/JX2
29
28
30
RQN/CAD1
SDIN4
31
32
SDA
SI/CAD0
33
34
VDD
LRCLKO
BITCLKI3
SDIN2A
LRCLKI3
PDN
SDIN2C
I2CSEL
AK7736B
JX0
VDD
EXPDN
VSS
VDD
RDY
TESTI2
SDOUT2A
VSS
LFLT
0.1uF
10uF
SDOUT3
SDOUT4
24
R4
51
23
R5
51
22
R6
51
20
21
20
19
19
18
18
C6
17
+
R8
15
R9
51
14
R10
51
13
R11
51
51
10uF
17
TP27
RDY
TP29
SDOUT2A
TP31
SDOUT3
TP32
SDOUT4
16
15
12
11
10
9
8
7
6
5
4
3
2
C7
0.1uF
16
46
1
C
21
XTO
TP28
43
22
CLKO
XTI
EXPDN
42
42
U1
BITCLKO
VSS
TP26
41
TVDD
JX0
40
LRCLK1
TP25
39
BITCLK1
SDIN2C
TESTI3
LRCLKI3
TP23
VSS
SDIN2B
TP21
41
SDIN3
SDIN1
38
SDOUT1
37
BITCLKI3
40
TESTI1
TP19
C
SCLK/SCL
AVDRV
0.1uF
VSS
+
10uF
39
VDD
C5
SDOUT2B
VDD3
36
C4
TP16
35
23
38
14
47
TP33
LFLT
R12 R13
R14 R15
51
51
13
C10
48
51
JP1
XTI-SEL
51
12n(DIP)
C12
C11
48pin_2
0.1uF
VSS
22pF(DIP)
Y1
12.288MHz(DIP)
+
C13
B
VSS
CRY-XTI
CN2
EXT-XTI
B
10uF
R16
0(DIP)
TP34
TP35
TP36
TP37
C14
TP38
22pF(DIP)
SDOUT2B
TP40
TP39
SDIN1
TESTI3
LRCLK1
EXT
TP41
TP42
TP43
SDIN2B
BITCLK1
TVDD
12
11
CN4
48pin_1
10
9
8
7
6
4
3
2
1
SDOUT1
5
TP44
TESTI1
VSS
VSS
A
A
Title
AKD7736B-A-SUB
Size
C
Date:
5
4
3
2
Document Number
Rev
0
AK7736B
Monday, August 19, 2013
Sheet
1
1
of
1
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