AK7754EN

[AKD7754-A]
AKD7754-A
AK7754 Evaluation Board Rev.1
GENERAL DESCRIPTION
The AKD7754-A is an evaluation board for the AK7754, which is an audio processor including a stereo
CODEC, SRC, 2 digital I/Fs, microphone pre-amplifier and bias /headphone amplifier and audio DSP.
This board is composed of a main board and a sub board. It is possible to control the setting of this board
via USB port. RCA and phonejack connectors are used for the analog input and output signal. This board
also has digital interface, enabling interfacing to digital audio systems via optical connector.
„ Ordering guide
AKD7754-A
---
Evaluation board for AK7754
Control software and USB cable are packed with this.
FUNCTION
† Read/Write access to PRAM, CRAM, OFFRAM and registers
† Compatible with 2 types of digital audio interface
- Optical input / output
- 10pin header for interface with external data source (x2)
† Stereo ADC input (single-end)
† Stereo DAC line output(single-end,differential), Headphone output (single-end)
† USB port for board control
+12V
Regulator
Regulator
Regulator
USB 3.3V
-12V GND
3.3V
3.3V
PIC4550
USB
AIN 2ch
Amp
FPGA
Opt In
AK7754
D-MIC 2ch
(XC95144)
MIC 2ch
AK4114
AOUT
Opt Out
HPOUT
10 Pin Header
SMUX1
SMUX2
1.8V
Figure 1. AKD7754-A Block Diagram
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[AKD7754-A]
Evaluation Board Diagram
HP
HPR
1
2
9
SMUX
PORT1
10
1
9
1
JTAG
2
TP41B
2
G
E
R
D1
Color led
GND
USB
XILINX
1
L
A
T
X
PIC18F
4550
2
W
S
Header5
TM1B
XTAL2
+1.8V
MICR
MICL
Digital
MIC
2
REG1
7754
-12V
TP3
10
74HC
221A
Header10
k
n
i
S
t
a
e
H
TP40B
3
G
E
R
SMUX
PORT2
10
NJM
5532M
k
n
i
S
t
a
e
H
Header10
GND
9
DVSS
TP5
+12V
HPL
OUTL
OUTR
„ Board Diagram
SPDIF
OUT
74HCT243
74HCT541
1
L
A
T
X
4114
1
W
S
SPDIF
IN
AGND
AK4359
REG4
DAC1-L
DAC1-R
DAC2-L
DAC2-R
DAC3-L
DAC3-R
DAC4-L
DAC4-R
AIN-R
TP6
AIN-L
5532
TP2
Figure 2. AKD7754-A Board Diagram
„ Description
Main board
(1) AIN/DAC (RCA-JACK)
AIN: These are analog signal input Jacks. The signals are input to AIN pins.
(The white Jack is used for left channel, and the red one is used for right channel.)
DAC: These are analog signal output Jacks. The signals are output from AK4359.(unused)
(2) AK4114
AK4114 has DIR, DIT and X’tal oscillator. It transports digital data to AK7754 when working in master mode and
outputs data from AK7754 when working in slave mode.
(3) SPDIF-IN/ SPDIF-OUT
SPDIF-IN: Optical input connector. It supports sampling frequencies from 32kHz to 96kHz for input. It is used as
digital data source for AK7754.
SPDIF-OUT: Optical output connector. It outputs the data from whichever among SDOUT1,2 and SDOUTM.
(4) Power supply
Connect to +12V, GND, -12V and 1.8V. Total power supply current of about 250mA is consumed when normal
operation.
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(5) PIC18F4550
USB control chip. It is possible to set up the registers of AK7754, Xilinx, AK4359 and AK4114 from PC via USB
port.
(6) SW2
Push type button. It is used to initialize the PICIF4550. When connecting the board to PC, it is required to push down
the button for initialization.
(7) Xilinx
Xilinx used for data path control. It is possible to run a variety of tests by way of controlling the data path via control
software.
(8) SW1
The SW1 is used to select clock source between [EXT] and [XTL] to change the clock mode of AK7754. The setting
of other jumper pins is according to Table 3 and Table 4.
(9) SMUX port
10 pin header for interface with external data source. Two ports are equipped and available to achieve with other
audio system.
Pin I/O Function
pin
I/O Function
1
I/O MCLK
2
P
GND
3
I/O BITCLK
4
P
GND
5
I/O LRCLK
6
P
GND
7
I
SDTI
8
P
GND
9
P
VDD
10
O
SDTO
Table 1. The assignments of the SMUX port
Sub Board
(10) MICL/MICR (PHONE jack)
Terminal of microphone unit. IN3L for Lch and IN3R for Rch
(11) Digital Mic (Unused)
(12) +1.8V(Power supply)
Power supply terminal。Supply power drain. (Table 2)
(13) OUTL/P、OUT/NR
Line output terminal of OUTL/P and OUTR/N pins
(14) HPL/R(RCA)、HP(Phonejack)
HP-amp output of HPL and HPR pins.
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Evaluation Board Manual
„ Operation sequence
(1) Set up the power supply lines.
[The main board jumper setting should be set as following]
JP1
JP2
JP6
AVDD
DVDD
P-DVDD
(Short)
(Short)
(Short)
Set up the power supply lines.
Name Color
Voltage
+12V
Red
+9∼+12V
-12V
Blue
-9∼-12V
GND
TM1B
Black
Red
0V
+1.8V
JP5
PIC-VDD-SEL
5V
3.3V DVDD
Comment
Regulator,
Power supply for op-amp
Power supply for op-amp
Ground
DVDD18
Attention
This jack is always needed.
Power line
This jack is always needed.
Power line
This jack is always needed.
This jack is always needed.
Power line
Table 2. Set up of power supply lines
Each supply line should be distributed from the power supply unit. The power of AK7754 and peripheral device
are supplied by two regulators equipped on the board convert from 12V to 3.3V.
(2) Set up the evaluation mode, jumper pins and connectors. ( according to the evaluation mode )
(3) Power On
(4) Connect the board to PC with the USB cable packed.
It is required to push down the button (SW2) to initialize the USB control chip.
(5) Start the control software(AK7754.exe) and download the appropriate script file. ( see script section )
„ Evaluation Mode
In case of AK7754 evaluation along with AK4114, it is necessary to correspond to audio interface format for AK7754
and AK4114. About AK7754’s audio interface format, refer to datasheet of AK7754. About AK4114’s audio interface
format, refer to Table 6 in this manual.
Applicable Evaluation Mode
1. Evaluation mode of CODEC using SPDIF of AK4114 : CKM Slave Mode = 2 (Default)
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(1) Evaluation mode of CODEC using SPDIF of AK4114: CKM Slave Mode = 2 (Default)
SPDIF-IN and SPDIF-OUT are used. Set the clock mode of AK7754 to Slave Mode (12.288MHz). AK4114
should provide MCLK, BICK, LRCK and digital data to/from AK7754.
1. Review the default jumper setting. ( See Setting Of Jumper Pins )
2. Connection of connector
For analog input, RCA connector RCA1 AINR and RCA2 AINL are available.
For analog output, RCA connector OUTL/P and OUTR/N are available.
For digital input, optical connector PORT1 (SPDIF-IN) is available.
For digital output, optical connector PORT2 (SPDIF-OUT) is available.
3. Download the script file from the script tab. In case of ADC evaluation , use “CKM2-AIN-ADC-DIT.txt”. In case
of DAC evaluation , use “CKM2-DIR-DAC-AOUT.txt”.
„ Control Board
It is possible to control AKD7754-A via general USB port. Connect cable with the USB port on board and PC
Control software is packed with this board. The software operation sequence is included in the evaluation board
manual.
„ Indication for LED
[LED] U9:
[LED] D1:
When power is supplied, LED is lighted to red. Monitor the PC-RQN clock signal and change green
when the board is communicating with PC.
The status of AK7754’s STO pin is displayed. ‘H’ → Light on; ‘L’ → Light off.
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„ Setting of Jumper Pins
(Main board)
Jumper
SW1 (AK4114 Clock)
JP1 (7754-AVDD)
JP2 (7754-DVDD)
JP3 (AGND-GND)
JP4(HEADER5)
JP5 (PIC-VDD-SEL)
JP6(P-DVDD)
JP7(SMUX PORT1)
JP8(SMUX PORT2)
JP9(JTAG)
Setting (Default)
Note
AK4114 Clock Source
XTL : Crystal Clock
EXT : External Clock
Short
AK7754 AVDD
Short
AK7754 DVDD
Short
Short of AGND and DVSS
Open
Download I/F ( unused )
USB chip power supply
“USB-5V”: USB 5V
“USB-3.3V”
“USB-3.3V”: USB 3.3V
“DVDD”: Peripheral DVDD 3.3V
Short
Peripheral DVDD
Open
Serial Audio I/F 1
Open
Serial Audio I/F 2
Open
JTAG I/F ( unused )
Table 3. Setting of jumper pins on main board
“EXT”
(Sub board)
Jumper(Name)
Default Setting
Note
JP4B (7754-AVDD)
Short
AK7754 Clock source
“CRY-XTI”: X’tal clock
“EXT-XTI”: External Clock
AK7754 AVDD
JP2B (7754-DVDD)
Short
AK7754 DVDD
JP9B(XTI-SEL)
“EXT-XTI”
JP10B (7754-DVDD)
Short
AK7754 DVDD
JP11B (7754-DVDD18)
Short
AK7754 DVDD18
JP1B (7754-HVDD)
Short
JP5B（INR/P）
IN1R
JP6B(INL/N)
IN1L
JP8B(EXT-MIC1)
OPEN
JP7B(EXT-MIC2)
OPEN
JP3B(DMVDD-SEL)
MPWR
AK7754 HVDD
Analog Input select
IN1R : Single Ended Rch
IN1P : Differential Positive
IN2R : Single Ended Rch
IN2P : Differential Positive
IN3R : Single Ended Rch
Analog Input Select
IN1L : Single Ended Lch
IN1N : Differential Negative
IN2L : Single Ended Lch
IN2N : Differential Negative
IN3L : Single Ended Lch
External microphone connection select 1
OPEN : D-MIC, A-MIC
Short : unused
External microphone connection select 2
OPEN : D-MIC, A-MIC
Short : unused
Microphone bias power select
AVDD : Analog Power Supply
MPWR : MPWR output
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JP16B(LAMP)
OPEN
JP17B(RAMP)
OPEN
JP14B(OL-THR/AMP)
THR
JP15B(OR-THR/AMP)
THR
JP12B(HPL-RCA)
SHORT
JP13B(HPR-RCA)
SHORT
External OP-Amp enable to use
OPEN : Disable
SHORT : Enable
External OP-Amp enable to use
OPEN : Disable
SHORT : Enable
Signal path of OUTL/P select
THR : OUTL/P output
AMP : AMP output
Signal path of OUTL/P select
THR : OUTR/N output
AMP : AMP output
Signal path HP-Amp Lch output select
OPEN : unused HPL-RCA output
SHORT : HPL-RCA output enable
Signal path HP-Amp Lch output select
OPEN : unused HPR-RCA output
SHORT : HPR-RCA output enable
Table 4. Setting of jumper pins on sub board
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[AKD7754-A]
Control Software Manual
„ Set-up of the evaluation board and control software
(1) Set up the AKD7754-A according to previous term.
(2) Connect AKD7754-A to PC with the cable packed Push down the reset button (SW1) to initialize the USB chip.
(3) Insert the CD-ROM labeled “AKD7754-A Evaluation Kit” into the CD-ROM drive.
(4) Access the CD-ROM drive and double-click the icon of “AK7754.exe” to set up the program.
(5) Then please evaluate according to the follows.
„ Operation flow
Keep the following flow
1. Set up the control program according to the explanation above.
2. Click “Board Init” button to initialize the board.
3. Select the needed dialogue to evaluate by changing the setting.
If the USB cable is removed when control software is used, please close the software and set up it again when operation
is needed again.
Figure 3. The image of control software
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[AKD7754-A]
Control software is possible to execute program downloading, to set up the registers, to set up the FPGA and to process
script file. They can be selected by the tab items above. The buttons of control signals which are frequently used and the
initialization buttons are placed outside the tab dialogue.
[INIT_RESET]:
[CODEC]:
[Clock]:
[Board Init]:
[READ]:
Initial Reset. It is used to initialize the AK7754.
CODEC Reset.
Clock Reset. Clock Reset is required when changing the clock mode or the frequency of input clock
without initial reset. The register will not be initialized.
The setting of registers of AK7754, FPGA and AK4114 is written to board together.
Read back CONT register or TEST register decided by [Read Select] button and show the result on
register column.
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(1) Download
Figure 4. [Download] Dialogue
File of Source column, Program column, CRAM column or OFFSET column can be selected by clicking the [refer]
button of each column or by way of dropping or tracking files from desktop.
CRAM file or OFFSET file can be selected and be written to CRAM or OFF-RAM by clicking the [refer] button of
CRAM write@operation column or OFF-RAM write@operation column when system is running. The data will be
written to specific address of CRAM or OFF-RAM when the [write] button at right side is clicked.
[Assemble]:
[Write]:
[Assemble Write]:
[PRAM read]:
[CRAM read]:
[Offset read]:
[CRAM SAVE]:
[Offset SAVE]:
[MICR1]:
[MICR2]:
[MICR3]:
[MICR4]:
[JX]:
Compile the source file and the output file will be selected to the download file automatically.
Download the program to AK7754.
Compile the source file and then download the file to AK7754.
Read the data of PRAM to temporary file.
Read the data of CRAM to temporary file.
Read the data of OFF-RAM to temporary file.
Read the data of CRAM and save to file.
Read the data of OFF-RAM and save to file.
Read the data of register MICR1 when program is running and show the result to dialogue.
Read the data of register MICR2 when program is running and show the result to dialogue.
Read the data of register MICR3 when program is running and show the result to dialogue.
Read the data of register MICR4 when program is running and show the result to dialogue.
JX code setting column.
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[AKD7754-A]
(2) Register Set up
Figure 5. [REG1] Dialogue
Tab Dialogues of REG1/REG2/REG3 are used to regulate the registers’ setting. (It is prohibited to process
test and reserved items.)
As the checkbox is clicked, the data is written to the register after system reset.
(See the control register setting in the datasheet.)
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[AKD7754-A]
(3) FPGA Set up
Figure 6. [FPGA1] Dialogue
The FPGA1/FPGA2 dialogues are used to regulate the data path of AK7754 and the setting of AK4114 via
FPGA.
FPGA Set up (It is prohibited to process test and reserved items.)
ADDRESS = 0 ( A[1:0] = 00 )
Bit
D[15]
Function
TEST1
D[14]
TEST2
D[13:12]
TX-DAT
Default: bold type
Description
TEST1 pin setting
0 : Low
1 : High
TEST2 pin setting
0 : Low
1 : High
Output data source for AK4114
00 : SDOUT1
01 : SDOUT2
10 : SDOUTM/RDY
11 : reserved
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D[11:10]
SDIN1/JX2
D[9:7]
SDIN2/JX2
D[6:1]
D[0]
reserved
Reserved(N/A)
Input data source to SDIN1 pin of AK7754
00 : AK4114 IN (RX_DAT)
01 : SMUX1_DAT1(Input)
10 : SMUX2_DAT1(Input)
11 : Low
Input data source to SDIN2/JX0 pin of AK7754
000 : AK4114 IN (RX_DAT)
001 : SMUX1_DAT1(Input)
010 : SMUX2_DAT1(Input)
011 : Low
100 : Low
101 : High
110 : Low
111 : Low
Reserved
Power down/up setting of PDN pin on
0 : Power Down(Low)
1 : Power up(High)
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ADDRESS = 1 ( A[1:0] = 01 )
Bit
D[15]
Function
reserved
D[14]
reserved
D[13]
reserved
D[12]
reserved
D[11:10]
BICK1/LRCK1
D[9:8]
BICK2/LRCK2
D[7:6]
EXT-XTI
D[5]
TRXPDN
D[4]
TRX-BICK/LRCK
AK4114
D[3]
SMUX2 In/Out
D[2]
SMUX1 In/Out
D[1]
reserved
D[0]
reserved
Description
reserved
0 : Low
1 : High
reserved
0 : Low
1 : High
reserved
0 : Low
1 : High
reserved
0 : Low
1 : High
Input switch of AK7754’s BICK1/LRCK1 (Slave mode)
00 : AK4114 BICK/LRCK
01 : SMUX1_BICK/LRCK
10 : SMUX2_BICK/LRCK
11 : Low
Input switch of AK7754’s BICK2/LRCK2(Slave mode)
00 : AK4114 BICK/LRCK
01 : SMUX1_BICK/LRCK
10 : SMUX2_BICK/LRCK
11 : Low
Input switch of AK7754’s XTI
External Clock select
00 : AK4114 RX_CLK
01 : SMUX1_MCLK
10 : SMUX2_MCLK
11 : Low
Select PDN pin of AK4114
0 : Low
1 : High
I/O direction of the AK4114 BICK/LRCK
0 : BIT, LR input (AK7754 slave)
1 : BITCLKO/LRCLKO output (master)
I/O direction of the BICK/LRCK on SMUX2
0 : BIT, LR input (AK7754 slave)
1 : BITCLKO/LRCLKO output (AK7754 master)
I/O direction of the BICK/LRCK on SMUX1
0 : BIT, LR input (AK7754 slave)
1 : BITCLKO/LRCLKO output (AK7754 master)
reserved
0 : Low
1 : High
reserved
0 : Low
1 : High
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ADDRESS = 2 ( A[1:0] = 10 )
Bit
D[15:14]
Function
SMUX2_DAT2
(SDTO)
D[13:12]
SMUX1_DAT2
(SDTO)
D[11:10]
TX-CLK
D[9]
reserved
D[8:7]
CAD[1:0]
D[6:5]
SMUX2_MCLK
D[4:3]
SMUX1_MCLK
D[2:0]
Reserved
Description
Output data source for DAT2 pin of port SMUX2
00 : SDOUT1
01 : SDOUT2
10 : SDOUTM
11 : Low
Output data source for DAT2 pin of port SMUX1
00 : SDOUT1
01 : SDOUT2
10 : SDOUTM
11 : Low
The clock setting of XTI pin of AK4114
00 : AK7754 CLKO
01 : SMUX1_MCLK
10 : SMUX2_MCLK
11 : Low
reserved
0 : Low
1 : High
CAD pin setting [CAD1:CAD0]
00 : Low, Low
01 : Low, High
10 : High, Low
11 : High, High
Input switch of the MCLK in SMUX2
00 : MCLK input (IN)
01 : AK7754-CLKO (OUT)
10 : AK4114_RX_CLK (IN)
11 : SMUX1_MCLK (1→2 OUT)
Input switch of the MCLK in SMUX1
00 : MCLK input (IN)
01 : AK7754-CLKO (OUT)
10 : AK4114_RX_CLK (IN)
11 : SMUX2_MCLK (2→1 OUT)
Table 5. FPGA Set up table3
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[AKD7754-A]
The setting of AK4114
Function
MCLK
CM
DIF
Description
Frequency setting of MCLK1 clock output on AK4114
00: 256fs
01: 256fs
10: 512fs
11: 128fs
Master clock operation mode(CM bit) of AK4114
00: CM = 00
01: CM = 01
10: CM = 10
11: CM = 11
Digital audio interface format of AK4114
000: 16bit Right( O )
001: 18bit Right( O )
010: 20bit Right( O )
011: 24bit Right( O )
100: 24bit Left( O )
101: 24bit I2S( O )
110: 24bit Left( I )
111: 24bit I2S( I )
Table 6. AK4114 Set up
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[AKD7754-A]
(4) Script
Figure 7. [SCRIPT] Dialogue
As the script file is selected, it is executed directly. If [Repeat] button is clicked, the selected script file will be executed
once again.
The script commands are listed as follow.
Command
[SCRIPT]
;Comment
W,<address>,<data>
W,0xC0,0x00
WL,<command>,<address>,<data>,…
WL,0x82,0x0022,0x4000,0x4000,0x4000,
D,<address>,<data>
X,<address>,<data>
P,<message>
RI: H / RI:L
RS:H / RS:L
RC:H / RC:L
T,<wait>
T,50mS
LP:<filename>
LC:<filename>
LO:<filename>
Description
Header of script file. The script file will be compiled to error without this header.
The content after semicolon is ignored as comment.
Write data to register. Both address and data must be BYTE(8bit).
Write data continuously. It can be used when CRAM is running. The command
must be BYTE(8bit) and the data below must be WORD(16bit).
Write data to AK4114.
Write data to the register of FPGA.
Show message and pause the processing of script.
Init reset.
CODEC reset.
Clock reset.
Wait some milliseconds.
When actual operation, it is possible to wait longer than this.
Download program file to DSP.
Download CRAM file to DSP.
Download OFRAM file to DSP.
Table 7. Script Command
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Measurement Results
[Measurement condition]
・ Measurement unit
・ MCKI
・ BICK
・ fs
・ Bit
・ Measurement Mode
・ Power Supply
・ Input Frequency
・ Measurement Frequency
・ Temperature
: Audio Precision, System two Cascade
: 12.288MHz
: 64fs
: 48kHz
: 24bit
: Slave Mode, CKM Mode 2
: +12V, -12V,+ 1.8V, GND
: 1kHz
: 20 ~ 20kHz
: Room
[Measurement Results]
1. ADC BW=20Hz∼20kHz@fs=48kHz
Results
ADC: AIN => ADC
S/(N+D) (-1dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
Lch
Rch
83.0
89.5
89.5
83.0
89.5
89.5
Unit
dB
dB
dB
2. DAC BW=20Hz∼20kHz@fs=48kHz
Results
DAC: Serial => DAC
S/(N+D) (0dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
Lch
Rch
86.3
96.3
96.3
86.3
96.4
96.4
Unit
dB
dB
dB
3. HP BW=20Hz∼20kHz@fs=48kHz
Results
HP: Serial => HP
S/(N+D) (-3dBFS)
S/N
(A-weighted)
<KM099001>
Lch
Rch
72.7
89.9
72.8
89.9
Unit
dB
dB
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[AKD7754-A]
[ADC Plot Data]
ADC
1. FFT Input -1dB (fs=48kHz)
AK7754 AIN1 > ADC > DIT
[FFT,fs=48kHz,fin=1kHz,InputLevel=-1dBFS]
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 1. FFT ( 1kHz, -1dBFS )
2. FFT Input -60dB (fs=48kHz)
AK7754 AIN1 > ADC > DIT
[FFT,fs=48kHz,fin=1kHz,InputLevel=-60dBFS]
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
-160
20
50
100
200
500
1k
2k
Hz
Figure 2. FFT ( 1kHz, -60dBFS )
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3. FFT No Input (fs=48kHz)
AK7754 AIN1 > ADC > DIT
[FFT,fs=48kHz,fin=1kHz,No Signal]
+0
-20
-40
d
B
F
S
-60
-80
-100
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 3. FFT ( No Input )
4. THD+N vs. Input Level (fs=48kHz)
AK7754 AIN1 > ADC > DIT
[THD+N vs Input Level,fs=48kHz,fin=1kHz]
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 4. THD+N vs. Input Level
<KM099001>
2009/05
- 20 -
[AKD7754-A]
5. THD+N vs. Input Frequency (fs=48kHz)
AK7754 AIN1 > ADC > DIT
[THD+N vs Frequency,fs=48kHz,InputLevel=-1dBFS]
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 5. THD+N vs. Input Frequency
6. Linearity (fs=48kHz)
AK7754 AIN1 > ADC > DIT
[Linearity,fs=48kHz,fin=1kHz]
+0
T TT T
-20
-40
d
B
F
S
-60
-80
-100
-120
-120
-100
-80
-60
-40
-20
+0
dBr
Figure 6. Linearity
<KM099001>
2009/05
- 21 -
[AKD7754-A]
7. Frequency Response (fs=48kHz)
AK7754 AIN1 > ADC > DIT
[Frequency Response,fs=48kHz,InputLevel=-1dBFS]
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 7. Frequency Response
8. Crosstalk (fs=48kHz)
AK7754 AIN1 > ADC > DIT
[Crosstalk,fs=48kHz,InputLevel=-1dBFS,Red=Lch,Blue=Rch]
-60
TTTTTTTTTTTTTTTTTTT TTTTTTTT TTTTTTTT TTTT TT T T TT
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 8. Crosstalk
<KM099001>
2009/05
- 22 -
[AKD7754-A]
[DAC Plot Data]
9. FFT Input 0dB (fs=48kHz)
AK7754 DIR > DAC > AOUT
[FFT,fs=48kHz,fin=1kHz,InputLevel=0dBFS]
+0
-20
-40
d
B
r
-60
A
-100
-80
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 9. FFT ( 1kHz, 0dBFS )
10. FFT Input -60dB (fs=48kHz)
AK7754 DIR > DAC > AOUT
[FFT,fs=48kHz,fin=1kHz,InputLevel=-60dBFS]
+0
-20
-40
d
B
r
-60
A
-100
-80
-120
-140
-160
20
50
100
200
500
1k
2k
Hz
Figure 10. FFT ( 1kHz, -60dBFS )
<KM099001>
2009/05
- 23 -
[AKD7754-A]
11. FFT No Input (fs=48kHz)
AK7754 DIR > DAC > AOUT
[FFT,fs=48kHz,fin=1kHz,No Singal]
+0
-20
-40
d
B
r
-60
A
-100
-80
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 11. FFT ( No Input )
12. THD+N vs. Input Level (fs=48kHz)
AK7754 DIR > DAC > AOUT
[THD+N vs InputLevel,fs=48kHz,fin=1kHz]
-60
-70
-80
d
B
r
A
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 12. THD+N vs. Input Level
<KM099001>
2009/05
- 24 -
[AKD7754-A]
13. THD+N vs. Input Frequency (fs=48kHz)
AK7754 DIR > DAC > AOUT
[THD+N vs Frequency,fs=48kHz,InputLevel=0dBFS]
-60
-70
-80
d
B
r
A
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 13. THD+N vs. Input Frequency
14. Linearity (fs=48kHz)
AK7754 DIR > DAC > AOUT
[Linearity,fs=48kHz,fin=1kHz]
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 14. Linearity
<KM099001>
2009/05
- 25 -
[AKD7754-A]
15. Frequency Response (fs=48kHz)
AK7754 DIR > DAC > AOUT
[Frequency Response,fs=48kHz,InputLevel=0dBFS]
+1
+0.8
+0.6
+0.4
d
B
r
A
+0.2
+0
-0.2
-0.4
-0.6
-0.8
-1
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
10k
20k
Hz
Figure 15. Frequency Response
16. Crosstalk (fs=48kHz)
AK7754 DIR > DAC > AOUT
[Crosstalk,fs=48kHz,InputLevel=0dBFS,Red=Lch,Blue=Rch]
-60
TTT
TT
T
-70
-80
d
B
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
Hz
Figure 16. Crosstalk
<KM099001>
2009/05
- 26 -
[AKD7754-A]
[HP Plot Data]
17. FFT Input -3dB (fs=48kHz)
AK7754 DIR > DAC > HPOUT
[FFT ,fs=48kHz,fin=1kHz,fc=212Hz(C=47uF,R=16ohm),InputLevel=-3dBFS]
+0
-20
-40
d
B
r
-60
A
-100
-80
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 17. FFT ( 1kHz, -3dBFS )
18. FFT Input -60dB (fs=48kHz)
AK7754 DIR > DAC > HPOUT
[FFT ,fs=48kHz,fin=1kHz,fc=212Hz(C=47uF,R=16ohm),InputLevel=-60dBFS]
+0
-20
-40
d
B
r
-60
A
-100
-80
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 18. FFT ( 1kHz, -60dBFS )
<KM099001>
2009/05
- 27 -
[AKD7754-A]
19. FFT No Input (fs=48kHz)
AK7754 DIR > DAC > HPOUT
[FFT ,fs=48kHz,fin=1kHz,fc=212Hz(C=47uF,R=16ohm),No Signal]
+0
-20
-40
d
B
r
-60
A
-100
-80
-120
-140
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 19. FFT ( No Input )
20. THD+N vs. Input Level (fs=48kHz)
AK7754 DIR > DAC > HPOUT
[THD+N vs InputLevel,fs=48kHz,fin=1kHz,fc=212Hz(C=47uF,R=16ohm)]
-60
-70
-80
d
B
r
A
-90
-100
-110
-120
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 20. THD+N vs. Input Level
<KM099001>
2009/05
- 28 -
[AKD7754-A]
21. THD+N vs. Input Frequency (fs=48kHz)
AK7754 DIR > DAC > HPOUT
[THD+N vs
Frequency,fs=48kHz,InputLevel=-3dBFS,fc=212Hz(C=47uF,R=16ohm)]
-60
-70
-80
d
B
r
A
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 21. THD+N vs. Input Frequency
22. Linearity (fs=48kHz)
AK7754 DIR > DAC > HPOUT
[Linearity,fs=48kHz,fc=212Hz(C=47uF,R=16ohm)]
+0
-20
-40
d
B
r
A
-60
-80
-100
-120
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 22. Linearity
<KM099001>
2009/05
- 29 -
[AKD7754-A]
23. Frequency Response (fs=48kHz)
AK7754 DIR > DAC > HPOUT
[Frequency
Response,fs=48kHz,InputLevel=-3dBFS,fc=212Hz(C=47uF,R=16ohm)]
+0
-5
d
B
r
-10
-15
A
-20
-25
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 23. Frequency Response
<KM099001>
2009/05
- 30 -
[AKD7754-A]
REVISION HISTORY
Date
(yy/mm/dd)
09/04/28
Manual
Revision
KM099000
Board
Revision
0
Reason
First edition
09/05/13
KM099001
1
Change
09/05/13
KM099001
1
09/05/13
KM099001
1
Measurement
Results Add
Plots Add
Page
Contents
Capacitance change:
C17,C18 (4.7uF→1uF),C17B,C18B(1uF→short),
Resistance change:
R18B,R20B(47k→open),R3B, R6B(100k→open)
R4B,R5B(51→open)
Mini jack change:
J1B,J2B(open)
HP part:fs=48KHz
HP part:fs=48KHz
IMPORTANT NOTICE
z These
products
and
their
specifications
are
subject
to
change
without
notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use
of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from
any and all claims arising from the use of said product in the absence of such notification.
<KM099001>
2009/05
- 31 -
4
3
DMCLK
C6
10uF
1
STO
2
SCL
CAD0
3
4
RDY/SDOUTM
SO/RDY
5
6
8
9
7
TEST2
INITRSTN
+
TEST2
TP5
R9
51
D
1
STO
TP7
HPR
25
STO
48pin_1
RDY/SDOUTM
TP13
51
SO/RDY
TP15
R13
40
RSV10
C17
(SHORT)
C18
(SHORT)
R20
AINL
(OPEN)
1
TP17
AVDD
9
R12
VCOM
SCL
TP28
AINL
JP4
AVDD
JP5
INR/P
1
3
5
7
9
2
4
6
8
10
1
3
5
7
9
2
4
6
8
10
JP6
INL/N
21
MPRF
CAD0
42
AK7754EN
MPWR
CAD1
19
43
IN1R/IN2P
LRCK2/JX0
18
DVDD
51
IN1L
IN1N
IN2L
IN2N
IN3L
44
IN1L/IN1P
BICK2/JX1
17
5
CLKO
TP29
R21
51
45
IN2R/IN2N
SDIN2/JX2
16
R22
IN2L/IN1N
SDOUT2
51
LRCKO
TP30
51
BICKO
TP31
51
LRCK1
TP32
15
47
IN3R/DMDAT
SDOUT1
14
2
1
AGND DGND
100uF(D/N)
RSV1
RSV2
TEST1
RSV3
RSV4
TP34
SDIN1/JX2
TP35
BICK1/JX1
2
1
LRCKO
CN6
12
BICKO
11
LRCK1/JX0
10
9
BICK1/JX1
SDIN1/JX2
8
DVDD18
7
6
VSS1
DVDD
5
+
R34
51
R33
51
B
AK7754
51
51
R29
51
TM1
DVDD18
100uF(D/N)
RSV5
A
1
i
RED(+1.8V)
TJ-563
BICK1
1
R32
51
VSS1
2
4
22pF(DIP)
TP38
TEST1
10uF
DVDD DVDD18 TP37
JP10
JP11 DVDD18
1 C27
C28 1
DVDD
1
TP36
DVDD
EXT-XTI
2
10uF
C26
CL4
Cut Land short
C25
+
1
1
R31
0(DIP)
0.1uF
C24
13
3
R25
R27
R28
+
2
1
CLKO
4
+
Y1
12.288MHz
A
1
C22
0.1uF
EXT-XTI
22pF(DIP)
R30
51
CL3
Cut Land short
C21
SDIN1
8.2k(DIP)
C23
CL2
Cut Land short
XTI
XTO
3
JP9
XTI-SEL
CRY-XTI
33nF(DIP)
R26
1
C20
1
0F(DIP)
TEST1
IN3L/DMCLK
2
C19
48
TP33
LFLT
LFLT
EXT-MIC1
VSS4
R24
IN3L
JP8
EXT-MIC1
1
IN3R
EXT-MIC2
CL1
Cut Land short
6
R19
JP7
EXT-MIC2
TP39
GND
7
R17
R23
12
8
TP26
SDOUT1
51
46
11
9
C
TP24
SDOUT2
51
10
1
TP23
51CAD0
R16
IN1R
IN1P
IN2R
IN2P
IN3R
10
TP21
SDIN2
20
1
B
48pin_1
TP20
51SCL
1
8
1
(OPEN)
TP27
AINR
1
AINR
22
R15
TP25
MPRF
R18
7
SDA
C16
1uF(DIP)
41
6
VSS4
1
RSV9
39
TP22
VCOM
1
C15
0.1uF
11
TP19
BICK2
1
5
TP18
SDA
51
1
RSV8
R14
1
4
C13
2.2uF
23
1
RSV7
SO/RDY
1
3
AVDD
C12
0.1uF
1
C
+
C11
100uF(D/N)
+
1
38
C14
10uF
+
12
TP16
LRCK2
51
2
1
24
1
RDY/SDOUTM
1
TP14
CAD1
1
26
27
DVDD
TEST2
28
29
0.1uF
VSS2
34
35
1uF(DIP)
R10
51
1
OUTL/OUTP
1uF
R8
51
C10
1
37
C9
INITRSTN
R11
OUTL/OUTP
HPR
0(D/N)
CN5
HPL
U1
C8
1
TP12
HVCOM
OUTR/OUTN
10uF
0.1uF
31
HPL
R7
36
MPWR
AVDD
JP3
DMVDD-SEL
OUTR/OUTN
TP9
DMP
C7
1
30
TP11
SRCLFLT
TP10
0(D/N)
1
GND
C5
HPR
VSS3
DMP
1
HPL
1
+
2pin
1
MICR(OPEN)
1
INITRSTN
TP6
TP3
DVDD
JP2
DVDD
MICL(OPEN)
R6
TP8
(OPEN)
DMCLK
CN3
RSV6
100uF(D/N)
1
TP4
1
SRCLFLT
1
2
3
4
5
32
2
1
R5
(OPEN)
DGND
100uF(D/N)
HVDD
J2
1
2
3
4
5
C4
C3
HVCOM
D
J1
DMDAT
33
1
1
DMP
AVDD
2.2K(DIP)
2.2K(DIP)
+
CN1
HVDD
1
JP1
R2
1
R1
TP1
R3
DMDAT
R4 (OPEN)
(OPEN)
SDA
AGND
CN2
10
TP2
HVDD
DVDD
1uF
11
C2
1uF
VSS2
C1
1
48pin_1
CN4
12
Digital MIC
2
+
5
Title
12
11
9
8
7
6
5
4
3
2
10
Place CL3,4 parts on the edge of L4layer
1
AKD7754-SUB-48QFN
Place CL1,2 parts on the edge of L1 layer
CN7
48pin_1
Size
A3
Date:
5
4
3
2
Document Number
AK7754
Thursday, May 14, 2009
Rev
0.5
Sheet
1
1
of
2
5
4
3
2
1
MR-552LS(W)
T
B
S
D
D
JP12
HPL-RCA
C29
HPL
+
R35
RCA1
HPL
C30
0.22uF(D/N)
C31
33pF(D/N)
0(DIP)
R36
16(DIP)
47uF(A)
MJ-354W
R37
10(D/N)
2
5
MR-552LS(R)
T
B
S
JP13
HPR-RCA
RCA2
C32
HPR
+
R38
HPR
C33
0.22uF(D/N)
C34
33pF(D/N)
0(DIP)
J3
4
1
R39
16(DIP)
47uF(A)
R40
10(D/N)
C
C
AMP-PW-
RCA:WHITE
JP14
TP40
AMP-PW+
RCA:RED
JP15
1
AMP-PW-
OR-THR/AMP
THR
OL-THR/AMP
THR
AMP
C37
AMP
+
C36
U2B
R47
4.7k(DIP)
RCA4
OUTR/OUTN
22uF(A)
C48
33pF(F)
7
5
4.7k
R49
100k
220pF(F)
NJM5532M
4.7k
R43
C43
C41
R41
22uF(A)
8
22uF(A)
MR-552LS(W)
T
B
S
6
R46
+
4
C47
8
+
4.7k
R45
100
+
C45
33pF(F)
-
3
4.7k
R50
100k
22uF(A)
R42
JP17
RAMP
100
+
1
C40
-
2
R44
+
OUTL/OUTP
JP16
LAMP
C39
+
C42
220pF(F)
NJM5532M
0.1uF
4
U2A
C38
220pF(F)
B
C35
10uF
R48
4.7k(DIP)
B
MR-552LS(R)
T
B
S
+
RCA3
C44
10uF
C46
220pF(F)
0.1uF
1
AMP-PW+
AMP-PWTP41
AMP-PW+
AREA:SHORTEST WIRING
AREA:SHORTEST WIRING
A
A
Title
AKD7754-SUB-48QFN ANALOG OUT
Size
A3
Date:
5
4
3
2
Document Number
AK7754
Tuesday, February 24, 2009
Rev
0.5
Sheet
1
2
of
2
5
4
3
7754-DVDD
RSV6
SDA
2
TEST2 INITRSTN
SO/RDY
RDY/SDOUTM
SCL
CAD0
1
STO
25
26
27
28
29
30
31
32
33
34
35
36
CN3
48pin_3
DGND
D
D
DVDD
JP2
7754-DVDD
->7754-DVDD
CN2
48pin_4
Show direction
using the arrow
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
13
CAD1
RSV7
LRCK2
RSV8
C
BICK2
RSV9
C
SDIN2
RSV10
SDOUT2
SDOUT1
AINR
7754-DVDD
AINL
AVDD
JP1
CLKO
->7754-AVDD
B
LRCKO
Show direction
using the arrow
B
BICKO
LRCK1
48pin_2
CN4
A
A
12
11
10
9
8
7
6
5
4
3
2
1
AGND
Title
CN1
48pin_1
Size
A3
TEST1
RSV1
RSV2
EXT-XTI RSV3
RSV4
RSV5
SDIN1 7754-DVDD
BICK1
Date:
5
4
3
2
AKD7754-A
Document Number
Rev
0
AK7754
Tuesday, April 28, 2009
Sheet
1
1
of
1
5
4
3
2
1
D
D
RCA4
+
C39
22uF
U5
MR-552LS(W)
DAC1
U3
C26
0.1uF
+ C28
10uF
1
U4
51
2
BICK
DZF2
29
51
3
SDTI1
AVDD
28
R15
51
4
LRCK
AVSS
27
R16
51
5
RSTB
VCOM
26
R21
51
6
SMUTE/CSN/CAD0
LOUT1
25
R17
51
7
ACKS/CCLK/SDL
ROUT1
24
R22
51
8
DIF0/CDTI/SDA
P/S
23
R18
51
9
SDTI2
LOUT2
22
R19
51
10
SDTI3
ROUT2
21
R20
51
11
SDTI4
LOUT3
20
12
DIF1
ROUT3
19
13
DEM0
LOUT4
18
C43
NC
GBA
13
3
1A
NC
12
PC-CS4N
4
2A
1B
11
PC-SCLK
5
3A
2B
10
PC-SI
6
4A
3B
09
7
GND
4B
08
DAC-PDN
C27
0.1uF
14
DVDD
ROUT4
17
15
DVSS
DEM/I2C
16
+ C29
10uF
+ C30
10uF
C25
0.1uF
C32
0.1uF
+ C31
10uF
C34
0.1uF
C33
10uF
22uF
R24
22k
T
B
S
MR-552LS(R)
C41
RCA5
22uF
R25
22k
T
B
S
MR-552LS(W)
DAC2
C
C42
RCA6
22uF
R26
22k
T
B
S
MR-552LS(R)
22uF
RCA7
R27
22k
T
B
S
MR-552LS(W)
DAC3
AK4359
C44
RCA8
+
2
30
DZF1
R14
DVDD-DAC
14
MCLK
R13
C
VCC
RCA3
+
20
10
51
DVDD-DAC
GAB
C40
VDD-DAC
R12
74HCT541
1
R23
22k
+
VCC
GND
18
17
16
15
14
13
12
11
+
G1
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
+
1
19
A1
A2
A3
A4
A5
A6
A7
A8
+
2
3
4
5
6
7
8
9
CAD1
LRCK2
CLKO
BICK2
LRCKO
BICKO
LRCK1
T
B
S
22uF
74HCT243
R28
22k
T
B
S
MR-552LS(R)
JP3
GND
C45
RCA10
+
B
22uF
R29
22k
B
T
B
S
MR-552LS(W)
DAC4
DVDD-DAC
AMP-PW+
VDD-DAC
C46
LM1117-5V
RCA9
10
2
+ C38
10uF
OUT
3
R31
GND
+
REG4
C36
0.1uF
IN
1
22uF
C35
0.1uF
+ C37
10uF
R30
22k
T
B
S
MR-552LS(R)
SILK-SCREEN
AGND
TP2
TP(BLACK)
A
1
A
Title
Size
A3
Date:
5
4
3
2
AKD7754-A
Document Number
Rev
0
DAC
Friday, March 13, 2009
Sheet
1
1
of
1
5
4
3
2
1
D
D
DVDD-3.3V
DVDD-3.3V
C1
+
SILK-SCREEN
SPDIN-IN
C2
L1
10uF
10uH
0.1uF
PORT1
SPDIF-IN
3
2
1
VCC
GND
OUT
R2
470
C3
R1
DIF-RX
0.1uF
18k
TORX141
SPDI/F Optical in
1
2
3
4
5
6
7
8
9
10
11
12
DVDD-3.3V
SILK-SCREEN
SPDIN-OUT
RX4
NC1
RX5
TEST2
RX6
NC3
RX7
IIC
P/SN
XTL0
XTL1
VIN
AK4114
13
14
15
16
17
18
19
20
21
22
23
24
L2
36
35
34
33
32
31
30
29
28
27
26
25
INT0
CSN
CCLK
CDTI
CDTO
PDN
XTI
XTO
DAUX
MCKO2
BICK
SDTO
EXT
TX-CLK
XTL
R3
R4
R5
100
100
100
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
XTAL1
22pF
C6
22pF
C7
AK4114
10uH
IN
VCC
GND
SW1
TRX-PDN
12.288MHz
PORT2
SPDIF-OUT
C
PC-CS3N
PC-SCLK
PC-SI
TVDD
NC4
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
DVSS
MCKO1
LRCK
C
RX3
NC6
RX2
TEST1
RX1
NC5
RX0
AVSS
VCOM
R
AVDD
INT1
U1
48
47
46
45
44
43
42
41
40
39
38
37
C5
10uF
+
C4
0.1uF
R6
100
R7
100
TRX-LRCK
RX-CLK
DIF-TX
3
2
1
C8
0.1uF
0.1uF C9
C12
10uF
10uF
TOTX141
SPDI/F Optical out
C10 +
0.1uF
C11
10uF
DVDD-3.3V
SILK-SCREEN
DVSS
DVSS
C13
B
+
+
B
DVDD-3.3V
DVDD-3.3V
1
TP1
TP(BLACK)
+
C14
100uF/16V(A)
A
A
Title
Size
A3
Date:
5
4
3
2
AKD7754-A
Document Number
AK4114
Tuesday, January 13, 2009
Rev
0
Sheet
1
2
of
8
5
4
3
2
1
AREA : SHORTEST WIRING
D
D
AMP-PW-
C15 +
0.1uF
C19
RCA2
R9
10k
22uF(A)
C20
T
B
S
+
T
B
S
R8
10k
C23
68pF
R10
10k
R11
10k
+
RCA1
C16
10uF
22uF(A)
C24
68pF
MR-552LS(W)
4
6
U2B
NJM5532D
C18
7
-
5
AINL
C
1uF(A)
8
+
AINR
+
1
+
3
SILK-SCREEN
AINL
C17
-
2
U2A
NJM5532D
+
C
SILK-SCREEN
AINR
4
MR-552LS(R)
8
1uF(A)
+
C21
0.1uF
C22
10uF
AMP-PW+
B
B
A
A
Title
Size
A3
Date:
5
4
3
2
AKD7754-A
Document Number
Rev
0
ANALOG-IN
Tuesday, April 28, 2009
Sheet
1
4
of
8
5
4
3
2
1
R32 10k
+
+
USB-VDD
C49
10uF
C61
10uF
D
R50
100k
D
C50
0.1uF
R33
10k
18
12
13
33
34
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
30
31
OSC1/CLKI
OSC2/CLKO/RA6
25
26
27
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
1
2
3
4
5
17
16
15
14
11
10
9
8
SILK-SCREEN
1: USB-5V
3: USB-3.3V
5: DVDD
2
4
6
29
JP4
MCLR_N/Vpp/RE3
SILK-SCREEN
1: VDD
2: MCLR
3: PGD
4: PGC
5: GND
1
3
5
USB-RST
VDD1
VSS0
APE 1F
VSS1
6
7
VDD0
SW2
Up
:Release
Down :Push Down
C48
0.1uF
28
C47
0.1uF
U6
default 3-4 pin short
JP5
PIC-VDD-SEL
DVDD-3.3V
HEADER 5
C51 22pF
C
DVDD-3.3V
R34
10k
R35
C57
470nF
37
PIC18F4550
TQFP 44-PIN
19
20
21
22
23
24
PC-SCL
PC-SO
38
39
40
41
2
3
4
5
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
32
35
36
PC-CS3N
PC-INITRSTN
PC-CS4N
PC-I2CSEL
PC-SCLK
PC-SI
PC-RQN
PC-CS2N
REG1
LM1117-3.3V
1
+
VUSB
100
PC-SDA
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
C55
C53
10uF
0.1uF
GND
C52 22pF
IN
OUT
2
C
C54
3
XTI
XTO
XTAL2
20MHz
C56
+
0.1uF
10uF
U7
R39
R40
42
43
44
1
VUSB
DD+
GND
22
22
1
2
3
4
VUSB
DD+
GND
USB(B type)
PIC18F4550
B
B
DVDD-3.3V
SILK-SCREEN
DVSS
DVDD-3.3V
DVDD-3.3V
TP3
TP(BLACK)
U8A
+
R36
C60
0.1uF
LED-IND
10k
VCC
CEXT
15
REXT/CEXT
U8B
16
6
C58
33uF(A)
1
2
3
8
A
B
CLR
GND
U9
13
Q
4
Q
R37
R38
100
100
1
3
7
GREEN
COM
2
9
10
11
8
RED
BICOLOR LED
74HC221
C59
+
VCC
CEXT
100uF/16V(A)
1
16
14
REXT/CEXT
A
B
CLR
GND
74HC221
Q
5
Q
12
A
A
Title
Size
A3
Date:
5
4
3
2
AKD7754-A
Document Number
PC I/F
Tuesday, January 13, 2009
Sheet
1
Rev
0
6
of
8
5
4
3
2
1
D
D
AMP-PW+
DVDD
AVDD
2
C63
0.1uF
+ C66
10uF
OUT
C64
0.1uF
TM1
1
IN
1
C65
0.1uF
3
+ C62
10uF
LM1084-3.3V
GND
SILK-SCREEN
CHIP-DGND
TP4
TP(BLACK)
REG2
L3
10uH
+ C67
10uF
+
i
RED(+12V)
TJ-563
C68
100uF/16V(A)
1
TM2
1
i
BLACK(GND)
TJ-563
+
C69
100uF/16V(A)
TM3
1
SILK-SCREEN
P-DVDD
2 PIN: [->]
C
i
BLUE(-12V)
TJ-563
AMP-PWC
DVDD-3.3V
JP6
P-DVDD
REG3
TP5
TP(BLACK)
2
1
+ C70
10uF
C71
0.1uF
OUT
SILK-SCREEN
AGND
LM1084-3.3V
IN
TP6
TP(BLACK)
1
C72
0.1uF
1
2
1
GND
default short
3
SILK-SCREEN
DVSS
+ C73
10uF
B
B
A
A
Title
Size
A3
Date:
5
4
3
2
AKD7754-A
Document Number
Rev
0
POWER
Tuesday, January 13, 2009
Sheet
1
7
of
8
5
4
3
2
1
DVDD-3.3V
SMUX-DVDD
SMUX PORT1
C74
0.1uF
+ C75
10uF
JP7
D
SMUX-MCLK
SMUX-BICK
SMUX-LRCK
SMUX-DAT1
1
3
5
7
9
D
2
4
6
8
10
SILK-SCREEN
SMUX PORT/SMUX PORT2
1: MCLK
3: BIT
5: LR
7: DI
10: DO
HEADER 5X2
SMUX-DAT2
SMUX PORT2
U10
TEST1
RSV1
RSV2
EXT-XTI
RSV3
RSV4
RSV5
SDIN1
BICK1
DAC-PDN
TRX-PDN
TX-CLK
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
TRX-LRCK
RX-CLK
C
PC-SO
PC-SCL
PC-SDA
PC-INITRSTN
PC-I2CSEL
PC-SI
PC-RQN
PC-CS2N
LED-IND
R64
R61
R60
R59
R65
R66
R67
51
51
51
51
51
51
51
R63
R62
51
51
R56
R58
51
51
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
25
28
29
30
32
33
34
35
36
37
39
40
41
42
43
46
49
50
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
JP8
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
I/O72
52
53
54
55
56
58
59
60
61
63
64
65
66
67
68
70
71
72
73
74
76
77
78
79
80
81
82
85
86
87
89
90
91
92
93
94
95
96
97
VINT0
VINT1
VINT2
5
57
98
VIO0
VIO1
VIO2
VIO3
26
38
51
88
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
21
31
44
62
69
75
84
100
SMUX2-MCLK
SMUX2-BICK
SMUX2-LRCK
SMUX2-DAT1
1
3
5
7
9
C87
0.1uF
2
4
6
8
10
HEADER 5X2
SMUX2-DAT2
R55
R54
R53
R52
51
51
51
51
R51
51
R49
51
R42
R43
R44
51
51
51
R45
R46
R47
R48
51
51
51
51
CAD0
SCL
SO/RDY
RDY/SDOUTM
INITRSTN
TEST2
C
DVDD-3.3V
RSV6
RSV8
RSV9
RSV10
CAD1
LRCK2
BICK2
SDIN2
SDOUT2
SDOUT1
D1
STO
2
1
R41
2
470
1
LEAD RED LED
CLKO
LRCKO
BICKO
LRCK1
DVDD-3.3V
B
PC-SCLK
R57
51
99
2
1
4
3
27
23
22
GSR
GTS4
GTS3
GTS2
GTS1
GCK3
GCK2
GCK1
JP9
1
3
5
7
9
TCK
TDI
TDO
TMS
C77
0.1uF
C78
0.1uF
+ C79
10uF
C80
0.1uF
C81
0.1uF
C82
0.1uF
C83
0.1uF
+ C84
10uF
DVDD-3.3V
JTAG
C85
48
45
83
47
2
4
6
8
10
C76
0.1uF
B
0.1uF
TP8
DVSS
1
TP7
DVSS (BLACK)
XC95144XL
DVDD (RED)
1
A
DVDD-3.3V
+ C86
100uF/16V(A)
A
Title
Size
A3
Date:
5
4
3
2
Document Number
AKD7754-A
XILINX
Friday, March 13, 2009
Sheet
1
Rev
0
8
of
8