AP1025

[AP1025BEN]
AP1025BEN
45V Single Stepper Motor Driver IC
1. Description
The AP1025BEN provides a complete stepper motor driver solution with built-in LDMOS FET and its
internal capacitors type charge pump circuit for the 45V & 1.6A constant current operation. Clock-in input
mode and Parallel input mode is selectable by the setting of an external terminal. 2 phase, 1-2 phase(1/2step),
W1-2 phase(1/4step) can be selected during parallel input mode, and 2 phase, 1-2 phase(1/2step), W1-2
phase(1/4step), 4W1-2 phase(1/16step) can be selected during clock-in input mode to realize calm motor
operation. The IC is housed in a small 32-pin QFN package and excellent in heat dissipation. It also includes
under voltage detection and thermal shut down circuits. It is suitable for various types of stepper motors.
2. Features
 Selectable input logic (Clock in input, Parallel input)
 Excitation mode is configurable
— Parallel input mode 2 phase, 1-2 phase(1/2step), W1-2 phase(1/4step)









— Clock-in input mode 2 phase, 1-2 phase(1/2step), W1-2 phase(1/4step), 4W1-2 phase(1/16step)
Operating Temperature Range
-30C to +85C
Operating Voltage Range
— Control Power Supply Voltage (VC)
3.0V to 5.5V
— Motor Power Supply Voltage (VM)
9.0V to 45V
Low H-Bridge On Resistance
[email protected]C
Built-in UVLO (under voltage lockout circuit)
Built-in TSD (thermal shut down circuit)
Built-in charge pump circuit
Built-in Sub-harmonic noise reduction function
Built-in Phase Synchronous function
Package
32-pin QFN (5.0mm□)
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3. Table of Contents
1.
Description ..................................................................................................................................................1
2.
Features .......................................................................................................................................................1
3.
Table of Contents ........................................................................................................................................2
4.
Block Diagram ............................................................................................................................................3
5.
Ordering Guide ...........................................................................................................................................3
6.
Pin Configuration and Functions ................................................................................................................4
■ Pin Configuration .....................................................................................................................................4
■
Functions .................................................................................................................................................4
7.
Absolute Maximum Ratings .......................................................................................................................5
8.
Recommended Operation Conditions .........................................................................................................6
9.
Electric Characteristics ...............................................................................................................................6
10. Functional Description ................................................................................................................................8
11. Recommended External Circuit ................................................................................................................17
■ External circuit .........................................................................................................................................17
■ Recommended Layout Example ..............................................................................................................18
12. Package .....................................................................................................................................................19
■ Outline Dimensions..................................................................................................................................19
■ Marking ....................................................................................................................................................19
13. Revise History ...........................................................................................................................................20
IMPORTANT NOTICE ............................................................................................................................21
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4. Block Diagram
M
OUT1A
OUT1A
OUT1B
OUT1B
OUT2A
OUT2A
OUT2B
OUT2B
VM
VM
VM
VM
VM
CVM
Charge
Pump
VREF
VREF
RR1
VIS
CVIS
1/2.5
RR2
OSC
Oscillator
UVLO
TSD
IN1~IN6
FS
SYN
CPU
INSEL
Control Circuit
EN
LV
H-Bridge
Control Circuit
VC
VC
CVC
Exposed Pad
IF1
IS1
RIS1
SL
IS2
CSL
IF2
RIS2
Figure 1. Block Diagram
5. Ordering Guide
AP1025BEN
-30°C ~+85°C
32-pin QFN
When AP1025AEN is replaced with AP1025BEN, note that the excitation mode(H,H) is changed as follows.
Table 1. Selection of the excitation mode
IN5
IN6
AP1025AEN
H
H
W1-2 phase (1/4step)
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AP1025BEN
4W1-2 phase (1/16step)
2015/01
[AP1025BEN]
6. Pin Configuration and Functions
VC
LV
VREF
VIS
SL
FS
INSEL
EN
24
23
22
21
20
19
18
17
Pin Configuration
VM
25
16
VM
OUT1B
26
15
OUT2B
OUT1B
27
14
OUT2B
IF1
28
13
IF2
12
IS2
11
OUT2A
10
OUT2A
9
VM
IS1
29
OUT1A
30
OUT1A
31
(Top View)
Exposed pad
2
3
2
4
5
6
7
8
IN2
IN3
IN4
IN5
IN6
SYN
OSC
32
1
VM
AP1025B
IN1
■
■
Functions
No.
Pin Name
1~6
IN1~IN6
7
SYN
8
OSC
9,16,25,32
VM
I/O
I
I
I/O
P
10,11
12
13
14,15
17
18
19
20
21
22
OUT2A
IS2
IF2
OUT2B
EN
INSEL
FS
SL
VIS
VREF
O
I
O
O
I
I
I
I
I
O
23
LV
O
24
26,27
28
29
30,31
Function
Control signal input terminal
Synchronic mode select input terminal
Chopper frequency I/O terminal
Motor power supply terminal
Motor driver output terminal
Current sense terminal
Current force terminal
Motor driver output terminal
Enable signal input terminal
Control logic select input terminal
Chopper frequency select terminal
Slope setting terminal
Motor current setting terminal
Reference voltage output terminal
Logic voltage output capacitor connection
terminal
Control power supply terminal
Motor driver output terminal
Current force terminal
Current sense terminal
Motor driver output terminal
Condition
200kΩ pull-down
VC
P
OUT1B
O
IF1
O
IS1
I
OUT1A
O
Exposed
P
Ground
Pad
Note 1. I(Input terminal), O(Output terminal), P(Power terminal)
Note 2. Exposed Pad must be connected to GND.
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7. Absolute Maximum Ratings
Parameter
Control power supply voltage
Motor power supply voltage
VC level terminal
(SL, EN, SYN, OSC, FS, INSEL, INn)
VM level terminal
(OUTnA, OUTnB)
1.8V level terminal
(LV, VREF, VIS)
1.2V level terminal
(ISn, IFn)
Symbol
VC
VM
min
-0.5
-0.5
max
5.5
45
Unit
V
V
Vterm1
-0.5
VC
V
Vterm2
-0.5
VM
V
Vterm3
-0.5
1.9
V
Vterm4
-0.5
1.3
V
1.6
1.2
3.9
2.0
150
150
±2
A
A
W
W
C
C
kV
Power dissipation
PD
Junction temperature
Tj
Storage temperature
Tstg
-40
ESD rating
HBM
Note 3. All above voltages are with respect to GND(Exposed Pad).
Note 4. Exposed Pad must be connected to GND.
Note 5. The each power supply of VC and VM is sequence-free.
Note 6. θJA=32C/W with 4 layer board (JEDEC51).
Maximum DC output current
Iload
Condition
Ta=25C
Ta=85C
Ta=25C
Ta=85C
(Note 6)
(Note 6)
(Note 6)
(Note 6)
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
operation is not guaranteed at these extremes.
4.5
4.0
Pwower dissipation, Pd ( W)
3.5
3.0
RθJA=32C/W at 4-layer PCB
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75 85 100
Temperature (C)
125
150
175
Figure 2. Maximum power dissipation
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8. Recommended Operation Conditions
Parameter
Symbol
min
typ
max
Unit
Motor power supply voltage
VM
9.0
24.0
45.0
V
Control power supply voltage
VC
3.0
5.0
5.5
V
VIS input voltage range
VIS
0.2
-
VREF
V
Clock in input frequency
FCL
-
-
20
kHz
Ta
-30
-
85
C
Operating Temperature range
Condition
Iload(100%)[A]=(VIS/2.5)/RISn
Note 7. All above voltages are with respect to GND(Exposed Pad).
9. Electric Characteristics
(Ta = 25C, VM=24V, VC = 5.0V, unless otherwise specified.)
Parameter
Symbol
Condition
min
typ
max
Unit
Quiescent current
VC Quiescent current at OFF
IVCOFF
EN=”L”
-
-
10
A
VM Quiescent current at OFF
IVMOFF
EN=”L”
-
-
20
A
EN=”H”, INSEL=”H”,
SYN=”L”, FS=”L”, IN1=1kHz
-
1.7
2.8
mA
-
0.85
1.0

-
1.0
1.5

-
1.0
1.5

-
1.5
2.0

-
0.8
1.2
V
0.7xVC
-
-
V
VIL
-
-
0.3xVC
V
Input pulse rise time
tR
-
-
1.0
s
Input pulse fall time
tF
-
-
1.0
s
High level input current
IIH
-1.0
-
1.0
A
VC Quiescent current at operate
IVC
H-bridge circuit
Driver on resistance
Iload 1ch/2ch=0.1A/0.1A
(High side + Low side)
Ta = 25C
RON1
Iload 1ch/2ch=0.1A/0.1A
Ta = 25C、VC=3.0V
Iload 1ch/2ch=
1.1A / 0A or 0.8A / 0.8A
Ta = 85C (Note 9)
RON2
I Iload 1ch/2ch=
1.1A / 0A or 0.8A / 0.8A
Ta = 85C (Note 9)
Body diode forward voltage
VF
IF = 100mA
Control logic
High level input voltage
Low level input voltage
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VC = 3.0V-5.5V
without EN terminal
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[AP1025BEN]
Parameter
Symbol
High level input current
IIHEN
Low level input current
IIL
Condition
EN terminal
min
typ
max
Unit
15
25
40
A
-1.0
-
1.0
A
1.22
1.25
1.28
V
Reference voltage
R1+R2=12k+47k 
VREF terminal voltage
VREF
VREF terminal current
IVREF
-
-
100
A
tB
2.0
2.23
2.6
s
VOSIS
-50
0
50
mV
SL terminal output current
ISL
-
50
-
A
OSC terminal frequency 1
fCPL
FS=”L”, SYN=”L”
20
25
30
kHz
OSC terminal frequency 2
fCPH
FS=”H”, SYN=“L”
40
50
60
kHz
VC-0.1
-
-
V
-
-
0.1
V
20
-
60
kHz
0
-
VC
V
0.7xVC
-
-
V
-
-
0.3xVC
V
1.9
2.2
2.5
V
150
175
200
C
-
30
-
C
Current operation
Blanking time
VIS offset voltage
OSC terminal High level output
voltage
VCPOH
OSC terminal Low level output
voltage
VCPOL
OSC terminal frequency input
range
fCPIN
OSC terminal input voltage range
VCPIN
OSC terminal High level input
voltage
VCPIH
OSC terminal Low level input
voltage
VCPIL
SYN=“L”, Iload=100A
SYN=”L”, Iload=-100A
SYN=”H”
SYN=”H”
SYN=”H”
SYN=”H”
Protection circuit
VC under voltage detect voltage
VVCUV
Thermal shut down temperature
Guaranteed by Design
TTSD
Temperature hysteresis
(Note 9)
Guaranteed by Design
TTSDHYS
(Note 9)
Note 8. All above voltages are with respect to GND.
Note 9. Not tested in production.
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10. Functional Description
10.1 Input terminal and protection circuit
 Common description (Parallel input mode and Clock-in input mode)
Table 2. Internal circuit operation by the ENABLE(EN) signal
EN pin
UVLO
TSD
Reference Voltage Circuit
H-Bridge
L
ON
Output
L
H
H
ON
Hi-Z
H
OFF
Hi-Z
L
OFF
Hi-Z
Note 10. UVLO, TSD and Reference Voltage Circuit show internal status. “-“ is Don’t Care.
Table 3. Selection of the chopper frequency by the SYN signal
SYN pin
FS pin
OSC pin
PWM chopper frequency
L
25kHz(typ)
L
Output
H
50kHz(typ)
H
Input
External frequency
Note 11. Do not change input level of the SYN and FS pin during operation. “-“ is Don’t Care.
Table 4. Selection of the chopper frequency by the INSEL signal
INSEL
Input Mode
Parallel input mode.
L
H-Bridge is controlled by input logic.
Excitation mode : 2phase, 1-2phase(1/2step), W1-2phase(1/4step)
Clock-in input mode.
H
H-Bridge is controlled by the count number of the clock.
Excitation mode : 2phase, 1-2phase(1/2step), W1-2phase(1/4step), 4W1-2phase(1/16step)
Note 12. Do not change input level of the INSEL terminal during operation.
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10.2 Parallel input mode (INSEL=”L”)
Table 5. Parallel input mode truth table
IN1
IN2
IN3
IN4
OUT1A
OUT1B
IS1
OUT2A
OUT2B
IS2
L
L
L
L
100%
Hi-Z
Hi-Z
0%
L
L
L
H
93%
38%
H
L
L
L
H
H
71%
71%
L
L
H
L
38%
93%
L
H
L
L
Hi-Z
Hi-Z
0%
H
L
100%
L
H
L
H
38%
93%
L
H
H
H
71%
71%
L
H
H
L
93%
38%
H
H
L
L
L
H
100%
Hi-Z
Hi-Z
0%
H
H
L
H
93%
38%
H
H
H
H
71%
71%
H
H
H
L
38%
93%
H
L
L
L
Hi-Z
Hi-Z
0%
L
H
100%
H
L
L
H
38%
93%
H
L
H
H
H
L
71%
71%
H
L
H
L
93%
38%
Note 13. The IN5 and IN6 pins are not used in Parallel input mode. They must be connected to ground.
IN1
IN2
IN3
IN4
Half step
W1-2
Full step
IOUT1
IOUT2
Figure 3. Input signal (Parallel input mode)
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10.3 Clock-in input mode (INSEL=”H”)
Table 6. Clock-in input mode truth table
IN3
IN1
IN2
IN4
↑
L
L
↑
H
L
↑
H
H
L
Note 14. “-“ is Don’t Care. “↑“ shows the rising edge.
Condition
Step +1(CW)
Step -1(CCW)
Reset
Output
Hi-Z
Table 7. Selection of the excitation mode
IN5
IN6
Step
L
L
W1-2 phase (1/4step)
L
H
1-2 phase (1/2step)
H
L
Full step
H
H
4W1-2 phase (1/16step)
Note 15. Do not change input level of the IN5 and IN6 terminals during operation.
 ISn terminal current revel
Table 8. Set current ratio at each excitation mode
1-2
W1-2
2
4W1-2 phase
phase
phase
phase
(1/16step)
(1/2step)
(1/4step)
0
0
0
1
2
3
1
4
5
6
7
0
1
2
8
9
10
11
3
12
13
14
15
2
4
16
17
18
19
5
20
21
22
23
1
3
6
24
25
26
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Phase1
Current
[%]
100
99.61
98.04
96.69
92.55
88.24
83.14
77.25
70.59
63.53
55.69
47.06
38.43
29.02
19.61
9.80
0.00
-9.80
-19.61
-29.02
-38.43
-47.06
-55.69
-63.53
-70.59
-77.25
-83.14
Phase2
Current
[%]
0.00
9.80
19.61
29.02
38.43
47.06
55.69
63.53
70.59
77.25
83.14
88.24
92.55
95.69
98.04
99.61
100
-99.61
-98.04
-95.69
-92.55
-88.24
-83.14
-77.25
-70.59
-63.53
-55.69
Step Angle
[°]
0.0
5.6
11.3
16.9
22.6
28.1
33.8
39.4
45.0
50.6
56.2
61.9
67.4
73.1
78.7
84.4
90.0
95.6
101.3
106.9
112.6
118.1
123.8
129.4
135.0
140.6
146.2
2015/01
[AP1025BEN]
27
28
29
30
31
4
8
32
33
34
35
9
36
37
38
39
5
10
40
41
42
43
11
44
45
46
47
6
12
48
49
50
51
13
52
53
54
55
7
14
56
57
58
59
15
60
61
62
63
64
: Home microstep position at Step Angle 45°
7
2
3
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-88.24
-92.55
-95.69
-98.04
-99.61
-100
-99.61
-98.04
-96.69
-92.55
-88.24
-83.14
-77.25
-70.59
-63.53
-55.69
-47.06
-38.43
-29.02
-19.61
-9.80
0.00
9.80
19.61
29.02
38.43
47.06
55.69
63.53
70.59
77.25
83.14
88.24
92.55
95.69
98.04
99.61
100
-47.06
-38.43
-29.02
-19.61
-9.80
0.00
-9.80
-19.61
-29.02
-38.43
-47.06
-55.69
-63.53
-70.59
-77.25
-83.14
-88.24
-92.55
-95.69
-98.04
-99.61
100
-99.61
-98.04
-95.69
-92.55
-88.24
-83.14
-77.25
-70.59
-63.53
-55.69
-47.06
-38.43
-29.02
-19.61
-9.80
0.00
151.9
157.4
163.1
168.7
174.4
180.0
185.6
191.3
196.9
202.6
208.1
213.8
219.4
225.0
230.6
236.2
241.9
247.4
253.1
258.7
264.4
270.0
275.6
281.3
286.9
292.6
298.1
303.8
309.4
315.0
320.6
326.2
331.9
337.4
343.1
348.7
354.4
360.0
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[AP1025BEN]
IN1
IN2
CW
IN3
IN4
CCW
Reset
Enable
IOUT1
IOUT2
Figure 4. Input signal (Parallel input mode, IN5=”L”, IN6=”L”)
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10.4 PWM Current Control
The current value of 100% PWM constant current setting ratio at each excitation mode of AP1025 (Iload
(100%) [A]) is determined by H-Bridge sense resistor(RIS) and PWM constant current setting voltage(VIS) as
follows.
Iload (100%)[A] = (VIS / 2.5) / RIS
PWM constant current setting voltage
VIS damping ratio
H-Bridge sense resistor
--- (1)
VIS
1/2.5
RIS
Calculation example1:VIS=1V, RIS=0.5ohm
Iload (100%)[A] = (1 / 2.5) / 0.5ohm = 0.8A
--- (2)
The minimum value of the control current in the PWM constant current control in each excitation mode (Iload
(min) [A]) is determined by the following equation.
Iload(min)[A]=VM/(Rm+RON+RIS) × tB × fCP
Motor power supply voltage
OSC frequency
Blanking time
Motor on resistance
H-Bridge on resistance
H-Bridge sense resistor
--- (3)
VM
fCP (fCPL/ fCPH)
tB
Rm
RON
RIS
Calculation example2:VM=24V, fCP=25kHz, tB=2.23us, Rm=9.4ohm, RON=1ohm, RIS=1ohm
Iload(min)[A]=24V/(9.4ohm+1ohm+1ohm) × 2.23us × 25kHz = 0.117A
--- (4)
The current value of 100% PWM constant current setting ratio should be set so that the minimum control
current (Iload (min) [A]) becomes larger than the minimum value of the PWM constant current setting ratio in
4W1-2 phase excitation. In case of calculation example 2, the current value of the 100% PWM constant
current setting ratio (Iload (100%) [A]) is as follows.
Iload(100%)[A]=0.117/9.8%=1.19A
---(5)
If the current value of 100% PWM constant current setting value ratio (Iload (100%) [A]) is smaller than
equation (5), minimum control current value (Iload (min) [A]) may be larger than 9.8%.
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10.5 Decay Mode
The AP1025 selects decay mode automatically for better current following property. Basically, it operates in
slow decay mode, but it operates in fast decay mode when the current setting value is lowered, till it reaches to
the setting value.
Charge
Charge
Charge
Slow
Slow
Charge
Slow
Fast
Charge
Slow
Charge
Fast
Slow
Charge
Slow
Slow
Setting
current
Banking time
Motor
current
OSC
Figure 5. Current waveform image during decay mode
 Charge Mode
 Fast Decay Mode
 Slow Decay Mode
VM
VM
VM
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
ON
GND
GND
GND
Figure 6. Decay Mode Image
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[AP1025BEN]
10.6 Protection Circuits
 Under Voltage Lockout Circuit (UVLO)
UVLO monitors Control power supply voltage (VC) and changes H-bridge driver output to Hi-Z if VC is
lower than the specified value (VVCUV =2.2V) when starting the VC source.
 Thermal Shut Down Circuit(TSD)
As soon as abnormal high temperature (TTSD=150C) is detected, H-Bridge driver output becomes
Hi-Z.
Table 9. Recovery type of abnormal heat generation detect circuit
Interface Mode
Recovery type
Parallel input
Automatic
Clock-in input
Latch
 Parallel Input Mode
Operation flow when detecting
abnormal heat generation
TSD
TDET
TDETHYS
Tj
VM
Detect high temp.
(150℃min)
UVLO
OUTnA/OUTnB are Hi-Z
VC
VCDET_LV
Wait cool down
IN
(Hystereseis : 30℃typ)
IOUT
Motor driver operation return
OUTnA/OUTnB follows
OUT
Hi-Z
Hi-Z
INnA/INnB
Hi-Z
Figure 7. Timing Chart of the protection circuits (parallel input mode)
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 Clock-in input mode
Operation flow when detecting
abnormal heat generation
TSD
TDET
TDETHYS
Tj
VM
Detect high temp.
(150℃min)
UVLO
VC
OUTnA/OUTnB are Hiz-Z
VCDET_LV
Wait cool down
EN
EN sign:H,L,H
IN
Motor driver operation return
OUTnA/OUTnB follows
INnA/INnB
IOUT
OUT
Hi-Z
Hi-Z
Hi-Z
Figure 8. Timing chart of the Protection circuit (parallel input mode)
・Shorted-Load, Shorted-to-Ground and Shorted-to-Power Protection
If the motor leads are shorted together, or if one of the leads is shorted to ground or shorted to power, when
current flowing is 3.3A or less, the motor driver IC will protect itself by hiccup behavior of thermal shutdown
circuit (TSD). When there is a power supply capacity of 3.3A or more, the appropriate protection fuse is
implemented between the motor power supply line(VM) and the power supply on the PCB.
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11. Recommended External Circuit
■ External circuit
VM
CVM
VM
VM
VM
VM
OUT1A
VC
VC
OUT1A
CVC
OUT1B
6
OUT1B
IN1~IN6
CPU
FS
OUT2A
SYN
OUT2A
INSEL
EN
AP1025B
M
OUT2B
OUT2B
IF1
LV
IS1
CLV
RIS1
VREF
IF2
RR1
VIS
IS2
RR2
RIS2
SL
OSC
Exposed Pad
CSL
Figure 9. External Circuit Example
Table 10. Recommended external components
Items
min
typ
max
Unit
Remark
CVM
47
Electrolytic Capacitor
F
1
Ceramic Capacitor
F
CVC
1.0
F
CLV
0.68
1.0
1.5
F
CSL
0.001
0.01
F
CVIS
1.0
F
Iload(100%)=0.8A
RISn
500
mΩ
R1
12
kΩ
R2
47
kΩ
Note 16. Above capacitances are examples. Please choose the best external capacitors for CVM, CVC and
CVIS for your system board.
Note 17. Capacitance of CVM and CVC should be adjusted considering the load current profile, the load
capacitance, the line resistance and etc. of the actual system board.
Note 18. Please choose the best external capacitor for CSL as sub harmonic noise measures. If not using the
CSL capacitor, please connect the SL terminal to ground.
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■ Recommended Layout Example
Top View
VM
OUT1A OUT1B
VC
GND
IN1
IN2
IN3
IN4
IN5
IN6
Bottom View
VC
LV
VREF
VIS
SL
IN_SEL
ENA
OSC
OUT2A OUT2B
Figure 10. Layout pattern example
Note 19. Please design the ground plane of the PCB as large as possible.
Note 20. Exposed Pad (exposed backside pad) must be connected to the ground of the PCB, because the
ground of IC and Exposed pad is in common.
Note 21. The ground via on the IC mounted area is effective for heat radiation to each layer of the PCB.
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12. Package
■ Outline Dimensions
・32-pin QFN package
Top View
Bottom View
1
0.3
3.60
5.00±0.05
32
0.50±0.05
3.60
32
0.25±0.05
1
0.40±0.10
0.75max
5.00±0.05
0.20 Ref
3.50
Unit : mm
■ Marking
AP1025B
YWWAA
(2)
(1)
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(3)
(4)
(5)
(1)
(2)
(3)
(4)
(5)
1pin Indication
Market No.
Year code (last 1 digit)
Week code
Management code
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13. Revise History
Date
(YY/MM/DD)
15/01/09
015000434-E-00
Revision
Page
Contents
00
-
First Edition
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[AP1025BEN]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of AKM or any third party with respect to the information in
this document. You are fully responsible for use of such information contained in this document in your
product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY
YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR
PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
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(mass destruction weapons). When exporting the Products or related technology or any information
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5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
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6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
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7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
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