AS0140AT Data Sheet Addendum: iCBGA Package

AS0140AT-ADD
Advance Information
AS0140AT Data Sheet
Addendum: iCBGA Package
1/4-Inch CMOS Image Sensor
and Signal Processor
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Introduction
The ON Semiconductor AS0140AT is a 1.0 MP format
digital image sensor and image sensor processor for
automotive viewing applications. The device includes full
auto-functions support (AWB and AE) and ALTM
(Adaptive Local Tone Mapping) to enhance HDR video.
The AS0140AT implements a high-sensitivity 3.0 mm pixel
with DR-Pixt technology, and advanced noise reduction, to
enable excellent low-light performance. It can be operated
in interlaced (NTSC or PAL) or progressive modes.
The AS0140AT may be operated in video (master) mode or
in single frame trigger mode, providing flexibility for
multi-camera systems.
NOTE: The iCBGA (Ceramic BGA) package version of
AS0140AT outlined in this addendum is for early
development sampling only. The iCBGA package
pinout shown in this addendum is a subset of the
final package pinout (outlined in the main data
sheet), allowing a common hardware design that
can support both package types. The optical
design will also need to account for a 50 mm
difference in the height of the image plane for this
iCBGA package vs. the final production package
design.
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
Ordering Information
Table 1. ORDERING INFORMATION − AVAILABLE PART NUMBERS
Product Description
Orderable Product
Attribute Description
AS0140ATSC00XPQM0−DR−E
AS Engineering Samples,
iCBGA Package
AS0140ATSC00XPQM0−DP−E
AS Engineering Samples,
iCBGA Package
Part Number
AS0140ATSC00XPQMH3−GEVB
Demo Board, iCBGA
AS0140ATSC00XPQMH3−GEVK
Demo Kit, iCBGA
Package
Shipping
Drypack,
Without Protective Film
iCBGA
TBD
Drypack,
With Protective Film
iCBGA
TBD
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
Package Information
Table 2. PIN DESCRIPTIONS
Pin (iCBGA)
Pin Name
Type
Description
L9
EXTCLK
Input
Master Input Clock
F1
STANDBY
Input
Standby Mode Control, Active HIGH
B10
RESET_BAR
Input
Master Reset Signal, Active LOW. This Signal has an Internal Pull Up
B8
FRAME_SYNC
Input
This signal is used to synchronize to external sources or multiple
cameras together. This signal should be connected to GND if not
used.
CLOCK AND RESET
© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. P0
1
Publication Order Number:
AS0140AT−ADD/D
AS0140AT−ADD
Table 2. PIN DESCRIPTIONS (continued)
Pin (iCBGA)
Pin Name
Type
Description
L12
TRIGGER_OUT
Output
If utilizing trigger modes, TRIGGER_OUT should be connected to the
TRIGGER pin; otherwise, this signal should be left unconnected.
H11
TRIGGER
Input
If utilizing trigger modes, TRIGGER_OUT should be connected to the
TRIGGER pin; otherwise, this signal should be connected to GND.
SCLK
Input
SCLK: Two-wire Serial Interface Clock (Host Interface)
CLOCK AND RESET
REGISTER INTERFACE
B3
C12
SDATA
I/O
A7
SADDR
Input
Two-wire Serial Interface Data (Host Interface)
J1
SPI_SCLK
Output
A8
SPI_SDI
Input
A4
SPI_SDO
Output
Data Out to SPI Flash or EEPROM Memory
A5
SPI_CS_BAR
Output
Chip Select Out to SPI Flash or EEPROM Memory
H1
FRAME_VALID
Output
Frame Valid Output (Synchronous to PIXCLK_OUT)
B4
LINE_VALID
Output
Line Valid Output (Synchronous to PIXCLK_OUT)
B5
PIXCLK_OUT
Output
Pixel Clock Output
E2
DOUT0
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
M10
DOUT1
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
L8
DOUT2
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
E12
DOUT3
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
L10
DOUT4
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
Selects device address for the two-wire slave serial interface. When
connected to GND the device ID is 0x90. When wired to VDDIO,
a device ID of 0xBA is selected.
SPI INTERFACE
Clock output for interfacing to an external SPI flash or EEPROM
memory.
Data in from SPI flash or EEPROM memory. When no SPI device is
fitted, this signal is used to determine whether the AS0140AT should
auto-configure:
0: Do not auto-configure; Two-wire interface will be used to
configure the device (host-config mode).
1: Auto-configure.
This signal has an internal pullup resistor.
PIXEL DATA OUTPUT
L3
DOUT5
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
D2
DOUT6
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
M9
DOUT7
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
D12
DOUT8
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
J2
DOUT9
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
H2
DOUT10
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
E1
DOUT11
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
C2
DOUT12
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
A10
DOUT13
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
G1
DOUT14
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
F12
DOUT15
Output
Pixel Data Output (Synchronous to PIXCLK_OUT)
COMPOSITE VIDEO OUTPUT
M3
DAC_REF
Output
External Reference Resistor for Video DAC
L7
DAC_POS
Output
Positive video DAC output in differential mode. Video DAC output in
single-ended mode. This interface is enabled by default using
NTSC/PAL signaling.
For applications where composite video output is not required, the
video DAC can be placed in a power-down state under software
control.
L6
DAC_NEG
Output
Negative Video DAC Output in Differential Mode
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AS0140AT−ADD
Table 2. PIN DESCRIPTIONS (continued)
Pin (iCBGA)
Pin Name
Type
Description
G2
GPIO_1
I/O
General Purpose Digital I/O
C1
GPIO_2
I/O
General Purpose Digital I/O
D1
GPIO_3
I/O
General Purpose Digital I/O
F2
GPIO_4
I/O
General Purpose Digital I/O
A3
GPIO_5
I/O
General Purpose Digital I/O
H12, J12
AGND
Supply
Analog Ground
K2, L4, B7, B9,
G12
DGND
Supply
Digital Ground
D11, E11
VDDIO
Supply
I/O Supply Power
K12
VAA
Supply
Analog Power
M4, M5, M7
VDD
Supply
Digital Power
M6
VDDA_DAC
Supply
Video DAC Analog Power
A6
LDO_OP
Output
Output from on Chip 1.8 to 1.2 V Regulator
GPIO
POWER
TEST PINS
F11
TEST1
Input
Must be Tied to VDDIO for Normal Operation
G11
TEST2
Input
Must be Tied to VDDIO for Normal Operation
A12
TEST3
Input
Must be Tied to VDDIO for Normal Operation
B6
TEST4
Input
Must be Tied to GND for Normal Operation
K11
TEST5
Input
Must be Tied to GND for Normal Operation
L2
TEST6
Input
Must be Tied to GND for Normal Operation
L11
TEST7
Input
Must be Tied to GND for Normal Operation
A1, B1, K1, L1,
M1, A2, B2, M2,
L5, M8, A9, A11,
B11, C11, J11,
M11, B12, M12
NC
Table 3. PACKAGE PINOUT
1
2
3
4
5
6
7
8
9
10
11
12
A
NC
NC
GPIO_5
SPI_SDO
SPI_CS_
BAR
LDO_OP
SADDR
SPI_SDI
NC
DOUT13
NC
TEST3
B
NC
NC
SCLK
LINE_
VALID
PIXCLK_
OUT
TEST4
DGND
FRAME_
SYNC
DGND
RESET_
BAR
NC
NC
C
GPIO_2
DOUT12
NC
SDATA
D
GPIO_3
DOUT6
VDDIO
DOUT8
E
DOUT11
DOUT0
VDDIO
DOUT3
F
STANDBY
GPIO_4
TEST1
DOUT15
G
DOUT14
GPIO_1
TEST2
DGND
H
FRAME_
VALID
DOUT10
TRIGGER
AGND
J
SPI_
SCLK
DOUT9
NC
AGND
K
NC
DGND
TEST5
VAA
L
NC
TEST6
DOUT5
DGND
NC
DAC_
NEG
DAC_
POS
DOUT2
EXTCLK
DOUT4
TEST7
TRIGGER_
OUT
M
NC
NC
DAC_
REF
VDD
VDD
VDDA_
DAC
VDD
NC
DOUT7
DOUT1
NC
NC
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AS0140AT−ADD
PACKAGE DIMENSIONS
Figure 1. 80-ball iCBGA Package
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AS0140AT−ADD
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