AiO - 200 W Power Supply for All-in-One PC

All in One PC Power Supply
Reference Design
Agenda
•
EPA efficiency requirements
•
Reference design goals
•
Topology selection
•
PFC stage design
•
LLC stage design
•
SR design
•
Standby management and handshaking
•
Reference design performance
•
Conclusions
•
Future work
Energy Efficiency:
Regulatory Agencies Targets
•Standby (no load) Power Reduction
• ~25% of total energy passing through power supplies is in standby mode[13]
• Concerted effort by worldwide regulatory agencies
•Active Mode Efficiency Improvement
• ~75% of total energy passing through power supplies is in active mode[13]
•Power Factor Correction (or Harmonic
Reduction)
• Applicable with IEC61000-3-2[11] (Europe, Japan)
• Some efficiency specifications also require >0.9 PF.
example: computers (ENERGY STAR® rev. 4[12])
Korea e-Standby
program[8]
China CSC[6]
(ex-CECP),
Japan Top Runner[9]
program
Japan Eco Mark[10]
program
Australia AGO[7]
California CEC[5]
Europe
COC[4]
ENERGY
STAR®[3]
Update on Energy Efficiency Regulations
Computing
•Desktops:
• ENERGY STAR® 5.0 effective on Jul. 1, 2009
• 80 PLUS & Climate Savers Computing Initiative
• Tiered efficiency levels
•Laptops (More information at ENERGY STAR® 2.0 for External Power Supplies)
• Efficiency: ≥ 87%
• Standby (no load) power: ≤ 500 mW
• PF ≥ 0.9
Set-Top Boxes (STB)
Solid State Lighting Luminaires
•ENERGY STAR® 1.1 effective on Feb. 1, 2009
• Off-state power: 0
• Minimum efficacy (Lumen/Watt) requirements by applications
(downlights, outdoor lights, etc…)
• PF ≥ 0.9 for Commercial
≥ 0.7 for Residential
•ENERGY STAR® 1.2 effective in 2H2009
•ENERGY STAR® additional requirements for LED bulbs
• PF ≥ 0.7
• High system efficacy
high efficiency power supply
•ENERGY STAR® 2.0 effective on Jan 1, 2009
•Europe Code of Conduct version 7 effective Jan 1, 2009
• Standard is based on maximum allowable TEC (Total
Energy Consumption in kWh/year) or allowance
• Base Allowance depends on the type of STB (Cable,
Satellite, etc…)
• Additional functionalities allowance (DVR, etc…)
• Annual Energy Allowance (kWh/year) = Base Functionality
Allowance + Additional Functionalities Allowance
For exhaustive and up-to-date information on agencies and regulations, check the PSMA energy efficiency data base at:
www.psma.com
Efficiency Targets for Single-output
Computing Power Supplies (Servers, Blades, All-in-1)
Single-Output
Levels
Specification
Efficiency (%)
20% of 50% of 100% of
rated
rated
rated
output output output
power power power
Effective
Date
• Single-Output
• Non-Redundant
• PFC 0.9 at 50%
81%
85%
81%
Start
June 2007
• Single-Output
• Non-Redundant
• PFC 0.9 at 50%
85%
89%
85%
Start
June 2008
All in 1 PC
• Single-Output
• Non-Redundant
• PFC 0.9 at 50%
• Single-Output
• Non-Redundant
• PFC 0.9 at 50%
88%
90%
92%
94%
Sources:
• 80 PLUS® : http://www.80plus.org/
• Climate Savers® Computing Initiative: http://www.climatesaverscomputing.org/
• ENERGY STAR®: http://www.energystar.gov/index.cfm?c=revisions.computer_spec
88%
91%
Start
June 2010
Target
Target for this
reference design
Agenda
•
EPA efficiency requirements
•
Reference design goals
•
Topology selection
•
PFC stage design
•
LLC stage design
•
SR design
•
Standby management and handshaking
•
Reference design performance
•
Conclusions
•
Future work
Reference Design Goals
• Must meet highest EPA eff. requirements (80+ silver or gold)
• Must fit into All-in-1 PC (Apple iMAC – 0.23 dm3)
• Input voltage range 90-265 Vac
• Single output – 12 V divided into two terminals:
=> Standby terminal: delivers power all the time
- 50 mA in off mode
- 100 mA in sleep mode
- 5 A maximum in active mode
=> Power terminal: delivers power in active mode (15 A
max.)
• Total maximum output power 216 W
Agenda
•
EPA efficiency requirements
•
Reference design goals
•
Topology selection
•
PFC stage design
•
LLC stage design
•
SR design
•
Standby management and handshaking
•
Reference design performance
•
Conclusions
•
Future work
PFC Stage Selection
• Input power for this application is > 75 W => need a PFC
• ON Semiconductor offers solutions for three modes:
Operating Mode
IL
IL
IL
Tclamp
Tclamp
Main Feature
Continuous
Conduction Mode
(CCM)
Always hard-switching
Inductor value is largest
Minimized rms current
e.g.: NCP1654
Critical conduction
Mode (CrM)
Large rms current
Switching frequency is not
fixed
e.g.: NCP1606
Frequency Clamped
Critical Conduction
Mode (FCCrM)
Large rms current
Frequency is limited
Reduced coil inductance
e.g.: NCP1605
PFC Stage Selection - FCCrM
Efficiency of a 300 W, wide mains PFC has been measured:
Efficiency at 100 Vrms
NCP1605 (FCCrM)
NCP1606 (CrM)
20%
30%
40%
NCP1654 (CCM)
50%
60%
70%
Output Load
80%
90%
100%
Frequency Clamped CrM seems the most efficient
solution while keeping reasonable cost
PFC Stage Selection – Controller
Some features useful in our application:
- Frequency Clamped Critical Conduction Mode
- Lossless High Voltage Current Source for Startup
- Soft Skip Cycle for Low Power Standby Mode
- Fast Line / Load Transient Compensation
- Signal to Indicate that the PFC is Ready “pfcOK”
- VCC range: from 10 V to 20 V
- Output Under and Overvoltage Protection
- Brown−Out Detection
NCP1605 integrates all needed features for all-inone power supply and thus reduces overall cost
Power Stage Selection
cr
n
I
g
n
i
s
ea
r
e
w
po
&
we
o
P
ity
s
en
D
r
Active clamp
forward
Forward
Flyback
Half-bridge
LLC
Power Stage Selection – LLC Benefits
• Series type of resonant converter that allows operation over
relatively wide input voltage and output load ranges
• Limited number of components: resonant tank can be partially
or fully integrated into main transformer
• Zero Voltage Switching (ZVS) condition for the primary
switches under all load conditions
• Zero Current Switching (ZCS) for secondary rectifier under all
load conditions
• Simple synchronous rectification (SR) implementation
Cost effective, highly efficient and EMI friendly
solution
Power Stage Selection – Controller
NCP1397
Features:
- High-frequency operation from 50 kHz up to 500 kHz
- 600 V high-voltage floating driver
- Adjustable minimum switching frequency (3% accuracy)
- Adjustable deadtime from 100 ns to 2 us
- Startup sequence via an externally adjustable soft-start
- Brown-out protection combined with latch input
- Timer-based auto-recovery and immediate latched OCP
- Disable input for ON/OFF control (skip mode)
- Low startup current of 300 µA
- 1 A / 0.5 A peak current sink / source drive capability
- Common collector or emitter optocoupler connections
Benefits for all-in-1 application:
• No driver transformer needed => size restrictions
• Simple skip mode implementation => needed for standby
• Simple OCP implementation => cost impact
NCP1397 is cost effective and reliable solution
for LLC power stage
Power Stage Selection – SR Justification
6
2.33 % of output power
5
4
Losses [W]
Losses
calculated for
one Shottky
diode
Here should be
SR turned off
3
Losses
calculated for
one SR
MOSFET
(including
driving)
2
2.17 % of output power
1
1.4 % of output power
0
0
3
6
9
12
15
18
Output current [A]
Synchronous Rectification can significantly improve
efficiency above certain output power
Power Stage Selection – SR Controller
Some features useful in our application:
NCP4303
- Operates in CCM and DCM Applications
- True Secondary ZCD with Adjustable Threshold
- Automatic Parasitic Inductance Compensation
- 50 ns Turn off Delay from CS to Driver
- Interface to External Signal for CCM Mode
- Trigger Input to enter Standby Mode
- Adjustable Min Ton Independent of Vcc Level
- Adjustable Min Toff Independent of Vcc Level
- 5 A / 2.5 A Peak Current Drive Capability
- Voltage range up to 28 V
- Gate drive clamp of either 12 V or 5 V
- Low startup and standby current consumption
- Maximum Frequency of Operation up to 500 kHz
NCP4303 is high performance driver for any SR
system
Secondary SR Turn On/Off
• Usage of SR boosts efficiency above certain power only
• Operation of SR for low output currents is inefficient
SR needs to be turned off based on the output
current information
OTP for Secondary Rectifiers
•
Max output current is 18 A. In case of fan or secondary rectification
system fail serious damage can occur to data or SMPS itself
SMPS needs to be protected against over temperature and
provide a signal to PC for fan speed control and to shut
down prior the SMPS would fail
Standby Management
• According to All-in-1 spec the power terminal has to be
turned off during standby mode by an external switch
NFET provides low Rds on compare to PFET
Complete Block Diagram
FCCrM maximize
eff. of front stage,
reduces PFC coil
size
ZVS maximizes
efficiency, LLC
topology minimizes
dimensions
SR improves
eff. under medium
and high loads
Disconnects
pwr. output
during STBY
Agenda
•
EPA efficiency requirements
•
Reference design goals
•
Topology selection
•
PFC stage design
•
LLC stage design
•
SR design
•
Standby management and handshaking
•
Reference design performance
•
Conclusions
•
Future work
NCP1605 Design Worksheet
200 uH PFC inductor keeps low operating
frequency => EMI impact
PFC Stage Schematic
Agenda
•
EPA efficiency requirements
•
Reference design goals
•
Topology selection
•
PFC stage design
•
LLC stage design
•
SR design
•
Standby management and handshaking
•
Reference design performance
•
Conclusions
•
Future work
Resonant Inductance Location?
External inductance
Internal leakage inductance
Benefits:
• Greater design flexibility
• Lower radiated EMI emission
• Transformer winding utilization
Benefits:
• Primary to secondary insulation is
easy to achieve
• Better cooling for windings
• One component only
Drawbacks:
• Worse windings cooling
• Primary to secondary insulation is
more complex to achieve
Drawbacks:
• Less design flexibility
• EMI radiation
• Eddy currents in SMPS metal cover
due to stray flux
• Pure winding window utilization
External resonant coil provides more benefits for
high power density designs
LLC Resonant Tank Parameters
Selected solution:
Standard transformer + external
resonant inductance
Transformer:
Primary inductance Lm= 430 uH
Leakage inductance Llk= 55 uH
Turn ratio prim. to sec. n = 17.5
Turn ratio prim. to aux. naux = 11.6
Resonant coil:
Ls= 30 uH
Resonant capacitor:
Cs= 2 x 12 nF
LLC Resonant Tank Model
•
•
This design uses transformer leakage and external coil as
resonant inductance
T model can be used
L
k = 1 − lk
Lm
Le1 = Le 2 = (1 − k ) ⋅ Lm
Lme = k ⋅ Lm
T model reflects the fact that Lm also participates
on resonance => transformer gain impact
LLC Stage Gain Characteristic
0.100
Full load
0.090
0.080
0.070
f op= 87 kHz@ V bulk=350 Vdc
f op= 103 kHz@ V bulk=385 Vdc
f op= 124 kHz@ V bulk=420 Vdc
Gain [-]
0.060
0.050
0.040
0.030
0.020
0.010
0.000
1.00E+04
1.00E+05
1.00E+06
Frequency [Hz]
Selected resonant tank provides narrow operating
frequency range
LLC Primary Side Schematic
NCP1397 simplifies LLC stage design
implementing dual OCP and skip mode
by
Agenda
•
EPA efficiency requirements
•
Reference design goals
•
Topology selection
•
PFC stage design
•
LLC stage design
•
SR design
•
Standby management and handshaking
•
Reference design performance
•
Conclusions
•
Future work
SR Design
Vds
SR MOSFET losses:
- Conduction losses
Id
π⎞
⎛
= ⎜ I out ⋅ ⎟ ⋅ Rds _ on
4⎠
⎝
2
Pcond
=> Rds_on selection
- Gate drive losses
Pdrv = Q g ⋅ Fsw ⋅ Vcc
=> gate charge selection
- Body diode losses
I
π⎞
⎛
= out ⋅V f + ⎜ I out ⋅ ⎟ ⋅ Rdyn
2
4⎠
⎝
2
SR controllers consumption and
gate drive losses in standby would
hamper standby efficiency
⇒ It is critical to turn off whole SR
system in standby mode
Pbody
=> Affected by diode Vf, dynamic
resistance and parasitic inductance,
external Shottky to be used
SR – Package Parasitic Inductance
• TO220 package is mostly used due to cost and also
simple soldering process
•
•
•
•
Parasitic inductances Ldrain and Lsource create voltage drop that is
proportional to the secondary current Isec(t) derivative.
The Vds voltage reaches zero level prior secondary current
SR controller detects zero voltage in the time the secondary current has
still significant level => efficiency degradation
Higher frequency or dIsec(t)/dt is, higher efficiency drop will be
SR Design – Package Parasitic Inductance
• This issue becomes really serious when very low
Rds_on MOSFET is used
SR controller
with Vth_zcd= 0 mV
SR controller
with Vth_zcd= -5 mV
SR controller with 0 mV ZCD threshold provides longer
conduction period for SR MOSFET
NCP4303 Parasitic Inductance Compensation
Lcomp can be
done on PCB or
using ferrite bead
Secondary
current
SR MOSFET
gate voltage
SR MOSFET conduction period is maximized when
NCP4303 implemented with compensation Inductance
Note: Parasitic inductance compensation not used in this PCB version
Note: Patent pending
SR Design – MOSFET Selection
• SR MOSFET works under ZVS conditions
=> Gate charge is given by Ciss capacitance (Cgs+Cgd) and
gate voltage
MOSFET
type
Qg @ 5 V
[nC]
Qg @ 12 V
[nC]
Rds_on @ 5V
[mΩ]
Rds_on @ 12V
[mΩ]
IPP015N04N
101
245
1.9
1.2
FDP047AN
39
96
5.8
4
IRFB3206
55
133
3.3
2.3
SR Design – Gate Voltage Clamp Selection
6
Vclamp= 5 V
Vclamp= 12 V
Fop=120 kHz
FDP047 AN
Total power loss [W]
5
4
3
2
1
0
0
3
6
9
12
15
18
Output current [A]
NCP4303 with 12 V gate voltage clamp to be used
SR Final Schematic with SR Turn On/Off
SR on/off
switch
Schottky
Improves efficiency
under light loads
NCP4303 with min.
ton and min. toff
adjust resistors
SR on/off
comparator
Secondary current
sensing and amplifier
Simple and cost effective SR implementation
Agenda
•
EPA efficiency requirements
•
Reference design goals
•
Topology selection
•
PFC stage design
•
LLC stage design
•
SR design
•
Standby management and handshaking
•
Reference design performance
•
Conclusions
•
Future work
OTP
To
All-in-1
PC
Either PFC or LLC can be latched-off in case of
overtemperature
Power Terminal On/Off
To
All-in-1
PC
N MOSFET provides low Rds_on
Primary Biasing
• HV startup is needed for All-in-1 application
NCP1605 simplifies primary biasing
X2 Capacitor Discharge Circuitry
• It is mandatory to discharge X2 cap after is application
unplugged from mains
• X2 discharge resistor increases standby consumption
Charge pump helps to decrease standby input power
by removing X2 cap. discharge resistor
Total Board Schematic
Full All-in-1 solution from ON semiconductor
Reference Design Photo – Top Side
PFC stage
Secondary
capacitor
Output
connector
SR MOSFETs
and STBY
switch on
cooler
EMI
filter
LLC
stage
Resonant
inductor
Transformer
Reference Design Photo – Bottom Side
NCP1397B LLC cnt.
NCS1002
regulator
LM324
amplifier
2 x NCP4303 SR cnt.
NCP1605 PFC cnt.
Agenda
•
EPA efficiency requirements
•
Reference design goals
•
Topology selection
•
PFC stage design
•
LLC stage design
•
SR design
•
Standby management and handshaking
•
Reference design performance
•
Conclusions
•
Future work
SMPS Efficiency Charts
94%
91.7%
92%
89%
Efficiency
90%
90.5%
90.4%
88%
87.8%
88.5%
86%
84%
82%
230 Vac
110 Vac
80%
0
3
6
9
Output current [A]
12
15
18
Reference design meets 80+ silver specification
SMPS Efficiency Charts, Comparison With
Original Solution Without SR
94%
92%
Efficiency
90%
88%
86%
230 V (ON reference design)
84%
230 V (Original SMPS)
110 V (ON reference design)
82%
110 V (Original SMPS)
80%
0
3
6
9
12
Output current [A]
15
18
Light Load Efficiency
2000
No load
1800
50 mA load
Consumption [mW]
1600
1400
1200
1000
800
600
400
200
0
90
115
140
165
190
AC voltage [V]
215
240
265
PF
C
co
il
SR
r
de
er
ifie
di
o
re
ct
.&
l
re
ct
.
PF
C
an
sf
or
m
sw
h
na
nt
co
i
Br
id
ge
Tr
itc
O
SF
ET
s
es
o
M
sw
8
R
LL
C
O
ut
pu
t
Pd [W]
Detail Losses Distribution
9
Vin=110 Vac
Vin=230 Vac
7
6
5
4
3
2
1
0
Future Work
• Implement parasitic inductance compensation in SR
stage and thus further boost the efficiency.
• Use different SR MOSFET(s) and gate clamp voltage to
reduce driving losses.
• Further optimization of the PFC stage efficiency
• Boost efficiency to meet 80+ gold specification ☺
Conclusion
• High efficient 80+ silver reference design from ON
Semicondcutr is now available!!
• FCCrM PFC stage driven by NCP1605 provides excellent
efficiency results and minimizes PFC inductor size. PFC OK
signal and skip mode featured in this controller simplifies
design of All-in-1 PC SMPS
• LLC power stage driven by NCP1397 provides high
efficiency, skip mode capability and cheap OCP
implementation
• Synchronous Rectifier driven by NCP4303 maximize the SR
MOSFET conduction time – thus maximize efficiency. Voltage
clamp on the driver reduces driving losses
• ON Semiconductor provides full support on this reference
design and mentioned ICs
For More Information
•
View the extensive portfolio of power management products from ON
Semiconductor at www.onsemi.com
•
View reference designs, design notes, and other material supporting
the design of highly efficient power supplies at
www.onsemi.com/powersupplies
Similar pages