7 Channel PMIC with 2 DC-DC Converters, 5 LDOs and a Triple Input 10 bits ADC Evaluation Kit Manual

NCP6925EVK
7 Channel PMIC with
2DC­DC Converters, 5 LDOs
and a Triple Input 10 bits
ADC Evaluation Kit Manual
The NCP6925EVK evaluation kit is a full assembled
circuit board for evaluation and test of the NCP6925. This
document provides documentation, test procedure and
equipment set-up for the complete evaluation of the
NCP6925. The NCP6925EVK comes with one NCP6925
evaluation board, 1 MCU board for I2C master and
associated cables.
EVALUATION KIT MANUAL
• 5 Low Noise – Low Dropout Regulators (2.2 mF,
General Description
The NCP6925 integrated circuit is part of the
ON Semiconductor mini power management IC family
(PMIC). It is optimized to supply battery powered portable
application sub-systems such as camera function,
microprocessors. This device integrates 2 high efficiency
1 A step-down DC-DC converters, 5 low dropout (LDO)
voltage regulators and a triple input 10 bits ADC in a
WLCSP36 2.4 x 2.4 mm package.
•
•
Features
• 2 DC−DC Converters (3 MHz, 1 mH / 10 mF, 1 A)
♦
♦
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•
•
Peak Efficiency 95%
Programmable Output Voltage from 0.6 V to 3.3 V
by 12.5 mV Steps
300 mA)
♦ Programmable Output Voltage from 0.8 V to 3.5 V
by 25 mV Steps
Triple Input 10 bits ADC
♦ Dual Resistors Measurement Mode
♦ General Purpose Mode
Control
♦ Fully Programmable Through a 400 kHz / 3.4 MHz
I2C with Pins Selectable I2C Address and Interrupt
Output
♦ Power on Input and General Purpose I/O Pins that
can be used as DC−DC Enable Pins
Very Low Quiescent Current at No Load
Small Footprint : 2.4 x 2.4 mm WLCSP 0.4 mm Pitch
Figure 1. Evaluation Board Picture
© Semiconductor Components Industries, LLC, 2014
February, 2014 − Rev. 0
1
Publication Order Number:
EVBUM2228/D
NCP6925EVK
Table 1. BOARD COMPONENTS DESCRIPTION
Qty
Reference
Value
PCB Footprint
MFR
−
ON Semiconductor
NCP6925
0603
Panasonic
ERJ−3GEY0R00V
Ceramic Capacitor 2.2 mF
6.3 V X5R
0402
TDK
C1005X5R0J225K050BC
C15, C16
Ceramic Capacitor 1 mF
6.3 V X5R
0402
TDK
C1005X5R0J105K05BB
2
C1, C3
Ceramic Capacitor 4.7 mF
6.3 V X5R
0603
TDK
C1608X5R0J475K080AB
2
C2, C4
Ceramic Capacitor 10 mF
6.3 V X5R
0603
TDK
C1608X5R0J475K080AB
2
C17, C19
Ceramic Capacitor 100 mF
6.3 V X5R
1210
TDK
C3225X5R0J107M250AC
2
L1, L2
Inductor
2016
TOKO
DFE2016R−H−2R2N
14
J3, J5, J8, J11, J12,
S102,
LTR100 → LTR107
Jumper Header Vertical
Mount, 3 positions,
100mils
Tyco Electronics /
AMP
5−826629−0
13
J13 → J21
J6, J7, J9, J10
Banana Jack
Hirchmann Test
and Measurement
930160000
1
J100
Connector header 26 pos
3M
N2526−6002−RB
23
TP1 … TP23
Test Point
Keystone
Electronics
5011
4
Q3, Q4, R15, R16,
Not Mounted
3
J4, J22, J23
Jumper Connector
Harwin
D3082−B01
3
S4, S6, S7
Shorted
4
Spacer nylon
H1, H2, H3, H4
Richco Plastic co
R908−4
1
−
NCP6925 PMIC
1
R13
SMD Resistor 10 KW
10
C5, C6, C7, C8, C9,
C10, C11, C12,
C13, C14
2
100 mils
400 mils
Table 2. CONNECTOR DESCRIPTION
Input Power
Vbat (J6−J9)
VIN_LDO
(J7−J10)
−
negative input connected to GND pin (J9)
AVIN and PVIN
Core and DCDCs power supply (J6)
−
negative input connected to GND pin (J10)
VIN_LDO
Dedicated LDOs power supply. S4 has to be unsoldered (J10)
Regulators Outputs
J(13 → J21)
−
negative output connected to GND pin (J14 and J21)
J13
DCDC1 output
J15
DCDC2 output
J16
LDO1 output
J17
LDO2 output
J18
LDO3 output
J19
LDO4 output
J20
LDO5 output
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2
Part Number
NCP6925EVK
Table 2. CONNECTOR DESCRIPTION
Chip Control
MCU
SDA
I2C data, connect to SDA pin or the 26 pins ribbon cable
SCL
I2C data, connect to SCL pin or the 26 pins ribbon cable
HWEN
Master enable pin connected to the 26 pins ribbon cable thru J3
A0
I2C address selectable pin connected to the 26 pins ribbon cable thru J11
A1
I2C address selectable pin connected to the 26 pins ribbon cable thru J12
GPIO1
GPIO pin connected to the 26 pins ribbon cable thru J5
GPIO2
GPIO pin connected to the 26 pins ribbon cable thru J8
Figure 2. Assembly Layer
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3
NCP6925EVK
SCHEMATIC
J13
TP23
DCDC_VOUT1
1
TP22
1
TP19
1
TP18
1
TP17
1
TP16
1
TP15
1
TP14
1
TP13
1
1
TP12
1
TP11
1
TP10
1
TP9
1
TP8
1
TP7
1
1
TP6
1
1
1
VBG
SW1
SW2
1
ADCIN3
ADCIN2
ADCIN1
INTB
GPIO2
GPIO1
SCL
SDA
HWEN
VOUT5
VOUT4
VOUT3
J14
VOUT2
1
TP5
VOUT1
TP4
DCDC_VOUT2
1
1
TP3
DCDC_VOUT1
1
VBAT
TP2
VIN_LDO
TP1
J15
DCDC_VOUT2
1
VOUT1
1
VOUT2
1
VOUT3
1
VOUT4
1
VOUT5
1
1
J16
1
J17
J6
1
VBAT
1
C17
100uF
C18
dnp
U1
VBAT
J9
C16
1uF
S4
J7
1
VIN_LDO
1
C19
100uF
12
1
VBG
C5
R11 NC
ADCIN1
C2
R12 NC
ADCIN2
B3
ADCIN3
B2
HWEN
D2
GPIO1
E2
GPIO2
E5
C20
dnp
J10
1
D1
C3
C4
D4
D3
C15
1uF
1
12
1
1
J18
PVIN1
AVIN
SW1
AGND
AGND
AGND
DGND
FB1
PGND1
VBG
PVIN2
ADCIN1
SW2
ADCIN2
FB2
ADCIN3
PGND2
HWEN
VIN1
GPIO1
VOUT1
GPIO2
VIN2
VOUT2
S5
B5
DCDC_VOUT1
A0
E3
A1
E4
SDA
D6
SCL
D5
INTB
B4
AGND
VIN3
A0
VOUT3
A1
VIN4
SDA
VOUT4
SCL
VIN5
INTB
VOUT5
F1
VBAT
F2
SW1
E1
FB1
C1 4.7uF
L1
2.2uH
S2
12
F6
VBAT
F5
SW2
E6
FB2
C3 4.7uF
L2
2.2uH
S3
J20
C4
10uF
VIN_LDOC5
2.2uF
C1
VOUT1 C6
2.2uF
A1
VIN_LDOC7
2.2uF
A2
VOUT2 C8
A4
VIN_LDOC9
2.2uF
A3
VOUT3 C10
2.2uF
A5
VIN_LDOC11
2.2uF
1
DCDC_VOUT2
12
F4
B1
J19
C2
10uF
F3
1
DCDC_VOUT1
1
J21
1
1
2.2uF
A6
VOUT4 C12
2.2uF
B6
VIN_LDOC13
2.2uF
C6
VOUT5 C14
2.2uF
NCP6925
AGND and PGND connected in one point
HWEN
VBAT
HWEN_MCU
J3
GPIO1
DCDC_VOUT1
GPIO1_MCU
DCDC_VOUT2
VOUT1
J5
GPIO2
VOUT2
VOUT3
GPIO2_MCU
VOUT4
VOUT5
LTR105
LTR100 LTR101 LTR102 LTR103 LTR104 LTR107
J8
A0
S102
LTR106
LOGIC_SUPPLY
A0_MCU
VBAT
J100
CON26A
VI2C
R13
10k
INTB
SH3
TP21
Load TR. Gen2
SDA
S7
12
SDA_MCU
VI2C
J11
A1
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
GPIO2_MCU
GPIO1_MCU
HWEN_MCU
SCL_MCU
A1_MCU
S6
SCL
12
J12
A0_MCU
A1_MCU
TP20
Load TR. Gen1
Q4
NTD4969NT4G
BSS138LT1
R16
50 Ohms
Q3
R15
50 Ohms
REV
DATE
Designed by
H1
FIXHOLE3.2
H2
FIXHOLE3.2
H3
FIXHOLE3.2
PDE
H4
FIXHOLE3.2
1
1
1
1
1
1
1
1
J22
GND JUMPER
2
1
J4
GND JUMPER
2
1
J23
GND JUMPER
2
1
DESCRIPTION
AUTHOR
ON SEMICONDUCTOR
132 Chemin Basso Cambo
BP53512
31035 TOULOUSE Cedex 1 France
Rev
NCP6925 Evaluation Board
TLS−P−001−B−0613−OM
A.0
DWG NO
TLS−P−001−B−0613−OM
Thursday, June 06, 2013
Figure 3. Evaluation Board Schematic
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Scale
Size
C
Sheet
1
of
<Total # of pages>
NCP6925EVK
SOFTWARE INSTALLATION
Important notice: In order to properly install drivers
and software, please launch NCP6925_setup.exe file
before connects the MCU board.
Double click on NCP6925_setup.exe file. Follow the
instructions set−up.
It is recommended to copy the NCP6925_setup.exe to a
local directory: If eval kit is already installed, a simple
double click on NCP6925.exe will launch the GUI.
Figure 4.
QUICK CONFIGURATION
Power Supply
Load
NCP6925 requires at least 1 external power supply :
Vbat (J6) : supply between 2.5 V to 5.5 V.
DCDCx Converters
An electronic load or passive load can be connected
between J13 and J14 for DCDC1, between J15 and J21 for
DCDC2.
LDOx Regulators
An electronic load or passive load can be connected
between J16 and J14 or J21 for LDO1, between J17 and J14
or J21 for LDO2, J18 and J14 or J21 for LDO3, J19 and J14
or J21 for LDO4, J20 and J14 or J21 for LDO5.
ADC
TP13, TP14, TP18 can be used as general purpose input
for the ADC.
Jumpers Configuration
The HWEN, A0 and A1 jumpers are configured by default
to work with the ONSEMI I2C interface board. GPIO1 and
GPIO2 jumpers are not configured.
S4 shunt is soldered to use only one power supply for the
DCDCs, LDOs and AVIN.
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5
NCP6925EVK
PCB LAYOUT
Figure 5. Top Layer
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6
NCP6925EVK
Figure 6. Bottom Layer
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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EVBUM2228/D
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