CIC310 Data Sheet

D a t a S h e e t, V 2 . 2 , J u n e 2 0 0 7
S AK- C IC 31 0 - O S M X 2 H T
FlexRay Communication Controller
I FL E X
Step A11
M i c r o c o n t r o l l e rs
Edition 2007-06
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2007.
All Rights Reserved.
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D a t a S h e e t, V 2 . 2 , J u n e 2 0 0 7
S AK- C IC 31 0 - O S M X 2 H T
FlexRay Communication Controller
I FL E X
Step A11
M i c r o c o n t r o l l e rs
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trademarks of Infineon Technologies AG.
™, and GPTA® are
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™ are trademarks of the FlexRay
Consortium.
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Template: mc_a5_um_tmplt.fm / 4 / 2004-09-15
IFLEX
SAK-CIC310-OSMX2HT
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
2.1
2.2
2.3
2.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MLI Host Link (Option One) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Host Link (Option Two) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Host Link (Option Three) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
13
14
3
3.1
3.2
3.2.1
3.2.2
3.2.3
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
19
19
20
42
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.4
4.4.1
4.4.2
4.4.3
4.4.4
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pad Driver and Input Classes Definitions . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristic Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Channel (SSC) Slave Mode Timing . . . . . . . . . . . .
MLI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XMU External Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Parameters (PG-TQFP-64) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
43
43
44
44
46
46
48
49
50
50
51
52
53
55
56
58
60
62
64
66
66
66
67
68
Data Sheet
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V 2.2, 2007-06
FlexRay Communication Controller
IFLEX
1
SAK-CIC310-OSMX2HT
Summary of Features
The major functions supported by the SAK-CIC310-OSMX2HT are summarized in this
section.
•
•
A powerful FlexRay v2.1 Protocol Controller
– Certified to be conform with FlexRay protocol specification v2.1
– Data rates of up to 10 MBit/s on each channel
– Up to 128 message buffers configurable
– 8 Kbyte of Message RAM for storage of e.g. 128 message buffers with maximum
48 Byte data field or up to 30 messages with 254 Byte data field
– Configuration of message buffers with different payload lengths
– One configurable receive FIFO
– Each message buffer can be configured as Receive Buffer, as Transmit Buffer, or
as part of the receive FIFO
– Host access to message buffers via Input and Output Buffer.
Input Buffer: holds message to be transferred to the Message RAM
Output Buffer: holds message read from the Message RAM
– Filtering for frame ID, channel ID, and cycle counter
– Network Management supported
– Two Channels enabling one redundant FlexRay Bus
– All data formats are little-endian
Independent 8-Channel DMA Controller
– 8 selectable request inputs per DMA channel
– Programmable priority of DMA channels within the DMA sub-block (2 levels)
– Software and hardware DMA request generation
– Hardware requests by selected peripherals
– Individually programmable operation modes for each DMA channel
– Single Mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous Mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated.
– Programmable address modification
– Support of circular buffer addressing mode
– Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit
– Individual register set for each DMA channel
– Source and destination address register
– Channel control and status register
– Transfer count register
Data Sheet
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V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Summary of Features
•
•
•
•
•
•
•
•
•
•
– Flexible interrupt generation
16-bit External Memory Interface Unit (XMU)
– 16-bit wide data bus (D[15:0])
– Automatic data assembly/disassembly operation
– Data width of external bus master can be 8-bit or 16-bit
– 13-bit wide address bus (A[12:0])
– Address extension mechanism to 32-bit
– Read (RD) and write (WR) Bus control signal
– External synchronous/asynchronous wait state bus control signal (WAIT)
– External master chip select (CSFPI) to access on-chip devices connected to the
crossbar switch
High performing on-chip crossbar bus structure
– 32-bit crossbar slave interface for FlexRay
– 32-bit crossbar slave interface for Ports and System Control
– 32-bit crossbar slave interface for MLI communication
– 32-bit crossbar slave interface for MLI and DMA peripheral
– 32-bit crossbar master interface for Host Communication Interfaces
– 32-bit crossbar master interface for DMA
Versatile High-Speed Synchronous Serial Channels (SSC) for Host Communication
– Full-duplex or half-duplex operation
– Automatic half-duplex pad control
– SSC supports proprietary protocol to drive an integrated move engine
– Maximum Master Mode baud rate: fSSC / 2
Maximum baud rate (master mode) of 40 MBit/s (@ 80 MHz module clock)
– Maximum Slave Mode baud rate: fSSC / 4
Maximum baud rate (slave mode) of 20 MBit/s (@ 80 MHz module clock)
Versatile High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication and Host Communication
– Fully transparent read/write access supported (including remote programming)
– Complete address range of target controller available
– Special protocol to transfer data, address offset, or address offset and data
– Error control using a parity bit
– 32-bit, 16-bit, and 8-bit data transfers
– Address offset width: from 1 to 16 bit
– Baud rate: fMLI / 2 (symmetric shift clock approach),
baud rate definition by the corresponding fractional divider
Maximum baud rate of 40 MBit/s (@ 80 MHz module clock)
Full automotive temperature range: -40°C to +125°C
26 digital general purpose I/O lines, 20 digital general purpose input lines
Digital I/O ports with 3.3 V capability
Clock Generation Unit with PLL
Core supply voltage of 1.5 V
I/O voltage of 3.3 V
Data Sheet
8
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Summary of Features
•
One Package Option only (PG-TQFP-64)
As the FlexRay Protocol Controller is on a separate chip, the so called standalone
Communication Controller, the access is handled via serial or parallel communication
links. These three types of link options are discussed in the following chapter.
Data Sheet
9
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Functional Description
2
Functional Description
The SAK-CIC310-OSMX2HT IC is supposed to be connected to devices of the Infineon
AUDO-NG 32bit microcontroller device family. The connection has to be done in a way
that today’s AUDO-NG 32-bit microcontroller MLI, ASC, or SSC interfaces remain
untouched. On the other hand the FlexRay Communication controller requires
communication bandwidth of 10 MBit/s and more to download the full message
bandwidth of the two FlexRay links. Beside this requirement additionally the SAKCIC310-OSMX2HT needs to be operative with a minimum pin account and area.
Therefore two small serial interfaces (MLI, SSC) and an additional parallel interface are
implemented.
For the SAK-CIC310-OSMX2HT concept three options are implemented in parallel to
minimize the risk and to increase the options for a system composed out of the SAKCIC310-OSMX2HT and an AUDO-NG 32-bit microcontroller device and still to handle
the application requirements. These three interfaces are the SSC Interface (usable as
SPI and synchronous ASC Interface), a parallel Interface, and the Micro Link Interface
(MLI). All AUDO-NG 32-bit microcontroller family member are equipped with serial
interfaces (ASC and SSC).
Three options are presented for the system solution based on these three
communication interfaces.
2.1
MLI Host Link (Option One)
The first and preferred option is to connect the SAK-CIC310-OSMX2HT via the MLI
interface to the AUDO-NG 32bit microcontroller family. The MLI has the advantage
realizing a fast and smart communication interface with a low pin count and SPI like SW
protocol handling. The transmission rate is high enough to handle the data traffic that is
generated from the SAK-CIC310-OSMX2HT FlexRay Protocol engine to the AUDO-NG
32-bit microcontroller device and vice versa.
MLI Feature Set
•
•
•
•
•
•
•
•
Serial communication from the MLI transmitter to MLI receiver of another controller
Fully transparent read/write access supported (including remote programming)
Complete address range of target controller available
Special protocol to transfer data, address offset, or address offset and data
Error control using a parity bit
32-bit, 16-bit, and 8-bit data transfers
Address offset width: from 1 to 16 bit
Baud rate: fMLI / 2 (symmetric shift clock approach),
baud rate definition by the corresponding fractional divider
Maximum baud rate of 40 MBit/s (@ 80 MHz module clock)
Data Sheet
10
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Functional Description
2 FlexRay
Channels
IFLEX
PORST (RESET)
MLI
AUDO-NG 32-bit
microcontrollers
MLI
SYSTEM_MLI
Figure 1
SAK-CIC310-OSMX2HT and AUDO-NG 32bit Microcontroller Device
Connected via MLI
The connectivity features of the MLI enables also connecting two different SAK-CIC310OSMX2HT devices with the host This requires two sets of MLI interface signals bonded
out of the host MLI.
2.2
SSC Host Link (Option Two)
The second option is to connect the SAK-CIC310-OSMX2HT via a SSC (SPI) interface
to e.g. the AUDO-NG 32-bit microcontroller family or the (X)C166 16-bit microcontroller
family. Pin count are in a similar range compared with the MLI interface. The SW
handling cost more host performance than the MLI interface requires. The single SPI link
does not provide enough bandwidth to handle the maximum bandwidth FlexRay may
require, but fulfil the needs of applications with lower bandwidth requirements.
SSC Feature Set
•
•
•
•
•
Master and slave mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
Flexible data format
– Programmable number of data bits: 2 to 16-bit
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
Baud rate (master): fSSC / 2;
Maximum master mode baud rate of 40 MBit/s (@ 80 MHz module clock)
Baud rate (slave): fSSC / 4;
Maximum slave mode baud rate of 20 MBit/s (@ 80 MHz module clock)
Interrupt generation
– On a transmitter empty condition
Data Sheet
11
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Functional Description
•
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
SSC supports proprietary protocol to drive an integrated move engine.
Note: Even so the SSC can be flexible configured, the SSC move engine can only
handle 16 bit, Slave Mode, Full-duplex mode and Half-duplex mode, leading edge
is high to low, shift on leading edge.
2 FlexRay
Channels
BUSY
IFLEX
PORST (RESET)
chip select
SCLK
SSC
MRST
MTSR
Figure 2
AUDO-NG 32-bit
microcontrollers
SSC
SYSTEM_SSC
SAK-CIC310-OSMX2HT and AUDO-NG 32bit Microcontroller Device
Connected by SPI
The SSC is configured in a manner it could communicate to the ASC of the TriCore
family. The TriCore ASC is configured in a manner using both RXDxA and RXDxB of the
ASC as MRST and MTSR and the TXDxA or TXDxB as Clock.
Data Sheet
12
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Functional Description
2 F lexRay
Channels
SSC
IFLEX
MRST and
MTSR
RXDxB or
RXDxA
SCLK
TXDxA or
TXDxB
direction
chip select
BUSY
ASC
AUDO-NG 32-bit
microcontrollers
PORST (RESET)
2 F lexRay
Channels
BUSY
IFLEX
SSC
PORST (RESET)
chip select
SCLK
TXDxA or
TXDxB
MRST
RXDxB or
RXDxA
MTSR
Figure 3
2.3
RXDxA or
RXDxB
AUDO-NG 32-bit
microcontrollers
ASC
SYSTEM_ASC
SAK-CIC310-OSMX2HT and AUDO-NG 32bit Microcontroller Device
Connected via ASC
Parallel Host Link (Option Three)
The third option is to connect the SAK-CIC310-OSMX2HT via the parallel interface e.g.
the AUDO-NG 32-bit microcontroller family or the (X)C166 16-bit microcontroller family.
The parallel interface provides enough bandwidth to handle the maximum data traffic
generated by the SAK-CIC310-OSMX2HT FlexRay Protocol Controller to the AUDO-NG
32-bit microcontroller device and vice versa.
XMU Features
•
•
•
16-bit wide data bus (D[15:0])
– Data width of external bus master can be 8 or 16 bit.
– Automatic data assembly/disassembly operation
13-bit wide address bus (A[12:0])
Bus control signals
– Read (RD) and write (WR)
– Two byte control signals (BC[1:0])
– External synchronous/asynchronous wait state control (WAIT)
– External master chip select (CSFPI) to access on-chip devices connected to the
MIF Bus
Data Sheet
13
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Functional Description
2 FlexRay
Channels
IFLEX
PORST (RESET)
XMU
AUDO-NG 32-bit
microcontrollers
EBU
SYSTEM_XMU
Figure 4
2.4
SAK-CIC310-OSMX2HT and AUDO-NG 32bit Microcontroller Device
Connected via XMU
DMA Controller
The Direct Memory Access (DMA) Controller of the SAK-CIC310-OSMX2HT transfers
data from data source locations to data destination locations without intervention of the
Host Controller. One data move operation is controlled by one DMA channel. Eight DMA
channels are provided. The Bus Switch provides the connection of the DMA Sub-Block
to the ERAY Peripheral, Host Communication peripheral, Ports, and an MLI bus
interface. Figure 5 shows the implementation details and interconnections of the DMA
module.
Clock
Control
DMA
Requests of
On-chip
Periph.
Units
fDMA
DMA Controller
DMA Sub-Block 0
Request
Selection /
Arbitration
DMA
Channels
00-07
Transaction
Control Unitl
CH0n_OUT
MCB05680_mod
Figure 5
Data Sheet
DMA Controller Block Diagram
14
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Functional Description
Features
•
•
•
•
•
•
•
•
•
•
8 independent DMA channels
– Up to 8 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within a DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
Programmable priority of the DMA Sub-Blocks on the crossbar switch
Buffer capability for move actions on the buses (at least 1 move per bus is buffered).
Individually programmable operation modes for each DMA channel
– Single mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated.
– Programmable address modification
Full 32-bit addressing capability of each DMA channel
– 4 GByte address range
– Support of circular buffer addressing mode
Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
Micro Link bus interface support
Register set for each DMA channel
– Source and destination address register
– Channel control and status register
– Transfer count register
Flexible interrupt generation (the service request node logic for the MLI channels is
also implemented in the DMA module)
Read/write requests of the System Bus Side to the Remote Peripherals are bridged
to the Remote Peripheral Bus (only the DMA is master on the RPB)
Data Sheet
15
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
3
General Device Information
This section provides an overview of the entire architecture of the SAK-CIC310OSMX2HT companion chip.
The overall building blocks of the SAK-CIC310-OSMX2HT are:
•
•
•
•
•
•
•
FlexRay v2.1 protocol controller
Slave (SPI) SSC interface
MLI interface
Parallel external memory interface unit (XMU).
8 independent channel DMA
Dual Voltage Power Supply
One Package Option only (PG-TQFP-64)
3.1
Block Diagram
Figure 6 summarizes the overall architecture of the SAK-CIC310-OSMX2HT.
SSC
XMU
slave master
Move
Engine
MLI
master
master
slave
DMA
slave master
Move
Engine
Init
Engine
slave 3
slave 2
Crossbar Switch
slave 0
slave
slave 1
slave
SCU
Ports
PLL
Figure 6
Crystal
Oscillator
slave
FlexRay
IRAY_OVERVIEW_TS
IFLEX Block Diagram
In Figure 6 the block diagram of the IFLEX is shown. This concept allows the access to
the FlexRay Protocol Controller for the host CPU without sacrificing any of the features
Data Sheet
16
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
of the FlexRay Protocol Controller. This can be achieved, as all registers of the FlexRay
Protocol Controller are mapped to the crossbar switch. This crossbar switch can be
accessed via one of the three host interfaces, which were introduced in Chapter 2. The
interface selection is done via the mode signals MODE[0] and MODE[1], which can be
directly connected to the supply voltage or via pull-up/down resistors (of about 1047 kΩ).
Table 1
Host Interface Select
Mode[1] Mode[0] Selected Host Interface
0B
0B
XMU Host Interface activate
1B
0B
0B
1B
MLI Host Interface activate
1B
1B
SSC Host Interface activate
The cross bar switch allows two parallel data operations, one initiated by the DMA, the
other by either the MLI, XMU, or SSC move engine and serving different ports of the
crossbar switch to slave interfaces. The address ranges of the slave ports are:
1.
2.
3.
4.
Slave Port 0 serves the address range from 0000 0800H to 0000 0FFFH
Slave Port 1 serves the address range from 0000 1000H to 0000 1FFFH
Slave Port 2 serves the address range from 0000 0200H to 0000 07FFH
Slave Port 3 serves all addresses 0000 0000H to 0000 01FFH and 0000 2000H to
FFFF FFFFH
So apart from a possible loss of speed due to the serial interfaces the complete
functionality of the FlexRay Protocol Controller is maintained.
The crossbar switch domain is completely separated from the address domain on the
CPU chip. The addresses of all modules on the FlexRay Communication Controller are
32-bit addresses. Transactions between the CPU and the SSC are executed with the
SSC transmission protocol and a high level protocol to drive the move engine,
transactions between the MLI and the CPU use the MLI transmission protocol and
transactions between the XMU and the CPU are based on the XMU transmission
protocol.
Each transaction via any of the three host interfaces is defined by address, data, data
width and type of frame. The address, where data is read from or written to, is related to
the crossbar switch address domain. The data width may be 8, 16, or 32 bit for the MLI,
8 or 16 bit for the XMU, and 16 bit for the SSC. The type of frame may be a read or write
access or an answer frame to a read access. The Move Engines request access to the
bus via the Bus Master. The Flex Protocol Controller and the MLI may send an interrupt
to the DMA.
There are several cases:
Data Sheet
17
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
•
•
•
•
The MLI, XMU, or the SSC interfaces requests to write.
The MLI, XMU, or the SSC interfaces requests to read.
The FlexRay Communication Controller requests to write.
A general peripheral beside the FlexRay Communication Controller requests to read.
Half-word (16-bit) accesses, read and write, are only allowed for half-word aligned
addresses (even addresses). Therefore if doing a half-word (16-bit) access, the least
significant address bit (A0) is ignored (assumed to be to 0) by the modules of the SAKCIC310-OSMX2HT. Therefore if addressing a half-word with an odd address n, a halfword is read instead from address n-1 (ignoring least significant address bit:
n AND FFFF FFFEH).
Word accesses (32-bit), read and write, are only allowed for word aligned addresses
(addresses modulo 4 = 0). Therefore if doing a word (32-bit) access, the two least
significant address bits (A0 and A1) are ignored (assumed to be to 0) by the modules of
the SAK-CIC310-OSMX2HT. Therefore if addressing a word with an address n
(n modulo 4 = {1,2,3}), a word is read instead from address (n AND FFFF FFFCH)
(ignoring the two least significant address bits).
Data Sheet
18
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
3.2
Pin Definition and Functions
To enable a clean power-up, the majority of pins have a “enable pad supply” (ENPS)
function. This ENPS is pad supply (VDDP) driven. So only if the pad supply and the core
supply is stable, the output pads may be activated. Four pins do no support ENPS:
JTAGEN, PORST, XTAL1, and XTAL2. In case of a low voltage signal at the input port
ENPS (PORST) the output port PAD activates the weak pull-up and disables the output
driver independent of the port direction. In case of a high voltage signal at the input port
ENPS (PORST) the bidirectional platform pads operate in normal mode.
3.2.1
Package Outline
P 2 .0/B C 0
P 2 .1/A 1
P 0 .8/TR S T/S R 8/A 1 2
P1 .12 /D 12/S R 7
P 1 .13 /D 1 3/SR 6
VD D
V S SP / V SS B / V SS
V DD P
P 1 .14 /D 1 4/SR 5
P 1 .15 /D 1 5/SR 4
P 2 .2/A 2
P 2 .3/A 3
P 2 .4/A 4
P 2 .5/A 5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P 0 .11 /B GT/R R E AD Y C /S R 10 /T D I
P 0 .7/B GE A/TR E AD Y C /SR 13 /TM S
The package outline and the signals of the pins are summarized in Figure 7.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SAK-CIC310OSMX2HT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PORST
JTAGEN
P0.12/MODE0/SR9
P2.14/BC1/TREADYB
P1.0/D0/TVALIDB
P1.1/D1/TCLK
VSSP / VSSB
VDDP
P1.2/D2/TDATA/SCLK
P1.3/D3/RREADYB/RDY
P1.4/D4/RVALIDB/SLS
P1.5/D5/RCLKB/MRST/DIR
P1.6/D6/RDATAB/MTSR
P1.7/D7/Mode1
P2.15/RD
P2.6/A6
D DP
Figure 7
Data Sheet
P1.9 /D 9/S R 1
P1.8 /D 8/S R 0
P 2 .7/A 7
P0 .13 /W A IT
P 2 .12/B YP AS S /C S FP I
P 2.13/W R
P 0.9/A R M /S R 12
P2.1 1/A 11
P2.1 0/A 10
P 2 .9/A 9
P 2.8/A 8
P1 .11 /D 11 /S R 3
P 1.10 /D 1 0/S R 2
V DD
V SS P / V S S B / V SS
V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P0.0/TXENB/TVALIDC/TDO
P0.1/TXENA/RVALIDC/TCK
P0.4/RXDB/RDATAC
P0.5/RXDA/RCKLC
P0.2/TXDB/TDATA
P0.3/TXDA/TCLK
VDDP
VSSP / VSSB
VSSAPLL
VDDAPLL / VDDOSC
VSSOSC / VSSPOSC
XTAL1
XTAL2
VDDPOSC
P0.6/BGEB/SR14
P0.10/MT/SR11
MC_IFLEX_PIN64
SAK-CIC310-OSMX2HT Pinning: PG-TQFP-64 Package (top view)
19
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
3.2.2
Pin Description
Table 2
Pin Definitions and Functions
Symbol
Pin
I/O
Function
1
I/O
Port 0 line 0
FlexRay Transmit Enable
(Channel B)
JTAG Module Serial Data Output
JTAG Enable Mode only
MLI Transmit Channel Valid Output
TXENA/
2
RVALIDC/
TCK
I/O
Port 0 line 1
FlexRay Transmit Enable
(Channel A)
JTAG Module Clock Input (TCK)
JTAG Enable Mode only
MLI Receive Channel Valid Input C
RXDB/
RCLKC
3
I
Port 0 line 4
FlexRay Data Receiver Input
(Channel B)
MLI Receive Channel Clock Input C
RXDA/
RDATAC
4
I
Port 0 line 5
FlexRay Data Receiver Input
(Channel A)
MLI Receive Channel Data Input C
TXDB/
TCLK
5
I/O
Port 0 line 2
FlexRay Data Transmitter Output
(Channel B)
MLI Transmit Channel Clock Output
TXDA/
TDATA
6
I/O
Port 0 line 3
FlexRay Data Transmitter Output
(Channel A)
MLI Transmit Channel Data Output
PGTQFP-64
FlexRay Bus Interface
TXENB/
TVALIDC/
TDO
Data Sheet
20
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
BGEB/
SR14
15
I
Port 0 line 6
FlexRay Bus Guardian Enable
(Channel B)
Interrupt Request input line 14
The logic 0 level at this pin indicates an interrupt request
from the external host device.
MT/
SR11
16
I/O
Port 0 line 10
FlexRay Bus Guardian Macro Tick
FlexRay corrected Macro Tick Clock
Interrupt Request Input/Output line 11
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
ARM/
SR12
17
I/O
Port 0 line 9
FlexRay Bus Guardian Arm Signal
Indicates the begin of a communication cycle to the bus
guardian.
Interrupt Request Input/Output line 12
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
I
Port 0 line 7
FlexRay Bus Guardian Enable
(Channel A)
JTAG Module State Machine Control Input
JTAG Enable Mode only
Interrupt Request input line 13
The logic 0 level at this pin indicates an interrupt request
from the external host device.
MLI Transmit Channel Ready Input C
BGEA/
63
TMS/
SR13/
TREADYC
Data Sheet
21
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
I/O
Port 0 line 11
FlexRay Bus Guardian Tick
Used by the Macro Tick Watchdog of the Bus Guardian
as Time Base
JTAG Module Serial Data Input
JTAG Enable Mode only.
Interrupt Request Input/Output line 10
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
MLI Receive Channel Ready Output C
BC[1]/
45
TREADYB
I
Port 2 line 14
MODE = 00B:
XMU Byte control line 1
Controls the byte access to corresponding byte location
D[15:8]
MODE = 01B:
MLI Transmit Channel Ready Input B
MODE = 10B:
XMU Byte control line 1
Controls the byte access to corresponding byte location
D[15:8]
MODE = 11B:
Port 2 line 14
(input only)
D0/
TVALIDB
I/O
Port 1 line 0
MODE = 00B:
XMU Data bus Line 0
MODE = 01B:
MLI Transmit Channel Valid Output
MODE = 10B:
XMU Data Bus line 0
MODE = 11B:
Port 1 line 0 (Input/Output)
PGTQFP-64
BGT/
64
TDI/
SR10/
RREADYC
Host Interfaces
Data Sheet
44
22
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
D1/
TCLK
43
I/O
Port 1 line 1
MODE = 00B:
XMU Data Bus Line 1
MODE = 01B:
MLI Transmit Channel Clock Output
MODE = 10B:
XMU Data Bus Line 1
MODE = 11B:
Port 1 line 1 (Input/Output)
D2/
TDATA/
SCLK
40
I/O
Port 1 line 2
MODE = 00B:
XMU Data Bus Line 2
MODE = 01B:
MLI Transmit Channel Data Output
MODE = 10B:
XMU Data Bus Line 2
MODE = 11B:
SSC Serial Channel Clock (Input/Output)
D3/
39
RREADYB
/
RDY
I/O
Port 1 line 3
MODE = 00B:
XMU Data Bus Line 3
MODE = 01B:
MLI Receive Channel Ready Output B
MODE = 10B:
XMU Data Bus Line 3
MODE = 11B:
SSC Ready Signal (Output)
Output signal indicating that the standalone device is
ready for data transfer.
Data Sheet
23
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
D4/
38
RVALIDB/
SLS
I/O
Port 1 line 4
MODE = 00B:
XMU Data Bus Line 4
MODE = 01B:
MLI Receive Channel Valid Input B
MODE = 10B:
XMU Data Bus Line 4
MODE = 11B:
SSC Select Slave
Input used to enable SSC action when active.
D5/
RCLKB/
MRST/
DIR
37
I/O
Port 1 line 5
MODE = 00B:
XMU Data Bus Line 5
MODE = 01B:
MLI Receive Channel Clock Input B
MODE = 10B:
XMU Data Bus Line 5
MODE = 11B:
SPI Master Receive Slave Transmit
Serial data output
Alternative:
Direction of SPI Half-Duplex communication.
D6/
RDATAB/
MTSR/
MRST
36
I/O
Port 1 line 6
MODE = 00B:
XMU Data Bus Line 6
MODE = 01B:
MLI Receive Channel Data Input B
MODE = 10B:
XMU Data Bus Line 6
MODE = 11B:
SPI Master Transmit Slave Receive
Serial data input
SPI Slave Transmit Master Receive
Serial data input (half duplex mode)
PGTQFP-64
Data Sheet
24
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
Parallel Host Interface
BC[0]
62
I
Port 2 line 0
MODE = 00B:
XMU Byte control line 0
Controls the byte access to corresponding byte location
D[7:0]
MODE = 01B:
Port 2 line 0
MODE = 10B:
XMU Byte control line 0
Controls the byte access to corresponding byte location
D[7:0]
MODE = 11B:
Port 2 line 0
A[1]
61
I
Port 2 line 1
MODE = 00B:
XMU Address bus line 1
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 1
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 1
Data Sheet
25
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
A[2]
52
I
Port 2 line 2
MODE = 00B:
XMU Address bus line 2
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 2
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 2
A[3]
51
I
Port 2 line 3
MODE = 00B:
XMU Address bus line 3
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 3
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 3
Data Sheet
26
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
A[4]
50
I
Port 2 line 4
MODE = 00B:
XMU Address bus line 4
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 4
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 4
A[5]
49
I
Port 2 line 5
MODE = 00B:
XMU Address bus line 5
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 5
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 5
Data Sheet
27
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
A[6]
33
I
Port 2 line 6
MODE = 00B:
XMU Address bus line 6
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 6
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 6
A[7]
29
I
Port 2 line 7
MODE = 00B:
XMU Address bus line 7
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 7
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 7
Data Sheet
28
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IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
A[8]
21
I
Port 2 line 8
MODE = 00B:
XMU Address bus line 8
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 8
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 8
A[9]
20
I
Port 2 line 9
MODE = 00B:
XMU Address bus line 9
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 9
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 9
Data Sheet
29
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
A[10]
19
I
Port 2 line 10
MODE = 00B:
XMU Address bus line 9
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 1
MODE = 10B:
XMU Address bus line 10
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 9
A[11]
18
I
Port 2 line 11
MODE = 00B:
XMU Address bus line 11
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 2 line 11
MODE = 10B:
XMU Address bus line 11
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 2 line 11
Data Sheet
30
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IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
D8/
SR0
28
I/0
Port 1 line 8
MODE = 00B:
XMU Data bus Line 8
MODE = 01B:
Port 1 line 8 (Input/Output)
MODE = 10B:
XMU Data Bus line 8
MODE = 11B:
Port 1 line 8 (Input/Output)
Alternative:
Interrupt Request Input/Output line 0
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
D9/
SR1
27
I/0
Port 1 line 9
MODE = 00B:
XMU Data bus Line 9
MODE = 01B:
Port 1 line 9 (Input/Output)
MODE = 10B:
XMU Data Bus line 9
MODE = 11B:
Port 1 line 9 (Input/Output)
Alternative:
Interrupt Request Input/Output line 1
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
Data Sheet
31
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IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
D10/
SR2
23
I/0
Port 1 line 10
MODE = 00B:
XMU Data bus Line 10
MODE = 01B:
Port 1 line 10 (Input/Output)
MODE = 10B:
XMU Data Bus line 10
MODE = 11B:
Port 1 line 10 (Input/Output)
Alternative:
Interrupt Request Input/Output line 2
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
D11/
SR3
22
I/0
Port 1 line 11
MODE = 00B:
XMU Data bus Line 11
MODE = 01B:
Port 1 line 11 (Input/Output)
MODE = 10B:
XMU Data Bus line 11
MODE = 11B:
Port 1 line 11 (Input/Output)
Alternative:
Interrupt Request Input/Output line 3
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
Data Sheet
32
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IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
D12/
SR7
59
I/0
Port 1 line 12
MODE = 00B:
XMU Data bus Line 12
MODE = 01B:
12 (Input/Output)
MODE = 10B:
XMU Data Bus line 12
MODE = 11B:
Port 1 line 12 (Input/Output)
Alternative:
Interrupt Request Input/Output line 7
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
D13/
SR6
58
I/0
Port 1 line 13
MODE = 00B:
XMU Data bus Line 13
MODE = 01B:
Port 1 line 13 (Input/Output)
MODE = 10B:
XMU Data Bus line 13
MODE = 11B:
Port 1 line 13 (Input/Output)
Alternative:
Interrupt Request Input/Output line 6
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
Data Sheet
33
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IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
D14/
SR5
54
I/0
Port 1 line 14
MODE = 00B:
XMU Data bus Line 14
MODE = 01B:
Port 1 line 14 (Input/Output)
MODE = 10B:
XMU Data Bus line 14
MODE = 11B:
Port 1 line 14 (Input/Output)
Alternative:
Interrupt Request Input/Output line 5
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
D15/
SR4
53
I/0
Port 1 line 15
MODE = 00B:
XMU Data bus Line 15
MODE = 01B:
Port 1 line 15 (Input/Output)
MODE = 10B:
XMU Data Bus line 15
MODE = 11B:
Port 1 line 15 (Input/Output)
Alternative:
Interrupt Request Input/Output line 4
The logic 0 level at this pin indicates an interrupt request
from/to the external host device.
RD
34
I
Port 2 line 15
MODE = 00B:
XMU Read control line
Active during read operation
MODE = 01B:
Port 2 line 15
MODE = 10B:
XMU Read control line
Active during read operation
MODE = 11B:
Port 2 line 15
Data Sheet
34
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
WR
32
I
Port 2 line 13
MODE = 00B:
XMU Write control line
Active during write operation input line
MODE = 01B:
Port 2 line 13
MODE = 10B:
XMU Write control line
Active during write operation input line
MODE = 11B:
Port 2 line 13
WAIT
30
I/O
Port 0 line 13
MODE = 00B:
XMU Wait output
MODE = 01B:
Port 0 line 13
MODE = 10B:
XMU Wait output
MODE = 11B:
Port 0 line 13
Control Signals
PORST
48
I
Power-on Reset
JTAGEN
47
I
JTAG Enabled Mode Selection/
Pin JTAGEN selects whether JTAG Enabled Mode is
used to access the SAK-CIC310-OSMX2HT device.
JTAGEN = 0B: JTAG Enabled Mode
JTAGEN = 1B: Normal Mode
Data Sheet
35
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IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
I/O
Port 0 line 8
Interrupt Request Input/Output Line 8
The logic 0 level at this pin indicates an interrupt request
to/from the external host device.
MODE = 00B:
XMU Address bus line 12
The XMU Address Bus Lines serve as external address
bus
MODE = 01B:
Port 0 line 8 or
Interrupt Request Input/Output Line 8
The logic 0 level at this pin indicates an interrupt request
to/from the external host device.
MODE = 10B:
XMU Address bus line 12
The XMU Address Bus Lines serve as external address
bus
MODE = 11B:
Port 0 line 8 or
Interrupt Request Input/Output Line 8
The logic 0 level at this pin indicates an interrupt request
to/from the external host device.
PGTQFP-64
TRST/
SR8/
A[12]
60
Test Reset
(JTAG Enable Mode)
Data Sheet
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SAK-CIC310-OSMX2HT
General Device Information
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin
I/O
Function
I/O
Port 0 line 12
Interface Selection 0
Pin MODE 0 selects if the on-chip serial Host
Communication Links (MLI or SSC) or the parallel XMU
Host Communication Link is enabled for communicating
to the SAK-CIC310-OSMX2HT device.
MODE 0 = 0B: On-chip XMU
MODE 0 = 1B: On-chip SSC or MLI
After latching the initial state with the rising edge of the
PORST signal (e.g. external pull-up or pull-down
resistors), this MODE 0 pin can be used as: Interrupt
Request Input/Output Line 9
The logic 0 level at this pin indicates an interrupt request
to/from the external host device.
PGTQFP-64
MODE[0]/
SR91)
Data Sheet
462)
37
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IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
I/O
Port 1 line 7
MODE = 00B:
XMU Data Bus Line 7
MODE = 01B:
Interface Selection 1
Pin MODE 1 selects if the on-chip serial MLI
Communication Link or the serial SPI Host
Communication Link is enabled for communicating to the
SAK-CIC310-OSMX2HT device if Mode[0] = 1.
MODE[0]= 1 AND MODE[1] = 0B: On-chip MLI
MODE[0]= 1 AND MODE[1]= 1B: On-chip SSC
After latching the initial state with the rising edge of the
PORST signal (e.g. external pull-up or pull-down
resistors), this MODE 1 pin can be used as standard IO
pin.
MODE = 10B:
XMU Data Bus Line 7
Active during write operation input line
MODE = 11B:
Interface Selection 1
Pin MODE 1 selects if the on-chip serial MLI
Communication Link or the serial SPI Host
Communication Link is enabled for communicating to the
SAK-CIC310-OSMX2HT device if Mode[0] = 1.
MODE[0]= 1 AND MODE[1] = 0B: On-chip MLI
MODE[0]= 1 AND MODE[1]= 1B: On-chip SSC
After latching the initial state with the rising edge of the
PORST signal (e.g. external pull-up or pull-down
resistors), this MODE 1 pin can be used as standard IO
pin.
PGTQFP-64
D7/
Mode[1]3)
Data Sheet
35
38
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IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
I
Port 2 line 12
With the rising edge of the PORST the BYPASS signal is
sampled:
0
The oscillator circuitry is bypassed and fosc is
directly derived from XTAL1 (OSCCON.OSCBY is
set to 1).
1
In normal operating mode the oscillator is running
and fosc is derived from the crystal or from an
external clock signal (OSCCON.OSCBY is set to
0).
After latching the initial state with the rising edge of the
PORST signal (e.g. external pull-up or pull-down
resistors), this BYPASS pin can be used as standard
Input pin as described following:
MODE = 00B:
XMU Chip Select
MODE = 01B:
Port 2 Line 12 (Input)
MODE = 10B:
XMU Chip Select
MODE = 11B:
Port 2 Line 12 (Input)
PGTQFP-64
BYPASS
CSFPI4)
31
VDDP
7, 26, 41, +3.3 Power Supply, supply for IO pads
55
V
VSSP5)
8,25,425
6
0V
Ground, for IO pads
VSSB5)
8,25,425
6
0V
Ground, for Bulk Contact
VDDAPLL5)
10
+1.5 Power Supply, supply for analogue PLL circuitries
V
VSSAPLL
VDDOSC5)
9
0V
10
+1.5 Power Supply, supply for oscillator
V
VSSOSC5)
VSSPOSC5)
11
0V
Ground, for oscillator
11
0V
Ground, for oscillator pad
Data Sheet
Ground, for analogue PLL circuitries
39
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IFLEX
SAK-CIC310-OSMX2HT
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol
Pin
I/O
Function
PGTQFP-64
VDDPOSC
14
+3.3 Power Supply, supply for oscillator pad
V
VDD
24, 57
+1.5 Power Supply, supply for digital module cores
V
VSS5)
25, 56
0V
Digital Ground, for digital module cores
XTAL1
12
I
XTAL1
Input of the inverting oscillator amplifier and input to the
internal clock generation circuit.
When the SAK-CIC310-OSMX2HT device is provided
with an external clock, XTAL1 should be driven while
XTAL2 is left unconnected.
Minimum and maximum high and low pulse width as well
as rise/fall times specified in the AC characteristics must
be respected.
XTAL2
13
O
XTAL2
Output of the inverting oscillator amplifier.
1) The initial logic state on pins MODE is latched while the PORST input is active.
2) During Reset an internal pull-up device is connected.
3) The initial logic state on pins MODE is latched while the PORST input is active.
4) The initial logic state on pin BYPASS is latched while the PORST input is active.
5) Some power supplies are multiple bonded to a common pin.
In Table 2 the signals and power lines going outside the standalone chip are
summarized. These signals are partially routed via the pad logic to the pins. The analog
signals go directly to the pins.
Figure 7 shows the pinning for a PG-TQFP-64 pin package.
Data Sheet
40
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
General Device Information
XMU
(Parallel
Interface)
TCLK
TVALIDB
TDATA
RCLKB
RREADYB
RVALIDB
RDATAB
TREADYB
INT_O[3:0]
SR[7:0]
MODE[1]
MLI
P1
Port
Control
TCK
TMS
WAIT
TREADYC
TVALIDC
RCLKC
RREADYC
RVALIDC
RDATAC
TCLK
TDATA
E-Ray
(FlexRay)
SCU
RXDA
TXDA
TXENA
RXDB
TXDB
TXENB
BGEA
BGEB
ARM
BGT
MT
MODE[0]
SR[15:8]
TRST
MODE[1]
SR[7:0]
TDI
TDO
TCK
TMS
BYPASS
PORST
JTAGEN
RD
D1/TCLK
P1.2
P1.3
D2/TDATA/SCLK
D3/RREADYB/RDY
P1.4
D4/RVALIDB/SLS
P1.5
D5/RCLKB/MRST/DIR
P1.6
D6/RDATAB/MTSR
P1.7
D7/MODE[1]
P1.8
P1.9
D8/SR0
D9/SR1
P1.10
D10/SR2
P1.11
D11/SR3
P1.12
D12/SR7
P1.13
D13/SR6
P1.14
D14/SR5
P1.15
D15/SR4
P0.0
TXENB/TVALIDC/TDO
P0.1
P0.2
TXENA/RVALIDC/TCK
TXDB/TDATA
P0.3
P0.4
TXDA/TCLK
RXDB/RDATAC
P0.5
RXDA/RCLKC
BGEB/SR14
BGEA/SR13/TREADYC /TMS
P0 P0.6
Port P0.7
Control P0.8
SR8/TRST/A12
P0.9
P0.10
P0.11
ARM/SR12
MT/SR11
BGT/SR10/RREADYC/TDI
P0.12
MODE[0]/SR9
P0.13
WAIT
TDO
TDI
A[12]
PORST
JTAGEN
VDD P
VSSP
2
VDD
4
VDDP
4
VSS
2
VSSB
4
VSSP
VSS
VSSB
XTAL1
XTAL2
VDDAPLL
VSSAPLL
VSSAPLL
VDD POSC
VSSPOSC
VDDPOSC
VSSPOSC
VDD OSC
VDDOSC
VSSOSC
Data Sheet
WR
BC[1]
P1.1
XTAL2
VDD APLL
Figure 8
CSFPI
D0/TVALIDB
XTAL1
COSC
PLL
A11
P1.0
VDD
Power
Function
A0/BC[0]
P2.15
D[15:8]
SLS
SCLK
MTSR
MRST
RDY
SSC/SPI
Pins
…
Ports
Ports P2.0
P2 P2.11
P2.12
Port
P2.13
Control P2.14
…
A[12:0]
CSFPI
WR
BC[1:0]
BYPASS
RD
WAIT
…
Modules
VSSOSC
PORTS
Pins for a PG-TQFP-64 Pin Package
41
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SAK-CIC310-OSMX2HT
General Device Information
3.2.3
Ordering Information
The ordering code for Infineon companion chip provides an exact reference to the
required product. This ordering code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery.
For the available ordering codes for the SAK-CIC310-OSMX2HT please refer to the
“Product Catalog Microcontrollers”, which summarizes all available microcontroller
variants.
This document describes the derivatives of the device.The Table 3 enumerates these
derivatives and summarizes the differences.
Table 3
SAK-CIC310-OSMX2HT Derivative Synopsis
Derivative
Ambient Temperature Range
SAK-CIC310-OSMX2HT
TA = -40oC to +125oC
Data Sheet
42
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4
Electrical Parameters
The operating range for the SAK-CIC310-OSMX2HT is defined by its electrical
parameters. For proper operation the indicated limitations must be respected when
designing a system.
4.1
General Parameters
These parameters are valid for all subsequent descriptions, unless otherwise noted.
4.1.1
Parameter Interpretation
The parameters listed on the following pages partly represent the characteristics of the
SAK-CIC310-OSMX2HT and partly its demands on the system. To aid in interpreting the
parameters easily, when evaluating them for a design, they are marked with a two-letter
abbreviation in column “Symbol”:
CC (Controller Characteristics):
Such parameters indicate Controller Characteristics which are distinctive features of the
SAK-CIC310-OSMX2HT and must be regarded for system design.
SR (System Requirements):
Such parameter indicate System Requirements which must be provided by the system
in which the SAK-CIC310-OSMX2HT is designed in.
4.1.2
Pad Driver and Input Classes Definitions
Table 4
Pad Driver and Input Classes Overview
Class Power Type
Supply
A
3.3 V
Sub
Class
LVTTL I/O,
A2
LVTTL outputs
Speed
Grade
Load Leakage Termination
1)
40 MHz 50 pF 6 µA
Series
termination
recommended
1) Values are for TJmax=150°C
Data Sheet
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.1.3
Absolute Maximum Ratings
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > related VDD or VIN < VSS) the
voltage on the related VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Table 5
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Min. Typ. Max.
Ambient temperature
Storage temperature
Junction temperature
Voltage at 1.5 V power
supply pins with respect to
Unit Notes
Conditions
TA
TST
TJ
VDD
SR -40
–
125
°C
Under Bias
SR -65
–
150
°C
–
SR -40
–
150
°C
Under Bias
SR –
–
2.25
V
–
VDDP
SR –
–
3.75
V
–
VSS1)
Voltage at 3.3 V power
supply pins with respect to
VSS2)
Voltage on any Class A input VIN
pin and dedicated input pins
with respect to VSS
Crossbar Switch Frequency
E-Ray Sampling Frequency
fSYS
fSAMPLE
-0.5 –
VDDP + 0.5 V
or
max. 3.7
Whatever is
lower
–
–
803)
MHz –
–
–
803)
MHz –
1) Applicable for VDD, VDDOSC, and VDDAPLL.
2) Applicable for VDDP.
3) The PLL jitter characteristics add to this value according to the application to the application settings. See PLL
jitter parameters.
4.1.4
Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the SAK-CIC310-OSMX2HT. All parameters specified in the following sections refer to
these operating conditions, unless otherwise noticed.
Data Sheet
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SAK-CIC310-OSMX2HT
Electrical Parameters
Table 6
Operating Conditions
Parameter
Symbol
Limit Values
Min. Typ. Max.
Digital supply voltage1)
VDD
VDDAPLL
VDDPOSC
VDDP
Unit Notes
Conditions
SR 1.42 –
1.582) V
–
SR 1.42 –
1.582) V
–
SR 3.13 –
3.473) V
–
3)
SR 3.13 –
3.47
V
For Class A
pins (3.3V±5%)
VSS
Ambient temperature under TA
SR 0
–
–
V
–
SR -40
–
+125 °C
fSYS
Short circuit current
ISC
Absolute sum of short circuit Σ|IIN|
SR –4)
–
80
MHz –
SR -5
–
+5
mA
5)
SR –
–
20
mA
See Note7)
1
mA
–
50
mA
See Note7)
Digital ground voltage
–
bias
Crossbar Frequency
currents of a pin group6)
Inactive device pin current
(VDD = 0)
IID
Absolute sum of short circuit Σ|ISC|
currents of a the device
SR -1
SR –
–
1) Digital supply voltages applied to the SAK-CIC310-OSMX2HT must be static regulated voltages which allow
a typical voltage swing of ±5%.
2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST pin low, provided the pulse duration is
less than 100µs and the accumulated summary of these pulses does not exceed 1 hour.
3) Voltage overshoot up to 4.0 V is permissible at Power-Up and PORST pin low, provided the pulse duration is
less than 100µs and the accumulated summary of these pulses does not exceed 1 hour.
4) The SAK-CIC310-OSMX2HT uses a static design, so the minimum operation frequency is 0 MHz. Due to test
time restriction no lower frequency boundary is tested, however.
5) The absolute sum of all currents (output current, overload current, short circuit current) on all digital IO pins of
a port must not exceed 20 mA. The supply voltage must remain within the specified limits.
6) pin group 0: P0.0; P0.1; P0.4; P0.5; P0.2; P0.3; P0.6; P0.10
pin group 1: P0.9; P2.11; P2.10; P2.9; P2.8; P1.11; P1.10
pin group 2: P1.9; P1.8; P2.7; P0.13; P2.12; P2.13
pin group 3: P2.6; P2.15; P1.7; P1.6; P1.5; P1.4; P1.3; P1.2
pin group 4: P1.1; P1.0; P2.14; P0.12; JTAGEN; PORST
pin group 5: P2.5; P2.4; P2.3; P2.2; P1.15; P1.14
pin group 6: P1.13; P1.12; P0.8; P2.1; P2.0; P0.7; P0.11
7) See additional document “TC1796 Pin Reliability in Overload” for overload current definitions.
Data Sheet
45
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.2
DC Parameters
These parameters are static or average values, which may be exceeded during
switching transitions (e.g. output current).
The leakage currents strongly depend on the operating temperature and the actual
voltage level at the respective pin. The maximum values given in the following tables
apply under worst case conditions.
The actual value for the leakage current can be determined by evaluating the respective
leakage derating formula using values from the actual application.
The pads of the SAK-CIC310-OSMX2HT are designed to operate in various driver
modes. The DC parameter specifications refer to the current limits given in Table 7.
4.2.1
Input/Output Characteristics
These parameters apply to the lower IO voltage area of 3.13 V ≤ VDDP ≤ 3,47 V.
Table 7
Input/Output DC-Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Typ. Max.
Unit Notes
Conditions
|IPUH| CC 10
|IPDL| CC 10
–
100
µA
–
150
µA
CIO
–
10
pF
f = 1 MHz
TA = 25 °C
V
–
Min.
General Parameters
Pull-up current1)
Pull-down
current1)
Pin capacitance1)
(Digital I/O)
CC –
VIN < VIHAmin
VIN > VILAmax
Input only Pads (VDDP = 3.13 to 3.47 V = 3.3V ±5%)
Input low voltage
class A2 pins (all
except XTAL1,
XTAL2)
VILA
SR -0.3
VDDP
Input high voltage VIHA2
class A2 pins (all
except XTAL1,
XTAL2)
SR 0.64
×VDDP
–
VILRatio /VIH1)
CC 0.53
Input hysteresis
Data Sheet
2)
0.34 ×
–
VDDP + V
Whatever is lower
–
–
–
–
HYSA CC 0.1
–
× VDDP
–
V
0.3 or
max.
3.6
46
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
Table 7
Input/Output DC-Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values
Min.
Typ. Max.
Unit Notes
Conditions
General Parameters
Input leakage
current
IOZI
CC –
±3000
±6000
–
nA
VDDP((/2)-1) < VIN
< ((VDDP/2)+1)
otherwise3)
Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V ±5%)
Output low
voltage4)
VOLA
CC –
Output high
voltage3)
VOHA
CC 2.4
Input low voltage
class A2 pins
VILA
–
0.4
V
IOL = 2 mA for strong
driver mode,
–
–
V
IOH = 2 mA for strong
driver mode,
CC VDDP
- 0.4
–
SR -0.3
0.34 ×
V
–
VDDP
VDDP
V
Whatever is lower
V
IOH = 1.4 mA for strong
driver mode,
Input high voltage VIHA
class A2 pins
SR 0.64
–
× VDDP
Ratio VIL/VIH1)
CC 0.53
+ 0.3
or
max
3.6V
–
–
Input hysteresis1)
HYSA CC 0.1
–
× VDDP
–
mV
5)
Input leakage
current Class A2
pins
IOZA24 CC –
±3000
±6000
nA
((VDDP/2)-1) < VIN
< ((VDDP/2)+1)
otherwise3)
–
–
1) Not subject to production test, verified by design/characterization.
2) Not subject to production test, verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses
switching due to external system noise.
3) Only one of these parameters is tested, the other is verified by design / characterization
4) Max. resistance between pin and next power supply pin 25 Ω for strong driver mode, (verified by design /
characterization)
5) Function verified by design, value verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot guaranteed that it suppresses
switching due to external system noise.
Data Sheet
47
V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.2.2
External Clock Drive
These parameters define the external clock supply for the SAK-CIC310-OSMX2HT. The
clock signal can be supplied either to pin XTAL1.
Table 8
Oscillator Pins Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit values
Min.
Frequency Range
Input low voltage at
XTAL11)
fOSC CC 20
VILX SR -0.2
Typ. Max.
Unit Notes
Conditions
–
40
MHz –
–
0.3 ×
V
–
VDDPOSC
VDDPOS V
–
±25
0 V < VIN < VDDPOSC
VIHX SR 0.7 ×
–
VDDPOSC
Input current at XTAL1 IIX1 CC –
–
Input high voltage at
XTAL11)
+ 0.2
µA
2)
1) If the XTAL1 pin is driven by a crystal, reaching an amplitude (peak-to-peak) of 0.3 × VDDPOSC is sufficient.
2) Not subject to production test, verified by design / characterization.
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal
supplier.
Data Sheet
48
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.2.3
Table 9
Power Supply Current
Power Supply Currents (Operating Conditions apply)
Parameter
Symbol
Values
Min. Typ. Max.
Unit Note
Conditions
PORST low current IDD_PORST CC –
at VDD
–
20
mA
The PLL running at
the base frequency
PORST low current IDDP_POR
at VDDP, and
ST
PORST high
current without any
port activity
CC –
–
4.5
mA
The PLL running at
the base frequency,
Mode[0]=0 and
Mode[1]=1
CC 25
–
80
mA
25
–
50
mA
fSAMPLE=80 MHz
fsample/fSYS = 1:1
fSAMPLE=80 MHz
fsample/fSYS = 2:1
Active mode core
supply current1)2)
IDD
Oscillator and PLL
core power supply
IDDAPLL
CC –
–
4
mA
–
Oscillator and PLL
pads power supply
IDDPOSC
CC –
–
3.5
mA
–
SR –
–
PD × RθJA –
Maximum Allowed PD
Power Dissipation3)
o
< 25 C
Worst case
TA = 125oC
1) Infineon Power Loop: all peripherals active. The power consumption of each custom application will most
probably be lower than this value, but must be evaluated separately.
2) The IDD decreases for typically 20mA if the fSAMPLE is decreased for 60 MHz, at constant TJ = 150°C, for the
Infineon Max Power Loop.
The dependency in this range is, at constant junction temperature, linear.
3) For the calculation of junction to ambient thermal resistance RTJA, see the chapter“Package and Reliability”
on Page 66.
Note: The power supply currents are not subject to production test. They are verified by
design / characterization.
Data Sheet
49
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.3
AC Characteristic Targets
These parameters describe the dynamic behavior of the SAK-CIC310-OSMX2HT.
4.3.1
Testing Waveforms
These references are used for characterization and production testing (except for pin
XTAL1).
V DDP
VSS
90%
90%
10%
10%
tR
tF
rise _ fa ll
Figure 9
Test Levels for Output Rise / Fall Times
V DDP
VDDP / 2
Test Points
VDDP / 2
V SS
mct0 4 8 8 1 _ I.vsd
Figure 10
Test Levels for Output Delay
VLoad + 0.1 V
Timing
Reference
Points
V Load - 0.1 V
V OH - 0.1 V
V OL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, but begins to float when a 100 mV
change from the loaded V OH /V OL level occurs (IOH / IOL = 20 mA).
MCA05565
Figure 11
Data Sheet
Test Levels for Output Floating / Driving
50
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SAK-CIC310-OSMX2HT
Electrical Parameters
4.3.2
Table 10
Parameter
Output Rise/Fall Times
Output Rise/Fall Times (Operating Conditions apply)
Symbol
Limit Values
Min. Typ. Max.
Unit Notes
Conditions
Class A2 Pads
Rise/fall
times
Rise/fall
time
matching
tRA2,
tFA2
CC –
–
CC 125 –
3.7
ns
7.5
7.0
18
50
140
18000
160
strong driver, sharp edge, 50 pF
strong driver, sharp edge, 100 pF
strong driver, med. edge,50 pF
strong driver, soft edge, 50 pF
medium driver, 50 pF
medium driver, 150 pF
medium driver, 20 000 pF
1)
%
1) Not subject to production test, verified by design / characterization.
Data Sheet
51
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.3.3
Power Sequencing
There is a restriction for the power sequencing of VDD and VDDP as shown in Figure 12:
VDDP must always be greater than VDD - 0.5 V. The gray area shows the valid range for
VDDP.
Power Supply Voltage
V
P
for
V
DD
P
r V DD
a fo
and
are
Val
id
V DDEB
are
a
and
VDD
(1.5V)
VDDP, VDDEBU
VDD
id
Val
DD
EBU
VDDP
(3.3V)
U
VDDP > VDD - 0.5V
Time
VDDP
(3.3V)
PORST
Time
PowerSeq_I1.vsd
Figure 12
VDDP / VDD Power Sequencing
All ground pins VSS, VSSP,VSSPLL, and VSSOSC must be externally connected to one single
star point in the system. The difference voltage between the ground pins must not
exceed 200 mV.
All power pins VDD and VDDAPLL must be externally connected to one single star point in
the system. The difference voltage between the ground pins must not exceed 100 mV.
All power pins VDDP and VDDPOSC must be externally connected to one single star point
in the system. The difference voltage between the ground pins must not exceed 100 mV.
The PORST signal must be activated at latest before any power supply voltage falls
below the levels shown on the figure below. Additionally the PORST signal should be
activated as soon as possible. The sooner the PORST signal is activated, the less time
the system operates outside of the normal operating power supply range.
Data Sheet
52
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.3.4
Power, Pad and Reset Timing
These parameters are not subject to production test. They are verified by
design/characterization.
Table 11
Power Up/Down Parameters
Parameter
Symbol
Limit Values
Unit Notes
Conditions
Min. Typ. Max.
Min. VDDP voltage to ensure
defined pad states1)
VDDPPA
–
–
V
–
Minimum VDD PORST activation
threshold
VPORST1.5 SR 1.32 –
–
V
–
CC 0.6
Minimum VDDP PORST activation VPORST3.3 SR 2.9
threshold
–
–
V
–
Oscillator start-up time2)
tOSCS
tPOA
CC –
–
10
ms
–
CC 10
–
–
ms
–
tPOR
tPOS
SR –
–
50
ms
–
SR 0
–
–
ns
–
Hold time from PORST rising
edge3)
tPOH
SR 100
–
–
ns
–
Ports inactive after any reset
active4)
tPIP
CC –
–
150
ns
–
Minimum PORST active time
after power supplies are stable at
operating levels
PORST rise time
Setup time to PORST rising
edge3)
1) This parameter is valid under assumption that PORST signal is constantly at low-level during the powerup/power-down of the VDDP.
2) tOSCS is defined from the moment when VDDPOSC = 3.13 V until the oscillations reach an amplitude at XTAL1 of
0,3*VDDPOSC. This parameter is verified by device characterization. The external oscillator circuitry must be
optimized by the customer and checked for negative resistance as recommended and specified by crystal
suppliers.
3) Applicable for input pins JTAGEN, MODE0 and MODE1 with noise suppression filter of PORST switched-on.
4) This parameter includes the delay of the analog spike filter in the PORST pad.
Data Sheet
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SAK-CIC310-OSMX2HT
Electrical Parameters
VDDP
Power Supply Voltage
VDDP
3.3V
3.13V
VDDPmin
-5%
-12%
2.9V
VPORST3.3
t
PORST
t
VDD
1.5V
VDD
1.42V
VDDmin
VPORST1.5min
1.32V
-5%
-12%
t
PORST
t
PowerDown3.3_1.5_reset_only_I1.vsd
Figure 13
Power Down/Power Loss Sequences
VDDPPA
VDDPPA
VDDP
VDDmin
VPORST1.5min
VDD
tOSCS
OSC
tPOA
tPOA
PORST
Pads
2)
Padstate
undefined
1)
2)
tpi
1) as programmed
2) Tri-state, pull device active
1)
2)
Padstate
undefined
Reset_Beh 4.vsd
Figure 14
Data Sheet
Power, Pad and Reset Timing
54
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.3.5
Input Clock Timing
Table 12
Input Clock Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Unit Notes
Typ. Max.
SR 20
−
40
MHz −
fOSC
SR 20
Input clock
bypass PLL fOSCDD SR −
frequency driving at with PLL
fOSCDD SR 20
−
40
MHz −
−
80
MHz −
−
40
MHz −
SR 0.4 × TOSCDD −
−
ns
1)2)3)
SR 0.4 × TOSCDD −
−
ns
1)2)3)
SR −
−
8
ns
1)2)3)
SR −
−
8
ns
1)2)3)
Oscillator clock
frequency
bypass PLL fOSC
with PLL
XTAL1
t1
t2
t3
t4
Input Clock high time
Input Clock low time
Input Clock rise time
Input Clock fall time
1) The clock input signal must reach the defined levels VILX and VIHX.
2) Not subject to production test, verified by design / characterization.
3) Applies to oscillator bypass mode.
Input Clock
at XTAL1
V IHX
0.5 V DD
V ILX
t1
t2
tOSCDD
Figure 15
t4
t3
Input Clock Timing .esd
Input Clock Timing
Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the
oscillator frequency is limited to a range of 20 MHz or 40 MHz.
It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimum
parameters for the oscillator operation. Please refer to the limits specified by the
crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is verified by design
only (not subject to production test).
Data Sheet
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.3.6
Phase Locked Loop (PLL)
Note: All PLL characteristics defined on this and the next page are verified by design
characterization.
Table 13
PLL Parameters (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Accumulated jitter
VCO frequency range
PLL base frequency1)
PLL lock-in time
DP
fVCO
fPLLBASE
tL
Unit Notes
Conditions
Typ. Max.
CC See Figure 16
–
–
–
–
CC 400
–
500
MHz –
CC 140
–
320
MHz –
CC –
–
200
µs
–
1) The system base frequency which is selected after reset is calculated by dividing the limit values by 16 (this
is the K factor after reset).
Data Sheet
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V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock fVCO (and with it the clock
fSYS) is constantly adjusted to the selected frequency. The relation between fVCO and fSYS
is defined by: fVCO = K × fSYS. The PLL causes a jitter of fSYS.
Figure 16 gives the jitter curve.
DP
ns
±1.45
±1.10
±0.75
fSAMPLE = 80 MHz (K = 6)
±0.35
±0.0
0
40
80
120
DP = Max. jitter
P = Number of consecutive fCPU periods
K = K-divider of PLL
Figure 16
160
200
240
oo
P
TC1705_PLL_JITT_K6
Approximated Maximum Accumulated PLL Jitter for Typical Clock
Frequencies fSAMPLE (overview)
Note: The specified PLL jitter values are valid if the capacitive load at the External Bus
Unit (XMU) is limited to CL=20 pF.
Note: The maximum peak-to-peak noise on the supply voltage pin VDDAPLL is limited to
a peak-to-peak voltage of VPP = 10mV and frequency less than 200 KHz. This
condition can be achieved by appropriate blocking of the Core Supply Voltage as
near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet
57
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.3.7
Synchronous Serial Channel (SSC) Slave Mode Timing
The following parameters define the behavior of the SAK-CIC310-OSMX2HT’s
synchronous serial communication interface.
Table 14
SSC Timing (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Limit Values
Unit Notes
Conditions
Min. Typ. Max.
Slave Mode Timing
t20
t30
t31
t21
SCLK clock period
SCLK high period
SCLK low period
MRST delay from
SCLK rising edge
SCLK falling edge
MTSR hold from
SCLK rising edge
SCLK falling edge
SLSI lead delay to
SCLK rising edge
SCLK falling edge
ns
SR 20% –
70% t20
SR 20% –
70% t20
CC 3
–
12
ns
t26 CC –
t22 SR 16
–
14
ns
–
–
ns
t23 SR 13
–
–
ns
t24 SR 122) –
–
ns
t25 CC 100 –
t27 SR 8
–
t28 SR 4
–
130
ns
–
ns
–
ns
t29 SR 12
–
14
ns
t20 SR 50
–
–
ns
1)
(CON.PO,CON.PH = 00)
(CON.PO,CON.PH = 10)
(CON.PO,CON.PH = 00)
(CON.PO,CON.PH = 10)
(CON.PO,CON.PH = 00)
(CON.PO,CON.PH = 10)
SLSI hold from RDY rising edge
DIR hold from
SCLK falling edge
SCLK rising edge
–
(CON.PO,CON.PH = 10)
RDY lead delay to SLSI falling edge
DIR lead delay to
SCLK rising edge
SCLK falling edge
–
(CON.PO, CON.PH = 00)
MRST hold from SLSI1 rising edge
MTSR setup to
SCLK rising edge
SCLK falling edge
SR 50
(CON.PO,CON.PH = 00)
(CON.PO,CON.PH = 10)
1)
(CON.PO,CON.PH = 00)
(CON.PO,CON.PH = 10)
SLSI falling edge delay to SLSI rising
edge
1) Not subject to production test, verified by design / characterization.
2) This is only valid if SSC move engine is idle (RDY = 1).
Data Sheet
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V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
t30
t20
t31
0.9 VDD
SCLK
0.1 VDD
(CON.PO, CON.PH = 00)
0.9 VDD
SCLK
(CON.PO, CON.PH = 10)
t21
t26
t21
MRST
First Data
t22
t23
Data
valid
MTSR
t24
0.1 VDD
Last Data
t22
t
23
Data
valid
t27
SLSI1
t20
t25
RDY
t28
t29
DIR
SSC_TMG_SLAVE
Figure 17
Data Sheet
SSC Slave Mode Timing
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SAK-CIC310-OSMX2HT
Electrical Parameters
4.3.8
MLI Interface Timing
The following parameters define the behavior of the SAK-CIC310-OSMX2HT’s microlink
interface.
Table 15
MLI Interface Timing (Operating Conditions apply); CL = 50 pF
Parameter
Symbol
Limit Values
Min.
Unit Notes
Conditions
Typ. Max.
CC/SR 2 × TMLI2)
–
–
ns
–
CC
20%
–
70% t40
–
CC
20%
–
70% t40
–
SR
20%
–
70% t47
–
SR
27%
–
70% t47
–
CC
–
–
25% t40
4)
CC
–
–
25% t40
4)
SR
–
–
25% t47
4)
SR
–
–
25% t47
4)
CC
-10%
–
35% t40
–
t46 SR
35%
–
–
t40
–
RVALID and RDATA setup to t46 SR
RCLK falling edge
25%
–
–
t47
–
TCLK clock period1)
TCLK high period
TCLK low period
RCLK high period
RCLK low period
TCLK rise time
3)
TCLK fall time1)
RCLK rise time
RCLK fall time
TDATA and TVALID valid
after TCLK rising edge
TREADY setup to TCLK
rising edge
t40
t41
t42
t41
t42
t43
t44
t43
t44
t45
RCLK clock period
(typically 50% duty cycle)
t47 SR
2 × TSYS = –
25
–
ns
–
RVALID and RDATA hold
from RCLK falling edge
t48 SR
45%
–
–
t47
–
RREADY valid after RCLK
falling edge
t49 CC
-10%
–
50% t47
–
1) TCLK high and low times can be minimum 1 × TMLI.
2) TMLImin = 2× TSYS = 2 × 1/fSYS. When fSYS = 80 MHz, t40 = 25 ns
3) Fastest driver strength selected.
4) Not subject to production test, verified by design / characterization.
Note: The handshake timing does not include any protocol delay times (number of TCLK
or RCLK clock periods), but only the respective hardware sampling time and setup
time windows.
Data Sheet
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V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
t43
t44
t40
t41
TCLKx
0.9 VDDP
0.1 VDDP
t42
t45
t45
TDATAx
TVALIDx
t46
TREADYx
t43
t44
t47
RCLKx
t41
0.9 VDDP
0.1 VDDP
t42
t46
t48
RDATAx
RVALIDx
t49
t49
RREADYx
MLI_Tmg
Figure 18
Data Sheet
MLI Interface Timing
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SAK-CIC310-OSMX2HT
Electrical Parameters
4.3.9
XMU External Access Timing
The following parameters define the behavior of the SAK-CIC310-OSMX2HT’s external
parallel memory interface.
Table 16
XMU External Access Timing (Operating Conditions apply), CL = 20 pF
Parameter
Symbol
Limit Values
Min.
Unit Notes
Conditions
Typ. Max.
RD delay from CSFPI falling edge t51 SR 3
–
–
ns
WR delay from CSFPI falling edge t51 SR 3
–
–
ns
t52
Address hold from RD falling edge t53
WAIT active after RD falling edge t54
WAIT active after WR falling edge t54
WAIT rising edge after RD falling t55
SR 3
–
–
ns
SR 10
–
–
ns
CC –
–
20
ns
CC –
–
20
ns
CC 11 × tSYS –
–
ns
t55
WAIT valid after RD rising edge
t56
WAIT valid after WR rising edge
t56
Data valid after WR rising edge
t56
WAIT float after CSFPI rising edge t57
Data float after CSFPI rising edge t57
WR rising edge delay from WAIT t58
CC 12 × tSYS –
–
ns
CC –
–
20
ns
1)
CC –
–
20
ns
1)
CC –
–
20
ns
1)
CC –
–
12
ns
1)
CC –
–
12
ns
1)
SR 3
–
–
ns
t59 SR 3
–
–
ns
Address setup to RD falling edge
edge
Data setup to RD falling edge
rising edge
Data, Address, and Byte Control
hold from WR rising edge
1) Not subject to production test, verified by design / characterization.
Data Sheet
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V 2.2, 2007-06
IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
R e a d T im in g
CSFPI
0 .9 V D D
0 .1 V D D
t51
RD
WR
A [1 1 :0 ]
B C [1 :0 ]
t52
A d d re ss V a lid
t54
W A IT
t53
t55
t56
D [1 5 :0 ]
D a ta V a lid
W rite T im in g (first)
t57
CSFPI
RD
WR
t51
t5 8
t59
A d d re ss V a lid
A [1 1 :0 ]
B C [1 :0 ]
D [1 5 :0 ]
t5 4
D a ta V a lid
t56
W A IT
t57
W rite T im in g (co n se cu tive )
CSFPI
RD
WR
t5 1
t5 8
t59
A d d re ss V a lid
A [1 1 :0 ]
B C [1 :0 ]
D [1 5 :0 ]
D a ta V a lid
t5 6
t5 4
W A IT
t5 7
X M U T IM IN G
Figure 19
Data Sheet
XMU External Access Timing
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.3.10
Table 17
ERAY Interface Timing
ERAY Interface Timing (Operating Conditions apply), CL = 35 pF
Parameter
Symbol
Limit Values
Min.
Typ. Max.
Unit Notes
Conditions
TxDA/TxDB Signal Timing at end of frame
Time span from
last BSS to FES
without the
influence of
external quartz
circuitry
tolerances
(d10Bit_TX))
t60
CC 997.75 –
1002.25 ns
fOSCDD = 20 MHz or
40 MHz;
CL = 35 pF;
PRT.BRP = 0;
P0_PDR.PD0 = 000B
(TxDA, TxDB)
External noise on
VDDAPLL:
Amplitude ≤ 10 mV
Frequency ≤ 200 kHz
TxD data valid
|t61 - t62| CC –
from fsample flip-flop
txd_reg ⇒
TxDA, TxDB)
(dTxAsym)1)
–
1.5
ns
Asymmetrical Delay
of rising and falling
edge
(TxDA, TxDB)
P0_PDR.PD0 = 000B
RxDA/RxDB Signal Timing at end of frame
Time span
t63
between last BSS
and FES that can
to be properly
decoded without
influence of
external quartz
circuitry
tolerances
(d10Bit_RX)
RxD capture by
fsample
SR 966.25 –
|t64 - t65| CC –
1045.97 ns
fOSCDD = 20 MHz or
40 MHz;
CL = 35 pF
PRT.BRP = 0;
PRT.SPP = 0
(RxDA, RxDB)
External noise on
VDDAPLL:
Amplitude ≤ 10 mV
Frequency ≤ 200 kHz
–
3.5
(RxDA/RxDB ⇒
sampling flip-flop)
(dRxAsym)1)
ns
Asymmetrical Delay
of rising and falling
edge
(RxDA, RxDB)
1) Not subject to production test, verified by design/characterization.
Data Sheet
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
Last CRC Byte
BSS
(Byte Start Sequence)
FES
(Frame End Sequence)
0.7 VDD
0.3 VDD
TXD
t60
tsample
TXD
0.9 VDD
t61
t62
Last CRC Byte
BSS
(Byte Start Sequence)
0.1 VDD
FES
(Frame End Sequence)
0.7 VDD
0.3 VDD
RXD
t63
tsample
RXD
0.9 VDD
t64
Figure 20
Data Sheet
t65
0.1 VDD
ERAY_TIMING
ERAY Timing
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SAK-CIC310-OSMX2HT
Electrical Parameters
4.4
Package and Reliability
4.4.1
Package Parameters (PG-TQFP-64)
Table 18
Thermal Characteristics of the Package
Parameter
Symbol
Thermal resistance junction case
top1)
RθJCTop CC –
Unit Note
Conditions
Min. Typ. Max.
Thermal resistance junction leads1) RθJLeads CC –
Values
17.1 K/W –
39
K/W –
1) The thermal resistances from the case top and the lead to the ambient (RΘCTA, RΘLA) are to be combined with
the thermal resistances between the junction and the case/leads given above (RΘJCTop, RΘJLeads), in order to
calculate the total thermal resistance between the junction and the ambient (RΘJA).
The thermal resistances between the case/leads and the ambient (RΘCTA, RΘLA) as well as the method of
combination/calculation depend on the external system (PCB, case) characteristics, and are under user
responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RΘJA × PD,
where the RΘJA is the total thermal resistance between the junction and the ambient. This total junction ambient
resistance RΘJA can be obtained from the upper four partial thermal resistances.
4.4.2
Package Outline
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products.
Figure 21
Data Sheet
Package Outlines PG-TQFP-64, Plastic Green Thin profile Quad Flat
Package
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.4.3
Table 19
Quality Declarations
Quality Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min. Typ. Max.
Operation
Lifetime1)2)
tOP
–
–
24000 hours at average weighted junction
temperature Tj = 127oC
–
–
66000 hours at average weighted junction
temperature Tj = 100oC
–
–
20
years at average weighted junction
temperature Tj = 85oC
ESD susceptibility VHBM
according to
Human Body
Model (HBM)
–
–
2000
V
Conforming to
EIA/JESD22-A114-B
ESD susceptibility VSDM
according to
Soldered Device
Model (SDM)
–
–
1000
V
Conforming to
EOS/ESD-DS5.3-1993
Moisture
Sensitivity Level
–
–
3
–
Conforming to Jedec
J-STD-020C for 240°C
MSL
1) This lifetime refers only to the time when the device is powered on.
2)One example of a detailed temperature profile is:
2000 hours at Tj = 150oC
16000 hours at Tj = 125oC
6000 hours at Tj = 110oC
This example is equivalent to the operation lifetime and average temperatures given in
the table.
Data Sheet
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IFLEX
SAK-CIC310-OSMX2HT
Electrical Parameters
4.4.4
Thermal Considerations
When operating the SAK-CIC310-OSMX2HT in a system, the total heat generated on
the chip must be dissipated to the ambient environment to prevent overheating and
resulting thermal damages.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” is a measure for these parameters.
The power dissipation must be limited so the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
∆T = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = Σ(VDDP × IDDP) + Σ(VDD × IDD) + (VDDAPLL × IDDAPLL) + (VDDPOSC × IDDPOSC) + (VDDOSC
× IDDOSC).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and the switching frequencies.
If the total power dissipation determined for a given system configuration exceeds the
defined limit countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, VDD, VDDPOSC, VDDOSC, and VDDAPLL if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
68
V 2.2, 2007-06
http://www.infineon.com
Published by Infineon Technologies AG
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