HI5810 TM DUCT E PRO PRODUCT T E L O OB S ITUTE SUBST 12 Data Sheet E L IB HI58 P O SS May 2001 CMOS 10 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold itle I581 bt MO 0 crod, -Bit, mng D nrter th erl ck d ld) utho ) eyrds ter- The HI5810 is a fast, low power, 12-bit, successiveapproximation, analog-to-digital converter. It can operate from a single 3V to 6V supply and typically draws just 1.9mA when operating at 5V. The HI5810 features a built-in track and hold. The conversion time is as low as 10µs with a 5V supply. The twelve data outputs feature full high speed CMOS three-state bus driver capability, and are latched and held through a full conversion cycle. The output is user selectable: [i.e., 12-bit, 8-bit (MSBs), and/or 4-bit (LSBs)]. A data ready flag, and conversion-start input complete the digital interface. An internal clock is provided and is available as an output. The clock may also be over-driven by an external source. File Number 3633.3 Features • Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µs • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 100kSPS • Built-In Track and Hold • Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V • Maximum Power Consumption . . . . . . . . . . . . . . . 40mW • Internal or External Clock • 1MHz Input Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . -3dB Applications • Remote Low Power Data Acquisition Systems • Digital Audio • DSP Modems • General Purpose DSP Front End • µP Controlled Measurement Systems Part Number Information • Process Controls PART NUMBER INL (LSB) (MAX OVER TEMP.) HI5810JIB-T ±2.5 TEMP. RANGE ( oC) PACKAGE PKG. NO. • Industrial Controls Related Literature -40 to 85 24 Ld SOIC M24.3 Tape and Reel • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” Pinout HI5810 (SOIC) TOP VIEW rpoion, minctor, D, C, sh, DRDY 1 (LSB) D0 2 24 VDD 23 OEL D1 3 22 CLK D2 4 21 STRT D3 5 20 VREF - D4 6 19 VREF+ D5 7 18 VIN D6 8 17 VAA+ D7 9 16 VAA - D8 10 15 OEM D9 11 14 D11 (MSB) VSS 1 12 13 D10 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001 HI5810 Functional Block Diagram STRT VDD TO INTERNAL LOGIC VSS VIN CONTROL AND TIMING CLOCK CLK DRDY 32C OEM VREF+ 16C D11 (MSB) 8C 50Ω SUBSTRATE D10 4C 2C D9 C D8 VAA+ VAA - 32C 64C 63 D7 16C 8C 12-BIT SUCCESSIVE APPROXIMATION REGISTER 12-BIT EDGE TRIGGERED “D” LATCHES D6 4C D5 2C D4 C P1 D3 C D2 D1 VREF D0 (LSB) OEL 2 HI5810 Absolute Maximum Ratings Thermal Information Supply Voltage VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V VAA+ to VAA- . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V) VAA+ to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V Analog and Reference Inputs VIN, VREF+, VREF - . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V) Digital I/O Pins . . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V) Thermal Resistance (Typical, Note 1) θJA ( oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 1.5MHz, Unless Otherwise Specified 25oC PARAMETER -40oC TO 85oC MIN TYP MAX MIN MAX UNITS 12 - - 12 - Bits Integral Linearity Error, INL (End Point) - - ±2.5 - ±2.5 LSB Differential Linearity Error, DNL - - ±2.0 - ±2.0 LSB Gain Error, FSE (Adjustable to Zero) - - ±3.5 - ±3.5 LSB Offset Error, VOS (Adjustable to Zero) - - ±2.5 - ±2.5 LSB fS = Internal Clock, fIN = 1kHz fS = 1.5MHz, fIN = 1kHz - 68.8 62.1 - - - dB dB fS = Internal Clock, fIN = 1kHz fS = 1.5MHz, fIN = 1kHz - 70.5 63.2 - - - dB dB Total Harmonic Distortion, THD fS = Internal Clock, fIN = 1kHz fS = 1.5MHz, fIN = 1kHz - -73.9 -68.4 - - - dBc dBc Spurious Free Dynamic Range, SFDR fS = Internal Clock, fIN = 1kHz fS = 1.5MHz, fIN = 1kHz - 75.4 69.2 - - - dB dB Input Current, Dynamic At VIN = VREF+, 0V - ±125 ±150 - ±150 µA Input Current, Static Conversion Stopped - ±0.6 ±10 - ±10 µA Input Bandwidth -3dB - 1 - - - MHz Reference Input Current - 160 - - - µA TEST CONDITIONS ACCURACY Resolution DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD RMS Signal RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal RMS Noise ANALOG INPUT Input Series Resistance, RS In Series with Input CSAMPLE - 420 - - - W Input Capacitance, C SAMPLE During Sample State - 380 - - - pF Input Capacitance, C HOLD During Hold State - 20 - - - pF 3 HI5810 Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 1.5MHz, Unless Otherwise Specified (Continued) 25oC PARAMETER -40oC TO 85oC MIN TYP MAX MIN MAX UNITS High-Level Input Voltage, VIH 2.4 - - 2.4 - V Low-Level Input Voltage, VIL - - 0.8 - 0.8 V - - ±10 - ±10 µA - 10 - - - pF 4.6 - - 4.6 - V TEST CONDITIONS DIGITAL INPUTS OEL, OEM, STRT Except CLK, VIN = 0V, 5V Input Leakage Current, IIL Input Capacitance, C IN DIGITAL OUTPUTS High-Level Output Voltage, VOH ISOURCE = -400µA Low-Level Output Voltage, VOL ISINK = 1.6mA - - 0.4 - 0.4 V Three-State Leakage, IOZ Except DRDY, VOUT = 0V, 5V - - ±10 - ±10 µA Output Capacitance, COUT Except DRDY - 20 - - - pF High-Level Output Voltage, VOH ISOURCE = -100µA (Note 2) 4 - - 4 - V Low-Level Output Voltage, VOL ISINK = 100µA (Note 2) - - 1 - 1 V Input Current CLK Only, VIN = 0V, 5V - - ±5 - ±5 mA 10 - - 10 - µs Internal Clock, (CLK = Open) 200 300 400 150 500 kHz External CLK (Note 2) 0.05 - 2.0 - - MHz Clock Pulse Width, tLOW, tHIGH External CLK (Note 2) 100 - - 100 - ns Aperture Delay, tDAPR (Note 2) - 35 50 - 70 ns Clock to Data Ready Delay, tD1DRDY (Note 2) - 105 150 - 180 ns Clock to Data Ready Delay, tD2DRDY (Note 2) - 100 160 - 195 ns Start Removal Time, tRSTRT (Note 2) 75 30 - 75 - ns Start Setup Time, tSU STRT (Note 2) 85 60 - 100 - ns Start Pulse Width, tWSTRT (Note 2) 10 4 - 15 - ns Start to Data Ready Delay, tD3 DRDY (Note 2) - 65 105 - 120 ns Clock Delay from Start, tDSTRT (Note 2) - 60 - - - ns Output Enable Delay, tEN (Note 2) - 20 30 - 50 ns Output Disabled Delay, tDIS (Note 2) - 80 95 - 120 ns - 2.6 8 - 8.5 mA CLOCK TIMING Conversion Time (tCONV + tACQ) (Includes Acquisition Time) Clock Frequency POWER SUPPLY CHARACTERISTICS Supply Current, IDD + IAA NOTE: 2. Parameter guaranteed by design or characterization, not production tested. 4 HI5810 Timing Diagrams 1 5 - 14 4 3 2 15 1 2 3 CLK (EXTERNAL OR INTERNAL) tLOW tD1DRDY tHIGH STRT tD2DRDY DRDY DATA N - 1 D0 - D11 VIN DATA N HOLD N TRACK N TRACK N + 1 OEL = OEM = VSS FIGURE 1. CONTINUOUS CONVERSION MODE 15 2 2 1 2 3 4 5 CLK (EXTERNAL) tSUSTRT tRSTRT tWSTRT STRT tD3DRDY DRDY HOLD HOLD TRACK VIN FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK 15 1 3 4 5 CLK (INTERNAL) 2 tDSTRT tRSTRT tWSTRT STRT DON’T CARE tD3DRDY DRDY HOLD VIN TRACK FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK 5 HOLD HI5810 Timing Diagrams (Continued) OEL OR OEM tDIS tEN D0 - D3 OR D4 - D11 HIGH IMPEDANCE TO HIGH HIGH IMPEDANCE TO LOW 90% 50% TO OUTPUT PIN 10% 50% 1.6mA 1.6mA +2.1V 50pF +2.1V 50pF -400µA -1.6mA FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM FIGURE 5. TIMING LOAD CIRCUIT Typical Performance Curves 2.0 1.9 VDD = VAA+ = 5V, VREF+ = 4.608V, CLK = 1.5MHz VOS ERROR (LSBs) INL ERROR (LSBs) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 -50 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE (oC) 60 70 80 90 1.75 1.70 VDD = VAA+ = 5V, VREF+ = 4.608V, CLK = 1.5MHz 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) FIGURE 8. DNL vs TEMPERATURE 6 80 90 FIGURE 7. OFFSET ERROR vs TEMPERATURE FSE (LSBs) DNL ERROR (LSBs) FIGURE 6. NL vs TEMPERATURE 1.00 0.95 VDD = VAA+ = 5V, VREF + = 4.608V, CLK = 1.5MHz 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 TEMPERATURE (oC) -1.0 -1.1 VDD = VAA+ = 5V, VREF+ = 4.608V, CLK = 1.5MHz -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2.0 -2.1 -2.2 -2.3 -2.4 -2.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) FIGURE 9. FULL SCALE ERROR vs TEMPERATURE HI5810 Typical Performance Curves (Continued) 6.5 6.0 INPUT FREQUENCY = 1kHz SAMPLING RATE = 100kHz SNR = 64.92dB SINAD = 63.82dB EFFECTIVE BITS = 10.30 THD = -69.44dBc PEAK NOISE = -70.1dB SFDR = 70.1dB 5.0 AMPLITUDE (dB) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) FREQUENCY FIGURE 10. SUPPLY CURRENT vs TEMPERATURE FIGURE 11. FFT SPECTRUM 500 INTERNAL CLOCK FREQUENCY (kHz) SUPPLY CURRENT (mA) 5.5 450 VDD = VAA+ = 5V, VREF + = 4.608V 400 350 300 250 200 150 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC) FIGURE 12. INTERNAL CLOCK FREQUENCY vs TEMPERATURE 7 HI5810 TABLE 1. PIN DESCRIPTIONS PIN NO. 1 NAME DESCRIPTION DRDY Output flag signifying new data is available. Goes high at end of clock period 15. Goes low when new conversion is started. 2 D0 Bit 0 (Least Significant Bit, LSB). 3 D1 Bit 1. 4 D2 Bit 2. 5 D3 Bit 3. 6 D4 Bit 4. 7 D5 Bit 5. 8 D6 Bit 6. 9 D7 Bit 7. 10 D8 Bit 8. 11 D9 Bit 9. capacitors to VREF -. The capacitor common node, after the charges balance out, will indicate whether the input was above 1/2 of (VREF+ - VREF -). At the end of the fourth period, the comparator output is stored and the MSB capacitor is either left connected to VREF+ (if the comparator was high) or returned to VREF -. This allows the next comparison to be at either 3/4 or 1/4 of (VREF+ - VREF -). At the end of periods 5 through 14, capacitors representing D10 through D1 are tested, the result stored, and each capacitor either left at VREF+ or at VREF -. At the end of the 15th period, when the LSB (D0) capacitor is tested, (D0) and all the previous results are shifted to the output registers and drivers. The capacitors are reconnected to the input, the comparator returns to the balance state, and the data ready output goes active. The conversion cycle is now complete. 12 VSS Digital Ground, (0V). Analog Input 13 D10 Bit 10. 14 D11 Bit 11 (Most Significant Bit, MSB) 15 OEM Three-State Enable for D4-D11. Active low input. The analog input pin is a predominately capacitive load that changes between the track and hold periods of the conversion cycle. During hold, clock period 4 through 15, the input loading is leakage and stray capacitance, typically less than 5µA and 20pF. 16 VAA- Analog Ground, (0V). 17 VAA+ Analog Positive Supply. (+5V) (See text.) 18 VIN Analog Input. 19 VREF+ Reference Voltage Positive Input, sets 4095 code end of input range. 20 VREF- Reference Voltage Negative Input, sets 0 code end of input range. 21 STRT Start Conversion Input active low, recognized after end of clock period 15. 22 CLK CLK Input or Output. Conversion functions are synchronized to positive going edge (see text). 23 OEL Three-State Enable for D0 D3. Active low input. 24 VDD Digital Positive Supply (+5V). At the start of input tracking, clock period 1, some charge is dumped back to the input pin. The input source must have low enough impedance to dissipate the current spike by the end of the tracking period as shown in Figure 13. The amount of charge is dependent on supply and input voltages. The average current is also proportional to clock frequency. 20mA I IN 10mA 0mA Theory of Operation The HI5810 is a CMOS 12-bit, Analog-to-Digital Converter that uses capacitor charge balancing to successively approximate the analog input. A binarily weighted capacitor network forms the A/D heart of the device. See the block diagram for the HI5810. 5V CLK 0V 5V DRDY 0V 200ns/DIV. The capacitor network has a common node which is connected to a comparator. The second terminal of each capacitor is individually switchable to the input, VREF+ or VREF -. CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V, VIN = 4.608V, CLK = 750kHz, TA = 25oC FIGURE 13. TYPICAL ANALOG INPUT CURRENT During the first three clock periods of a conversion cycle, the switchable end of every capacitor is connected to the input and the comparator is being auto balanced at the capacitor common node. As long as these current spikes settle completely by end of the signal acquisition period, converter accuracy will be preserved. The analog input is tracked for 3 clock cycles. With an external clock of 1.5MHz the track period is 2µs. During the fourth period, all capacitors are disconnected from the input; the one representing the MSB (D11) is connected to the VREF+ terminal; and the remaining A simplified analog input model is presented in Figure 14. During tracking, the A/D input (VIN ) typically appears as a 380pF capacitor being charged through a 420Ω internal 8 HI5810 switch resistance. The time constant is 160ns. To charge this capacitor from an external “zero Ω” source to 0.5 LSB (1/8192), the charging time must be at least 9 time constants or 1.4µs. The maximum source impedance (RSOURCE Max) for a 2µs acquisition time settling to within 0.5 LSB is 164Ω. If the clock frequency was slower, or the converter was not restarted immediately (causing a longer sample time), a higher source impedance could be tolerated. VIN RSW ≈ 420Ω CSAMPLE ≈ 380pF RSOURCE -tACQ - RSW RSOURCE (MAX) = CSAMPLE ln [2-(N + 1)] FIGURE 14. ANALOG INPUT MODEL IN TRACK MODE Reference Input The reference input VREF+ should be driven from a low impedance source and be well decoupled. As shown in Figure 15, current spikes are generated on the reference pin during each bit test of the successive approximation part of the conversion cycle as the charge balancing capacitors are switched between VREF - and VREF+ (clock periods 5 - 14). These current spikes must settle completely during each bit test of the conversion to not degrade the accuracy of the converter. Therefore VREF+ and VREF - should be well bypassed. Reference input VREF is normally connected directly to the analog ground plane. If VREF- is biased for nulling the converters offset it must be stable during the conversion cycle. Control Signal The HI5810 may be synchronized from an external source by using the STRT (Start Conversion) input to initiate conversion, or if STRT is tied low, may be allowed to free run. Each conversion cycle takes 15 clock periods. The input is tracked from clock period 1 through period 3, then disconnected as the successive approximation takes place. After the start of the next period 1 (specified by tD data), the output is updated. The DRDY (Data Ready) status output goes high (specified by tD1DRDY) after the start of clock period 1, and returns low (specified by tD2DRDY) after the start of clock period 2. The 12 data bits are available in parallel on three-state bus driver outputs. When low, the OEM input enables the most significant byte (D4 through D11) while the OEL input enables the four least significant bits (D0 - D3). tEN and tDIS specify the output enable and disable times. When STRT input is used to initiate conversions, operation is slightly different depending on whether an internal or external clock is used. Figure 3 illustrates operation with an internal clock. If the STRT signal is removed (at least tR STRT) before clock period 1, and is not reapplied during that period, the clock will shut off after entering period 2. The input will continue to track and the DRDY output will remain high during this time. 5V 0V DRDY Full scale and offset error can also be adjusted to zero in the signal conditioning amplifier driving the analog input (VIN). 10mA 0mA CLK The VREF+ and VREF - pins reference the two ends of the analog input range and may be used for offset and full scale adjustments. In a typical system the VREF- might be returned to a clean ground, and the offset adjustment done on an input amplifier. VREF+ would then be adjusted to null out the full scale error. When this is not possible, the VREF - input can be adjusted to null the offset error, however, VREF - must be well decoupled. If the output data is to be latched externally, either the trailing edge of data ready or the next falling edge of the clock after data ready goes high can be used. 20mA IREF+ accuracy is of utmost importance full scale and offset errors may be adjusted to zero. 5V 0V 2µs/DIV. CONDITIONS: V DD = VAA+ = 5.0V, VREF+ = 4.608V, VIN = 2.3V, CLK = 750kHz, TA = 25oC FIGURE 15. TYPICAL REFERENCE INPUT CURRENT The HI5810 is specified with a 4.608V reference, however, it will operate with a reference down to 3V having a slight degradation in performance. Full Scale and Offset Adjustment In many applications the accuracy of the HI5810 would be sufficient without any adjustments. In applications where 9 A low signal applied to STRT (at least tWSTRT wide) can now initiate a new conversion. The STRT signal (after a delay of (tD STRT)) causes the clock to restart. Depending on how long the clock was shut off, the low portion of clock period 2 may be longer than during the remaining cycles. The input will continue to track until the end of period 3, the same as when free running. HI5810 Figure 2 illustrates the same operation as above but with an external clock. If STRT is removed (at least tRSTRT) before clock period 2, a low signal applied to STRT will drop the DRDY flag as before, and with the first positive going clock edge that meets the (tSUSTRT) setup time, the converter will continue with clock period 3. Clock The HI5810 can operate either from its internal clock or from one externally supplied. The CLK pin functions either as the clock output or input. All converter functions are synchronized with the rising edge of the clock signal. Figure 16 shows the configuration of the internal clock. The clock output drive is low power: if used as an output, it should not have more than 1 CMOS gate load applied, and stray wiring capacitance should be kept to a minimum. The internal clock will shut down if the A/D is not restarted after a conversion. The clock could also be shut down with an open collector driver applied to the CLK pin. This should only be done during the sample portion (the first three clock periods) of a conversion cycle, and might be useful for using the device as a digital sample and hold. If an external clock is supplied to the CLK pin, it must have sufficient drive to overcome the internal clock source. The external clock can be shut off, but again, only during the sample portion of a conversion cycle. At other times, it must be above the minimum frequency shown in the specifications. In the above two cases, a further restriction applies in that the clock should not be shut off during the third sample period for more than 1ms. This might cause an internal charge pump voltage to decay. If the internal or external clock was shut off during the conversion time (clock cycles 4 through 15) of the A/D, the output might be invalid due to balancing capacitor droop. An external clock must also meet the minimum tLOW and tHIGH times shown in the specifications. A violation may cause an internal miscount and invalidate the results. INTERNAL ENABLE Except for VAA+, which is a substrate connection to VDD , all pins have protection diodes connected to VDD and VSS . Input transients above VDD or below VSS will get steered to the digital supplies. The VAA+ and VAA- terminals supply the charge balancing comparator only. Because the comparator is autobalanced between conversions, it has good low frequency supply rejection. It does not reject well at high frequencies however; VAA- should be returned to a clean analog ground and VAA+ should be RC decoupled from the digital supply as shown in Figure 17. There is approximately 50Ω of substrate impedance between VDD and VAA+. This can be used, for example, as part of a low pass RC filter to attenuate switching supply noise. A 10µF capacitor from VAA+ to ground would attenuate 30kHz noise by approximately 40dB. Note that back-to-back diodes should be placed from VDD to VAA+ to handle supply to capacitor turn-on or turn-off current spikes. Dynamic Performance Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the A/D. A low distortion sine wave is applied to the input of the A/D converter. The input is sampled by the A/D and its output stored in RAM. The data is than transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THD. See Typical Performance Characteristics. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured RMS signal to RMS sum of noise at a specified input and sampling frequency. The noise is the RMS sum of all except the fundamental and the first five harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR = (6.02N + 1.76)dB. For an ideal 12-bit converter the SNR is 74dB. Differential and integral linearity errors will degrade SNR. Sinewave Signal Power SNR = 10 Log Total Noise Power CLOCK CLK Signal-To-Noise + Distortion Ratio OPTIONAL EXTERNAL CLOCK 100kΩ 18pF FIGURE 16. INTERNAL CLOCK CIRCUITRY Power Supplies and Grounding VDD and VSS are the digital supply pins: they power all internal logic and the output drivers. Because the output drivers can cause fast current spikes in the VDD and VSS lines, VSS should have a low impedance path to digital ground and VDD should be well bypassed. 10 SINAD is the measured RMS signal to RMS sum of noise plus harmonic power and is expressed by the following. SINAD = 10 Log Sinewave Signal Power Noise + Harmonic Power (2nd - 6th) Effective Number of Bits The effective number of bits (ENOB) is derived from the SINAD data; ENOB = SINAD - 1.76 6.02 HI5810 Total Harmonic Distortion Spurious-Free Dynamic Range The total harmonic distortion (THD) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. The spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. THD = 10Log Total Harmonic Power (2nd - 6th Harmonic) SFDR = 10Log Sinewave Signal Power Sinewave Signal Power Highest Spurious Signal Power TABLE 2. CODE TABLE BINARY OUTPUT CODE INPUT VOLTAGE † VREF+ = 4.608V VREF - = 0V (V) DECIMAL COUNT Full Scale (FS) 4.6069 FS - 1 LSB CODE DESCRIPTION MSB LSB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 4095 1 1 1 1 1 1 1 1 1 1 1 1 4.6058 4094 1 1 1 1 1 1 1 1 1 1 1 0 3/ FS 4 1/ FS 2 1/ FS 4 3.4560 3072 1 1 0 0 0 0 0 0 0 0 0 0 2.3040 2048 1 0 0 0 0 0 0 0 0 0 0 0 1.1520 1024 0 1 0 0 0 0 0 0 0 0 0 0 1 LSB 0.001125 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Zero †The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage. +5V 0.1µF 10µF 0.1µF 0.01µF VAA+ VREF VDD D11 . . . D0 VREF+ 4.7µF 0.1µF 4.7µF 0.001µF OUTPUT DATA DRDY OEM ANALOG INPUT OEL VIN STRT CLK VREF - VAA- 1.5MHz CLOCK VSS FIGURE 17. GROUND AND SUPPLY DECOUPLING 11 HI5810 Die Characteristics DIE DIMENSIONS PASSIVATION 3200µm x 3940µm Type: PSG Thickness: 13kÅ ±2.5kÅ METALLIZATION WORST CASE CURRENT DENSITY Type: AlSi Thickness: 11kÅ ±1kÅ 1.84 x 105 A/cm 2 Metallization Mask Layout HI5810 D1 D0 (LSB) DRDY VDD OEL CLK D2 STRT D3 VREF - D4 D5 VREF + D6 D7 VIN D8 VAA + VAA - D9 12 VSS D10 D11 (MSB) OEM HI5810 Small Outline Plastic Packages (SOIC) M24.3 (JEDEC MS-013-AD ISSUE C) N 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e µα B S 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 N α NOTES: MILLIMETERS 24 0o 1.27 6 24 8o 0o 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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