A1128 Datasheet

A1128
Highly Programmable Hall-Effect Switch
Features and Benefits
Description
• Chopper stabilization for stable switchpoints throughout
operating temperature range
• Externally programmable:
▫ Operate point (through the VCC pin)
▫ Output polarity
▫ Output fall time for reduced EMI in
automotive applications
• On-board voltage regulator for 3 to 24 V operation
• On-chip protection against:
▫ Supply transients
▫ Output short-circuits
▫ Reverse battery condition
The A1128 is a field-programmable, unipolar Hall-effect switch
designed for use in high-temperature applications. This device
uses a chopper-stabilization technique to eliminate offset
inherent in single-element devices.
The devices are externally programmable. A wide range of
programmability is available on the magnetic operate point,
BOP , while the hysteresis remains fixed. This advanced
feature allows optimization of the sensor IC switchpoint and
can drastically reduce the effects of mechanical placement
tolerances found in end-use production environments.
A proprietary dynamic offset cancellation technique, with
an internal high-frequency clock, reduces the residual offset
voltage, which is normally caused by device overmolding,
temperature dependencies, and thermal stress. Having the Hall
element and amplifier in a single chip minimizes many problems
normally associated with low-level analog signals.
Packages: 3-pin SIP (suffix UA) and 3-pin
SOT89 (suffix LT)
Two package styles provide a magnetically optimized package
for most applications. Type LT is a miniature SOT89/TO-243AA
surface mount package that is thermally enhanced with an
exposed ground tab, and type UA is a three-lead ultramini SIP
for through-hole mounting. The packages are lead (Pb) free,
with 100% matte tin plated leadframes.
Not to scale
Functional Block Diagram
V+
Regulator
To All Subcircuits
VCC
Trim Control
TC Trim
Switchpoint
Dynamic Offset
Cancellation
VOUT
CBYPASS
Amp
Signal Recovery
Output Fall Time
Program Control
Output Polarity
GND
A1128-DS, Rev. 1
A1128
Highly Programmable Hall-Effect Switch
Selection Guide
Part Number
Packing*
Package
A1128LLTTR-T
7-in. reel, 1000 pieces/reel
3-pin SOT89/TO-243 surface mount
A1128LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
*Contact Allegro™
for additional packaging options.
Absolute Maximum Ratings
Characteristic
Symbol
Rating
Unit
28
V
VRCC
–18
V
VOUT
26.5
V
Forward Supply Voltage
VCC
Reverse Supply Voltage
Forward Output Voltage
Reverse Output Voltage
Output Sink Current
Notes
VROUT
IOUT(SINK)
VCC to VOUT
V
20
mA
Operating Ambient Temperature
TA
–40 to 150
ºC
Maximum Junction Temperature
TJ(max)
165
ºC
Tstg
–65 to 170
ºC
Storage Temperature
L temperature range
–0.7
Pin-out Diagrams
1
2
3
1
2
3
VCC
GND
VOUT
VCC
GND
VOUT
Terminal List Table
LT Package
Number
Name
Function
1
VCC
Input power supply
2
GND
Ground
3
VOUT
Output signal
UA Package
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A1128
Highly Programmable Hall-Effect Switch
OPERATING CHARACTERISTICS Valid with TA = –40°C to 150°C, CBYPASS = 0.1 μF, VCC = 12 V, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
ELECTRICAL CHARACTERISTICS
Supply Voltage
VCC
Supply Current
ICC
3
12
24
V
No load on VOUT
–
–
5.5
mA
Supply Zener Clamp Voltage
VZSUPPLY
TA = 25°C, ICC = ICC(max) + 3 mA
28
–
–
V
Output Zener Clamp Voltage
VZOUTPUT
IOUT = 3 mA
28
–
–
V
–
–
-18
V
VCC = –18 V
–5
–
–
mA
–
400
–
kHz
TA = 25°C; CLOAD (PROBE) = 10 pF
–
–
30
μs
POL = 0; B < BRP , t > ton
–
High
–
–
POL = 1; B < BRP , t > ton
–
Low
–
–
IOUT = 20 mA
–
175
400
mV
Reverse Battery Zener
VRCC
Reverse Battery Current
IRCC
Chopping Frequency
fC
POWER-ON CHARACTERISTICS
Power-On Time
tPO
Power-On State2
POS
OUTPUT STAGE CHARACTERISTICS
Output Saturation Voltage
Output Leakage Current
VOUT(sat)
IOFF
Output Current Limit
IOUT(lim)
Output Rise Time3,4
tr
Output Fall Time4
tf
VOUT = 24 V; Switch state = Off
–
–
10
μA
Short-Circuit Protection, Output = On
30
–
90
mA
VCC = 12 V, RLOAD = 820 Ω, CLOAD = 10 pF
–
–
2
μs
VCC = 12 V, RLOAD = 2 kΩ, CLOAD = 4.7 nF
–
21
–
μs
FALL = 0, VCC = 12 V, RLOAD = 820 Ω,
CLOAD = 10 pF
–
–
2
μs
FALL = 1, VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF
–
6.5
–
μs
FALL = 2, VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF
–
10
–
μs
FALL = 3, VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF
–
12.5
–
μs
POL = 0
Output Polarity2
POL
POL = 1
Continued on the next page…
B > BOP
–
Low
–
–
B < BRP
–
High
–
–
B > BOP
–
High
–
–
B < BRP
–
Low
–
–
V+
VOUT(High)
%
100
90
10
0
VOUT(Low)
tr
tf
Rise Time and Fall Time Definitions
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A1128
Highly Programmable Hall-Effect Switch
OPERATING CHARACTERISTICS (continued) Valid with TA = –40°C to 150°C, CBYPASS = 0.1 μF, VCC = 12 V,
unless otherwise noted
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
–
–35
–
G
MAGNETIC CHARACTERISTICS valid VCC = 3 to 24 V, TJ ≤ TJ(max), unless otherwise noted
Pre-Programming BOP Target
BOPinit
Switchpoint Thermal Drift5
ΔBOP
Hysteresis
Bhys
TA = 25°C, BOPPOL = 0
TA = 25°C, BOPPOL = 1
–
35
–
G
LT package, BOP = ±650 G
–0.14
–0.03
0.08
%/°C
UA package, BOP = ±650 G
–0.08
0.00
0.08
%/°C
5
15
30
G
BOP - BRP
PROGRAMMING CHARACTERISTICS
Switchpoint Magnitude Selection Bits
BitBOPSEL
–
8
–
Bit
Switchpoint Polarity Bits
BitBOPPOL
–
1
–
Bit
BitPOL
–
1
–
Bit
Fall Time Bits
BitFALL
–
2
–
Bit
Device Lock Bits
BitLOCK
–
1
–
Bit
TA = 25°C, BOPPOL = 1 (minimum at
BOPSEL = 255, maximum at BOPSEL = 0)
–650
–
20
G
TA = 25°C, BOPPOL = 0 (minimum at
BOPSEL = 0, maximum at BOPSEL = 255)
–20
–
650
G
–
4
8
G
Output Polarity Bits
Programmable BOP Range
BOP Step Size
BOP
ResBOP
Bit = LSB of BOPSEL
11
G (gauss) = 0.1 mT (millitesla).
state when device configured as shown in figure 1.
3Output Rise Time is governed by external circuit tied to VOUT.
4Measured from 10% to 90% steady state output.
5Internal trimming utilized to minimize switchpoint drift across the operating temperature range.
2Output
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A1128
Highly Programmable Hall-Effect Switch
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Symbol
RθJA
Package Thermal Resistance
Test Conditions*
Value
Units
Package UA, 1-layer PCB with copper limited to solder pads
165
ºC/W
Package LT, 1-layer PCB with copper limited to solder pads
180
ºC/W
Package LT, 2-layer PCB with 0.94 in2 copper each side
78
ºC/W
*Additional thermal information available on Allegro website.
Maximum Allowable VCC (V)
Power Derating Curve
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
VCC(max)
1-layer PCB, Package LT
(RθJA = 180 ºC/W)
1-layer PCB, Package UA
(RθJA = 165 ºC/W)
2-layer PCB, Package LT
(RθJA = 78 ºC/W)
VCC(min)
20
40
60
80
100
120
140
160
180
160
180
TA (ºC)
Power Dissipation, PD (m W)
Power Dissipation
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
2
(R -lay
θJ
A
er
= PC
78 B
ºC , Pa
/W ck
) ag
1-la
(R yer P
CB
θJA =
165 , Pac
1-la
ºC/ kage
W)
(R yer P
UA
CB
θJA =
180 , Pac
ºC/ kage
W)
LT
20
40
60
e
LT
80
100
120
Temperature (°C)
140
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A1128
Highly Programmable Hall-Effect Switch
Characteristic Performance
Supply Current (On) versus Ambient Temperature
Supply Current, ICC (mA)
6
5
4
VCC (V)
3.3
3
5
24
2
1
0
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
Supply Current (Off) versus Ambient Temperature
Supply Current, ICC (mA)
6
5
4
VCC (V)
3.3
3
5
24
2
1
0
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
Saturation Voltage, VOUT(sat) (V)
Saturation Voltage versus Ambient Temperature
500
400
ICC = 20 mA
300
VCC (V)
3.3
5
200
24
100
0
-50
-25
0
25
50
75
100
125
150
175
Ambient Temperature, TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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A1128
Highly Programmable Hall-Effect Switch
Application Information
V+
100 Ω
RLOAD
1.2 kΩ
1
A
VCC
A1128
CBYPASS
0.1 μF
VOUT
IC Output
3
A
A
GND
2
CLOAD
120 pF
A
A Tie to device pins using
traces as short as possible
Figure 1. Typical Application Circuit
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for switch
point accuracy is the small signal voltage developed across the
Hall element. This voltage is disproportionally small relative to
the offset that can be produced at the output of the Hall sensor IC.
This makes it difficult to process the signal while maintaining an
accurate, reliable output over the specified operating temperature
and voltage ranges. Chopper stabilization is a unique approach
used to minimize Hall offset on the chip. Allegro employs a
patented technique to remove key sources of the output drift
induced by thermal and mechanical stresses. This offset reduction
technique is based on a signal modulation-demodulation process.
The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at base band, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. In addition to the removal of the thermal and stress
related offset, this novel technique also reduces the amount of
thermal noise in the Hall sensor IC while completely removing
the modulated residue resulting from the chopper operation. The
chopper stabilization technique uses a high frequency sampling
clock. For demodulation process, a sample and hold technique is
used. This high-frequency operation allows a greater sampling
rate, which results in higher accuracy and faster signal-processing
capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling. This technique is made
possible through the use of a BiCMOS process, which allows the
use of low-offset, low-noise amplifiers in combination with highdensity logic integration and sample-and-hold circuits.
Regulator
Clock/Logic
Hall Element
Amp
Anit-aliasing
LP Filter
Tuned
Filter
Figure 2. Concept of Chopper Stabilization Technique
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115 Northeast Cutoff
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A1128
Highly Programmable Hall-Effect Switch
Functional Description
V+
VOUT(off)
V+
VOUT(off)
VOUT
Switch Off
Note that for the Pre-Programming BOP Target, BOPinit , when BOPPOL
= 0 although the operating range is 0 to B+, the initial BOPinit is
actually negative, and likewise, when BOPPOL = 1, although the
operating range 0 to B– , the initial BOPinit is actually positive.
Switch On
Switch On
VOUT
at the Hall sensor IC exceeds the operate point threshold, BOP .
When the magnetic field is reduced to below the release point
threshold, BRP , the device output switches on.
Switch Off
When the Output Polarity bit is not set (POL = 0), the A1128
output switches on after the magnetic field at the Hall sensor IC
exceeds the operate point threshold, BOP . When the magnetic field
is reduced to below the release point threshold, BRP , the device
output switches off. The difference between the magnetic operate
and release points is called the hysteresis of the device, BHYS.
In the alternative case, in which the Output Polarity bit is set
(POL = 1), the A1128 output switches off when the magnetic field
VOUT(on)(sat)
(B) BOPPOL = 0
POL = 1
(A) BOPPOL = 0
POL = 0
VOUT(off)
VOUT
Switch Off
VOUT(off)
Switch On
Switch On
VOUT
V+
BHYS
(C) BOPPOL = 1
POL = 0
B–
BRP
0 BOPinit
VOUT(on)(sat)
BOP
BRP
BOP
VOUT(on)(sat)
B–
B+
BHYS
BHYS
V+
BOP
BOPinit 0
Switch Off
BRP
B+
BRP
BOP
BOPinit 0
VOUT(on)(sat)
0 BOPinit
BHYS
(D) BOPPOL = 1
POL = 1
Figure 3. Hysteresis Diagrams. These plots demonstrate the behavior of the A1128 with the applied magnetic field
impinging on the branded face of the device case (refer to Package Outline Drawings section). On the horizontal axis,
the B+ direction indicates increasing south or decreasing north magnetic flux density, and the B– direction indicates
increasing north or decreasing south magnetic flux density.
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115 Northeast Cutoff
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A1128
Highly Programmable Hall-Effect Switch
Programming Guidelines
Overview
Programming is accomplished by sending a series of input voltage pulses serially through the VCC (supply) pin of the device.
A unique combination of different voltage level pulses controls
the internal programming logic of the device to select a desired
programmable parameter and change its value. There are three
voltage levels that must be taken into account when programming. These levels are referred to as high (VPH), mid (VPM), and
low (VPL).
highly recommends using the Allegro Sensor IC Evaluation Kit,
available on the Allegro website On-line Store. The manual for
that kit is available for download free of charge, and provides
additional information on programming these devices. (Note: This
kit is not recommended for production purposes.)
The A1128 features three programmable modes, Try mode, Blow
mode, and Read mode:
Bit Field The internal fuses unique to each register, represented
as a binary number. Changing the bit field settings of a particular
Definition of Terms
Register The section of the programming logic that controls the
choice of programmable modes and parameters.
• In Try mode, programmable parameter values are set and measured simultaneously. A parameter value is stored temporarily,
and reset after cycling the supply voltage.
tACTIVE
Supply Voltage, VCC
• In Blow mode, the value of a programmable parameter may
be permanently set by blowing solid-state fuses internal to the
device. Device locking is also accomplished in this mode.
• In Read mode, each bit may be verified as blown or not blown.
The programming sequence is designed to help prevent the device
from being programmed accidentally; for example, as a result of
noise on the supply line. Note that, for all programming modes, no
parameter programming registers are accessible after the devicelevel LOCK bit is set. The only function that remains accessible is
the overall Fuse Checking feature.
Although any programmable variable power supply can be used
to generate the pulse waveforms, for design evaluations, Allegro
tPr
VPH
tBLOW
tPf
VPM
VPL
(Supply
cycled)
tLOW
tLOW
GND
Programming
pulses
Blow
pulse
Figure 4. Programming pulse definitions (see table 1)
Table 1. Programming Pulse Requirements, Protocol at TA = 25°C
Characteristics
Symbol
Notes
Min.
VPL
Programming Voltage
VPM
Measured at the VCC pin
VPH
Programming Current
IPP
tLOW
Pulse Width
Pulse Rise Time
Pulse Fall Time
Blow Pulse Slew Rate
VCC = 5 → 26 V, CBLOW = 0.1 μF (min); minimum supply current required to
ensure proper fuse blowing.
Typ.
Max.
Unit
4.5
5
5.5
V
12.5
–
14
V
21
–
27
V
175
–
–
mA
Duration of VPL separating pulses at VPM or VPH
20
–
–
μs
tACTIVE
Duration of pulses at VPM or VPH for key/code selection
20
–
–
μs
tBLOW
Duration of pulse at VPH for fuse blowing
90
100
–
μs
tPr
VPL to VPM or VPL to VPH
5
–
100
μs
tPf
VPM to VPL or VPH to VPL
5
–
100
μs
0.375
–
–
V/μs
SRBLOW
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115 Northeast Cutoff
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A1128
Highly Programmable Hall-Effect Switch
Blow Pulse A high voltage pulse of sufficient duration to blow
the addressed fuse.
Cycling the Supply Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the programming settings in Try mode.
Programming Procedure
Programming involves selection of a register and mode, and then
setting values for parameters in the register for evaluation or fuse
blowing. Figure 8 provides an overview state diagram.
Register Selection
Each programmable parameter can be accessed through a specific
register. To select a register, from the Initial state, a sequence of
voltage pulses consisting of one VPH pulse, one VPM pulse, and
then a unique combination of VPH and VPM pulses, is applied
serially to the VCC pin (with no VCC supply interruptions). This
sequence of pulses is called the key, and uniquely identifies each
register. An example register selection key is shown in figure 5.
Try Mode
In Try mode, the bit field addressing is accomplished by applying a series of VPM pulses to the VCC pin of the device, as shown
in figure 6. Each pulse increases the total bit field value of the
selected parameter, increasing by one on the falling edge of each
additional VPM pulse. When addressing a bit field in Try mode,
the number of VPM pulses is represented by a decimal number
called a code. Addressing activates the corresponding fuse locations in the given bit field by increasing the binary value of an
internal DAC, up to the maximum possible code. As the value
of the bit field code increases, the value of the programmable
parameter changes. Measurements can be taken after each VPM
pulse to determine if the desired result for the programmable
parameter has been reached. Cycling the supply voltage resets
all the locations in the bit field that have un-blown fuses to their
initial states. This should also be done before selection of a different register in Try mode.
When addressing a parameter in Try mode, the bit field address
(code) defaults to the value 1, on the falling edge of the final register selection key VPH pulse (see figure 6). A complete example
is shown figure 10. Note that, in the four BOP selection virtual
registers, after the maximum code is entered, the next VPM pulse
wraps back to the beginning of the register, and selects code 0.
VPH
VPM
VPL
GND
Figure 5. Example of Try mode register selection pulses, for the BOP
Negative Trim, Up-Counting register.
VCC
VCC
VPH
VPM
Code 2n –1
Fuse Blowing Applying a high voltage pulse of sufficient
duration to permanently set an addressed bit by blowing a fuse
internal to the device. Once a bit (fuse) has been blown, it cannot
be reset.
Mode Selection
The same physical registers are used for all programming modes.
To distinguish Blow mode and Read mode, when selecting the
registers an additional pulse sequence consisting of eleven VPM
pulses followed by one VPH pulse is added to the key. The combined register and mode keys are shown in table 3.
Code 2n –2
Addressing Increasing the bit field code of a selected register
by serially applying a pulse train through the VCC pin of the
device. Each parameter can be measured during the addressing
process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent.
Code 3
Code The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Code 2
Key A series of voltage pulses used to select a register or mode.
To simplify Try mode, the A1128 provides a set of four virtual
registers, one for each combination of: BOP selection (BOPSEL),
BOP polarity (BOPPOL), and a facility for transiting BOP magnitude values in an increasing or decreasing sequence. These registers also allow wrapping back to the beginning of the register
after transiting the register.
Code 1
register causes its programmable parameter to change, based on
the internal programming logic.
VPL
GND
Figure 6. Try mode bit field addressing pulses.
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A1128
Highly Programmable Hall-Effect Switch
The four BOP selecting virtual registers allow the programmer
to adjust the BOP parameter for use in north or south magnetic
fields. In addition, values can be traversed from low to high, or
from high to low. Figure 12 shows the relationship between the
BOP parameter and the different Try mode registers. Note: See the
Output Polarity section for information about setting the POL bit
before using Try mode.
The FALL and POL fields are in the same register (FALL is
bits 1:0, and POL is bit 2). Therefore, in Try mode both can be
programmed simultaneously by adding the codes for the two
parameters, and send the sum as the code. For example, sending
code 7 (111) sets FALL to 3 (x11) and sets POL (1xx).
Blow Mode
After the required code is determined for a given parameter, its
value can be set permanently by blowing individual fuses in the
appropriate register bit field. Blowing is accomplished by selecting the register and mode selection key, followed by the appropriate bit field address, and ending the sequence with a Blow
pulse. The Blow mode selection key is a sequence of eleven VPM
pulses followed by one VPH pulse. The Blow pulse consists of a
VPH pulse of sufficient duration, tBLOW , to permanently set an
addressed bit by blowing a fuse internal to the device. The device
power must be cycled after each individual fuse is blown.
Due to power requirements, a 0.1 μF blowing capacitor, CBLOW ,
must be mounted between the VCC pin and the GND pin during programming, to ensure enough current is available to blow
fuses. If programming in the application, CBYPASS (see figure 1)
can serve the same purpose.
The fuse for each bit in the bit field must be blown individually.
The A1128 built-in circuitry allows only one fuse at a time to be
blown. During Blow mode, the bit field can be considered a “onehot” shift register. Table 2 illustrates how to relate the number of
VPM pulses to the binary and decimal value for Blow mode bit
field addressing. It should be noted that the simple relationship
between the number of VPM pulses and the required code is:
2n = Code,
where n is the number of VPM pulses, and the bit field has an initial state of decimal code 1 (binary 00000001). To correctly blow
the required fuses, the code representing the required parameter
value must be translated to a binary number. For example, as
shown in figure 7, decimal code 5 is equivalent to the binary
number 101. Therefore bit 2 must be addressed and blown, the
device power supply cycled, and then bit 0 must be addressed
and blown. The order of blowing bits, however, is not important. Blowing bit 0 first, and then bit 2 is acceptable. A complete
example is shown in figure 11.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
Locking the Device
After the required code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters. To do so, perform the following steps:
1. Ensure that the CBLOW capacitor is mounted.
2. Select the Output/Lock Bit register key.
3. Select Blow mode selection key.
4. Address bit 4 (10000) by sending four VPM pulses.
5. Send one Blow pulse, at IPP and SRBLOW, and sustain it for
tBLOW.
6. Delay for a tLOW interval, then power-down.
7. Optionally check all fuses.
Table 2. Blow Mode Bit Field Addressing
Quantity of
VPM Pulses
Binary
Register Bit Field
Decimal Equivalent
Code
0
0000 0001
1
1
0000 0010
2
2
0000 0100
4
3
0000 1000
8
4
0001 0000
16
5
0010 0000
32
6
0100 0000
64
7
1000 0000
128
Bit Field Selection
Address Code Format
(Decimal Equivalent)
Code 5
Code in Binary
(Binary)
1 0 1
Fuse Blowing
Target Bits
Bit 2
Fuse Blowing
Address Code Format
Bit 0
Code 4
Code 1
(Decimal Equivalents)
Figure 7. Example of code 5 broken into its binary components.
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A1128
Highly Programmable Hall-Effect Switch
Table 3. Programming Logic Table
Register Name
[Selection Key]
Bit Field Address (Code)
Notes
Binary
Decimal
(MSB→LSB) Equivalent
Try Mode Register Selections
BOP Positive, Trim Up-Counting
[ 2 × VPH ]
BOP Negative, Trim Up-Counting
[ VPH → VPM → 2 × VPH ]
BOP Positive, Trim Down-Counting
[ 2 × VPH → 4 × VPM → VPH ]
BOP Negative, Trim Down-Counting
[VPH → VPM → 2 × VPH
→ 4 × VPM → VPH ]
Increase BOP (South field). Code 1 automatically selected when register
entered, wraps back to code 0.
0000 0000
0
1111 1111
255
0000 0000
0
1111 1111
255
1111 1111
0
0000 0000
255
1111 1111
0
0000 0000
255
x01
1
Output Fall Time (FALL). Code 1 automatically selected. Minimum value.
x11
3
Output Fall Time (FALL) selection is at maximum value.
0xx
0
Output Polarity Bit (POL). Default, no fuse blowing required.
POL = 0, see figures 3A and 3C.
1xx
4
Output Polarity Bit (POL). Code 1 automatically selected.
POL = 1, see figures 3B and 3D. Code references a single bit only.
1000
8
Fuse Threshold Low Register. Code 1 automatically selected when register
entered. Checks un-blown fuses. Code references a single bit only.
1001
9
Fuse Threshold High Register. Checks blown fuses.
0000 0000
0
BOP magnitude selection. Default, no fuse blowing required.
Minimum value, corresponding to BOP(min).
1111 1111
255
0
0
South field polarity. Default, no fuse blowing required.
1
1
North field polarity. Code 1 (bit 0) automatically selected.
00
0
Output Fall Time (FALL). Default, no fuse blowing required.
11
3
Output Fall Time (FALL) selection is at maximum value. Code 1 (bit 0)
automatically selected.
000
0
Output Polarity Bit (POL). Default, no fuse blowing required.
POL = 0, see figures 3A and 3C.
100
4
Output Polarity Bit (POL). Code 1 (bit 0) automatically selected. Code refers to
bit 2 only. POL = 1, see figures 3B and 3D.
10000
16
Lock bit (LOCK). Locks access to all registers with exception of Fuse
Threshold registers. Code 1 (bit 0) automatically selected in Blow mode. Code
refers to bit 5 only.
0 to 111 1111
–
Read mode bit values. Sequentially selects each bit in selected Blow
mode register for reading bit status as blown or not blown. Code 1 (bit 0)
automatically selected. Monitor VOUT after each pulse.
Output / Fuse Checking
[ VPH → 3 × VPM → VPH ]
BOP selection is at maximum value.
Increase BOP (North field). Code 1 automatically selected when register
entered, wraps back to code 0.
BOP selection is at maximum value.
Decrease BOP (South field). Code 1 automatically selected when register
entered, wraps back to code 0. Code is automatically inverted (code 1 selects
BOP selection maximum value minus 1.)
BOP selection is at minimum value.
Decrease BOP (North field). Code 1 automatically selected when register
entered, wraps back to code 0. Code is automatically inverted (code 1 selects
BOP selection maximum value minus 1.)
BOP selection is at minimum value.
Blow or Read Mode Register Selections
BOP Selection
(BOPSEL)
[ 2 × VPH
→ 11 × VPM → VPH ]
BOP Polarity
(BOPPOL)
[ VPH → VPM → VPH
→ 11 × VPM → VPH ]
Output / Lock Bit
[ VPH → 3 × VPM → VPH
→ 11 × VPM → VPH ]
BOP magnitude selection. Maximum value, corresponding to BOP(max).
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A1128
Highly Programmable Hall-Effect Switch
Power-up
VPM
Initial State
VPH
Register Selection
VPM
→VPH
VPM
→VPH
→11×VPM
→VPH
3 × VPM
→VPH
→11×VPM
→VPH
Output/
Lock Bit
VPH
→11×VPM
→VPH
(BOPPOL)
BOP
Polarity
→VPH
VPH
BOP
Positive
Trim Up
VPM
→2 × VPH
→4 × VPM
→ VPH
VPH
→4 × VPM
→ VPH
BOP
Negative
Trim Up
BOP
Positive
Trim Down
3 × VPM
→VPH
BOP
Negative
Trim Down
Output/
Fuse
Checking
(BOPSEL)
BOP
Selection
User power-down
required
Try Mode
VPM
Code 0
VPM
Yes
VPM
BOP Trim
register?
VPM
Code 2
Code 1
Code 2n–1
[Optional: test output or check fuse integrity]
Blow Mode
VPM
VPM
Bit 1
Bit 0
VPH
VPH
(Blow Pulse) (Blow Pulse)
Bit n-1
VPH
(Blow Pulse)
Blow Fuse
Read Mode
VPM
Bit 0
VPM
Bit 1
Bit n-1
Figure 8. Programming State Diagram
[Read fuse status on VOUT]
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13
A1128
Highly Programmable Hall-Effect Switch
Additional Guidelines
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
• The power supply used for programming must be capable of
delivering at least VPH and 175 mA.
Fuse Checking
Incorporated in the A1128 is circuitry to simultaneously check
the integrity of the fuse bits. The fuse checking feature is enabled
by using the Fuse Checking registers, and while in Try mode,
applying the codes shown in table 3. The register is only valid
in Try mode and is available before or after the programming
LOCK bit is set.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
• Set the LOCK bit (only after all other parameters have been
programmed and validated) to prevent any further programming
of the device.
Selecting the Fuse Threshold High register checks that all blown
fuses are properly blown. Selecting the Fuse Threshold Low
register checks all un-blown fuses are properly intact. The supply
current, ICC , increases by 250 μA if a marginal fuse is detected.
If all fuses are correctly blown or fully intact, there will be no
change in supply current.
Read Mode
The A1128 features a Read mode that allows the status of each
programmable fuse to be read back individually. The status,
blown or not blown, of the addressed fuse is determined by monitoring the state of the VOUT pin. A complete example is shown
in figure 9.
Output Polarity
When selecting the BOP registers in Try mode, the output polarity
is determined by the value of the Output Polarity bit (POL). The
default value is POL = 0 (fuse un-blown). For applications that
require the output states defined by POL = 1 (see Operating Characteristics table), it is recommended to first permanently blow the
POL bit by selecting the Output / Lock bit register, and code 4.
The output is then defined by POL = 1 when selecting the BOP
Try mode registers. See table 3 for parameter details.
Read mode uses the same register selection keys as Blow mode
(see table 3), allowing direct addressing of the individual fuses in
the BOPPOL and BOPSEL registers (do not inadvertently send a
Blow pulse while in Read mode). After sending the register and
mode selection keys, that is, after the falling edge of the final VPH
pulse in the key, the first bit (the LSB) is selected. Each additional VPM pulse addresses the next bit in the selected register, up
Register (and Mode) Selection Key
Bit Field (Fuse) Address Codes
VPM
1
2
3
4
5
6
8
9
10 11
1
2
3
4
5
6
7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 3 Blown
Bit 4 Blown
Bit 5 Un-Blown
Bit 6 Blown
Bit 7 Un-Blown
Don’t Care
Bit 2 Un-Blown
VPM
Bit 1 Un-Blown
VPH
Bit 0
VPL
GND
VOUT
7
Bit 0 Blown
VCC
VPH
VPL
Fuse intact
Fuse blown
GND
Read-out on VOUT pin
Figure 9. Read mode example. Pulse sequence for accessing the BOP Selection register
(BOPSEL) and reading back the status of each of the eight bit fields. In this example, the code
(blown fuses) is 20 + 23 + 24 + 26 = 89 (0101 1001). After each address pulse is sent, the voltage
on the VOUT pin will be at GND for blown fuses and at VCC (at VPL or VPM) for un-blown fuses.
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14
A1128
Highly Programmable Hall-Effect Switch
(the status of the Output Polarity bit, POL, does not affect Read
mode output values, allowing POL to be tested also). If the output
state is high, the fuse can be considered un-blown. During Read
mode VOUT must be pulled high using a pull-up resistor (see
RLOAD in the Typical Application Circuit diagram).
to the MSB. Read mode is available only before the LOCK bit
has been set.
After the final VPH key pulse, and after each VPM address pulse,
if VOUT is low, the corresponding fuse can be considered blown
Bit Field
Address Codes
Register (and Mode)
Selection Key
6
Code 7
7
8
9
10 11
VPL
GND
Code 12
5
Code 11
4
Code 10
3
Code 9
2
Code 8
1
Code 6
4
Code 5
3
Code 4
2
Code 3
1
Code 2
VPM
Code 1
VCC
VPH
Figure 10. Example of Try mode programming pulses applied to the VCC pin. In this example, BOP Positive Trim, DownCounting register is addressed to code 12 by the eleven VPM pulses (code 1 is selected automatically at the falling edge
of the register-mode selection key).
Bit Field (Fuse)
Address Codes
Register (and Mode) Selection Key
2
3
4
5
6
7
8
9
10 11
1
2
3
Code 8 Bit 3
1
Bit 2
VPM
Bit 1
Blow
Pulse
VPL
GND
tLOW
VCC
VPH
Figure 11. Example of Blow mode programming pulses applied to the VCC pin. In this example, the BOP Magnitude
Selection register (BOPSEL) is addressed to code 8 (bit 3, or 3 VPM pulses) and its value is permanently blown.
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A1128
Highly Programmable Hall-Effect Switch
Magnetic Field Intensity, B (G)
BOP can be set to any value within the range allowed by the
BOPSEL registers. This includes switchpoints of south or north
polarity, and switchpoints at or near the zero crossing point for B.
However, switching is recommended only within the Programmable BOP Range, specified in the Operating Characteristics table.
B+ (south)
BOP(max)
BOP Setpoint
0
BOP(min)
B– (north)
0
Trimming of BOP is typically done in two stages. In the first
stage, BOP is adjusted temporarily using the Try mode programming features, to find the fuse value that corresponds to the
optimum BOP . After a value is determined, then it can be permanently set using the Blow mode features.
As an aid to programming the A1128 has several options available in Try Mode for adjusting the BOP parameter. As shown in
figure 12, these allow trimming of BOP for operation in north or
south polarity magnetic fields. In addition the BOP parameter can
either trim-up, start at the BOP minimum value and increase to
the maximum value, or trim-down, starting at the BOP maximum
value and decreasing to the minimum value.
Magnetic Field Intensity, B (G)
BOP Selection
The A1128 allows accurate trimming of the magnetic operate
point, BOP , within the application. This programmable feature
reduces effects due to mechanical placement tolerances and
improves performance when used in proximity or vane sensing
applications.
B+ (south)
BOP(max)
BOP Setpoint
0
BOP(min)
B– (north)
0
255
Try Mode, Bit Field Code
(A) BOP Positive, Trim Up-Counting Register
(B) BOP Positive, Trim Down-Counting Register
B+ (south)
Try Mode, Bit Field Code
255
BOP(min)
0
BOP Setpoint
BOP(max)
B– (north)
(C) BOP Negative, Trim Up-Counting Register
Magnetic Field Intensity, B (G)
Magnetic Field Intensity, B (G)
Try Mode, Bit Field Code
0
255
Try Mode, Bit Field Code
B+ (south)
0
255
BOP(min)
0
BOP Setpoint
BOP(max)
B– (north)
(D) BOP Negative, Trim Down-Counting Register
Figure 12. BOP profiles for each of the four BOP Selection virtual registers available in Try mode.
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A1128
Highly Programmable Hall-Effect Switch
Power Derating
The device must be operated below the maximum junction
temperature of the device, TJ(max) . Under certain combinations of peak conditions, reliable operation may require derating
supplied power or improving the heat dissipation properties of
the application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems website.)
The Package Thermal Resistance, RJA, is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RJC, is
relatively small component of RJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.


PD = VIN × IIN
(1)
T = PD × RJA
(2)
TJ = TA + ΔT
(3)
Example: Reliability for VCC at TA = 150°C, package UA, using a
single-layer PCB.
Observe the worst-case ratings for the device, specifically:
RJA = 165 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
ICC(max) = 5.5 mA.
Calculate the maximum allowable power level, PD(max) . First,
invert equation 3:
Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = Tmax ÷ RJA = 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 5.5 mA = 16.5 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est) .
Compare VCC(est) to VCC(max) . If VCC(est) ≤ VCC(max) , then
reliable operation between VCC(est) and VCC(max) requires
enhanced RJA. If VCC(est) ≥ VCC(max) , then operation
between VCC(est) and VCC(max) is reliable under these conditions.
For example, given common conditions such as: TA= 25°C,
VIN = 12 V, IIN = 4 mA, and RJA = 140 °C/W, then:
PD = VIN × IIN = 12 V × 4 mA = 48 mW

T = PD × RJA = 48 mW × 140 °C/W = 7°C
TJ = TA + T = 25°C + 7°C = 32°C
A worst-case estimate, PD(max) , represents the maximum allowable power level, without exceeding TJ(max) , at a selected RJA
and TA.
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17
A1128
Highly Programmable Hall-Effect Switch
Package Outline Drawings
Package LT 3-Pin SOT-89
+0.13
4.47 –0.08
1.73 ±0.10
2.50
2.00
+0.03
0.41 –0.06
E
2.24
B
D
0.38 MIN
0.80
E
6° REF
1.14
+0.10
4.14 –0.20
+0.03
2.57 –0.28
2.16 REF
2.60
Parting Line
4.60
1.20
10° REF
1
2
3
1.04 ±0.15
10° REF
1.50
C
Branded Face
Basic pads for low-stress, not self-aligning
Additional pad for low-stress, self-aligning
Additional area for IPC reference layout
+0.15
1.45 –0.05
+0.05
0.43 –0.07
0.70
PCB Layout Reference View
+0.05
0.51 –0.07
NNN
2X 1.50 NOM
1
A
Standard Branding Reference View
= Supplier emblem
N = Last three digits of device part number
Updated package drawing only. Allegro package assembly tooling has not changed.
For Reference Only; not for tooling use (reference DWG-9064)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Branding scale and appearance at supplier discretion
B
Gate and tie bar burr area
C
Reference land pattern layout;
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances
D Active Area Depth, 0.77 mm
E Hall element; not to scale
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18
A1128
Highly Programmable Hall-Effect Switch
Package UA 3-Pin SIP
+0.08
4.09 –0.05
45°
B
C
E
2.04
1.52 ±0.05
1.44 E
Mold Ejector
Pin Indent
+0.08
3.02 –0.05
E
Branded
Face
NNN
45°
1
2.16
MAX
D Standard Branding Reference View
= Supplier emblem
N = Last three digits of device part number
0.79 REF
A
0.51
REF
1
2
3
+0.03
0.41 –0.06
15.75 ±0.51
For Reference Only; not for tooling use (reference DWG-9049)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Dambar removal protrusion (6X)
B Gate burr area
C Active Area Depth, 0.50 mm REF
+0.05
0.43 –0.07
D
Branding scale and appearance at supplier discretion
E
Hall element, not to scale
1.27 NOM
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A1128
Highly Programmable Hall-Effect Switch
Copyright ©2010-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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