A1260 Datasheet

A1260
Chopper-Stabilized Precision Vertical Hall-Effect Latch
FEATURES AND BENEFITS
•
•
•
•
•
•
•
AEC-Q100 automotive qualified
Magnetic sensing parallel to surface of the package
Highly sensitive switch thresholds
Symmetrical latch switch points
Operation from unregulated supply down to 3 V
Small package sizes
Automotive grade
□□ Output short-circuit protection
□□ Resistant to physical stress
□□ Reverse-battery protection
□□ Solid-state reliability
□□ Superior temperature stability
□□ Supply voltage Zener clamp
PACKAGES:
3-Pin SOT23-W
(Suffix LH)
3-Pin SIP
(Suffix UA)
DESCRIPTION
The A1260 vertical Hall-effect sensor IC is an extremely
temperature-stable and stress-resistant magnetic-sensing
device ideal for harsh operating environments. The sensor
is actuated by alternating north and south polarity magnetic
fields in plane with the device’s branded face. Two package
options, the SOT23W surface-mount and SIP through-hole,
allow sensing in a variety of orientations with respect to the
mounting position. Superior high-temperature performance
is made possible through dynamic offset cancellation, which
reduces the residual offset voltage normally caused by device
overmolding, temperature dependencies, and thermal stress.
Each device includes on a single silicon chip a voltage regulator,
a Hall-voltage generator, a small-signal amplifier, chopper
stabilization, a Schmitt trigger, and a short-circuit protected
NMOS output to sink up to 25 mA. The on-board regulator
permits operation with supply voltages of 3 to 24 V. The
advantage of operating down to 3 V is that the device can be
used in 3.3 V applications, while allowing additional external
resistance in series with the supply pin for greater protection
against high-voltage transient events.
The output is turned on when a south pole of sufficient strength
perpendicular to the vertical Hall element is present. A north
pole is necessary to turn the output off. Package type LH is a
modified SOT23W surface-mount package that switches with
magnetic fields oriented perpendicularly to the non-leaded side
of the package. The UA package is an ultra-mini SIP, equipped
Continued on next page...
Not to scale
VCC
Regulator
Vertical
Hall
Dynamic Offset
Cancellation
To All Subcircuits
VOUT
Hall
Amp
Sample, Hold,
& Averaging
Control
Low-Pass
Filter
Current
Limit
GND
Functional Block Diagram
A1260-DS, Rev. 2
Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
DESCRIPTION (continued)
for through-hole mounting and lead forming, that switches when a
magnetic field is presented to the top of the package, parallel with
the branded face. Both packages are RoHS-compliant and lead (Pb)
free (suffix, -T), with 100% matte-tin-plated leadframes.
SPECIFICATIONS
Selection Guide
Part Number
A1260ELHLT-T
A1260ELHLX-T
A1260LLHLT-T
A1260LLHLX-T
A1260EUA-T1
A1260LUA-T1
1
Packing
7-in. reel, 3000 pieces/reel
13-in. reel, 10000 pieces/reel
7-in. reel, 3000 pieces/reel
13-in. reel, 10000 pieces/reel
500 pieces per bulk bag
500 pieces per bulk bag
Package
3-pin surface mount SOT23W
3-pin surface mount SOT23W
3-pin surface mount SOT23W
3-pin surface mount SOT23W
SIP-3 through hole
SIP-3 through hole
Ambient, TA (°C)
-40 to 85
-40 to 85
-40 to 150
-40 to 150
-40 to 85
-40 to 150
Please contact Allegro for availability.
Absolute Maximum Ratings
Rating
Unit
Forward Supply Voltage
Characteristic
Symbol
VCC
Notes
26.5
V
Reverse Supply Voltage
VRCC
-18
V
Output off voltage
VOUT
26
V
Continuous Output Current
IOUT
25
mA
Reverse Output Current
IOUTR
-50
mA
Range E
-40 to 85
°C
Range L
-40 to 150
°C
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(MAX)
165
°C
TS
-65 to 170
°C
Storage Temperature
GND
Pin-Out Diagrams and Terminal List Table
3
Terminal List Table
Pin Number
VH
Package LH Pin-Out
2
3
VOUT
1
GND
2
VOUT
VCC
1
VCC
VH
Symbol
LH
Package
UA
Package
VCC
1
1
Power Supply to Chip
VOUT
2
3
Output from Circuit
GND
3
2
Ground
Description
Package UA Pin-Out
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Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
ELECTRICAL CHARACTERISTICS: valid over full operating voltage and temperature ranges (unless otherwise specified)
Characteristics
Symbol
Min.
Typ.1
Max.
Unit2
Operating, TJ < 165°C
3
–
24
V
IOUTOFF
VOUT = 24 V, B < BRP
–
–
10
µA
VOUT(SAT)
IOUT = 20 mA, B > BOP
–
230
500
mV
IOM
B > BOP
30
–
60
mA
Power-On Time 3
tPO
VCC > 3.0 V, B < BRP(MIN) – 10 G, B > BOP(MAX)
+ 10 G
–
–
25
µs
Chopping Frequency
fC
–
800
–
kHz
Output Rise Time 3,4
tr
RL = 820 Ω, CS = 20 pF
–
0.2
2
µs
tf
RL = 820 Ω, CS = 20 pF
Supply Voltage
VCC
Output Leakage Current
Output Saturation Voltage
Output Current Limit
Output Fall Time
3,4
Supply Current
ICC
Reverse Battery Current
IRCC
Test Conditions
–
0.1
2
µs
–
2.5
4
mA
VRCC = -18 V
–
–
–5
mA
Supply Zener Clamp Voltage
VZ
ICC = 5 mA; TA = 25°C
28
34
–
V
Zener Impedance
IZ
ICC = 5 mA; TA = 25°C
–
50
–
Ω
MAGNETIC CHARACTERISTICS: valid over full operating voltage and temperature ranges (unless otherwise specified)
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit2
Operate Point
BOP
5
25
50
G
Release Point
BRP
–50
–25
–5
G
Hysteresis
BHYS
20
50
80
G
BOP - BRP
N
N
S
Z
1A
X
Y
Y
X
S
Z
1B
Figure 1: Magnet Orientation for Switching Output On for LH package (Panel 1A) and UA Package (Panel 1B)
Typical data is at TA = 25ºC and VCC = 12 V and it is for design information only
1 G (gauss) = 0.1 mT (millitesla).
3 Power on time, Rise time and Fall time are guaranteed through device characterization
4 C = oscilloscope probe capacitance.
S
1
2
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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3
Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
Thermal Characteristics: may require derating at maximum conditions; see application information
Symbol
Maximum Allowable VCC (V)
Package Thermal Resistance
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RθJA
Notes
Rating
Unit
Package LH, 2-layer PCB with 0.463 in.2 of copper area each
side connected by thermal vias
110
°C/W
Package LH, 1-layer PCB with copper limited to solder pads
228
°C/W
Package UA, 1-layer PCB with copper limited to solder pads
165
°C/W
VCC(max)
Package LH, 2-layer PCB
(RJA = 110ºC/W)
Package UA, 1-layer PCB
(RJA = 165ºC/W)
Package LH, 1-layer PCB
(RJA = 228ºC/W)
VCC(min)
20
40
60
80
100
120
140
Temperature (ºC)
Power Derating Curve
160
180
Maximum Power Dissipation, PD (mW)
Characteristic
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Package LH, 2-layer PCB
(RJA = 110ºC/W)
Package UA, 1-layer PCB
(RJA = 165ºC/W)
Package LH, 1-layer PCB
(RJA = 228ºC/W)
20
40
60
80
100
120
140
160
180
Temperature (ºC)
Power Dissipation versus Ambient Temperature
TJ(max) = 165ºC; ICC = ICC(max)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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4
Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.5
ICC (mA)
ICC (mA)
ELECTRICAL OPERATING CHARACTERISTICS
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0.0
2
6
10
14
VCC (V)
18
22
26
–60
–40
–20
0
20
40
60
80
100
120
140
160
TA (ºC)
Average Supply Current versus Supply Voltage
Average Supply Current versus Ambient Temperature
500
500
450
450
400
400
350
350
VOUT(SAT) (mV)
VOUT(SAT) (mV)
2.0
300
250
200
150
300
250
200
150
100
100
50
50
0
0
2
6
10
14
18
22
26
–60
–40
–20
0
20
40
TA (ºC)
VCC (V)
Average Low Output Voltage versus Supply Voltage
–40
TA (ºC)
25
150
60
80
100
120
140
160
Average Low Output Voltage versus Ambient
Temperature for IOUT = 20 mA
3
VCC (V)
12
24
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Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
50
50
45
45
40
40
35
35
30
BOP (G)
BOP (G)
MAGNETIC OPERATING CHARACTERISTICS
25
20
30
25
20
15
15
10
10
5
5
0
0
2
6
10
14
18
22
26
–60
–40
–20
0
20
VCC (V)
0
0
–5
–5
–10
–10
–15
–15
–20
–25
80
100
120
140
160
–20
–25
–30
–30
–35
–35
–40
–40
–45
–45
–50
–50
2
6
10
14
18
22
26
–60
–40
–20
0
20
40
TA (ºC)
VCC (V)
Average Release Point versus Supply Voltage
60
80
100
120
140
160
Average Release Point versus Ambient Temperature
80
80
70
70
60
60
BHYS (G)
BHYS (G)
60
Average Operate Point versus Ambient Temperature
BRP (G)
BRP (G)
Average Operate Point versus Supply Voltage
40
TA (ºC)
50
50
40
40
30
30
20
20
2
6
10
14
18
22
26
–60
–40
–20
0
20
VCC (V)
Average Switchpoint Hysteresis versus Supply Voltage
–40
TA (ºC)
25
40
60
80
100
120
140
160
TA (ºC)
150
Average Switchpoint Hysteresis versus Ambient
Temperature
3
VCC (V)
12
24
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115 Northeast Cutoff
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6
Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
FUNCTIONAL DESCRIPTION
Removal of the magnetic field will leave the device output
latched on if the last crossed switch point is BOP, or latched off if
the last crossed switch point is BRP.
The difference in the magnetic operate and release points is the
hysteresis (BHYS) of the device. This built-in hysteresis allows
clean switching of the output even in the presence of external
mechanical vibration and electrical noise.
Switch to High
B–
VCC
VOUT(SAT)
0
BRP
0
BOP
The magnetic field is perpendicular to the Hall-effect sensor
when the direction of the field is parallel to the X-axis for the LH
package (see panel 2A in Figure 2) and Y-axis for the UA package (see panel 2B in Figure 2). After turn-on, the output voltage
is VOUT(SAT). The output transistor is capable of sinking current
up to the short circuit current limit IOM, which is a minimum of
30 mA. The device output goes high (turns off) when the magnetic field is reduced below the release point (BRP), which
requires a north pole of sufficient strength.
V+
Switch to Low
The output of these devices switches low (turns on) when a south
polarity magnetic field perpendicular to the Hall-effect sensor
exceeds the operate point threshold (BOP). The LH package is
offered with a vertical Hall element capable of sensing magnetic
fields perpendicular to the non-leaded side of the package closest
to pin 1. The UA package vertical Hall element senses fields perpendicular to the top of the package opposite of the device leads.
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) will give an indeterminate output state. A valid
state is attained after the first excursion beyond BOP or BRP.
VOUT
Operation
B+
BHYS
Figure 3: Switching Behavior of Latches
On the horizontal axis, the B+ direction indicates increasing south
polarity magnetic field strength, and the B– direction indicates
increasing north polarity magnetic field strength. Removal of the
magnetic field will leave the device latched in its current state.
Magnet
N
S
Y
Vertical
Hall
Device
S
N
X
Magnet
LH Package
2A
UA Package
2B
Figure 2: Vertical Hall Sensing
(Left) LH package orientation and (Right) UA package orientation (Not to scale)
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Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
APPLICATIONS
It is strongly recommended that an external capacitor be connected (in close proximity to the Hall-effect sensor IC) between
the supply and ground of the device to reduce both external noise
and noise generated by the chopper stabilization technique. As
shown in Figure 4, a 0.1 µF capacitor is typical.
Extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines For Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMT and ThroughHole, AN26009
All are provided on the Allegro Web site:
VS
VDD
RLOAD
A1260
CBYP
0.1 µF
OUT
Sensor
Output
GND
GND
www.allegromicro.com
Figure 4: Typical Application Circuit
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Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
CHOPPER STABILIZATION
A limiting factor for switchpoint accuracy when using Hall-effect
technology is the small-signal voltage developed across the Hall
plate. This voltage is proportionally small relative to the offset
that can be produced at the output of the Hall sensor. This makes
it difficult to process the signal and maintain an accurate, reliable
output over the specified temperature and voltage range. Chopper
stabilization is a proven approach used to minimize Hall offset.
The Allegro patented technique, dynamic quadrature offset
cancellation, removes key sources of the output drift induced by
temperature and package stress. This offset reduction technique
is based on a signal modulation-demodulation process. Figure 5:
Model of Chopper Stabilization Circuit (Dynamic Offset Cancellation) illustrates how it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation.
The subsequent demodulation acts as a modulation process for
the offset causing the magnetically induced signal to recover its
original spectrum at baseband while the dc offset becomes a highfrequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innovative chopper stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate
that produces higher accuracy, reduced jitter, and faster signal
processing. Additionally, filtering is more effective and results
in a lower noise analog signal at the sensor output. Devices
such as the A1260 that utilize this approach have an extremely
stable quiescent Hall output voltage, are immune to thermal
stress, and have precise recoverability after temperature cycling.
This technique is made possible through the use of a BiCMOS
process which allows the use of low offset and low noise amplifiers in combination with high-density logic and sample-and-hold
circuits.
Regulator
Clock/Logic
Low-Pass
Filter
Hall
Element
Amp.
Sample, Hold &
Averaging
Figure 5: Model of Chopper Stabilization Circuit (Dynamic Offset Cancellation)
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9
Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
POWER DERATING
The device must be operated below the maximum junction temperature of the device (TJ(max)). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.)
The Package Thermal Resistance (RθJA) is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity (K)
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case (RθJC) is relatively
small component of RθJA. Ambient air temperature (TA) and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN(1)
∆T = PD × RθJA
(2)
TJ = TA + ∆T(3)
For example, given common conditions such as:
TA = 25°C, VCC = 12 V, ICC = 2.5 mA, and RθJA = 110°C/W for
the LH package, then:
PD = VCC × ICC = 12 V × 2.5 mA = 30 mW
∆T = PD × RθJA = 30 mW × 110°C/W = 3.3°C
TJ = TA + ∆T = 25°C + 3.3°C = 28.3°C
A worst-case estimate (PD(max)) represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max),
at a selected RθJA and TA.
Example: Reliability for VCC at TA = 150°C, package LH, using
low-K PCB.
Observe the worst-case ratings for the device, specifically:
RθJA = 228°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
ICC(max) = 4 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
∆Tmax = TJ(max) – TA = 165°C – 150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation.
Then, invert equation 2:
PD(max) = ∆Tmax ÷ RθJA = 15°C ÷ 228°C/W = 66 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 66 mW ÷ 4 mA = 16.4 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤ VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
VCC(max) is reliable under these conditions.
In cases where the VCC(max) level is known, and the system
designer would like to determine the maximum allowable ambient temperature (TA(max)), the calculations can be reversed.
For example, in a worst case scenario with conditions VCC(max) =
24 V, ICC(max) = 4 mA, and RθJA = 228 °C/W using equation 1 the
largest possible amount of dissipated power is:
PD = VIN × IIN
PD = 24 V × 4 mA = 96 mW
Then, by rearranging equations 3:
TA(max) = TJ(max) – ΔT
TA (max) = 165°C/W – (96 mW × 228°C/W)
TA (max) = 165°C/W – 21.9°C = 143.1°C
In another example, the regulated supply voltage is equal to 3 V.
Therefore, VCC(max) = 3 V and ICC(max) = 4 mA. By using equation 1 the largest possible amount of dissipated power is:
PD = VIN × IIN
PD = 3 V × 4 mA = 12 mW
Then, by rearranging equation 3:
TA(max) = TJ(max) – ΔT
TA(max) = 165°C/W – (12 mW × 228°C/W)
TA(max) = 165°C/W – 2.7°C = 162.3°C
The operating temperature range of the device (TA) is limited to
between -40°C and 150°C, and in the above case there is sufficient power dissipation head room to operate the device throughout this range.
In the above example, we are not exceeding the maximum junction temperature; however, performance beyond the maximum
operating ambient temperature of 150ºC is not guaranteed.
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10
Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference DWG-2840)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.12
2.98 –0.08
D
0.43
4°±4°
A
3
0.180
+0.020
–0.053
0.96 D
2.90
+0.10
–0.20
1.91
+0.19
–0.06
2.40
0.70
D
0.25 MIN
1.00
2
1
0.55 REF
0.25 BSC
0.95
Seating Plane
B
Gauge Plane
8X 10° REF
PCB Layout Reference View
Branded Face
1.00 ±0.13
0.05
0.95 BSC
+0.10
–0.05
0.40 ±0.10
NNN
C
Standard Branding Reference View
N = Last three digits of device part number
A Active Area Depth, 0.28 mm
B Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion
D Hall elements, not to scale
Figure 6: Package LH, 3-Pin SOT23-W
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
For Reference Only – Not for Tooling Use
(Reference DWG-9013)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
45°
B
4.09
+0.08
–0.05
1.52 ±0.05
E
2.04
C
E
3.02
+0.08
–0.05
2 X 10°
Mold Ejector
Pin Indent
E 0.425
45°
Branded
Face
1.02 MAX
A
0.79 REF
1
2
3
0.43
+0.05
–0.07
0.41
+0.03
–0.06
1.27 NOM
NNN
14.99 ±0.25
1
D
Standard Branding Reference View
= Supplier emblem
N = Last three digits of device part number
A
Dambar removal protrusion (6X)
B
Gate and tie bar burr area
C
Active Area Depth, 0.50 mm REF
D
Branding scale and appearance at supplier discretion
E
Hall element, not to scale
Figure 7: Package UA, 3-Pin SIP
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115 Northeast Cutoff
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12
Chopper-Stabilized Precision
Vertical Hall-Effect Latch
A1260
Revision History
Revision
Revision Date
–
March 10, 2015
1
July 13, 2015
2
September 21, 2015
Description of Revision
Initial Release
Corrected LH package Active Area Depth value
Added AEC-Q100 qualification under Features and Benefits
Copyright ©2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
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The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
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