A1174 Datasheet

A1174
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample
and Sleep Periods for Track Ball and Scroll Wheel Applications
Last Time Buy
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: December 3, 2013
Deadline for receipt of LAST TIME BUY orders: May 30, 2014
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A1174
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
Features and Benefits
▪ Micro-power latch operation
▪ 1.65 to 3.5 V battery operation
▪ Push-pull output eliminates the need for an external pullup resistor
▪ User configured, internally or externally controlled sample
and sleep periods
▫ Floating the two clock pins results in the use of a fixed
sampling clock internal to the device
▫ Toggling the clock pins allows the user to control the
sampling and sleep times of the device for extreme low
power operation
▪ External control of the clock pins allows the user to
implement synchronous sampling of multiple sensors in
direction detection systems
▪ Chopper stabilization
▫ Superior temperature stability
▫ Extremely low switchpoint drift
▫ Insensitive to physical stress
▪ Solid state reliability
▪ Small size
Package: 6-contact MLP/DFN (suffix EW)
1.5 mm × 2 mm × 0.40 mm
Description
The A1174 is a micro-power, Hall-effect latch for use in portable
devices that employ rotational detection systems, and have a
power supply voltage between 1.65 and 3.5 V. The device has
a single push-pull output structure and requires no external
pull-up resistor for reliable operation.
When a sufficient positive magnetic field is present on the
device, the device output transitions to the low state and is
latched in this state until a negative field of sufficient strength
latches the device output into the high state. The latched output
is ideal when using multiple sensors in rotational speed and
direction sensing systems (for example, track ball and scroll
bar systems in portable devices).
The device includes an innovative clocking scheme that
satisfies the micro-power needs of almost any application,
including track balls for PDAs and cell phones. Using the
EXTERNAL_CLK and DUAL_CLK pins as described in this
datasheet, the device can be set into various working modes.
In Dual Clock mode, the device switches between predefined
slow and fast sampling rates. The average current consumption
of the device is extremely low when rotation is not detected.
In External Clock mode, the user sets the clock rate for the
device to achieve the required on and off times for controlling
average power. This user-determined clocking also helps to
Continued on the next page…
Not to scale
+B
Magnetic Flux
Density
BOP
BOP
BOP
0
BRP
BRP
BRP
–B
+V
A1174 Output
On
Off
On
Off
On
Figure 1. Timing diagram for output switching
A1174-DS, Rev. 7
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
Description (continued)
achieve synchronous clocking of multiple devices. This allows a
defined phase relationship between the output transitions of each
device in direction detection systems.
by integrating, on a single silicon chip, a Hall-voltage generator,
a small-signal amplifier, chopper stabilization, a latch, and a
MOSFET output.
Improved stability is made possible through dynamic offset
cancellation using chopper stabilization, which reduces the residual
offset voltage normally caused by device overmolding, temperature
dependencies, and thermal stress. Solid state reliability is provided
The device package is a 6-contact, 1.5 mm × 2 mm, 0.40 mm nominal
overall height MLP/DFN, with exposed pad for enhanced thermal
dissipation. It is lead (Pb) free, with NiPdAu leadframe plating.
Selection Guide
Part Number
Packing1
Package
A1174EEWLT-P2
DFN/MLP 1.5×2 mm; 0.40 mm maximum height
3000 pieces per 7-inch reel
1Contact Allegro™ for additional packing options.
2Allegro products sold in DFN package types are not intended for automotive applications.
Absolute Maximum Ratings
Rating
Units
Forward Supply Voltage
Characteristic
Symbol
VDD
Notes
5.0
V
Reverse Supply Voltage
VRDD
–0.3
V
Output Voltage
VOUT
5.0
V
Reverse Output Voltage
VROUT
–0.3
V
EXTERNAL_CLK and DUAL_CLK
Pins Input Voltage
VIN
5.0
V
EXTERNAL_CLK and DUAL_CLK
Pins Reverse Input Voltage
VRIN
–0.3
V
IOUT(sink)
–1
mA
IOUT(source)
1
mA
Continuous Output Current
Magnetic Flux Density*
B
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(MAX)
165
°C
Tstg
–65 to 170
°C
Storage Temperature
Range E
Unlimited
G
–40 to 85
°C
*1G = 0.1 mT (millitesla)
Terminal List
Pin-out Diagram
VDD 1
NC 2
6 DUAL_CLK
PAD
VOUT 3
(Top View)
5 GND
4 EXTERNAL_CLK
Number
Name
1
VDD
2
NC
3
VOUT
4
EXTERNAL_CLK
5
GND
6
DUAL_CLK
Function
Supply Voltage
No connect
Output
In combination with DUAL_CLK , allows external control of the device
sampling period and duty cycle
Ground
In combination with EXTERNAL_CLK , drives the part in Dual Clock mode
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115 Northeast Cutoff
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2
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
Functional Block Diagram
VDD
VOUT
Latch
Amp
Sample Control
Block
EXTERNAL_CLK
DUAL_CLK
Input
Decoder
Internal
Clock
GND
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115 Northeast Cutoff
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3
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
Operating Characteristics Valid over full operating voltage and ambient temperature ranges (unless otherwise specified)
Characteristic
Symbol
Min.
Typ.1
Max.
Unit
TA = 25°C
1.65
–
3.5
V
–40°C ≥ TA ≥ 85°C
1.8
–
3.5
V
–
100
300
mV
Test Conditions
Electrical Characteristics
Supply Voltage2
VDD
Output On Voltage
Supply Current
VOUT(SAT)
NMOS on, IOUT = 1 mA
VOUT(HIGH) PMOS on, IOUT = 1 mA
–
mV
IDD(EN)
Chip in awake state (enabled)
–
–
2.0
mA
IDD(DIS)
Chip in sleep state (disabled)
–
–
8.0
μA
Normal Clock mode, VDD = 2.5 V
–
–
71
μA
IDD(AV)
Internal Chopper Stabilization Clock Frequency
fC
EXTERNAL_CLK and DUAL_CLK Pins Input Current
IIN
Normal Clock mode, VDD = 3.0 V
VEXTERNAL_CLK = VDD, VDUAL_CLK = VDD
EXTERNAL_CLK and DUAL_CLK Pins Leakage Current
IOFF
VEXTERNAL_CLK = 0 V, VDUAL_CLK = 0 V
Supply Slew Rate3
SR
tOFF = 100 ms
VDD – 300 VDD – 100
–
–
82
μA
–
200
–
kHz
–
0.5
–
μA
–
0.02
–
μA
0.1
–
–
V/ms
Normal Clock Mode Characteristics4
Normal Mode Awake Duration
tawake_norm
–
25
46
μs
Normal Mode Period
tperiod_norm
–
0.7
1.05
ms
Vth(HIGH)
–
–
0.75 × VDD
V
Vth(LOW)
0.25 × VDD
–
–
V
External Clock Mode Characteristics4
EXTERNAL_CLK and DUAL_CLK Pins Threshold
External Clock Mode Awake Duration
tawake_ext
VEXTERNAL_CLK > Vth(HIGH)
46
–
–
μs
External Clock Mode Period
tperiod_ext
VEXTERNAL_CLK > Vth(HIGH)
80
–
–
μs
tdelay_ext
–
25
46
μs
Dual Clock Mode Awake Duration
tawake_dual
–
25
46
μs
Dual Clock Mode Fast Sampling Period
tperiod_fast
–
8×
tawake_dual
–
μs
Dual Clock Mode Slow Sampling Period
tperiod_slow
–
28
–
ms
ttimeout
–
100 ×
tperiod_slow
–
ms
State Transition
Delay5
Dual Clock Mode Characteristics4
Dual Clock Mode Timeout6
Magnetic Characteristics2
Operate Point
BOP
South pole to device branded side
5
36
55
G
Release Point
BRP
North pole to device branded side
–55
–36
–5
G
Hysteresis
BHYS
BOP – BRP
–
72
110
G
1Typical
values are at TA = 25°C and VDD = 2.75 V. Performance may vary for individual units, within the specified maximum and minimum limits.
2Magnetic operate and release points vary with supply voltage.
3If the device power supply is chopped, power-up slew rate dV
DD / dt has to be adjusted to ensure correct functioning of the device. tOFF is the time of
the power cycle when VDD < VDD(min).
4Defined in the Functional Description section of this datasheet.
5Time between external clock transition and resulting transition of the device between the awake and sleep states. See Functional Description section.
6If no output transition is detected during the timeout interval, the device goes back into slow sampling. See Functional Description section.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
Characteristic Performance
Saturation Voltage versus Temperature
Saturation Voltage versus Supply Voltage
300
300
250
250
VDD (V)
200
1.65
1.8
2.5
2.75
3.0
3.5
150
100
50
IOUT = 1 mA
200
VOUT(SAT) (mV)
VOUT(SAT) (mV)
IOUT = 1 mA
-40
-20
0
20
40
60
80
85°C
-40°C
25°C
150
100
50
0
-60
TA (°C)
0
100
1.0
1.5
2.0
TA (°C)
100
100
90
90
VDD (V)
1.65
1.8
2.5
3.0
3.5
70
3.5
4.0
60
50
40
80
TA (°C)
70
IDD(AV) (μA)
80
IDD(AV) (μA)
3.0
Average Supply Current versus Supply Voltage
Average Supply Current versus Temperature
85°C
-40°C
25°C
60
50
40
30
30
20
20
10
10
0
0
-60
-40
-20
0
20
40
60
80
100
1.0
1.5
2.0
TA (°C)
2.5
3.0
3.5
4.0
VDD (V)
Normal Mode Period versus Supply Voltage
Normal Mode Period versus Temperature
1000
1000
900
900
800
800
600
500
400
300
700
tperiod (μs)
VDD (V)
1.65
1.8
2.5
3.0
3.5
700
tperiod (μs)
2.5
VDD (V)
600
TA (°C)
500
85°C
-40°C
25°C
400
300
200
200
100
100
0
0
-60
-40
-20
0
20
TA (°C)
40
60
80
100
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VDD (V)
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5
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
Dual Mode Fast Period versus Supply Voltage
Dual Mode Fast Period versus Temperature
400
400
350
350
VDD (V)
250
1.65
1.8
2.5
3.0
3.5
3.5
200
150
100
50
300
tfast_period (μs)
tfast_period (μs)
300
250
TA (°C)
200
85°C
-40°C
25°C
150
100
50
0
-60
-40
-20
0
20
40
60
80
0
100
1.0
1.5
2.0
TA (°C)
50
45
45
40
VDD (V)
1.65
1.8
2.5
3.0
3.5
35
30
25
20
t slow_period (ms)
t slow_period (ms)
50
15
4.0
TA (°C)
35
85°C
-40°C
25°C
30
25
20
15
10
5
5
0
-60
-40
-20
0
20
TA (°C)
40
60
80
100
1.0
1.5
2.0
2.5
VDD (V)
3.0
3.5
4.0
Operate Point versus Supply Voltage
Operate Point versus Temperature
55
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
50
45
VDD (V)
40
1.65
1.8
2.5
2.75
3.0
3.5
35
BOP (G)
(G)
3.5
40
10
0
OP
3.0
Dual Mode Slow Period versus Supply Voltage
Dual Mode Slow Period versus Temperature
B
2.5
VDD (V)
TA (°C)
30
85°C
-40°C
25°C
25
20
15
10
5
-60
-40
-20
0
20
TA (°C)
40
60
80
100
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VCC (V)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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6
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
Release Point versus Temperature
Release Point versus Supply Voltage
0
0
-5
-5
-10
-10
-15
1.65
1.8
2.5
2.75
3.0
3.5
-25
-30
-35
-40
-45
BRP (G)
BRP(G)
-15
VDD (V)
-20
TA (°C)
-25
85°C
-40°C
25°C
-30
-35
-40
-45
-50
-55
-20
-50
-60
-40
-20
0
20
40
60
80
-55
100
1.0
TA (°C)
1.5
2.5
3.0
3.5
4.0
VDD (V)
Hysteresis versus Supply Voltage
Hysteresis versus Temperature
110
110
100
100
90
90
70
60
50
40
30
20
10
VDD (V)
80
TA (°C)
1.65
1.8
2.5
2.75
3.0
3.5
70
85°C
-40°C
25°C
B HYS (G)
80
BHYS(G)
2.0
60
50
40
30
20
10
0
0
-60
-40
-20
0
20
TA (°C)
40
60
80
100
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VDD (V)
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115 Northeast Cutoff
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7
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
Functional Description
Output State Operation
The output state (VOUT pin) of this device switches to low (on)
when an incident magnetic field, perpendicular to the Hall element, exceeds the operate point threshold, BOP . After turn-on,
the output voltage is VOUT(SAT) (see figure 2). When the magnetic
field is reduced below the release point, BRP , the device output
goes high (off), VOUT(HIGH) . The difference in the magnetic operate and release points is the hysteresis, BHYS, of the device. This
built-in hysteresis allows clean switching of the output even in
the presence of external mechanical vibration and electrical noise.
Removal of the magnetic field leaves the device output latched
low (on) if the last crossed switchpoint is BOP , or latched high
(off) if the last crossed switchpoint is BRP .
This is illustrated in figure 3. The awake state duration, tawake_x ,
is common in all defined modes of operation. The sleep state
duration is set at a longer duration than the awake period in order
to conserve power. During the sleep state, current consumption
is insignificant (equal to IDD(DIS)), but the device output does not
switch in response to changing incident magnetic fields.
The device shows maximum current consumption, IDD(EN) , during the awake state and minimal current consumption, IDD(DIS) ,
during the sleep state. Average current, IDD(AV) , for micro-power
operation is derived from following formula:
IDD(AV) = IDD(EN) × tawake_x + IDD(DIS) × tsleep_x
tperiod_x
.
Three micro-power control modes are available:
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) gives an indeterminate output state. The correct
state is attained after the first excursion beyond BOP or BRP .
• Normal Clock mode
Micro-power Operation
Micro-power operation of the device involves duty cycle control
achieved by:
Selection of clock mode is determined by the configuration of
the EXTERNAL_CLK pin and the DUAL_CLK pin, and applied
voltages as illustrated in figure 4 and table 1.
• powering all circuits in the chip and latching the device output
state at the end of awake state periods, and
• turning off the bias current to most circuits in the chip and
maintaining the device output state through sleep state periods.
• External Clock mode
• Dual Clock mode
Normal Clock Mode When both device clock pins are left
floating or are grounded, the internal timing circuitry activates
the device for tawake_norm and deactivates it for the remainder,
tsleep , of the duty cycle period, tperiod_norm. The short awake time
tPeriod
V+
VOUT
Switch to Low
Switch to High
VOUT(HIGH) (off)
I DD(EN)
Awake
Sleep
0
BOP
BRP
VOUT(SAT)(on)
B–
B+
I DD(DIS)
0
Sample and Output Latched
BHYS
Figure 3. Micro-power behavior of the device
Figure 2. Device output switching logic
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Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
allows stabilization prior to the IC sampling and data latching on
the falling edge of the timing pulse. The output during the sleep
time, tsleep , is latched in the last sampled state.
External Clock Mode Applying a voltage greater than
Vth(HIGH) to both clock pins puts the device into the awake state
(without automatic cycling through the sleep state). The device
uses the maximum defined supply current, reaching maximum
power consumption.
Applying a voltage greater than Vth(HIGH) to the EXTERNAL_
CLK pin and a voltage lower than Vth(LOW) to the DUAL_CLK
pin puts the device into the sleep state (without automatic cycling
through the awake state), and latches the device output in the
output state determined during the prior awake state.
The duration of the awake and sleep periods can be controlled
externally by applying a voltage greater than Vth(HIGH) to the
EXTERNAL_CLK pin and applying an external clock to the
DUAL_CLK pin. The user can define the input sampling time
and frequency to reach a target consumption current level, but the
minimum sample time must remain longer than tawake_ext. Note
that the device should be periodically put into the awake state in
order to update the device output state.
State Transition Delay, text_delay , appears as the time between
an external clock transition and the resulting transition of the
device between the awake and the sleep state. This is illustrated
in figure 5.
Dual Clock Mode When the EXTERNAL_CLK pin is left
floating, or is grounded, and the DUAL_CLK pin is pulled to
a voltage greater than Vth(HIGH) , the device enters Dual Clock
mode. Figure 6 gives an overview of the device operation algorithm in Dual Clock mode.
Table 1. Clock Mode Selection Options
Connection
Mode
Description
EXTERNAL_CLK Pin
DUAL_CLK Pin
Low / NC
Low / NC
Normal Clock
High
External Clock, Awake State
Low
External Clock, Sleep State
High
Dual Clock
High
Low / NC
Awake and sleep state durations
defined by device internal clock
Awake and sleep state durations
defined by external clock
Awake and sleep state durations
defined by internal fast or slow clock
High = V ≥ Vth(HIGH) , Low = V ≤ Vth(LOW) , NC = no connect (float or connect to ground)
Power on
EXTERNAL_CLK
pin high?
NO
DUAL_CLK
pin high?
NO
Dual Clock Mode
DUAL_CLK
pin high?
NO
External Clock Mode
Sleep State
Figure 4. Clock mode selection algorithm; determined by clock pins
connections in the application
tdelay_ext
tdelay_ext
Internal
Clocking
Normal Clock Mode
YES
External Clock Mode
Awake State
tawake_ext
External
Clocking
YES
YES
tsleep_ext
Device Awake State
Supply
Current
Device Sleep State
IDD(EN)
IDD(DIS)
Figure 5. External Clock mode clocking; tdelay_ext corresponding to the
device transition delay into the awake or sleep states after an external
clock transition
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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9
A1174
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
Initially, the device operates in the slow sampling state with a
typical sleep time duration, tsleep_slow . The awake time duration,
tawake , is common in all defined modes of operation. After the
first output state transition, the device switches into the fast sampling state, with a sleep time duration, tsleep_fast , of 8 × tawake_dual.
Fast input sampling ensures that the device does not miss any
subsequent transitions of the incident magnetic field. This is
advantageous in applications such as track ball monitoring, when
Dual Clock Mode
Initial State
the track ball can be rotated at very high speeds. If there is no
output switching for the duration of the specified timeout, ttimeout,
then the device switches back into the slow sampling state to
conserve battery life in handheld devices.
Figure 7 shows the case in which the field does not change within
the ttimeout period. The behavior of the device in the presence of a
rapidly changing magnetic field is shown in figure 8.
Set SleepTimer
to tsleep_slow
Magnetic
field change?
YES
Update device
output
NO
ReturnTimer
expired ?
NO
Reset
ReturnTimer
to ttimeout
YES
Set SleepTimer
to tsleep_slow
Has
SleepTimer
expired?
Set SleepTimer
to tsleep_fast
NO
YES
Sample magnetic field
during tawake_dual
Figure 6. Dual Clock mode operation algorithm
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10
Magnetic Field (G)
50
0
-50
0
1000
2000
3000
(ms)
4000
5000
6000
0
1000
2000
3000
(ms)
4000
5000
6000
0
1000
2000
3000
(ms)
4000
5000
6000
0
1000
2000
3000
(ms)
4000
5000
6000
Output
Off
On
Clock
High
Supply Current (μA)
Low
300
200
100
0
Magnetic Field (G)
Figure 7. Device output response in Dual Clock mode with no change of the
magnetic field for the duration of ttimeout
50
0
-50
0
1000
2000
3000
(ms)
4000
5000
6000
0
1000
2000
3000
(ms)
4000
5000
6000
0
1000
2000
3000
(ms)
4000
5000
6000
0
1000
2000
3000
(ms)
4000
5000
6000
Output
Off
On
Clock
High
Low
Supply Current (μA)
A1174
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
400
200
0
Figure 8. Device output response in Dual Clock mode with a rapid change of the
magnetic field
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11
A1174
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
Application Information
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to reduce both external noise and
noise generated by the chopper stabilization technique (0.1 μF
is a typical value). Additionally, it is recommended that, when
possible, pins be tied to either the VDD pin or ground potential in
order to improve the EMC performance of the device. However,
it is feasible to float the EXTERNAL_CLK and DUAL_CLK
pins in the application. In the case where these pins are floating,
care should be taken to locate the device as far as possible from
system antennas and transceivers.
VDD
EXTERNAL_CLK
DUAL_CLK
Vbat
A1174
VOUT
Cbypass
(A)
GND
The schematics on this page represent typical application circuits.
(A) Device is working in Normal Clock mode. Power consumption is determined by device internal clock.
VDD
EXTERNAL_CLK
(B) Device is working in Dual Clock mode. Power consumption
is determined by device internal clock; frequent usage of device
in fast sampling state.
(C) Device is working in External Clock mode; externally-controlled power consumption.
Vbat
A1174
VOUT
DUAL_CLK
Cbypass
(B)
GND
(D) Device is working in External Clock mode; high power consumption.
VDD
Vbat
EXTERNAL_CLK
DUAL_CLK
A1174
VOUT
Cbypass
(C)
GND
VDD
EXTERNAL_CLK
DUAL_CLK
(D)
Vbat
A1174
VOUT
Cbypass
GND
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
Package EW 6-Contact MLP/DFN
1.50 ±0.15
0.75 F
E
6
0.50
0.30
6
1.00 F
2.00 ±0.15
A
0.70
1.575
F
1
1
0.325
1.10
7X
D
SEATING
PLANE
0.08 C
C
C
PCB Layout Reference View
0.38 ±0.02
0.50 BSC
B
+0.055
0.325 –0.045
0.70 ±0.10
NN
YWW
0.25 ±0.05
1
1
1.25 ±0.05
G
Standard Branding Reference View
N = Last two digits of device part number
Y = Last digit of year of manufacture
W = Week of manufacture
6
1.10 ±0.10
For Reference Only, not for tooling use (refernce DWG-2856; similar to
JEDEC Type 1, MO-229X2BCD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
SON50P200X200X100-9M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
E Active Area Depth 0.15 mm REF
F Hall Element (not to scale)
G Branding scale and appearance at supplier discretion
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
A1174
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
Revision History
Revision
Revision Date
Rev. 7
October 26, 2011
Description of Revision
Update Selection Guide
Copyright ©2008-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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