X9421
®
Low Noise/Low Power/SPI Bus
Data Sheet
September 23, 2005
Single Digitally Controlled (XDCP™)
Potentiometer
FN8196.1
DESCRIPTION
The X9421 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
FEATURES
• Single Voltage Potentiometer
• 64 Resistor Taps
• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Wiper Resistance, 150Ω Typical at 5V
• 4 Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
• Standby Current < 5µA Max
• VCC : 2.7V to 5.5V Operation
• 2.5kΩ, 10kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes per Bit per
Register
• 14 Ld TSSOP, 16 Ld SOIC
• Low Power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
The digital controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to
and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
address
data
status
SPI
bus
interface
RH/VH
write
read
transfer
inc / dec
Wiper Counter
Register (WCR)
Bus
Interface &
Control
control
VSS
1
10kΩ
Power-on Recall
64-taps
wiper
POT
Data Registers
4 Bytes
RW/VW
RL/VL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9421
Ordering Information
PART NUMBER
PART MARKING VCC LIMITS (V)
X9421YS16*
X9421YS
X9421YS16Z* (Note)
X9421YS Z
5 ±10%
POTENTIOMETER
ORGANIZATION
(kΩ)
TEMP RANGE (°C)
2.5
X9421YS16I*
X9421YS16IZ* (Note)
X9421YS Z I
PACKAGE
0 to 70
16 Ld SOIC (300 mil)
0 to 70
16 Ld SOIC (300 mil) (Pb-free)
-40 to 85
16 Ld SOIC (300 mil)
-40 to 85
16 Ld SOIC (300 mil) (Pb-free)
X9421YV14*
0 to 70
14 Ld TSSOP (4.4mm)
X9421YV14I*
-40 to 85
14 Ld TSSOP (4.4mm)
X9421WS16*
X9421WS
X9421WS16Z* (Note)
0 to 70
16 Ld SOIC (300 mil)
X9421WS Z
0 to 70
16 Ld SOIC (300 mil) (Pb-free)
X9421WS16I*
X9421WS I
-40 to 85
16 Ld SOIC (300 mil)
X9421WS16IZ* (Note)
X9421WS Z I
-40 to 85
16 Ld SOIC (300 mil) (Pb-free)
X9421WV14*
X9421WV
0 to 70
14 Ld TSSOP (4.4mm)
X9421WV14I*
X9421WV I
-40 to 85
14 Ld TSSOP (4.4mm)
X9421YS16-2.7*
X9421YS16Z-2.7* (Note)
10
2.7 to 5.5
2.5
X9421YS Z F
X9421YS16I-2.7*
X9421YS16IZ-2.7* (Note)
X9421YS Z G
X9421YV14-2.7*
0 to 70
16 Ld SOIC (300 mil)
0 to 70
16 Ld SOIC (300 mil) (Pb-free)
-40 to 85
16 Ld SOIC (300 mil)
-40 to 85
16 Ld SOIC (300 mil) (Pb-free)
0 to 70
14 Ld TSSOP (4.4mm)
-40 to 85
14 Ld TSSOP (4.4mm)
X9421YV14I-2.7*
X9421YV G
X9421WS16-2.7*
X9421WS F
X9421WS16Z-2.7* (Note)
X9421WS Z F
X9421WS16I-2.7*
X9421WS G
-40 to 85
16 Ld SOIC (300 mil)
X9421WS16IZ-2.7* (Note)
X9421WS Z G
-40 to 85
16 Ld SOIC (300 mil) (Pb-free)
X9421WV14-2.7*
X9421WV F
0 to 70
14 Ld TSSOP (4.4mm)
X9421WV14I-2.7*
X9421WV G
-40 to 85
14 Ld TSSOP (4.4mm)
10
0 to 70
16 Ld SOIC (300 mil)
0 to 70
16 Ld SOIC (300 mil) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8196.1
September 23, 2005
X9421
DETAILED FUNCTIONAL DIAGRAM
VCC
Power-on Recall
DR0
DR1
HOLD
Control
CS
SCK
SO
SI
DR2 DR3
INTERFACE
AND
CONTROL
CIRCUITRY
A0
WIPER
COUNTER
REGISTER
(WCR)
10kΩ
64--taps
RH/VH
RL/VL
RW/VW
DATA
WP
VSS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage
amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
3
FN8196.1
September 23, 2005
X9421
PIN CONFIGURATION
TSSOP
SOIC
VCC
S0
1
14
VCC
NC
1
16
NC
2
13
RL/VL
SO
2
15
NC
NC
3
12
RH/VH
NC
3
14
RL/VL
CS
SCK
4
11
RW/VW
CS
4
13
RH/VH
5
10
SCK
5
12
RW/VW
SI
6
SI
6
11
HOLD
VSS
7
9
8
HOLD
A0
WP
NC
VSS
7
10
A0
8
9
WP
X9421
X9421
PIN ASSIGNMENTS
TSSOP pin
SOIC pin
Symbol
1
2
SO
Serial Data Output
2
3
NC
No Connect
NC
No Connect
3
Brief Description
4
4
CS
Chip Select
5
5
SCK
Serial Clock
6
6
SI
Serial Data Input
7
8
VSS
System Ground
8
9
WP
Hardware Write Protect
9
10
A0
Device Address
10
11
HOLD
Device select. Pause the serial bus.
11
12
RW / V W
Wiper Terminal of the Potentiometer.
12
13
R H / VH
High Terminal of the Potentiometer.
13
14
RL / V L
Low Terminal of the Potentiometer.
14
16
VCC
System Supply Voltage
1
NC
No Connect
7
NC
No Connect
15
NC
No Connect
4
FN8196.1
September 23, 2005
X9421
PIN DESCRIPTIONS
Potentiometer Pins
Host Interface Pins
VH/RH, VL/RL
Serial Output (SO)
The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
VW/RW
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched
by the rising edge of the serial clock.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9421.
Chip Select (CS)
When CS is HIGH, the X9421 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9421, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
System/Digital Supply (VCC)
VCC is the supply voltage for the system/digital
section. VSS is the system ground.
PRINCIPLES OF OPERATION
The X9421 is a highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing
direct communication between the host and the XDCP
potentiometer.
Serial Interface
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
The X9421 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
Device Address (A0)
The address input is used to set the least significant bit
of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9421. A maximum of 2 devices may occupy the
SPI serial bus.
5
The X9421 is comprised of one resistor array
containing 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
FN8196.1
September 23, 2005
X9421
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within the individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches. The block
diagram of the potentiometer is shown in Figure 1.
Wiper Counter Register (WCR)
The X9421 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9421 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Data Registers
The potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of the Data Registers is
a nonvolatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Register Descriptions
Table 1. Data Registers, (6-bit), Nonvolatile
0
0
(MSB)
D5
D4
D3
D2
D1
D0
(LSB)
There are four 6-bit Data Registers associated with the
potentiometer.
– {D5~D0}: These bits are for general purpose Nonvolatile data storage or for storage of up to four different wiper values.
Table 2. Wiper Counter Register, (6-bit), Volatile
0
(MSB)
0
WP5 WP4 WP3 WP2 WP1 WP0
(LSB)
– {WP5~WP0}: These bits specify the wiper position
of the potentiometer.
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FN8196.1
September 23, 2005
X9421
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
VH
Serial
Bus
Input
From Interface
Circuitry
Register 0
8
REGISTER 2
C
O
U
N
T
E
R
Register 1
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
REGISTER 3
D
E
C
O
D
E
INC/DEC
Logic
IF WCR = 00[H] THEN VW = VL
IF WCR = 3F[H] THEN VW = VH
UP/DN
Modified SCK
UP/DN
VL
CLK
VW
Write in Process
Figure 2. Address/Identification Byte Format
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
Device Type
Identifier
0
1
0
1
1
1
0
A0
Device Address
INSTRUCTIONS
Address/Identification (ID) Byte
Instruction Byte
The first byte sent to the X9421 from the host,
following a CS going HIGH to LOW, is called the
Address or Identification byte. The most significant
four bits of the slave address are a device type
identifier, for the X9421 this is fixed as 0101[B] (refer
to Figure 2).
The next byte sent to the X9421 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four Data Registers. The format is
shown below in Figure 3.
The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address
is defined by the state of the A0 input pin. The X9421
compares the serial data stream with the address
input state; a successful compare of the address bit is
required for the X9421 to successfully continue the
command sequence. The A0 input can be actively
driven by a CMOS input signal or tied to VCC or VSS.
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
0
0
Instructions
The remaining three bits in the ID byte must be set to 110.
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FN8196.1
September 23, 2005
X9421
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits are defined as 0.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9421; either between the host and
one of the Data Registers or directly between the host
and the WCR. These instructions are:
Two of the eight instructions are two bytes in length
and end with the transmission of the instruction byte.
These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the pot,
– Write Wiper Counter Register—change current
wiper position of the pot,
– XFR Data Register to Wiper Counter Register —
This instruction transfers the contents of one specified Data Register to the Wiper Counter Register.
– Read Data Register—read the contents of the
selected data register;
– XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by tWRL. A transfer from
the WCR (current wiper position), to a Data Register is
a write to nonvolatile memory and takes a minimum of
tWR to complete. The transfer can occur between the
potentiometer and one of its associated registers.
The sequence of these operations is shown in Figure
5 and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of
the sequence and timing for this operation are shown
in Figure 7 and Figure 8.
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
8
1
0
1
1
1
0
A0
I3
I2
I1
I0
R1 R0
0
0
FN8196.1
September 23, 2005
X9421
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
1
0
1
1
1
0
A0
I3
I2
I1 I0
R1 R0
0
0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
1
0
1
1
1
0
A0
I3
I2
I1 I0
R1 R0 0
0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
1
1
0
A0
I3
I2
I1
I0
0
0
0
0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Figure 8. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW
INC/DEC CMD Issued
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FN8196.1
September 23, 2005
X9421
Table 3. Instruction Set
I3
I2
Instruction Set
I1 I0 R1 R0
1
0
0
1
0
0
0
0
Read the contents of the Wiper Counter Register
1
0
1
0
0
0
0
0
Write new value to the Wiper Counter Register
Read Data Register
1
0
1
1
1/0
1/0
0
0
Write Data Register
1
1
0
0
1/0
1/0
0
0
Instruction
Read Wiper Counter
Register
Write Wiper Counter
Register
Operation
Read the contents of the Data Register pointed to
by R1 - R0
Write new value to the Data Register pointed to by
R1 - R0
XFR Data Register to
Wiper Counter
Register
XFR Wiper Counter
Register to Data
Register
Increment/Decrement
Wiper Counter
Register
1
1
0
1
1/0
1/0
0
0
Transfer the contents of the Data Register pointed
to by R1 - R0 to the Wiper Counter Register
1
1
1
0
1/0
1/0
0
0
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by R1 - R0
0
0
1
0
0
0
0
0
Enable Increment/decrement of the Wiper Counter
Register
Read Status (WIP bit)
0
1
0
1
0
0
0
1
Read the status of the internal write cycle, by
checking the WIP bit.
10
FN8196.1
September 23, 2005
X9421
Instruction Format
Notes: (1) “A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
device
instruction
wiper position
identifier
addresses
opcode
(sent by X9421 on SO)
CS
CS
Falling
Rising
W W W W W W
Edge 0 1 0 1 1 1 0 A 1 0 0 1 0 0 0 0 0 0 P P P P P P Edge
0
5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by Host on SI)
CS
CS
Falling
W W W W W W Rising
Edge 0 1 0 1 1 1 0 A 1 0 1 0 0 0 0 0 0 0 P P P P P P Edge
0
5 4 3 2 1 0
Read Data Register (DR)
Read the contents of the Register pointed to by R1 - R0.
device type
device
instruction
register
Data Byte
identifier
addresses
opcode
addresses
(sent by X9421 on SO)
CS
CS
Falling
Rising
W W W W W W
Edge 0 1 0 1 1 1 0 A 1 0 1 1 R R 0 0 0 0 P P P P P P Edge
0
1 0
5 4 3 2 1 0
Write Data Register (DR)
Write a new value to the Register pointed to by R1 - R0.
device type
device
identifier
addresses
instruction
opcode
register
addresses
Data Byte
(sent by host on SI)
CS
CS
Falling
W W W W W W Rising
Edge 0 1 0 1 1 1 0 A 1 1 0 0 R R 0 0 0 0 P P P P P P Edge
0
1 0
5 4 3 2 1 0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1 - R0 to the WCR.
device type
device
instruction
register
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 1 1 0 A 1 1 0 1 R R 0 0 Edge
0
1 0
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September 23, 2005
X9421
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction
register
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 1 1 0 A 1 1 1 0 R R 0 0 Edge
0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
device type
device
instruction
increment/decrement
CS
CS
identifier
addresses
opcode
(sent by master on SDA)
Falling
Rising
Edge 0 1 0 1 1 1 0 A 0 0 1 0 0 0 0 0 I/D I/D . . . . I/D I/D Edge
0
Read Status
device type
device
instruction
Data Byte
identifier
addresses
opcode
(sent by X9421 on SO)
CS
CS
Falling
Rising
W
Edge 0 1 0 1 1 1 0 A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
0
P
12
FN8196.1
September 23, 2005
X9421
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias. . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on SCK any address input
with respect to VSS. . . . . . . . . . . . . . . . . .-1V to +7V
∆V = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Lead temperature (soldering, 10 seconds) . . . . . . 300°C
IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . .±6mA
Any VH/RH, VL/RL, VW/RW . . . . . . . . . . . VSS to VCC
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9421
X9421-2.7
Supply Voltage (VCC) Limits
5V ± 10%
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
IW
RW
Parameter
Min.
End to End Resistance Tolerance
Power Rating
Wiper Current
Wiper Resistance
Limits
Typ.
Max.
±20
50
±3
150
250
400
VTERM
CH/CL/CW
IAL
Voltage on any VH/RH, VL/RL, VW/RW
Noise
Resolution(4)
Absolute Linearity(1)
Relative Linearity(2)
Temperature Coefficient of RTOTAL
Ratiometric Temperature
Coefficient
Potentiometer Capacitances
Rh, RI, Rw leakage current
VSS
Test Conditions
25°C, each pot
Wiper Current = ± 1mA,
VCC = 5V
Wiper Current = ± 1mA,
VCC = 3V
1000
Ω
VCC
V
±1
±0.2
±20
dBV
%
MI(3)
MI(3)
ppm/°C
ppm/°C
Ref: 1kHz
See Note 5
Vw(n)(actual) - Vw(n)(expected)
Vw(n + 1) - [Vw(n) + MI]
See Note 5
See Note 5
10
pF
µA
See Circuit #3
Vin = Vss to Vcc. Device is in
stand-by mode.
-120
1.6
±300
10/10/25
0.1
Units
%
mW
mA
Ω
VSS = 0V
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as
a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH - VL)/63, single pot
(4) Typical = Individual array resolution.
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
VCC Supply Current
(Active)
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC2
VCC Supply Current
(Non-volatile Write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC Current (Standby)
1
µA
SCK = SI = VSS, Addr. = VSS
ILI
Input Leakage Current
10
µA
VIN = VSS to VCC
ILO
Output Leakage Current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW Voltage
-0.5
VCC x 0.1
V
VOL
Output LOW Voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum Endurance
100,000
Data Changes per Bit per Register
Data Retention
100
Years
CAPACITANCE
Symbol
COUT
CIN
Test
Max.
Units
Test Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (A0, SI, and SCK)
6
pF
VIN = 0V
(5)
(5)
POWER-UP TIMING
Symbol
Parameter
Max.
Max.
Units
tRVCC(5)
VCC Power-up Ramp
0.2
50
V/msec
POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC and then the potentiometer pins, RH, RL, and RW. Voltage
should not be applied to the potentiometer pins before VCC is applied. The VCC ramp rate specification should be
met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not
reverse polarity by more than 0.5V. Recall of wiper position will not be complete until VCC reaches its final value.
Notes: (5) This parameter is periodically sampled and not 100% tested.
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x
0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
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EQUIVALENT A.C. LOAD CIRCUIT
5V
Circuit #3 SPICE Macro Model
2.7V
RTOTAL
RH
1533Ω
CL
CH
CW
RL
10pF
SDA Output
10pF
100pF
25pF
100pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Units
2.0
MHz
fSCK
SSI/SPI Clock Frequency
tCYC
SSI/SPI Clock Cycle Time
500
ns
tWH
SSI/SPI Clock High Time
200
ns
tWL
SSI/SPI Clock Low Time
200
ns
tLEAD
Lead Time
250
ns
tLAG
Lag Time
250
ns
tSU
SI, SCK, HOLD and CS Input Setup Time
50
ns
tH
SI, SCK, HOLD and CS Input Hold Time
50
ns
tRI
SI, SCK, HOLD and CS Input Rise Time
2
µs
tFI
SI, SCK, HOLD and CS Input Fall Time
2
µs
500
ns
100
ns
tDIS
SO Output Disable Time
0
tV
SO Output Valid Time
tHO
SO Output Hold Time
tRO
SO Output Rise Time
50
ns
tFO
SO Output Fall Time
50
ns
0
ns
tHOLD
HOLD Time
400
ns
tHSU
HOLD Setup Time
100
ns
tHH
HOLD Hold Time
100
ns
tHZ
HOLD Low to Output in High Z
100
ns
tLZ
HOLD High to Output in Low Z
100
ns
TI
Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs
20
ns
tCS
CS Deselect Time
2
µs
tWPASU
WP, A0 and A1 Setup Time
0
ns
tWPAH
WP, A0 and A1 Hold Time
0
ns
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HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
tWR
High-voltage Write Cycle Time (Store Instructions)
5
10
ms
XDCP TIMING
Symbol
Parameter
Min.
Max. Units
tWRPO
Wiper Response Time After The Third (Last) Power Supply Is Stable
10
µs
tWRL
Wiper Response Time After Instruction Issued (All Load Instructions)
10
µs
tWRID
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement
Instruction)
450
ns
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
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TIMING DIAGRAMS
Input Timing
tCS
CS
tLAG
tCYC
tLEAD
SCK
...
tSU
tH
tWL
...
MSB
SI
tRI
tFI
tWH
LSB
High Impedance
SO
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
SCK
tHH
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
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XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
SI
...
MSB
LSB
VW
SO
High Impedance
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
...
VW
SI
SO
ADDR
Inc/Dec
Inc/Dec
...
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
tWPAH
WP
A0
A1
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APPLICATIONS INFORMATION
Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solidstate potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory
used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
VR
VR
VH
VW
VL
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Basic Circuits
Buffered Reference Voltage
Cascading Techniques
R1
+V
Noninverting Amplifier
+5V
+V
+V
VS
+5V
VW
VW
X
-5V
VOUT = VW
–
VO
–
OP-07
+
LM308A
+
VW
R2
+V
-5V
R1
VW
(a)
Offset Voltage Adjustment
Voltage Regulator
VIN
VO = (1+R2/R1)VS
(b)
VO (REG)
317
R1
Comparator with Hysterisis
R2
VS
VS
–
VO
+
100kΩ
R1
–
VO
+
}
TL072
R2
}
Iadj
R1
R2
10kΩ
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
10kΩ
+12V
19
10kΩ
VUL = {R1/CR1+R2} VO(max)
VLL = {R1/CR1+R2} VO(min)
-12V
FN8196.1
September 23, 2005
X9421
PACKAGING INFORMATION
16-Lead Plastic SOIC (300 Mil Body) Package Type S
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.403 (10.2 )
0.413 ( 10.5)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50) X 45°
0.050" Typical
0° - 8 °
0.0075 (0.19)
0.010 (0.25)
0.050"
Typical
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
16 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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