3-phase Inverter IPM Application Note using the STK5U4UFxx series

 AND9426/D
3-phase Inverter IPM
Application Note
using the STK5U4UFxx series
www.onsemi.com
1. Product synopsis APPLICATION NOTE
This application note provides practical guidelines for designing with the STK5U4UFxx series. The STK5U4UFxx series of Intelligent Power Modules (IPM) for three‐phase motor drives contains the IGBT’s, gate drivers and protection functions for a three‐phase inverter. The key functions are outlined below:  Highly integrated device containing independent gate drivers with isolated power stages for the high‐side. Each high‐side driver has a control input and a fault detection output sharing the same power supply driver. These signals require additional isolation in their connection to the control circuit.  Output stage uses IGBT/FRD technology. The drivers implement Under Voltage Protection (UVP) and Short Circuit Protection (DESATP) with a Fault Detection output flag. Internal Boost diodes are provided for high‐side gate boost drive.  Separate pins for each of the three Low‐side emitter terminals  Thermistor for substrate temperature measurement.  Single control power supply due to internal bootstrap circuit for high‐side pre‐driver circuit. An external flyback power supply may also be used.  The modules are provided in a DIP package with screw holes for easy mounting of the heatsink. A simplified block diagram of a motor control system is shown in Figure 1. PWM1
PWM3
PWM5
PWM1
PWM3
PWM5
AC
Opto
isolator
Gate
Driver
Motor
MCU
PWM4
PWM2
PWM0
Opto
isolator
Gate
Driver
PWM0
PWM2
PWM4
Figure 1. Motor Control System Block Diagram © Semiconductor Components Industries, LLC, 2016
April 2016 - Rev. 0
1
Publication Order Number:
AND9426/D
AND9426/D
2. Product description Table1 gives an overview of the device. For package drawing, please refer to Chapter 6.
Device Package Voltage (VCEmax) Current (Ic) Peak current (Ic) Isolation voltage Input logic Shunt resistor STK5U4UF90D‐E 15A 30A STK5U4UFB0D‐E STK5U4UFE0D‐E DIP‐C2 1200V 25A 50A 50A 100A 2500V Active‐low triple shunts / external Table 1. Device Overview VDU (29)
VP (33,34,35)
FoU (31)
HINU (30)
Gate Driver
With
Desaturation
Protection
GNDU (32)
U (39,40,41)
VDV (22)
FoV (24)
HINV (23)
Gate Driver
With
Desaturation
Protection
GNDV (25)
V (45,46,47)
VDW (15)
FoW (17)
HINW (16)
Gate Driver
With
Desaturation
Protection
W (51,52,53)
GNDW (18)
VDN (10)
GND (11)
LINU (8)
Gate Driver
With
Desaturation
Protection
NU (57,58)
LINV (7)
Gate Driver
With
Desaturation
Protection
NV (60,61)
FoN (5)
LINW (6)
Gate Driver
With
Desaturation
Protection
NW (63,64)
TH1 (3)
TH2 (2)
Figure 2. Internal Block Diagram www.onsemi.com
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The module has independent gate drivers for each of the six IGBTs. It is possible to easily drive the IGBT by connecting the isolated control signal to the IPM. The high‐side drive is used with a bootstrap circuit to generate the higher voltage needed for gate drive. The Boost diodes are internal to the part and sourced from VDN (15V). 3. Performance test guidelines The methods used to test some datasheet parameters are shown in Figures 3 to 7. 3.1.
Switching time definition and performance test method active low Input signal Figure 3. Switching time definition Ex) Low side U phase measurement
VP
VDU
VD1=15V
GNDU
VDV
VD2=15V
GNDV
U
VDW
VD3=15V
VCC
CS
GNDW
VDN
Io
VD4=15V
Input signal
NU
LINU
GND
Figure 4. Evaluation circuit (Inductive load) IPM
Ho
CS
Driver
Input signal
VCC
U,V,W
Lo
Io
Input signal
Io
Figure 5. Switching loss measurement circuit www.onsemi.com
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IPM
Ho
CS
Driver
VCC
U,V,W
Lo
Input signal
Io
Input signal
Io
Figure 6. R.B.SOA measurement circuit IPM
Ho
CS
Driver
VCC
U,V,W
Lo
Input signal
Io
Input signal
Io
Figure 7. S.C.SOA measurement circuit www.onsemi.com
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3.2.
Thermistor Characteristics The thermistor is built‐in between TH1 pin and TH2 pin. This is used to sense the temperature of the in‐
ternal module. Its characteristic is outlined below. Parameter
Symbol
Condition
Min
Typ.
Max
Unit
Resistance
R25
Tc = 25C
97
100
103
kΩ
Resistance
R100
Tc = 100C
5.07
5.38
5.71
kΩ
Temperature range
-
-
40
-
+125
C
Table 2. NTC Thermistor value Thermistor resistance Rt versus Case temperature Tc
Thermistor resistance Rt [kΩ]
10000
1000
min
typ
max
100
10
1
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
Case temperature Tc [C]
Figure 8. typical NTC value versus temperature www.onsemi.com
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Tc [°C] ‐40 ‐39 ‐38 ‐37 ‐36 ‐35 ‐34 ‐33 ‐32 ‐31 ‐30 ‐29 ‐28 ‐27 ‐26 ‐25 ‐24 ‐23 ‐22 ‐21 ‐20 ‐19 ‐18 ‐17 ‐16 ‐15 ‐14 ‐13 ‐12 ‐11 ‐10 ‐9 ‐8 ‐7 ‐6 ‐5 ‐4 ‐3 ‐2 ‐1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resistance value [kΩ] Min Typ Max 4106.85 4397.12 4703.67 3825.43 4092.87 4375.08 3565.18 3811.72 4071.64 3324.37 3551.75 3791.26 3101.43 3311.24 3532.05 2894.91 3088.60 3292.28 2703.51 2882.40 3070.35 2526.01 2691.31 2864.84 2361.33 2514.14 2674.42 2208.45 2349.78 2497.90 2066.46 2197.23 2334.16 1934.52 2055.56 2182.21 1811.84 1923.93 2041.12 1697.72 1801.57 1910.05 1591.52 1687.77 1788.23 1492.64 1581.88 1674.95 1400.33 1483.10 1569.35 1314.32 1391.11 1471.07 1234.13 1305.41 1379.57 1159.35 1225.53 1294.33 1089.56 1151.04 1214.89 1024.41 1081.54 1140.82 963.55 1016.66 1071.73 906.69 956.08 1007.25 853.54 899.48 947.04 803.83 846.58 890.80 757.31 797.11 838.25 713.77 750.83 789.11 673.00 707.52 743.15 634.80 666.97 700.14 599.00 628.99 659.88 565.38 593.34 622.12 533.86 559.93 586.75 504.28 528.60 553.60 476.51 499.21 522.52 450.44 471.63 493.37 425.98 445.77 466.06 403.00 421.48 440.41 381.38 398.65 416.33 361.05 377.19 393.70 341.92 357.01 372.43 323.90 338.01 352.41 306.93 320.12 333.58 290.94 303.29 315.87 275.88 287.43 299.20 261.69 272.50 283.50 248.30 258.43 268.72 235.68 245.16 254.79 223.77 232.65 241.66 212.53 220.85 229.28 201.92 209.71 217.61 191.89 199.20 206.59 182.42 189.27 196.19 173.47 179.89 186.38 165.01 171.03 177.11 157.01 162.65 168.35 Tc [°C] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Resistance value [kΩ] Min Typ Max 149.43 154.73 160.07 142.26 147.23 152.24 135.48 140.14 144.83 129.06 133.43 137.83 122.97 127.08 131.21 117.21 121.07 124.94 111.75 115.37 119.00 106.57 109.97 113.38 101.66 104.85 108.05 97.00 100.00 103.00 92.49 95.40 98.31 88.22 91.03 93.85 84.16 86.89 89.62 80.32 82.96 85.60 76.67 79.22 81.79 73.20 75.68 78.16 69.91 72.31 74.72 66.78 69.10 71.44 63.81 66.06 68.33 60.99 63.17 65.36 58.31 60.42 62.54 55.76 57.80 59.86 53.33 55.31 57.30 51.02 52.93 54.87 48.82 50.68 52.55 46.73 48.53 50.35 44.74 46.48 48.24 42.85 44.53 46.24 41.04 42.67 44.33 39.32 40.90 42.51 37.68 39.21 40.77 36.12 37.60 39.11 34.63 36.06 37.53 33.20 34.60 36.01 31.85 33.19 34.57 30.55 31.86 33.19 29.32 30.58 31.88 28.14 29.37 30.62 27.01 28.20 29.42 25.94 27.09 28.27 24.91 26.03 27.17 23.93 25.01 26.12 22.99 24.04 25.12 22.09 23.11 24.16 21.24 22.22 23.24 20.42 21.37 22.36 19.63 20.56 21.52 18.88 19.78 20.71 18.16 19.04 19.94 17.47 18.32 19.20 16.82 17.64 18.49 16.19 16.99 17.81 15.58 16.36 17.16 15.01 15.76 16.54 14.45 15.18 15.94 13.92 14.63 15.36 Tc [°C] 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 Table 3. NTC Thermistor Resistance Values www.onsemi.com
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Resistance value [kΩ] Min Typ Max 13.41 14.10 14.81 12.92 13.59 14.28 12.45 13.10 13.77 12.01 12.64 13.29 11.58 12.19 12.82 11.16 11.76 12.37 10.77 11.34 11.94 10.39 10.95 11.53 10.02 10.57 11.13 9.67 10.20 10.75 9.33 9.85 10.38 9.01 9.51 10.03 8.70 9.18 9.69 8.40 8.87 9.36 8.11 8.57 9.05 7.84 8.28 8.75 7.57 8.01 8.46 7.32 7.74 8.18 7.07 7.48 7.91 6.84 7.23 7.65 6.61 7.00 7.40 6.39 6.77 7.16 6.18 6.55 6.93 5.98 6.34 6.71 5.78 6.13 6.49 5.60 5.93 6.29 5.41 5.74 6.09 5.24 5.56 5.90 5.07 5.38 5.71 4.91 5.21 5.53 4.76 5.05 5.36 4.61 4.89 5.19 4.46 4.74 5.03 4.32 4.59 4.88 4.19 4.45 4.73 4.06 4.32 4.59 3.93 4.18 4.45 3.81 4.06 4.31 3.69 3.93 4.19 3.58 3.82 4.06 3.47 3.70 3.94 3.37 3.59 3.82 3.27 3.48 3.71 3.17 3.38 3.60 3.08 3.28 3.50 2.99 3.19 3.40 2.90 3.09 3.30 2.81 3.00 3.20 2.73 2.92 3.11 2.65 2.83 3.02 2.57 2.75 2.94 2.50 2.67 2.85 2.43 2.60 2.77 2.36 2.52 2.70 AND9426/D
4. Protective functions and Operation Sequence This chapter describes the protection functions.  short circuit protection (Desaturation Protection function ,DESATP)  under Voltage protection (UVP) 4.1.
Short circuit protection (Desaturation Protection function, DESATP) The Desaturation Protection function (DESATP) is implemented by comparing the saturated voltage be‐
tween the collector and the emitter of IGBT to an internal reference of 6.5V (typ). If a short circuit occurs after the IGBT is turned on and saturated, the delay time will be the time required for the current source to charge up the blanking capacitor from the VCE(sat) level of the IGBT to the trip voltage of the comparator. If the voltage on this terminal (i.e. the collector exceeds the trip level) a DESATP fault is triggered. VDx
DESAT
Diode
DESAT
Comparator
FRD
Vref
IGBT
Fault
Output
Driver
Figure 9. Desaturation Protection circuit Note 1: In case of a DESATP event all internal gate drive signal for the IGBTs of each channel become inactive and the related FoU, FoV, FoW, FoN fault signal output is activated (High). This implies that the system microcontroller needs to disable all input signals to the IPM by driving them High upon detection of a fault condition. High‐side: independent fault outputs FoU, FoV, FOW for the three channels Low‐side: one common fault output FoN shared by the three channels Note 2: In order to prevent false DESATP events due to switching noise – a blanking time of 2us (typ.) implemented. This blanking time will also filter repetitive short high current pulses without tripping the DESATP. www.onsemi.com
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4.2.
DESAT blanking time design The DESAT blanking time must be shorter than the IGBT’s short circuit withstand time (TSC) according to Figure 10,12,14. The SCSOA performance of the IGBT used in IPM is shown in Figure 11,13,15. STK5U4UF90D‐E DESAT blanking time design Figure 11. Typical SCSOA performance of IGBT Figure 10. Typical TSC‐VCE performance vs. IC SC vs. TSC IPM DESAT blanking time design STK5U4UFB0D‐E DESAT blanking time design Figure 12. Typical TSC‐VCE performance vs. IPM DESAT blanking time design STK5U4UFE0D‐E DESAT blanking Figure 14. Typical TSC‐VCE performance vs. IPM DESAT blanking time design Figure 13. Typical SCSOA performance of IGBT IC SC vs. TSC time design Figure 15. Typical SCSOA performance of IGBT IC SC vs. TSC www.onsemi.com
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4.3.
Logic and Protection Timing IGBT output
Protected
Operation
High-side - U
High-side - V
High-side - W
Low-side - U
Low-side - V
UVP
DESATP
UVP
DESATP
UVP
DESATP
UVP
DESATP
UVP
DESATP
UVP
DESATP
High-side
Fault output
Low-side
High-side
U
V
W
U
V
W
U
V
W
Low
side
OFF
OFF
-
OFF
OFF
-
OFF
OFF
-
OFF
OFF
OFF
OFF
-
OFF
OFF
OFF
OFF
-
OFF
OFF
OFF
OFF
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
High
Low
High
Low-side - W
*) ‐ (hyphen) follows the actual input signals using negative logic (e.g. LINU = LOW turns on the Low‐side U phase IGBT). Table 4. Input / Output Logic Table DESAT protection reset signal
/VIN
HINx, LINx OFF
ON
VDx VD*
Output
Current
OFF
ON
VDESAT threshold
Internal
DESAT
Voltage
Fault
output
Fox protection reset voltage
VD undervoltage
Desaturation blanking time
Figure 16. Logic and Protection Timing Diagram Notes 1. The VDx supply under voltage protection is the feature to protect a device when the gate driver supply voltage falls due to an operating malfunction. It will typically start up at about 12 V. The UVP circuit has about 1.0 V of hysteresis and will disable the output if the supply voltage falls below about 11 V. The gate driver power supply low voltage protection operates is gate turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage. 2. The Low‐side gate driver of each phase are individual devices. Their VDN and GND terminals are internally connected. Each device has its individual DESATP circuit. As the FoN terminal is common, it is not possible to identify which driver has detected the fault. 3. When using the over‐current protection with external shunt resistor, please set the current protection level to be equal to or less than the rating of output peak current (Iop). www.onsemi.com
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4.4.
Under Voltage Protection The under voltage protection UVP is designed to prevent unexpected operating behavior as described in Table 5. Both high‐side and Low‐side have under voltage protecting function. However the fault signal output is keeping low level. VDD Voltage (typ. Value)
Operation behavior
< 12.5V
As the voltage is lower than the UVLO threshold the control
circuit is not fully turned on.
A perfect functionality cannot be guaranteed.
12.5 V – 13.5 V
IGBTs can work, however conduction and switching losses
increase due to low voltage gate signal.
13.5 V – 16.5 V
Recommended conditions
16.5 V – 20.0 V
IGBTs can work. Switching speed is faster and saturation
current higher, increasing short-circuit broken risk.
> 20.0 V
Control circuit is destroyed. Absolute max. rating is 20 V.
Table 5. Module operation according to control supply voltage The sequence of events in case of UVP event (IGBTs turned off, no fault output) is shown in Figure 17. /VIN
HINx, LINx HIN
Reset
Protection state
Control supply voltage VD x Set
set Under voltage trip
Reset
Under voltage reset
Normal operation
Output Current Ic (A)
After the voltage level reaches UV reset, the circuits start to
operate when next input is applied .
IGBT turn off
Fault output
Fox level output ( No Fault output )
Keeping high
low
Figure 17. UVP timing Diagram www.onsemi.com
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4.5.
Dead time active LOW The driving signals for IGBTs (high‐side and Low‐side) need to include a “dead time”. This period where both inputs are inactive between either one becoming active is required due to the in‐
ternal delays within the IGBTs. Figure 18 shows the delay from the input signal via the internal gate driver to high‐side IGBT, the similar path for the Low‐side and the resulting minimum dead time which is equal to the potential shoot through period: HINx LINx Figure 18. Shoot Through Period www.onsemi.com
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5. PCB design and mounting guidelines This chapter provides guidelines for an optimized design and PCB layout as well as module mounting recommendations to appropriately handle and assemble the IPM. 5.1.
Application (schematic) design Figure 19 gives an overview of the external components and circuits used when designing with the STK5U4UFxx series module. Motor
MCU
Sample interface circuit detail
VDU
VP
FoU
Interface Circuit
(see detail)
+
CS
Gate Driver
with
Desaturat ion
Prot ection
Cbulk
HINU
GNDU
U
VDV
FoV
Gate Driver
with
Desaturat ion
Prot ection
Interface Circuit
(see detail)
HINV
V
GNDV
VDW
FoW
Gate Driver
with
Desaturat ion
Prot ection
Interface Circuit
(see detail)
HINW
W
GNDW
VDN
GND
Interface Circuit
(see detail)
LI NU
Gate Driver
with
Desaturat ion
Prot ection
NU
Interface Circuit
(see detail)
LI NV
Gate Driver
with
Desaturat ion
Prot ection
NV
LI NW
Gate Driver
with
Desaturat ion
Prot ection
Interface Circuit
(see detail)
FoN
NW
TH1
Sensing, isolation
TH2
To op-amp circuit
VDx
To DESAT circuit
MCU
Fox
HINx
/LINx
To IGBT Gate drive
GNDx
GND
Figure 19. STK5U4UFxx series application circuit www.onsemi.com
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5.2.
Notes on PCB design 1. External shunt resistors should be placed very close to the terminals NU, NV, NW. 2. Power side GND and control side GND must not be a solid common wiring. Signal side GND is recommended to design the patterns in one point of connection to GND terminal so that it does not flow to the power side the GND signal current. 3. The power GND copper area and the control GND copper area shall be connected with a short trace. 4. The snubber capacitor between the positive terminal and the negative terminal of the power, must be placed very close to the IPM power terminals. 5. Capacitor and zener diode should be placed close to the terminals. 6. Isolation distance between high voltage. Recommend insert PCB cutting. STK5U4UFxx series FOU GNDU VP + VDU HINU Vcc FOV GNDV U + VDV HINV Snubber FOW V capacitor +
GNDW Bulk + VDW HINW capacitor MCU Signal Power W GND GND GND +15V + VDN Shunt resistors +5V LINU NU LINV LINW Power GND FON N
TH1 TH2 NW
Figure 20. PCB design reference www.onsemi.com
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5.3.
Pin by pin design and usage notes This section provides pin by pin PCB layout recommendations and usage notes. For a complete list of module pins refer to the datasheet or Chapter 6. VP, These pins are connected with the main DC power supply. The applied voltage is up to NU,NV,NW the HV DC bus level. Overvoltage on these pins could be generated by voltage spikes during switching due to the trace inductance. To avoid this behavior the wire traces need to be as short as possible to reduce the inductance. In addition a snubber capacitor needs to be placed as close as possible to these pins to stabilize the voltage and absorb voltage surges. U, V, W These terminals are the output pins for connecting the 3‐phase motor. They share the same GND potential with each of the high‐side control power supplies. Therefore they are also used to connect the GND of the bootstrap capacitors. These bootstrap capacitors should be placed as close to the module as possible. VDN, GND These pins connect to the internal protection circuit and gate drivers for the Low‐side 3 channel power elements and also with the control power supply of the logic circuit. The voltage between VDN and GND terminals is monitored by the under voltage protection circuit. The GND terminal is the reference voltage for the Low‐side control inputs signals as well as Low‐side Fault Output (FoN). When the “VDN“ and “GND” pins are connected externally care must be taken to select a single connection point as close as possible to the IC. In case of multiple connections to these pins and longer traces being used, the overcurrent protection level may be‐
come low. Therefore this should be avoided. VDU, VDV, The VDx pins are internally connected to the positive supply of the high‐side drivers. VDW The supply needs to be floating and electrically isolated. The boot‐strap circuit shown in Figure 21 forms this power supply individually for every phase. Due to integrated boot resistor and diode (RB & DB) only an external boot capacitor (CB) is required. CB is charged when the following two conditions are met. 1. Low‐side signal is input 2. Motor terminal voltage is low level The capacitor is discharged while the high‐side driver is activated. Thus CB needs to be selected taking the maximum on time of the high‐side and the switching frequency into account. DB
CB
Driver
RB
Driver
VDN
Figure 21. Boot Strap Circuit www.onsemi.com
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LINU, HINU, LINV, HINV, LINW,HINW The voltages on the high‐side drivers are individually monitored by the under voltage protection circuit. If there is a UVP fault on any given phase, the output on that phase is disabled. Typically a CB value of less or equal 47uF (±20%) is used. If the CB value needs to be higher, an external resistor (20Ω or less) should be used in series with the capacitor to avoid high currents which can cause malfunction of the IPM. These pins are the control inputs for the power stages. The inputs on HINU/HINV/HINW control the high‐side transistors of U/V/W, and the inputs on LINU/LINV/LINW control the Low‐side transistors of U/V/W respectively. These inputs are ACTIVE LOW. A low level turns on the IGBT. A high level turns off the IGBT. The STK5U4UFxx series may be used with an optically isolated input. The optoisolator can be used to provide level shifting, and if desired, isolation from AC line voltages. An optoisolator with a very high dv/dt capability should be used. The STK5U4UFxx series have an inverting input pin to interface directly with an optoisolator using a pullup resistor. The input may also be interfaced directly to 5.0 V CMOS logic or a microcontroller. The IGBT IGBT switching delays the control signals must include a dead‐time. The equivalent input stage circuit is shown in Figure 22. VDx
/ Input signal
GNDx
Figure 22. Internal Input Circuit FoN,FoU,Fo
V,FoW The output might not respond when the width of the input pulse is less than 1µs (both ON and OFF). IPM has an active high fault output. The fault output may be easily interfaced to an optoisolator. While it is important that all faults are properly reported, it is equally important that no false signals are propagated. Again, a high dv/dt optoisolator should be used. High‐side Fault circuit is shown in Figure 23. The LED drive provides a resistor programmable current of 10 to 20 mA when on, and provides a low impedance path when off. VDx
GNDx
Figure 23. High‐side Fault Connection www.onsemi.com
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Low‐side Fault circuit is shown in Figure 24. FoN is common fault output detection of Low‐side 3 IGBTs. Fault WN
Fault VN
Fault UN
VDN
GND
Figure 24. Low‐side Fault Connection Note: The desaturation protection Latch will turn off the IGBT for the remainder of the cycle when a fault is detected. When input goes high, latch is reset. TH1,TH2 5.4.
An internal thermistor to sense the substrate temperature is connected between TH1 and TH2. By connecting an external pull‐up resistor to the same as the microcontroller I/O voltage, the module temperature can be monitored. Please refer to heading 3.2 for details of the thermistor. Note: This is the only means to monitor the substrate temperature indirectly. Input signal terminal and Fault terminal interface 0.1uF
Vz=18V
10uF
100pF
MCU
0.1uF
The input signal of a Low level makes IGBT turn on (active LOW). The signal architecture of this IPM is optimized for totem pole type optoisolator drive of Rail‐to‐Rail. Please use the high‐speed optoisolator of the totem pole buffer type to use performance of IPM to the maximum. This is because reduction of the dead time is effective to make use of the low loss features. The wirings between the IPM terminals and each optoisolator must be as short as possible, and the floating capacitance between the primary and the secondary must be considered in order to select a layout design. VDx to DESAT circuit
VD*
Fox CB
HINx Fo*
LINx to IGBT gate drive
I*P/I*N
GND
GNDx GND*
Figure 25. Interface circuit example and IPM internal architecture www.onsemi.com
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5.5.
Example for signal interface circuit design The following part is necessary for an input circuit to the IPM 1. Optoisolator for Input signal An optoisolator with a very high dv/dt capability of the totem pole type(Rail‐to‐Rail) should be used. IPM has an inverting input pin to interface directly with an optoisolator using a pullup resistor. The input may also be interfaced directly to 5.0 V CMOS logic or a microcontroller. Please design it in consideration of CTR and the aging characteristics and use the optoisolator that satisfies the following characteristics. ‐ tPHL=tPLH : <500ns ‐ High CMR e.g.) ACPL‐W483 (Avago Technologies) 2. Optoisolator for Fault signal Please use the optoisolator that satisfies the following characteristics. ‐ CTR : >100% e.g.) ACPL‐W50L (Avago Technologies) Fault terminal is active high output. The LED drive provides a resistor programmable current of 10 to 20 mA when on, and provides a low impedance path when off. An active high output, resistor, and small signal diode provide an excellent LED driver. 3. Smoothing capacitor and decoupling capacitor ‐ Smoothing capacitor recommendation value : Depends on motor design and power, at least 10uF. ‐ Decoupling capacitor recommendation value : 0.1uF to 10uF 4. External CIN capacitor The signal terminal is sensitive for the optoisolator of the high‐speed type. If you want to improve the malfunction due to noise, connection of external capacitor CIN helps to stabilize operation. ‐ External capacitor recommendation value : 100pF to 1000pF. Values in this range do not affect the dead time as is shown below. Ch1(Blue) : P.C. input signal 2.5V/DIV Ch2(green) : IPM Input signal VIN 5V/DIV Ch3(Pink) : Gate Output signal 5V/DIV Time scale : 400ns/DIV Figure 26. Example of CIN comparison turnON/turnOFF waveform [Note] ‐ The above circuit diagram is an example of circuit configuration. This configuration does not guarantee all operating conditions. ‐ High‐side and Low‐side are common signal architecture. ‐ In the case of PWM <= 1us, there is a possibility that appropriate signals could not be carried, which results in no response etc. www.onsemi.com
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5.6.
Heat sink mounting and torque If a heat sink is used, insufficiently secure or inappropriate mounting can lead to a failure of the heat sink to dissipate heat adequately. The following general points should be observed when mounting IPM on a heat sink: 1. Verify the following points related to the heat sink:  There must be no burrs on aluminum or copper heat sinks.  Screw holes must be countersunk.  There must be no unevenness in the heat sink surface that contacts IPM.  There must be no contamination on the heat sink surface that contacts IPM. 2. Highly thermal conductive silicone grease needs to be applied to the whole back (aluminum substrate side) uniformly, and mount IPM on a heat sink. If device removed, grease must be applied again. 3. For a good contact between the IPM and the heat sink, the mounting screws should be tightened gradually and sequentially while a left/right balance in pressure is maintained. Either a bind head screw or a truss head screw is recommended. Please do not use tapping screw. We recommend using a flat washer in order to prevent slack. The standard heat sink mounting condition of the STK5U4UFxx series is as follows. Item Recommended Condition Pitch 67.8±0.1mm (Please refer to Package Outline Diagram) Screw Diameter : M4 Screw head types: pan head, truss head, binding head Washer Heat sink Torque Grease Plane washer dimensions D = 9mm, d = 4.8mm and t = 0.8mm JIS B 1256 Material: Aluminum or Copper Warpage (the surface that contacts IPM ) : 50 to 100 μm Screw holes must be countersunk. No contamination on the heat sink surface that contacts IPM. Temporary tightening : 20 to 30 % of final tightening on first screw Temporary tightening : 20 to 30 % of final tightening on second screw Final tightening : 0.79 to 1.17Nm on first screw Final tightening : 0.79 to 1.17Nm on second screw Silicone grease. Thickness : 100 to 200 μm Uniformly apply silicon grease to whole back. Thermal foils are only recommended after careful evaluation. Thickness, stiffness and compressibility parameters have a strong influence on performance. Table 6. Heat sink mounting www.onsemi.com
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Mount IPM on a Heat sink Size of washer About uniformly application Figure 27. Mount on Heat Sink steps to mount an IPM on a heat sink 1st: Temporarily tighten maintaining a left/right balance. 2nd : Finally tighten maintaining a left/right balance. 5.7.
Mounting and PCB considerations (general information) In designs in which the PCB and the heat sink are mounted to the chassis independently, use a mechanical design which avoids a gap between IPM and the heat sink, or which avoids stress to the lead frame of IPM by an assembly that slipping IPM is forcibly fixed to the heat sink with a screw. Figure 28. Fix to Heat Sink Maintain a separation distance of at least 1.5 mm between the IPM case and the PCB. In particular, avoid mounting techniques in which the IPM substrate or case directly contacts the PCB. www.onsemi.com
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Do not mount IPM with a tilted condition for PCB. This can result in stress being applied to the lead frame and IPM substrate could short out tracks on the PCB. If stress is given by compulsory correction of a lead frame after the mounting, a lead frame may drop out. Since the use of sockets to mount IPM can result in poor contact with IPM leads, we strongly recommend making direct connections to PCB. IPM is flame retardant. However, under certain conditions, it may burn, and poisonous gas may be gener‐
ated or it may explode. Therefore, the mounting structure of the IPM should also be flame retardant. Mounting on a PCB 1. Align the lead frame with the holes in the PCB and do not use excessive force when inserting the pins into the PCB. To avoid bending the lead frames, do not try to force pins into the PCB unrea‐
sonably. 2. Do not insert IPM into PCB with an incorrect orientation, i.e. be sure to prevent reverse insertion. IPM may be destroyed or suffer a reduction in their operating lifetime by this mistake. 3. Do not bend the lead frame. 5.8.
Cleaning IPM has a structure that is unable to withstand cleaning. Do not clean independent IPM or PCBs on which an IPM is mounted. www.onsemi.com
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6. Package Outline STK5U4UFxx series is DIP‐C2 package. (Dual‐line‐package) 6.1.
Package outline and dimension to
unit : mm Missing pin : 1,4,9,12,13,14,19,20,21,26,27,28, 36,37,38,42,43,44,48,49,50,54,55,56,59,62 22.5 64 Figure 29. STK5U4UFxx series Package Outline 32 A top veiw 33 30 x 1.778 = 53.34 Figure 30. Recommended Land Pattern www.onsemi.com
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1.5 3.0 22.5 2 45 φ1.2 Detail A AND9426/D
6.2.
IPM Package Geometry DIP-C2
ITEM
Clearance
Creepage
Between live power terminals
with high potential
6.11mm
6.11mm
Between live control terminals
with high potential
6.41mm
6.41mm
Between terminals and
heat sink
4.0mm
5.0mm
Package Size
73.2 mm x 40.2 mm x 6 mm
Creepage Mold compound 4.0 (Clearance) Substrate Heat sink Details A
to
A Figure 31. IPM Package Geometry 5.0 www.onsemi.com
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6.3.
Pin Out Description Pin 2 3 5 6 7 8 10 11 15 16 17 18 22 23 24 25 29 30 31 32 33,34,35 39,40,41 45,46,47 51,52,53 57,58 60,61 63,64 Name TH1 TH2 FoN LINW LINV LINU VDN GND VDW HINW FoW GNDW VDV HINV FoV GNDV VDU HINU FoU GNDU VP U V W NU NV NW Description Thermistor connection Thermistor connection Fault output Low‐side Logic Input Low‐side Gate Driver ‐ Phase W Logic Input Low‐side Gate Driver ‐ Phase V Logic Input Low‐side Gate Driver ‐ Phase U Control power supply Low‐side Control power GND Low‐side Control power supply high‐side – Phase W Logic input high‐side – Phase W Fault output high‐side – Phase W Control power GND high‐side – Phase W Control power supply high‐side – Phase V Logic input high‐side – Phase V Fault output high‐side – Phase V Control power GND high‐side – Phase V Control power supply high‐side – Phase U Logic input high‐side – Phase U Fault output high‐side – Phase U Control power GND high‐side – Phase U Positive Bus Input Voltage U Phase Output V Phase Output W Phase Output Low‐side Emitter Connection ‐ Phase U Low‐side Emitter Connection ‐ Phase V Low‐side Emitter Connection ‐ Phase W Note : Pins 1, 4, 9, 12, 13, 14, 19, 20, 21, 26, 27, 28, 36, 37, 38, 42, 43, 44, 48, 49, 50, 54, 55, 56, 59, and 62 are not present. www.onsemi.com
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7. Evaluation Board The evaluation board consists of the minimum required components such as snubber capacitor and bootstrap circuit elements of the STK5U4UFxx series. Figure 32. Evaluation Board Schematic Although IPM is active Low control, this evaluation board is an active High input
control by the circuit of opt isolator and logic interface.
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Top side back side Length : 100mm Side : 97mm Thickness : 1.6mm Rigid double‐sided substrate (Material : FR‐4) Both sides resist coating Copper foil thickness : 70um Figure 33. PCB Layout (Top view) Figure 34. Photo of Evaluation Board www.onsemi.com
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JP1
JP2
JP3
JP5
JP8
JP7
J4
JP6
J3
JP4
J2
J1
J5
Figure 35. Pin description Connect to control part JP1 1 : HU 5 : HW 9 : NV 2 : FoU 6 : FoW
10 : NW 3 : HV 7 : GND 11 : FoN 4 : FoV 8 : NU 12 : GND JP2 : +5V ‐ GND JP3 : +15V ‐ PGND JP4 : VDU ‐ GNDU JP5 : TH ‐ PGND JP6 : VDV ‐ GNDV JP7 : VDW – GNDW JP8 1 : SPG 3 : SPG 5 : SPG 2 : SW 4 : SV 6 : SU Connect to DC power supply and motor J1 : P J2 : U J3 : V J4 : W J5 : N For monitoring control signals TP1 : GND TP14 : LINU TP2 : +5V TP15 : LINV TP4 : LINW_PI TP16 : LINW TP5 : HINW_PI TP17 : FoN TP7 : FoN_PO TP18 : +15V TP11 : HINU TP19 : PGND TP12 : HINV TP20 : PGND TP13 : HINW www.onsemi.com
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Figure 36. Connection Example Step1 : Connect IPM, each power supply, logic parts and the motor to the evaluation board, and confirm that each power supply is OFF at this time. Step2 : Apply DC15V and DC5V. Step3 : Perform a voltage setup according to specifications, and apply HV DC power supply between P and N terminals. Step4 : The IPM will start when signals are applied. The Low‐side inputs must be switched on first to charge up the bootstrap capacitors. Note : When turning off the power supply part and the logic part, please carry out in the reverse order to above steps. ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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