A 75 W TV Power Supply Operating in Quasi-square Wave Resonant Mode Using NCP1207 Controller

AND8145/D
A 75 W TV Power Supply
Operating in Quasi−square
Wave Resonant Mode using
the NCP1207 Controller
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Prepared by: Nicolas Cyr
ON Semiconductor
APPLICATION NOTE
Introduction
Quasi−square wave resonant converters, also known as
quasi−resonant (QR) converters, allow designing flyback
Switch−Mode Power Supplies (SMPS) with reduced
Electro−Magnetic Interference (EMI) signature and
improved efficiency. Due to the low level of generated
noise, QR SMPS are therefore very well suited to
applications dealing with RF signals, such as TVs.
ON Semiconductor NCP1207 is a QR controller that will
ease your design of an EMI−friendly TV power supply with
only a few additional components, and able to lower its
standby power down to 1.0 W.
230
VDS (t) (V)
170
IP Lf
CTOT
110
50
−10
What is Quasi−Resonance?
Figure 1. A Truly Resonating VDS Signal on a
Quasi−resonant Flyback Converter
The term quasi−resonance is normally related to the
association of a real hard−switching converter and a
resonant tank. While the operation in terms of control is
similar to that of a standard PWM controller, an additional
network is added to shape the variables around the
MOSFET: current or voltage. Depending on the operating
mode, it becomes possible to either switch at zero current
(ZCS) or zero voltage (ZVS). Compared to a conventional
PWM converter, a QR operation offers less switching losses
but the RMS current circulating through the MOSFET
increases and forces higher conduction losses; with a careful
design, efficiency can be improved. However, one of the
main advantages in favor of the quasi−resonance is the
reduced spectrum content either conducted or radiated.
True ZVS quasi−resonance means that the voltage present
on the switch looks like a sinusoidal arch. Figure 1 shows
how such a signal could look like.
 Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 0
The main problem with this technique lies in the very high
voltage generated at the switch opening. Most of the time,
these resonant offline designs require around 1.0 kV BVdss
MOSFETs whose price is clearly incompatible with high
volume markets. As a result, designers orientate their choice
toward another compromise called quasi−square wave
resonant power supply.
Quasi−Square Wave Resonant Converters
As we saw, true resonant operation put a constraint on
MOSFET selection by imposing a high voltage at the switch
opening. If we closely look at the standard hard−switching
waveform (Figure 2), we can see that at a given time the
drain voltage goes to a minimum. This occurs just after the
core reset.
1
Publication Order Number:
AND8145/D
AND8145/D
1
2 LLEAK CTOT
CORE IS RESET
DRAIN VOLTAGE
1
2 LP CTOT
VDS IS MINIMUM
IP
DRAIN CURRENT
Figure 2. Hard−switching Waveforms in Discontinuous Conduction Mode (DCM)
From Figure 2, it is possible to imagine a controller that
turns a MOSFET ON until its current grows−up to the
setpoint. Then it turns the MOSFET OFF until the core reset
is detected (usually via an auxiliary winding). As a result, the
controller does not include any stand alone clock but only
detects the presence of events conditioned by load/line
conditions: this is a so−called free−running operation.
Converters based on this technique are often designated as
Self−Oscillating Power Supplies (SOPS), valley switching
converters, etc.
Oscillations origins can be seen from Figure 3
arrangement where L−C networks appear.
RP
Depending on the event, two different configurations are
seen:
• At the switch closing, the primary current flows through
the primary inductance LP but also the leakage
inductance, LLEAK. When the turn−on time expires, the
energy stored in LP is transferred to the secondary side of
the transformer via the coupling flux. However, the
leakage inductance, which models the coupling between
both transformer sides, reverses its voltage and imposes
a quickly rising drain voltage. The slope of this current is
IP
CTOT (eq. 1)
surrounding the drain node: MOSFET capacitors,
primary transformer parasitic capacitors but also those
reflected from the secondary side, etc. As a result, LLEAK
together with CTOT form a resonating network of natural
1:N
+
LP
VOUT
frequency
+
VIN
where CTOT gathers all capacitors
1
.
2 LLEAK CTOT (eq. 2)
maximum drain voltage can then be computed using the
characteristic impedance of this LC network:
LLEAK
VDS max VIN 1 (VOUT VF) IP N
DRV
The
CTOT
VDS
LCLEAK
TOT
(eq. 3)
Figure 3. A Typical Flyback Arrangement Shows Two
Different Resonating Networks
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AND8145/D
• When the transformer core resets, primary and secondary
resonating network, this time made by LP, the primary
inductance, and nearly the same CTOT as before. A
sinusoidal ringing takes place, damped by the presence of
ohmic losses (DC + AC resistance of the primary
winding, modeled by RP). The drain−source shape rings
as the formula below details:
currents drop to zero. The secondary diode stops its
conduction and the reflected voltage on the primary
naturally dies out. From equation 3, this means that terms
after VIN all collapse to zero and VDS tends toward VIN.
However, the transition would be brutal in the lack of a
VDS(t) VIN 1 (VOUT VF) e at cos (2 FPRIM t)
N
RP
the damping factor
2 LP (eq. 5)
1
FPRIM FPRIM 2 LP CTOT (eq. 6)
with: a 700
1 (V
OUT VF)
N
VDS(t) (V)
N
and N the S turn ratio.
NP
e
RP
t
2 LP
t=0
500
the natural ringing frequency
VIN the input voltage, VF the diode’s forward drop
(eq. 4)
VIN
300
100
tvalley
We can see from Figure 4 that the drain is the seat of
various local minimums when going along the ringing wave.
These drops are called “valleys”. If we manage to switch the
MOSFET right in the middle of these valleys, we ensure
minimum turn−on losses, particularly those related to
capacitive dissipation:
Multiple Valleys
−100
Figure 4. A Typical Flyback Ringing Waveform
Occurring at the Switch Opening
PavgCAP 1 CTOT VDS2 FSW
→ 0.
2
(eq. 7)
Thus, quasi−square wave operation (or valley switching)
will imply a re−activation of the switch when VDS is
minimum. As various figures portray, this occurs some time
further to the transformer core reset. By implementing this
method, we build a converter that naturally exhibits a
variable frequency operation since the reset time depends
upon the input/output operating conditions. Figure 5 shows
a typical shot of a quasi−square wave converter.
As one can see, the total period is made of different events,
where the core is first magnetized (TON), then fully reset
(TOFF) and finally a time delay (TW) is inserted to reach the
lowest value on the drain. Let us look at how the frequency
moves by respect to the input/output conditions.
TOFF
TW
First Valley
TON
Figure 5. A Typical Drain−Source Shot of a
Quasi−square Wave Converter
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AND8145/D
Evaluating the Free−Running Switching Frequency
For the TW event, which is one fourth of the natural
ringing frequency given by equation 4, we will compute the
derivative of equation 4 and null it to find its minimum:
d (VIN e at cos (2 FPRIM t))
IPEAK
SN
IP(t)
V
S IN
LP
dt
VOUT VF
LP
0
(eq. 10)
Which gives a result of:
ON
OFF
IP = 0
TW 1 1 2 ft 2
2FaPRIM
a tan
FPRIM
0
(eq. 11)
However, this result is not very practical because of its
inherent complexity. If we observe equation 10, we can see
that the minimum is reached when the term
cos (2 FPRIM t) equals −1. Otherwise stated, we can
solve t for which the cosine is equal to zero, or the full
product equals . This gives:
TW
Figure 6. The Primary Inductance Current is made of
Two Different Slopes
The free−running frequency can be evaluated by looking
at Figure 6, where the primary current (circulating in the
primary inductance) is depicted. From the definition of the
various slopes, we can express the first two events, TON and
TOFF quite easily:
TON LP
I
VIN P
TOFF TW 1
LP CP
2 FPRIM
(eq. 12)
However, this result is valid only for low damping
coefficient, that is to say, e at 1. Experience shows that
it is good enough for the vast majority of cases.
(eq. 8)
LP
IP
NP (V
V
)
OUT
F
NS
(eq. 9)
As a result, the final switching period is computed by summing up all these sequences and introducing the input power
expression: T TON TOFF TW. (eq. 13)
1
1
TON TOFF TW IP LP LP CP 1
VIN
FSW
NNPS (VOUT VF)
P
1
2
PIN OUT
2 LP IP FSW
from equation 15, IP 2 LPPOUT
FSW
N
with: VREFLECT P [VOUT VF]
(eq. 15)
NS
TW LP CP
the converter efficiency
POUT the output power
VOUT and VF, respectively the output voltage and
the rectifier drop @ ID = IOUT
LP the primary inductance.
(eq. 16).
Now, plugging FSW in equation 16 gives:
(eq. 14)
LP IP 2 1
IP LP 1 TW VIN VREFLECT
2 POUT
(eq. 17)
Stating that: 2 LP POUT A;
IP A VREFLECT A VIN A VREFLECT2 2 A VREFLECT VIN A VIN2 2 VIN2 VREFLECT2 TW LP VIN VREFLECT
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(eq. 18)
AND8145/D
From equation 16, we can then compute the switching
frequency using the calculated peak current:
FSW FSW LP 2 POUT
2 POUT
LP IP 2
(eq. 19)
However, equation 18 is not very practical since it
involves LP, what we are actually looking for... It can
certainly be used to discover the operating peak current from
known inductance and capacitor values. But neglecting TW,
a simpler formula can be used as first frequency iteration
(e.g. to feed a SPICE simulator for instance):
V
VIN
IP 2 POUT REFLECT
VIN VREFLECT
2
VINNVOUTVF
Entering equation 21 into a spreadsheet and plotting FSW
versus various parameters (VOUT, IOUT, etc.) gives an idea
about the high frequency variability of the system. Figure 7
and Figure 8 respectively plot FSW in function of the input
voltage and the output current for a given application.
(eq. 20)
2*105
POUT = 100 W
LP = 1 mH
VOUT = 16 V
NP:NS = 1:10
CP = 100 pF
LP = 1 mH
VOUT = 16 V
NP:NS = 1:10
CP = 100 pF
VIN = 100 V
FSW (Hz)
1.5*105
4*104
1*105
3*104
5*104
2*104
1*104
100
150
200
250
300
350
0
400
0
20
40
VIN (V)
80
100
Figure 8. Frequency Dependency with Load at a
Given Input Voltage (100 V)
3.5
LP = 1 mH
VOUT = 16 V
NP:NS = 1:10
CP = 100 pF
POUT = 100 W
3.0
2.5
2.0
1.5
100
60
POUT (W)
Figure 7. Frequency Variations for a 100 W SMPS
Operated from a Universal Mains
IP (A)
FSW (Hz)
5*104
NVOUTVFVIN
(eq. 21)
7*104
6*104
1
150
200
250
300
350
400
VIN (V)
Figure 9. Peak Current Variations for a 100 W Output
Power with Different Line Voltages
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AND8145/D
A Quiet EMI Signature
Detecting the Core Reset Event
Manipulating sinusoidal (or close−to) variables always
offer a narrower spectrum content compared to
hard−switching systems. Figure 10 and Figure 11 depict the
conducted EMI signature of two systems operated at the
same point but implementing different switching
techniques.
Since the MOSFET is re−activated at the lowest drain
level, the classical COSS capacitor discharge at the switch
closing does not exist and the very narrow peak current has
gone (also this peak is often confusing the current−sense
comparator when it is really energetic, even sometimes
despite the presence of the LEB circuitry). As a result,
Quasi−square wave converters are recommended where the
Switch−Mode Power Supply (SMPS) needs to operate close
to Radio−Frequency section, notably in TV chassis.
Core reset detection is usually done via a dedicated
auxiliary winding whose voltage image is directly linked to
the transformer flux by:
VAUX N (eq. 22)
Depending on the controller device, the polarity of the
observed signal must fit its detection circuitry. In
ON Semiconductor NCP1207, this polarity should be of
Flyback type, that is to say, when the MOSFET closes, the
auxiliary voltage dips below ground and stays there, safely
clamped at −0.7 V, until the MOSFET is turned off.
Figure 12 gives an example of the demagnetization signal
for NCP1207.
Figure 10. A Soft−switching Approach Reduces
the Energy Content Above 1 MHz
Figure 11. A Hard−switching System Generates
a lot of Noise in the Same Portion
20.0
Leakage Contribution
10.0
VAUX(t) (V)
d
dt
0
50 mV
−10.0
−N.VIN
−20.0
Figure 12. Core Reset Detection Signal Coming
from a Flyback Winding
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AND8145/D
A 75 W TV Power Supply Design
The NCP1207 Quasi−resonant Controller
Quasi−square Wave Resonant Operation: Due to its
dedicated pin, NCP1207 is able to detect the end of the
transformer core demagnetization before starting a new
switching cycle. The closing of the MOSFET thus occurs at
zero current, cutting out switch turn−on losses and
secondary diode recovery losses. By delaying the turn−on
event, it is possible to turn the MOSFET on in the minimum
of the drain−source wave, further reducing the losses and the
electromagnetic interference (EMI). NCP1207 also features
a minimum TOFF, preventing a frequency runaway at light
loads: when the demagnetization occurs before the end of
the blanking delay, the device waits for the next valley
before enabling a new cycle.
Low Standby Power: When the output power demand
decreases, the feedback (FB) pin voltage decreases at the
same time. When it becomes lower than the selected
threshold, the device starts to skip cycles, generating just
enough switching pulses to maintain the output voltage. This
cycle skipping only occurs at low peak current, ensuring a
noise−free standby operation.
Short−circuit Protection: The IC permanently monitors
the feedback line activity, ready to enter a safe burst mode
if it detects a short circuit. Once the short−circuit has
disappeared, the controller automatically goes back to
normal operation.
OVP Protection: By sampling the plateau voltage of the
demagnetization winding, the NCP1207 is able to detect an
over voltage on the output. In this case the IC goes in fault,
permanently disabling the output. This protection is fully
latched, which means that the power supply has to be
unplugged from the mains to unlatch it.
External MOSFET Connection: By leaving the
MOSFET external from the IC, you can choose the device
exactly suited for your application. You also have the ability
to control the shape of the gate signal, giving you an
additional way to reduce the amount of EMI and video noise.
SPICE Model: A free−running model allows running
transient cycle−by−cycle simulations to verify theoretical
design and help to speed up the design stage of a power
supply. An averaged model dedicated to AC analysis is also
available to ease the stabilization of the loop. Ready−to−use
templates can be downloaded in OrCAD’s PSpice and
Intusoft’s ISPICE from ON Semiconductor web site,
NCP1207 related section.
The data sheet gives complete details regarding the
implementation of the NCP1207.
Power Supply Specification
Input Voltage
Universal input 90 VAC to 265 VAC
Output Power
60 to 75 W
Outputs
+108 V 500 mA max (54 W) Regulated
+12 V 920 mA max (11 W)
−12 V 670 mA max (8.0 W)
+5 V 70 mA derived from +12 V
through a regulator
+3.3 V 50 mA derived from +5.0 V
through a regulator
Protections
Short−circuit, over−voltage and over−
power
Standby Power
Below 1.0 W
Design Steps
1. Reflected Voltage
Let us first start the design by selecting the amount
of secondary voltage we want to reflect on the
primary side, which will give us the primary to
secondary turn ratio of the transformer. If we decide
that we want to use a rather cheap and common
600 V MOSFET, we will select the turn ratio by:
VIN max N (VOUT VF) 600 V
VINmax is 370 V and (VOUT + VF) is about 110 V. If
we decide to keep a 10% safety margin, it gives
N < 1.5. We will choose a turn ratio of N = 1.2, which
will give a reflected voltage of 130 V.
2. Peak Current
Knowing the turn ratio, we can now calculate the
peak primary current needed to supply the 75 W of
output power. If we neglect the delay TW between
the zero of the current and the valley of the drain
voltage, we can calculate IPmax (from equation 20)
by:
VINmin N (VOUT VF)
IPmax 2 POUT N VINmin (VOUT VF)
VINmin is 110 V and η is 85%. Plugging the other
values gives us a maximum peak current of
IPmax = 2.96 A. We will choose a value of 3.5 A to
take into account various tolerances. NCP1207 max
current sense setpoint is 1.0 V, so we should put a
sense resistor RS 1.0 V 0.286 . We will use
3.5 A
four standard 1.1 resistors in parallel.
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AND8145/D
clamp. You can also use a SPICE simulator to test the
right values for the components.
We chose to use an RCD clamp, using a 1N4937
diode with a 220 pF snubber capacitor, a 47 k
resistor and a 10 nF capacitor: it is an aggressive
design (the maximum drain voltage will be very
close to the maximum voltage allowable for the
MOSFET), but it gives enough protection without
degrading too much the efficiency.
Once again, if we design the SMPS to work in ZVS,
we can have a bigger drain capacitor, that will damp
the leakage inductor effect (see below).
3. Primary Inductance
To calculate the primary inductance LP, we need to
decide the switching frequency range we allow the
controller to operate. There are two constraints; at
low line, maximum power, the switching frequency
should be above the audible range (higher than
20 kHz), at high line, lowest nominal power, the
OFF time (TOFF + TW) of the MOSFET should be
higher than 8.0 s, to prevent the controller to jump
between valleys (because these discrete jumps
between 2 valleys can generate noise in the
transformer as well). If we still neglect TW, LP is then
given by (equation 19):
Same Calculation (1 to 4) for a ZVS Power Supply:
1
LP 2 FSWmin POUTmax VINminN(VOUTVF)
NV
INmin(VOUTVF)
Let us start the design from the beginning, to implement
a true ZVS: if we decide to reflect 300 V, assuming that we
have an 800 V MOSFET, we will have a turn ratio of 2.8. The
exact reflected voltage will be 308 V, and the available
margin for leakage inductance effect will be 117 V. IPmax
will then be equal to 2.18 A. Applying the same conditions
for LP will give LP 1.26 mH. If we choose 1.0 mH,
CDRAIN should be higher than 1.6 nF to avoid valley
jumping at 375 Vdc for a 60 W output consumption. If we
want to avoid the use of a clamping network to protect the
MOSFET, CTOT should be higher than 2.05 nF (stating that
LLEAK = 25H, and that the maximum overvoltage due to
leakage inductance is 115 V). We can choose a capacitor
CDRAIN = 2.2 nF to be safe.
You can see through the lines we wrote that many
parameters could be changed to obtain different converters
at the end. The reflected voltage is obviously one of the most
sensitive parameters that influence others. Increasing the
reflected voltage to keep a wider ZVS operating range has
a price on other numbers:
• The switching frequency increases (reset voltage on LP
is stronger)
• The primary peak current and conduction losses are
improved (if FSW goes up, the peak demand goes low)
• The secondary peak current and conduction losses
increase
• The MOSFET undergoes a bigger stress at the switch
opening
• MOSFET turn−on losses can be really null (if ZVS is
achieved).
To simplify the design of your power supply, a
spreadsheet (that includes all the parasitic elements) is
available to download from the ON Semiconductor web site
(www.onsemi.com), under NCP1207 page. The formulae
are described in the application note AND8089/D. You can
also simulate the complete power supply in a SPICE
simulator, using the NCP1207 models also available from
the website.
2
If we choose 25 kHz min for 75 W of output power
at 110 Vdc, we obtain: LP 687 H.
To take tolerances into account, we can choose
LP = 600 H, and verify if it satisfies the second
condition:
For 60 W output power at 375 Vdc, IP = 1.46 A. From
equation 9, TOFF = 6.74 s.
If we connect a 330 pF drain−to−source capacitor,
we calculate TW from equation 12: TW = 1.4 s.
TOFF + TW = 8.14 s, which is higher than 8.0 s.
If nominal output power range of the power supply
is wider, we can choose a higher LP (650 H for
instance) or increase CDRAIN. But this last solution
will decrease efficiency, as VDS is not equal to 0
when the MOSFET is turned on: in this case Zero
Voltage Switching (ZVS) can be a good choice (see
below).
4. Clamp
In equation 3, we can calculate the overvoltage due
to the leakage inductance: VOVLEAK IP
LLEAK
.
CTOT
At this time we don’t know the value of LLEAK, but
we can choose a value of 2% of the primary
inductance (i.e. 12 H), which would not be too far
from the final value. Considering again 330 pF on
the drain, at 375 V input voltage and 75 W of output
power, which give IP = 1.83 A, we obtain
VOVLEAK 349 V.
But we only have 95 V available before reaching the
MOSFET breakdown voltage. So we will need to
add a clamp to limit the spike at turn−off.
Please refer to application note AN1679/D
(available at www.onsemi.com) to calculate this
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AND8145/D
arrangement, the system simulates very quickly and
allows an immediate assessment of what has been
suggested by the Excel spreadsheet. The feedback
loop is purposely simplified with a Zener diode
arrangement, but you can upgrade it with a TL431
circuitry. It will simply take longer simulation time
to settle.
5. SPICE Simulation
The faster and easier way to simulate this power
supply is to use a simplified free−run model to have
an idea of the final results. Figure 13 offers a possible
way to represent a free−running controller: the
demagnetization path includes a standard flip−flop
that latches the transition while the feedback signal
fixes the current setpoint. Due to a simple
Vpos12
pos12
D5
MR851
hv
23
X5
XFMR−AUX
RATIO_POW = −0.17
RATIO_AUX = 0.17
Vneg12
neg12
B2
Current
7.0/V(pos12)
R14
120 m
12
D6
MR851
d
B3
21
Current
7.0/V(pos12)
R15
120 m
22
C11
470 IC = 10
C10
470 IC = 10
Vf
X4
XFMR−AUX
RATIO_POW = −1.2
RATIO_AUX = −0.06
hv
RPRIM
0.5
IOUT
+
Idiode
R7
47 k
LPRIM
600 13
X2
Free Run DT
rgate = 10
LEB = 250 n
toffmin = 7.5
VIN
120
R1
22 k
dem
fb
31
dem
R6
2.8 K
+
V4
Id
8
7
3
6
4
5
fb
VDRAIN
24
R5
10
1
COUT1
140 IC = 107
B1
Current
30/V(VOUT)
VOUT
11
2
14
LPEAK
12 4
Free Run
C6
330 p
Resr1
60 m
d
D2
MUR160
1
VOUT
5
D1
MR856
Icoil
+
+
7
28
C1
10 n
VOUT
6
X1
MTP6N60E
C3
330 p
15
R10
4.7 k
16
X3
MOC8101
C4
1.0 n
3
17
Rsense
0.275
D3
BV= 107
Figure 13. Simulation Schematic of the TV Power Supply
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AND8145/D
As Figure 14 and Figure 15 show, the simulation is very
close to what is obtained on the board:
VDRAIN (100 V/div)
VSENSE (500 mV/div)
Figure 14. Simulation Results
Figure 15. Real Measurements
The SPICE simulation offers another advantage, which is
the evaluation of the component stresses. Due to good
models, you can immediately measure the MOSFET
conduction losses worse case, the RMS current in the
rectifiers, in the resonating capacitor and in the output
capacitors, and choose the right components accordingly.
For instance we used the simulated RMS currents to
determinate the winding characteristics of the transformer,
knowing that low line imposes the highest stress on the
transformer. Based on the simulation results, the following
specification has been sent to the transformer manufacturer:
16 V (max voltage to be applied on VCC pin): we can
choose a value of 12 V.
The voltage applied on demagnetization pin (pin 1)
should be lower than the over−voltage protection
(OVP) threshold, which is 7.2 V. We will add an
external resistor to divide the auxiliary voltage by 2:
the plateau voltage during normal operation will be
6.0 V. It will allow a 2.4 V over−voltage on the
auxiliary winding, corresponding to a 21.6 V
over−voltage on +108 V output, which is acceptable.
There is an internal 28 k resistor, so we just need to
add another external 28 k, or 27 k for a more standard
value. There is an internal clamping diode to protect
pin 1 against lethal over−voltages, and the current in
this diode should never be higher than
+3 mA/−2 mA: we must verify that the chosen
resistor is in accordance with this specification. If
during turn−on, the auxiliary winding delivers 35 V
(at the highest line level), then the maximum current
flowing from pin 1 is: (35 V + 0.7 V)/27 k =
1.32 mA, which is safe.
This resistor, which connects the winding to the pin
(called ROVP1 on the schematic), will also be used to
delay the turn−on of the MOSFET to be sure to be
right in the valley of the drain voltage. If the total
internal capacitance of pin1 (10 pF) is not giving
enough delay, an external capacitor will be added. In
our case, we will add a 82 pF capacitor, which will
delay the turn−on exactly in the valley.
Primary: Input voltage: 90 VAC to 275 VAC
Switching frequency: 30 kHz to 80 kHz
LP = 600 H
IPpeak = 3.6 A
IP RMS = 1.3 A
Aux: ratio NP/NAUX = 9.0, IRMS = 10 mA
Secondaries:
B+ (+108 V): ratio NP / NB+ = 1.0, IRMS = 1.0 A
POW1 (+12 V): ratio NP / NPOW1 = 9.0, IRMS = 1.2 A
POW2 (−12 V): ratio NP / NPOW2 = 9.0, IRMS = 900 mA
6. Auxiliary Winding
The auxiliary winding will be used to supply the
controller and to detect the transformer
demagnetization. To supply VCC, the voltage should
be higher than 11 V (VCCOFF + VF), but lower than
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AND8145/D
reconfiguration is made by a thyristor, activated by
a manual switch to simplify the use of the evaluation
board (see Figure 16).
In fact, the energy stored in the high voltage winding
is used to refuel the low voltage output capacitor, and
regulation is now made on this low voltage output.
As the windings are imposing currents (not
voltages), connecting a high voltage winding to a
low voltage output is completely safe. But as the
regulation loop now forces the high voltage winding
to deliver a low voltage, then all the other windings
are also delivering lower voltages than in normal
conditions (in the same ratio). The sum of the
consumptions on all the windings is drastically
reduced due to this division of all the output
voltages.
During standby, the regulation is made through the
Zener diode DZ2 (Figure 17). As NCP1207 is still
powered due to the DSS, even is there is no more
auxiliary voltage, the regulation point can be lower
than in normal mode. The only constraint for the
output voltage is to be higher than the minimum
input voltage of the voltage regulator, but there is no
need for any guard band. To regulate the 5.0 V
output, we use a standard MC7805 in TO220, with
a drop voltage of 2.0 V: the regulation point can be
as low as 7.0 V. R9 and C22 can be added to soften
the transitions between standby and normal modes.
They are usually not necessary if the loop
compensation is correctly designed (by adding RC
networks around the TL431).
7. DSS
The main reason why the auxiliary winding will also
be used to supply the controller is that the maximum
total gate charge of a 6.0 A, 600 V MOSFET can be
as high as 50 nC. Knowing that the current consumed
by the output stage is IDRV = FSW x Qg x VDRV, even
for a 20 kHz frequency and VDRV = 10 V, IDRV will
be higher than 10 mA. And this current will directly
flow through the DSS if no auxiliary supply is used.
Nevertheless, the DSS is of great interest in a TV
power supply. When a secondary reconfiguration is
used (or at least the regulation point is lowered) to
reduce the standby power, the auxiliary voltage
collapses. Due to the DSS, the controller is still fully
powered during standby. This allows to regulate at
the lowest possible voltage (minimum input voltage
of the standby regulator), and the transition from
standby to normal mode is smoother (see
measurements section of this document).
The high voltage pin will be connected to one of the
mains inputs through a simple 1N4007 diode to
lower the standby power, due to the reduced average
voltage due to half−wave rectification (see
NCP1207 data sheet for details).
8. Standby
The standby consumption should be below 1.0 W. To
achieve this target, the secondary current
consumption should be reduced. We choose to use a
secondary reconfiguration that, by re−routing the
high voltage winding to the low voltage output,
reduces the voltage of all the unused outputs. The
D12
+12 V
+12 V
C15
R8
+
C16
+108 V
IC3
C19
R10
DZ2
C21
D13
+108 V
D14
+
C20
R9
R12
STBY
IC2
C22
R17
C24
C25
R18
STBY
Figure 17. Standby Regulation for Secondary
Reconfiguration
Figure 16. Secondary Reconfiguration with Thyristor
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Approach 1 (Overpower Compensation):
The NCP1207 enters a low peak current skip mode
to lower the consumption in low−load conditions.
But with some cheap transformers, the peak current
might be too high, generating an audible noise. In
that case, we propose a different implementation for
the standby regulation (Figure 18): by imposing a
ripple on the regulated output, we force the
controller to run in a burst mode, which generates
less mechanical stress in the transformer.
A classical way to compensate this effect is to add an
amount of the input voltage to the primary current sense
information (Figure 19):
+
LPRIM
RCOMP
STBY
OUTPUT
R8
Cbulk
DRV
RCS
IC3x
CS
R19
C28
RSENSE
Burst Generator
DZ2
DZ3
R31
R34
Q1
Figure 19. Classical Overpower Compensation
+
R33
C26
+
C27
SW1
Unfortunately, it is not possible to implement this scheme
with NCP1207 as the resistor in series with the current sense
information (RCS) has to be low, since it is used to adjust the
skip cycle level. It would require a low compensation
resistor RCOMP, wasting a lot of power.
It would be interesting to have an image of the input
voltage, but at a lower level. It is possible by using the
forward voltage on the auxiliary winding: by adding a diode
in series with the auxiliary winding, we have access to the
forward voltage (Figure 20).
R14
Q3
R15
Figure 18. This Standby Regulation Circuitry
Imposes a Noise−free Burst Mode
+
9. Overpower Protection
NCP1207 integrates a short−circuit protection,
based on the sensing of the peak primary current.
Unfortunately, as we have seen before, this peak
current is dependent of the input voltage (Figure 19):
the sense resistor has to be chosen to allow the
maximum peak current at low input voltage to flow
in the MOSFET. But at high input voltage, the peak
current necessary to deliver the same output power
is much lower: the sense resistor being fixed, the
maximum output power deliverable at high input
voltage is much greater. The conclusion is that the
built−in short−circuit protection is not an overpower
protection (OPP).
It is however possible to implement an OPP by
adding few additional components beside the
controller. We propose two different approaches,
one by compensating the CS pin voltage depending
on the input voltage, the other by sensing the output
current.
+
Cbulk
LPRIM
D2
CVCC
RVCC
RFWD
LAUX
CRES
Rdmg
D1
8
7
6
5
NCP1207
RCOMP
1
Cdmg
2
3
4
RSKIP
RSENSE
Figure 20. Overpower Compensation using
Forward Voltage
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AND8145/D
resistor RCOMP to create the desired offset on the current
sense signal at high input voltage.
Here are some screen shots describing the effect of the
compensation:
This forward voltage is proportional to N.VIN (N being
the turn ratio of the windings). RFWD is added to supply the
reverse current during the forward activity. Knowing the
value of the forward voltage and the series resistor RSKIP, it
is then easy to calculate the value of the compensation
: 400 mV
COMPENSATION OFFSET
1 − CURRENT SENSE PIN VOLTAGE
2 − SENSE RESISTOR VOLTAGE
3 − COMPENSATION VOLTAGE
4 − DRAIN VOLTAGE
Figure 21. Line Compensation at VIN = 365 Vdc
: 400 mV
COMPENSATION OFFSET = 0 V
1 − CURRENT SENSE PIN VOLTAGE
2 − SENSE RESISTOR VOLTAGE
3 − COMPENSATION VOLTAGE
4 − DRAIN VOLTAGE
Figure 22. Line Compensation at VIN = 100 Vdc
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AND8145/D
Approach 2 (Regulation Foldback):
Final Schematic
By sensing the current flowing in an output, it is possible
to build an efficient overcurrent protection, folding back the
regulation level when the current threshold is reached. It is
purposely completely independent of the input voltage.
A simple bipolar NPN transistor can sense the voltage
across the resistor and pull down the optocoupler emitting
diode (Figure 23). The protection is temperature dependent,
but it gives enough precision in most applications. The main
drawback of this approach is that only one output is
protected: the circuitry must be duplicated on each output
that needs to be protected.
Figure 24 on the following page, shows the final
schematic implemented on the demonstration board. It
includes all the options presented in the design steps.
The board is equipped by default with the following options:
• An RCD clamp for non−ZVS designs
• A regulation by Zener diode when the secondary
reconfiguration is activated
• An overcurrent protection on the 108 V output
+12 V
The PCB also accepts the following options:
• A regulation by the ripple generator when the
secondary reconfiguration is activated (see bill of
material for components mounting for this option)
• An overpower compensation through the use of the
forward voltage on the auxiliary winding
Two types of transformers can be soldered on the board,
either from OREGA or from VOGT ELECTRONIC.
+108 V
108 V
RSENSE
R8
R10
0V
IC1
Q1
R11
C21
P1
IC2
R12
Figure 23. Overcurrent Foldback on the 108 V Output
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GND
C13
+
C14
D11
−12 V
+12 V
D12
C15
+
+5.0 V
IC4
IN
REG
5.0 V
+
C16
IC4
IN
OUT
GND
+
C17
C18
GND
R1
D5
+3.3 V
OUT
REG
3.3 V
C8
R2
GND
C19
B+
D13
ROVP1
108 V
+
R8
C20
D14
D1
+
D6
R3
R22
0V
R19
R23
7
3
6
D7
R17
TH1
C12
D16
C24
R35
R11
Q4
5
4
C3
D8
R5
C28
C25
X1
ROVP2
DZ2
R32
C2
C21
+12 V
R18
R6
D9
R9
P1
IC2
Rs4 Rs3 Rs2 Rs1
C6
+
DZ1
C11
D10
C10
C22
IC3
R12
C1
C23
DZ3
R13
Q2
F1
R34
Q1
R21
R16
R14
Q3
R7
R20
MAINS
Figure 24. Schematic of the Demonstration Board
R15
+
C26
R33
+
C27
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2
D19
R4
C7
R10
IC3x
R31
8
C5
1
15
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C4
C9
IC1
AND8145/D
Board Performance
length = 1 hour). At VIN = 230 VAC, 5.0 V output loaded
with 30 mA (i.e. 150 mW output power):
• With simple Zener regulation: PSTBY = 850 mW (but
might be noisy with some transformers)
• With ripple generator: PSTBY = 1.0 W
Efficiency
At VIN = 250 VAC, POUT = 70 W, η = 84.3%
At VIN = 90 VAC, POUT = 70 W, η = 85.1%
At VIN = 250 VAC, POUT = 65 W, η = 83.6%
At VIN = 90 VAC, POUT = 65 W, η = 84.7%
Conducted EMI Signature
An EMI test has been conducted on the board, at 110 VAC
and 220 VAC, with full load on all the outputs (75 W total
secondary power): Figure 25. The measurement is done in
quasi−peak (QP) mode.
Standby Power
Measured on an Infratek wattmeter operating in
watt−hour accumulation mode for better accuracy (run
Figure 25. EMI Signature Captured at 110 VAC and 230 VAC
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WAVEFORMS
P1
P2
P3
P4
Figure 26. VDRAIN for Different Output Power (P1 > P2 > P3 > P4)
Figure 26 shows valley jumping when output power
decreases (P3 < P2 < P1), and skip in case of really light load
(P4).
Maximum drain voltage is obtained at high line, full load.
At 380 Vdc, 80 W on the output, we can see from Figure 27
that the MOSFET is safe.
Figure 27. Max VDRAIN at High Line, Full Load
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AND8145/D
As Figure 28 shows, the transition from standby to normal
mode is smooth, without any steps. As the “+12 V” output
is still regulated in standby, it can be lowered as much as
needed to supply the 5.0 V regulator.
12 V
2 − VCC
10 V
1 − + 12 V Output
12 V
8.5 V
108 V
3 − + 108 V Output
13 V
Figure 28. Standby to Normal Mode Transition
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AND8145/D
BILL OF MATERIAL
Standard Equipment of the Board
GENERIC TABLE
Part Number
Part Number
Reference
Reference
P1
500 R
IC1
NCP1207
Rs1, Rs2, Rs3, Rs4
1.1 R
IC2
TL431
RVOP1
33 k
IC3
SFH615
R1
15 k
IC4
MC7805
R2
47 k/2 W
IC5
LP2950−3.3 V
R3
47 R
X1
IRFIB6N60
R4
10 R
Q1, Q2, Q3, Q4
BC547C
R5
Replaced by a wire
D1
KBU4K
R6
390 R
D5, D9, D10
1N4007
R7
4.7 Meg/4 kV
D7, D8, D16
1N4148
R8, R18, R19
1k
D6, D14
1N4937
R10
56 k
D13
MR856
R11
47 k
D11, D12
MR852
R12
2.2 k
D19
Replaced by a wire
R13, R14, R15, R16, R20, R21
10 k
DZ1
Zener 15 V
R17
4.7 k
DZ2
Zener 5.6 V
R22, R23
1.5 R
DZ3
Replaced by a wire
R34
Replaced by a wire
TH1
MCR22−6
R35
27 k
F1
250 VAC/2.0 A
T1*
Transformer VOGT reference
UL030 121/21 or OREGA
reference G7209−01
L1
Mains filter OREGA
SW1
TL36P
C1, C2
220 nF/275 VAC classe X2
C3, C4
1 nF/1 kV
C5
150 F/400 V
C6, 21
1 nF/50 V
C7
82 pF/50 V
C8
10 nF/630 V
C9, C19
220 pF/1 kV
C10
33 F/50 V
C11, C13, C15, C25, C28
100 nF/50V
C12
330 pF/1 kV
C14, C16
470 F/35 V
C17, C18
100 F/16 V
C20
47 F/250 V
C23
2.2 nF/4 kV classe Y
C24
100 pF/200 V
*For a ZVS transformer, order OREGA ref. G7209−03
(C22, C26, C27, R9, R31, R32 and R33 are not implemented, a
15 V Zener diode is added in parallel to IC2)
Modifications needed to implement the standby ripple
generator:
Part Number
Reference
DZ2
Replaced by a wire
DZ3
Zener 3.9 V
C26, C27
1.0 F/25 V
R13
22 R
R33
15 k
R34
47 k
Overpower Compensation:
Part Number
D19
1N4148
R31
4.7 k
R32
18 k
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Reference
AND8145/D
PCB LAYOUT
−12 V GND
+12 V GND
5V
GND
3.3 V
GND
108 V
0V
STANDBY
• The drain track is the shortest possible
• The heatsink is connected to ground. It acts as a shield
Some important points that have been taken into account
to make a proper layout:
• The high alternating current loops areas both on
primary and secondary are the smallest possible to
minimize noise and EMI emission
between the noisy signals (drain, RCD clamp,
transformer) and the sensitive signals around the
controller
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AND8145/D
Notes
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AND8145/D
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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