BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS

SN74LS168
BCD DECADE
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL
COUNTERS
The SN54 / 74LS168 is a fully synchronous 4-stage up/down
counter featuring a preset capability for programmable operation,
carry lookahead for easy cascading and a U / D input to control the
direction of counting. The SN54/ 74LS168 counts in a BCD decade (8,
4, 2, 1) sequence. All state changes, whether in counting or parallel
loading, are initiated by the LOW-to-HIGH transition of the clock.
•
•
•
•
•
•
•
Low Power Dissipation 100 mW Typical
High-Speed Count Frequency 30 MHz Typical
Fully Synchronous Operation
Full Carry Lookahead for Easy Cascading
Single Up / Down Control Input
Positive Edge-Trigger Operation
Input Clamp Diodes Limit High-Speed Termination Effects
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BCD DECADE
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL COUNTERS
LOW POWER SCHOTTKY
16
J SUFFIX
CERAMIC
CASE 620-09
1
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
TC
Q0
Q1
Q2
Q3
CET
PE
16
15
14
13
12
11
10
9
N SUFFIX
PLASTIC
CASE 648-08
16
1
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as the Dual
In-Line Package.
D SUFFIX
SOIC
CASE 751B-03
16
1
U/D
2
CP
3
P0
4
P1
5
P2
6
P3
1
8
7
CEP GND
PIN NAMES
HIGH
CEP
CET
CP
PE
U/D
P0−P3
Q0−Q3
TC
Count Enable Parallel (Active LOW) Input
Count Enable Trickle (Active LOW) Input
Clock Pulse (Active positive going edge) Input
Parallel Enable (Active LOW) Input
Up-Down Count Control Input
Parallel Data Inputs
Flip-Flop Outputs
Terminal Count (Active LOW) Output
ORDERING INFORMATION
LOADING (Note a)
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
LOW
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
Ceramic
Plastic
SOIC
LOGIC SYMBOL
9
1
7
10
2
3
4
5
6
PE P0 P1 P2 P3
U/D
CEP
TC
CET
CP
Q0 Q1 Q2 Q3
15
14 13 12 11
VCC = PIN 16
GND = PIN 8
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 7
1
Publication Order Number:
SN74LS168/D
SN74LS168
STATE DIAGRAM
UP / DOWN DECADE COUNTER
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
UP:
TC = Q0 Q3 (U / D)
DOWN:
TC = Q0 Q1 Q2 Q3 (U / D)
Count Up
Count Down
8
LOGIC DIAGRAM
P0
PE
P1
P2
P3
CEP
CET
U/D
CP
CP
D
Q0
Q1
Q2
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2
Q3
SN74LS168
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
−55
0
25
25
125
70
°C
IOH
Output Current — High
54, 74
−0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Min
Parameter
Typ
2.0
54
0.7
74
0.8
−0.65
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
V
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = − 18 mA
2.5
3.5
V
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
20
40
μA
VCC = MAX, VIN = 2.7 V
0.1
0.2
mA
VCC = MAX, VIN = 7.0 V
−0.4
−0.8
mA
VCC = MAX, VIN = 0.4 V
−100
mA
VCC = MAX
34
mA
VCC = MAX
Other Input
CET Input
Input LOW Current
Other Input
CET Input
−1.5
Unit
54
Input HIGH Current
Other Inputs
CET Input
IIL
Max
−20
Note 1: Not more than one output should be shorted at one time, nor for more than 1 second.
FUNCTIONAL DESCRIPTION
The Terminal Count (TC) output is normally HIGH and
goes LOW, provided that CET is LOW, when a counter
reaches zero in the COUNT DOWN mode or reaches 15 (9
for the SN54/74LS168) in the COUNT UP mode. The TC
output state is not a function of the Count Enable Parallel
(CEP) input level. The TC output of the SN54/74LS168
decade counter can also be LOW in the illegal states 11, 13
and 15, which can occur when power is turned on or via
parallel loading. If illegal state occurs, the SN54/74LS168 will
return to the legitimate sequence within two counts. Since
the TC signal is derived by decoding the flip-flop states, there
exists the possibility of decoding spikes on TC. For this
reason the use of TC as a clock signal is not recommended.
The SN54/74LS168 uses edge-triggered D-type flip-flops
that have no constraints on changing the control or data input
signals in either state of the Clock. The only requirement is
that the various inputs attain the desired state at least a
set-up time before the rising edge of the clock and remain
valid for the recommended hold time thereafter.
The parallel load operation takes precedence over the
other operations, as indicated in the Mode Select Table.
When PE is LOW, the data on the P0 −P3 inputs enters the
flip-flops on the next rising edge of the Clock. In order for
counting to occur, both CEP and CET must be LOW and PE
must be HIGH. The U/D input then determines the direction
of counting.
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3
SN74LS168
MODE SELECT TABLE
PE
CEP
CET
U/D
Action on Rising Clock Edge
L
H
H
X
L
L
X
L
L
X
H
L
Load (Pn ³ Qn)
Count Up (increment)
Count Down (decrement)
H
H
H
X
X
H
X
X
No Change (Hold)
No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Parameter
Symbol
Min
Typ
25
32
Max
Unit
fMAX
Maximum Clock Frequency
tPLH
tPHL
Propagation Delay,
Clock to TC
23
23
35
35
ns
tPLH
tPHL
Propagation Delay,
Clock to any Q
13
15
20
23
ns
tPLH
tPHL
Propagation Delay,
CET to TC
15
15
20
20
ns
tPLH
tPHL
Propagation Delay,
U / D to TC
17
19
25
29
ns
Max
Unit
Test Conditions
MHz
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Limits
Parameter
Symbol
Min
Typ
tW
Clock Pulse Width
25
ns
ts
Setup Time,
Data or Enable
20
ns
ts
Setup Time
PE
25
ns
ts
Setup Time
U/D
30
ns
th
Hold Time
Any Input
0
ns
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4
Test Conditions
VCC = 5.0 V
SN74LS168
AC WAVEFORMS
1/fmax
1.3 V
CP
1.3 V
tW
tPLH
tPHL
Q OR TC
1.3 V
CET
1.3 V
tPLH
Figure 2. Count Enable Trickle Input
To Terminal Count Output Delays
1.3 V
CP
ts(H)
1.3 V
1.3 V
P0 • P1 • P2 • P3 1.3 V
1.3 V
tPLH
th(H) = 0
1.3 V
1.3 V
ts(L)
1.3 V
ts(H)
th(H) = 0
1.3 V
1.3 V
1.3 V
1.3 V
tPLH
1.3 V
CET 1.3 V
1.3 V
Figure 4. Setup Time (ts) and Hold (th)
for Parallel Data Inputs
U/D
ts(H)
1.3 V
1.3 V
th(L) = 0
SR OR PE 1.3 V
CEP 1.3 V
th(L) = 0
Q0 • Q1 • Q2 • Q3
CP
ts(H)
ts(L)
1.3 V
Figure 3. Clock to Terminal Delays
CP
1.3 V
tPHL
1.3 V
TC
1.3 V
1.3 V
Figure 1. Clock to Output Delays,
Count Frequency, and Clock Pulse Width
CP
tPHL
1.3 V
TC
1.3 V
1.3 V
1.3 V
th(H) = 0
1.3 V
ts(L)
1.3 V
1.3 V
th(L) = 0
1.3 V
1.3 V
1.3 V
Figure 6. Up-Down Input to
Terminal Count Output Delays
1.3 V
th(H) = 0
TC
tPHL
ts(L)
th(L) = 0
1.3 V
1.3 V
The shaded areas indicate when the
input is permitted to change for
predictable output performance.
Figure 5. Setup Time and Hold Time for
Count Enable and Parallel Enable Inputs,
and Up-Down Control Inputs
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SN74LS168
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