DECADE COUNTER; 4-BIT BINARY COUNTER

SN74LS290
DECADE COUNTER;
4-BIT BINARY COUNTER
The SN54/74LS290 and SN54/74LS293 are high-speed 4-bit
ripple type counters partitioned into two sections. Each counter has a
divide-by-two section and either a divide-by-five (LS290) or
divide-by-eight (LS293) section which are triggered by a
HIGH-to-LOW transition on the clock inputs. Each section can be
used separately or tied together (Q to CP)to form BCD, Bi-quinary, or
Modulo-16 counters. Both of the counters have a 2-input gated Master
Reset (Clear), and the LS290 also has a 2-input gated Master Set
(Preset 9).
• Corner Power Pin Versions of the LS90 and LS93
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Binary
• Input Clamp Diodes Limit High Speed Termination Effects
http://onsemi.com
DECADE COUNTER;
4-BIT BINARY COUNTER
LOW POWER
SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
MR
MR
CP1
CP0
Q0
Q3
14
13
12
11
10
9
8
14
1
NOTE:
The Flatpak version
has the same pinouts (Connection
Diagram) as the Dual In-Line Package.
LS290
N SUFFIX
PLASTIC
CASE 646-06
14
1
MS
2
NC
3
MS
4
Q2
5
Q1
6
NC
7
GND
VCC
MR
MR
CP1
CP0
Q0
Q3
14
13
12
11
10
9
8
1
14
1
LS293
1
NC
2
NC
3
NC
4
Q2
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
5
Q1
6
NC
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
7
GND
LOADING (Note a)
PIN NAMES
HIGH
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Ceramic
Plastic
SOIC
Clock (Active LOW going edge) Input to ÷ 2 Section.
Clock (Active LOW going edge) Input to ÷ 5 Section (LS290).
Clock (Active LOW going edge) Input to ÷ 8 Section (LS293).
Master Reset (Clear) Inputs
Master Set (Preset-9, LS290) Inputs
Output from ÷ 2 Section (Notes b & c)
Outputs from ÷ 5 & ÷ 8 Sections (Note b)
LOW
0.05 U.L.
0.05 U.L.
0.05 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
1.5 U.L.
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
c) The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 Input of the device.
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 6
1
Publication Order Number:
SN74LS290/D
SN74LS290
LOGIC SYMBOL
1 3
Figure
1.
LS290
Figure
2.
LS293
1 2
MS
10
CP0
11
CP1
MR
Q0 Q1 Q2 Q3
10
CP0
11
CP1
MR
1 2
12 13
Q0 Q1 Q2 Q3
1 2
9
5 4
8
12 13
VCC = PIN 14
GND = PIN 7
NC = PINS 2, 6
9
5 4
8
VCC = PIN 14
GND = PIN 7
NC = PINS 1, 2, 3, 6
LOGIC DIAGRAMS
MS1
MS2
CP0
LS290
1
3
SD
J
10
Q
J
CP
MR1
MR2
J
CP
KC Q
CD Q
CP1
Q
Q
R
CP
KC Q
D
SD
Q
CP
SC Q
D
D
11
VCC = PIN 14
GND = PIN 7
12
9
13
5
Q0
4
Q1
= PIN NUMBERS
8
Q2
Q3
LS293
CP0
CP1
MR1
MR2
10
J
Q
J
CP
K Q
CD
Q
J
CP
K Q
CD
Q
J
CP
K Q
CD
Q
CP
K Q
CD
11
VCC = PIN 14
GND = PIN 7
12
9
13
Q0
5
4
Q1
Q2
http://onsemi.com
2
= PIN NUMBERS
8
Q3
SN74LS290
FUNCTIONAL DESCRIPTION
The LS290 and LS293 are 4-bit ripple type Decade, and
4-Bit Binary counters respectively. Each device consists of
four master/ slave flip-flops which are internally connected to
provide a divide-by-two section and a divide-by-five (LS290)
or divide-by-eight (LS293) section. Each section has a
separate clock input which initiates state changes of the
counter on the HIGH-to-LOW clock transition. State changes
of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks
or strobes. The Q0 output of each device is designed and
specified to drive the rated fan-out plus the CP1 input of the
device.
A gated AND asynchronous Master Reset (MR1 ⋅ MR2) is
provided on both counters which overrides the clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1 ⋅ MS2) is provided on the LS290 which
overrides the clocks and the MR inputs and sets the outputs
to nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes:
receives the incoming count and a BCD count sequence
is produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a
divide-by-ten square wave is obtained at output Q0.
C. Divide-By-Two and Divide-By-Five Counter — No
external interconnections are required. The first flip-flop is
used as a binary element for the divide-by-two function
(CP0 as the input and Q0 as the output). The CP1 input is
used to obtain binary divide-by-five operation at the Q3
output.
LS293
A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are
applied to input CP0. Simultaneous division of 2, 4, 8, and
16 are performed at the Q0, Q1, Q2, and Q3 outputs as
shown in the truth table.
B. 3-Bit Ripple Counter — The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4,
and 8 are available at the Q1, Q2, and Q3 outputs.
Independent use of the first flip-flop is available if the reset
function coincides with reset of the 3-bit ripple-through
counter.
LS290
A. BCD Decade (8421) Counter — the CP1 input must be
externally connected to the Q0 output. The CP0 input
LS290 MODE SELECTION
RESET/SET INPUTS
OUTPUTS
MR1
MR2
MS1
MS2
Q0
Q1
H
H
X
L
X
L
X
H
H
X
X
L
X
L
L
X
H
L
X
X
L
X
L
H
X
L
L
X
L
L
H
L
L
L
Q2
L
L
L
Count
Count
Count
Count
Q3
L
L
H
LS290
BCD COUNT SEQUENCE
COUNT
0
1
2
3
4
5
6
7
8
9
OUTPUT
Q0
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
NOTE: Output Q0 is connected to Input CP1
for BCD count.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
http://onsemi.com
3
SN74LS290
LS293 MODE SELECTION
RESET INPUTS
OUTPUTS
MR1
MR2
Q0
Q1
H
L
H
L
H
H
L
L
L
L
Q2
Q3
L
Count
Count
Count
L
TRUTH TABLE
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUTPUT
Q0
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Note: Output Q0 connected to input CP1.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
−55
0
25
25
125
70
°C
IOH
Output Current — High
54, 74
−0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
http://onsemi.com
4
SN74LS290
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Min
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
MS, MR
CP0
CP1 (LS290)
CP1 (LS293)
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
Typ
Max
2.0
54
0.7
74
0.8
−0.65
−1.5
Unit
Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
V
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = − 18 mA
54
2.5
3.5
V
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
20
μA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
mA
VCC = MAX, VIN = 0.4 V
−100
mA
VCC = MAX
15
mA
VCC = MAX
−0.4
−2.4
−3.2
−1.6
−20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
http://onsemi.com
5
SN74LS290
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF)
Limits
LS290
Symbol
Min
Parameter
LS293
Typ
Max
Min
Typ
Max
Unit
fMAX
CP0 Input Clock Frequency
32
32
MHz
fMAX
CP1 Input Clock Frequency
16
16
MHz
tPLH
tPHL
Propagation Delay,
CP0 Input to Q0 Output
10
12
16
18
10
12
16
18
ns
tPLH
tPHL
CP0 Input to Q3 Output
32
34
48
50
46
46
70
70
ns
tPLH
tPHL
CP1 Input to Q1 Output
10
14
16
21
10
14
16
21
ns
tPLH
tPHL
CP1 Input to Q2 Output
21
23
32
35
21
23
32
35
ns
tPLH
tPHL
CP1 Input to Q3 Output
21
23
32
35
34
34
51
51
ns
tPHL
MS Input to Q0 and Q3 Outputs
20
30
ns
tPHL
MS Input to Q1 and Q2 Outputs
26
40
ns
tPHL
MR Input to Any Output
26
40
26
40
ns
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
LS290
Symbol
Min
Parameter
Max
LS293
Min
Max
Unit
tW
CP0 Pulse Width
15
15
ns
tW
CP1 Pulse Width
30
30
ns
tW
MS Pulse Width
15
tW
MR Pulse Width
15
15
ns
trec
Recovery Time MR to CP
25
25
ns
ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition form HIGH-to-LOW in order to
recognize and transfer HIGH data to the Q outputs.
AC WAVEFORMS
*CP
1.3 V
tW
tPHL
Q
1.3 V
1.3 V
tPLH
1.3 V
Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
MR & MS
1.3 V
MS
1.3 V
tW
1.3 V
trec
tW
trec
CP
CP
1.3 V
tPHL
Q
1.3 V
Q0 Q3
(LS290)
1.3 V
Figure 2
1.3 V
tPLH
1.3 V
Figure 3
http://onsemi.com
6
SN74LS290
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
SN74LS290/D
Similar pages